Switch-mode power supply device with a gain modulation circuit

Abstract

The present invention relates to a switch-mode power supply device (100) configured to deliver an output voltage across the terminals of a load on the basis of an input voltage delivered by a source, the device comprising: - a transformer (TRMAIN) comprising a primary winding and a secondary winding to which the load is connected; - a main switch (TMAIN) connected to the primary winding and configured to switch between an activated state in which a current flows therethrough and a deactivated state; - a main control circuit (U1) configured to apply a gain to the current (IT) so as to keep the output power constant; - a gain modulation circuit (M1) connected at input to the source and at output to the main control circuit (U1), and configured to generate, as output, on the basis of a rectified voltage representative of the source voltage, a control signal configured to modulate the gain, the gain modulation circuit (M1) comprising a plurality of N stages, the voltage controlling activation of a set of stages from among the plurality of N stages.

Description

Switching power supply device with gain modulation circuit

[0001] The invention relates to the field of power electronics for acoustic applications. More particularly, the invention relates to switched-mode power supply devices, especially for loudspeakers and acoustic systems.

[0002] A power supply provides one or more DC voltages, for example from the voltage of an electrical network or mains supply, thus delivering power to a connected load. The load corresponds to circuits and modules within an electrical device, which could be a loudspeaker.

[0003] Switching power supplies, particularly those with indirect transfer (flyback converters), are well suited for the realization of a single-stage power supply device, the advantage of which is to provide galvanic isolation and power factor correction.

[0004] These devices include switching means that regulate the DC voltage delivered at the output. The energy injected into the transformer is controlled by the switching means.

[0005] We are familiar with power supply devices in which the output power is controlled by taking into account a peak current (peak current mode) flowing through the switching means. Such a control device is widely used due to its simplicity of implementation.

[0006] However, this type of control device is vulnerable to distortion and significant fluctuations in mains voltage, which can degrade the power factor of the single-stage indirect transfer power supply and cause the output power to exceed the maximum permissible power. This vulnerability to distortion and mains voltage fluctuations is even greater for high-power power supplies.

[0007] Some control circuits for such power supply devices use an analog arithmetic block. However, such a component is complex to implement. This is a complex and costly undertaking, and cannot be achieved using standard electronic components. Furthermore, such control circuits generally do not allow for galvanic isolation between the primary and secondary circuits of the power supply unit that incorporates them.

[0008] The present invention aims to provide a solution for switched-mode power supplies, particularly those with indirect transfer (also known as flyback converters), which allow the use of galvanic isolation and power factor correction. The proposed solution improves output power control of a flyback converter regardless of the speed and magnitude of source voltage variations. The solution also aims to make the control device of such power supplies less sensitive to distortions and mains voltage variations by isolating the direct electrical path between the source and the control means of this device. Description of the invention

[0009] To this end, the invention proposes to integrate an additional module into the classic architecture of a switched-mode power supply device.- A switching power supply device is thus proposed, configured to deliver an output voltage intended to power a load from an input voltage supplied by a source, comprising: a transformer including a primary winding and a secondary winding to which the load is connected; a main switch connected to the primary winding and configured to switch between an activation state in which a current flows through it and a deactivation state; a main control circuit delivering a control signal to the main switch and being configured to apply a gain to the control signal so as to maintain the output power constant;a gain modulation circuit connected at input to the source and at output to said main control circuit, and configured to generate at output, on the basis of a voltage from the source, a control signal configured to modulate said gain, the gain modulation circuit comprising a plurality of N stages, said voltage; controlling an activation of a set of stages from among the plurality of N stages, the activated set of stages determining the corresponding gain modulation amplitude which is applied, in operation, to the gain of the main control circuit. [001 OJL'intégration de un circuit de contrôle selon la invention dans un dispositif d'alimentation d'interrupteur-s'une dispositif d'emploi de gain appliqué dans la boucle d'current de ce dispositif d'alimentation d'un dispositif d'exercice d'une s'a mesure à l'a s ...

[0011] More specifically, each stage of the gain modulation circuit modifies a proportion of the current loop gain according to the target output power, which depends on the input voltage of the power supply. Consequently, the gain modulation circuit allows for better control of the power supply's output power regardless of variations in the input voltage, such as the mains voltage. Furthermore, the coupling between the source and the control device is reduced. There is no longer a direct electrical connection between the source and the control device. In other words, the gain modulation circuit according to the invention immunizes a switched-mode power supply, in which this gain modulation circuit is integrated, against variations and distortions in the source voltage, making the latter more stable.

[0012] Furthermore, the influence of the input voltage on the gain applied by the main control circuit improves the control of the power supply's output power against fluctuations in this input voltage. The output power is strictly maintained below the maximum power intended during operation.

[0013] According to one embodiment, the gain modulation circuit is configured to: generate, from the input voltage, a plurality of N' binary signals encoding together an N-bit binary word representing a gain rank determining the set of stages, the set of activated stages determining a gain modulation amplitude; and generate the control signal from said gain modulation amplitude.

[0014] According to one embodiment, the value of the binary word is a decreasing function of the input voltage.

[0015] According to one embodiment, the gain modulation circuit comprises: a first module configured to receive as input, in operation, said input voltage and to generate as output said plurality of N' binary signals; a second module configured to receive as input, in operation, the plurality of N' binary signals and an electrical signal representative of said current flowing in said main switch, the second module comprising said plurality of N stages, each of the N stages being voltage controlled by one of the N' binary signals, the plurality of the N stages joining at a common terminal connected to the main control circuit, so that the control signal is delivered, in operation, by said common terminal.

[0016] According to one embodiment, each stage comprises a series association of a transistor with a resistor.

[0017] According to one embodiment, the first module includes a microcontroller, the microcontroller comprising: an analog-to-digital converter configured to receive a rectified voltage image of the voltage across the source terminals; a first circuit connected at the output of the analog-to-digital converter, and configured to perform, in operation, a first logic function, so as to deliver at the output, a first output voltage as a function of the rectified voltage image of the voltage across the source terminals; a second circuit connected at the output of the first circuit and configured to perform, in operation, a second logic function, so as to generate the plurality of N' binary signals.

[0018] According to one embodiment, the first logic function is configured to perform: a first action of extracting a maximum voltage value; a second action of maintaining said first output voltage at said maximum voltage value; a third action of decreasing said first output voltage from said maximum voltage value.

[0019] According to one embodiment, the second circuit comprises N” output terminals, the second logic function is configured to convert the first output voltage into a plurality of binary values ​​intended to be applied to the N” output terminals of the second circuit, such that the gain rank is between 1 and 2 N+1 .

[0020] According to one embodiment, the first module is, in operation, synchronized with a control signal from the main control circuit, the control signal being configured to control the main switch.

[0021] According to one embodiment, the first module comprises a circuit and a network of N' switches, the first circuit being configured to divide, in operation, the value of the input voltage into N ranges, so as to generate N first signals, each of the first N signals being a function of a corresponding range, each switch being configured to switch between a conducting state and a blocking state, and to deliver, in operation, a binary signal from among the plurality of N' binary signals, each first signal determining, in operation, the switching of a corresponding switch in the network of N' switches.

[0022] According to one embodiment, the first circuit comprises a network of resistors connected in series.

[0023] According to one embodiment, the first module further comprises a comparator network, each comparator comprising a non-inverting terminal and an inverting terminal, each non-inverting terminal being configured to receive, in operation, a corresponding signal, and each inverting terminal being connected to a common voltage source delivering a voltage, each on / off signal being configured to control the switching of a corresponding switch in the network of switches.

[0024] According to one embodiment: the first circuit includes intermediate branches, each delivering a corresponding signal, and each comparator is connected to a branch of the corresponding intermediate branches in an increasing order of the corresponding ranges.

[0025] A second aspect of the invention relates to an acoustic enclosure comprising a switching power supply device according to the first aspect of the invention.

[0026] A third aspect of the invention relates to an acoustic amplification device comprising a switching power supply device according to the first aspect of the invention. Brief description of the drawings

[0027] Other features, details, and advantages of the invention will become apparent upon reading the detailed description below. This description is purely illustrative and should be read in conjunction with the accompanying drawings, on which:

[0028] Figure 1 represents an example of a switched-mode power supply device comprising a gain modulation circuit according to an embodiment of the invention;

[0029] Figure 2 represents an embodiment of the gain modulation circuit of Figure 1, comprising a first module and a second module;

[0030] Figure 3 represents an example of the implementation of the second module of the gain modulation circuit of Figure 2;

[0031] Figure 4 represents an analog embodiment of the first module of the gain modulation circuit of Figure 2;

[0032] Figure 5 represents an example of an embodiment of the switching power supply device according to the invention incorporating the first module of Figure 4 and the second module of Figure 3;

[0033] Figure 6 represents the evolution of a binary word according to an analog embodiment of the invention and of a corresponding effective resistance as a function of an input voltage received by the switching power supply device according to this digital embodiment;

[0034] Figure 7 represents an example of the time profile of an input voltage received by a switching power supply device and the corresponding time profile of the effective resistance according to an analog embodiment of the invention;

[0035] Figure 8 represents a digital embodiment of the first module of the gain modulation circuit of Figure 2;

[0036] Figure 9 shows an example of a time profile of an input voltage received by the first module in Figure 8, as well as reading points of this input voltage;

[0037] Figure 10 represents an example of input voltage peaks detected by a first action of a first logic function performed by a first circuit of the first module of Figure 8;

[0038] Figure 11 illustrates the operation of a second action of a first logic function carried out by a first circuit of the first module of Figure 8;

[0039] Figure 12 illustrates the operation of a third action of a first logic function carried out by a first circuit of the first module of figure 8;

[0040] Figure 13 represents an example of an embodiment of the switching power supply device according to the invention incorporating the first module of Figure 8 and the second module of Figure 3;

[0041] Figure 14 represents the evolution of a binary word according to a digital embodiment of the invention and of a corresponding effective resistance as a function of an input voltage received by the switching power supply device according to this digital embodiment;

[0042] Figure 15 represents an example of the time profile of the current flowing in a main switch of the switching power supply device according to the invention;

[0043] Figure 16 represents an example of the evolution, as a function of the input voltage of a source, of the power received by a load connected to a switching power supply device according to the invention and connected to the source;

[0044] Figure 17 represents a comparison of an example of a time profile of a current delivered by a source without the integration of a gain modulation circuit according to the invention and with the integration of the gain modulation circuit according to the invention;

[0045] Figure 18 schematically represents an acoustic enclosure comprising the switching power supply device according to the invention;

[0046] Figure 19 schematically represents an acoustic amplification device comprising the switching power supply device according to the invention. Detailed description

[0047] According to a first aspect of the invention, a switching power supply device 100 is proposed, illustrated in Figure 1 according to an example of an embodiment of the invention, and integrating a gain modulation circuit M1.

[0048] The switching power supply 100 is of the indirect transfer type (also known as a flyback converter), but the switching power supply can be of another type. All switching power supplies using current-based control of the main transistor are covered by the invention.

[0049] In the example illustrated in Figure 1, the 100 switching power supply unit comprises: - a TRMAIN transformer comprising a primary winding connected to a primary circuit and a secondary winding supplying a secondary circuit to which a LOAD load is connected; - a main TMAIN switch coupled to the primary winding; - a main control circuit U1 configured to, in operation, apply a gain to an IT current flowing in the main switch TMAIN, so as to control this IT current; - a VOLTAGE_LOOP control loop controlling an output voltage across the terminals of the LOAD load; - a CLAMP_NETWORK voltage clamp circuit.

[0050] The switching power supply device 100 is connected at its input, via the primary circuit, to a source SOURCE.

[0051] In the example in Figure 1, the SOURCE supplies power via a bridge formed by four diodes Db. Typically, the SOURCE is derived from the mains voltage, ranging between 85 and 265 VAC. The SOURCE delivers a current ISOURCE downstream of the bridge.

[0052] The primary circuit includes a branch comprising a series association of an input capacitor CIN and an input resistor RIC.

[0053] Optionally, the primary circuit includes a LIN input inductor, the integration of which into the 100 power supply device is advantageous for high output powers, for example, exceeding several kilowatts. This LIN input inductor helps smooth the source current and reduces potential difficulties in obtaining an electromagnetic compatibility certificate.

[0054] Advantageously, the input capacitor CIN is of low value, on the order of 5 to 15 microfarads, as is the input resistance RIC, which can be on the order of 50 to 5 milliohms. The value of the input inductance LIN, when present, can range from a few tens to a few hundred microhenries.

[0055] The secondary circuit includes a DOUT output diode and a COUT output capacitor.

[0056] The VOLTAGE_LOOP control loop is configured to control the voltage across the LOAD load.

[0057] The main control circuit U1 includes a first input terminal FB configured to receive, during operation, a signal from the VOLTAGE_LOOP control loop, and an output terminal configured to deliver a PWM_MAIN control signal to the main switch TMAIN. In preferred embodiments, the main control circuit U1 operates in peak current mode. The main control circuit U1 is configured to dynamically apply a gain to the PWM_MAIN control signal, thereby modifying the duty cycle of the main switch TMAIN.

[0058] The main switch TMAIN is connected to a current-gathering network from which, during operation, a signal representing the IT current flowing through the main switch TMAIN is derived. As will be explained below, the use of this signal in the present invention differs from prior art solutions.

[0059] Figure 2 illustrates one embodiment of the gain modulation circuit M1.

[0060] In the illustration of Figure 2, the gain modulation circuit M1 includes a first input terminal AC REC, a second input terminal l_SENS+, a third output terminal RCIN and an output terminal R.

[0061] Advantageously, the gain modulation circuit M1 is configured to: - receive, via the first AC REC input terminal, an input voltage from the SOURCE to which the switching power supply device 100 is connected; - be connected, via the first output terminal R, to the main control circuit U1 of the switching power supply device 100, so as to send via an input terminal CS of the main control circuit U1, in operation, to this main control circuit U1, a control signal.

[0062] The input voltage from the source refers to a voltage either delivered directly by the source or a voltage across the output terminals of an electrical circuit that transforms the voltage across the source. The input voltage can be alternating current (AC), direct current (DC), or arbitrary. For example, the transforming electrical circuit could be a full-wave rectifier circuit consisting of two diodes, D1 and D2, converting the AC voltage from the source into a DC voltage.

[0063] Advantageously, the gain modulation circuit M1 is connected during operation, via the second input terminal l_SENS+, to a current sensing network of the associated switching power supply. The current sensing network is configured to measure, during operation, a signal representative of the IT current flowing through the main switch TMAIN of the switching power supply 100.

[0064] In preferred embodiments, and as illustrated in Figure 2, the gain modulation circuit M1 comprises a first module M100 and a second module M110.

[0065] In these embodiments, the first module M100 includes the first AC REC input terminal and N output terminals. The second module M110 includes N input terminals connected to the first module M100 via the N output terminals of the first module M100. The second module M110 also includes the second input terminal l_SENS+, the third input terminal RCIN, and the output terminal R of the gain modulation circuit M1.

[0066] According to the invention, the gain modulation circuit M1 comprises a plurality of N stages, preferably included in the second module M110. N is an integer greater than or equal to 2. For example, N is equal to 4. Advantageously, N is between 4 and 32.

[0067] Preferably, the first module M100 receives, during operation, a DC voltage that is a reflection of the voltage across the SOURCE terminals. This DC voltage constitutes the input voltage. In the example shown in Figure 2, this voltage can be derived from a full-wave rectifier circuit comprising two diodes D1 and D2, each receiving a signal from one of the AC IN 1 and AC IN 2 terminals of the SOURCE, when the latter is an AC source.

[0068] The first M100 module is configured to generate, from this input voltage, a plurality of N binary signals Bi, for i between 0 and N-1. In Figure 1, N is equal to 4. Each binary signal Bi takes, during operation, a value representing a high state or a value representing a low state. Each of the plurality of N output terminals of the first M100 module delivers one of the binary signals Bi.

[0069] Advantageously, the plurality of N binary signals is configured to encode together an N-bit binary word representing a gain rank. The gain rank designates the order of a gain modulation amplitude value that will be applied, during operation, to the gain of the main control circuit U1. Advantageously, the gain rank varies within a range of values ​​depending on the number N of stages in the gain modulation circuit. For example, the gain rank varies between 0 and N+1. In another example, the gain rank varies between 0 and 2. A N - 1 .

[0070] Advantageously, the gain rank encoded by the N-bit word determines the activation of a set of stages among the N stages of the gain modulation circuit M1. The activated set of stages determines the corresponding gain modulation amplitude that will be applied, during operation, to the gain of the circuit. The main control circuit U1 is controlled by a gain modulation amplitude applied to it during operation. This amplitude is a function of the input voltage from the source. Consequently, the gain modulation amplitude applied to the main control circuit U1 takes into account not only the signal representing the IT current but also fluctuations in the voltage across the source.

[0071] We now refer to figure 3 which illustrates one embodiment of the second module M110.

[0072] In this embodiment, the second module M110 comprises a set of N stages, with N equal to 4 in Figure 3. Each stage includes an input terminal receiving one of the N binary signals Bi.

[0073] More specifically, each stage is connected to one of the output terminals of the first M100 module. Therefore, a stage is controlled, in operation, by the binary signal from the corresponding output terminal of the first M100 module.

[0074] According to one example, each stage comprises a series association of a transistor Si and a resistor Rsi, i being an integer between 1 and N.

[0075] The N stages meet at a common terminal forming the output terminal R of the second module M110.

[0076] Advantageously, the input terminal I SENS+ and a complementary resistor RsO are also connected to the common terminal.

[0077] Thus, the current collection network is advantageously connected to the common terminal.

[0078] Advantageously, a ramp-shaped voltage is also injected at the common terminal during operation. This ramp-shaped voltage is advantageously synchronized with a clock signal from the main control circuit U1. Such a voltage allows compensation for the right half-plane zero (RHPZ).

[0079] Therefore, a resulting voltage is induced at the common terminal, which is the sum of the different voltages from the N stages and an image voltage of the IT current flowing through the main TMAIN switch. This resulting voltage depends on the activation state of each stage.

[0080] Advantageously, the gain modulation circuit M1 is also connected, via its output terminal RCIN, to the input resistor RIC of the primary circuit of the switching power supply M100, thereby stabilizing the current loop. This connection enables active control of the input impedance of the SOURCE. The SOURCE impedance is not constant and depends on its connection point to the power grid. These impedance variations, if left uncontrolled, can destabilize the current loop.

[0081] Thus, by injecting a voltage proportional to the current ISOURCE flowing through the input capacitor CIN at the common terminal, and through a resistor RDAMP, it is possible to achieve active damping of the source impedance SOURCE. The result is improved current loop stability of the power supply device 100, as well as increased robustness of the main control circuit to potential variations in the source impedance SOURCE.

[0082] In embodiments called analog embodiments, the first M100 module is a module operating in analog mode, an example of which is illustrated in Figure 4.

[0083] In the analog embodiment, the first module M100 comprises a first circuit, a second circuit connected to the first circuit, and a network of N switches Ti, i between 1 and N.

[0084] Each switch Ti is configured to switch between a conducting state and a blocked state, so as to control, depending on its state, the value of one of the plurality of N binary signals Bi. The switching of the switches Ti is determined by the first circuit and the second circuit.

[0085] The first circuit is configured to divide the input voltage value into N ranges during operation. In one example, the N ranges are equal. In another example, the N ranges are different from each other. In yet another example, at least two of the N ranges are different from each other. The first circuit This defines a set of N intermediate branches, each delivering a first signal that is a function of a corresponding range of the input voltage value. Each intermediate branch is connected to an input terminal of the second circuit.

[0086] In the example in Figure 4, the second circuit comprises a plurality of input terminals, some of which are connected to one of the N intermediate branches of the first circuit, and a plurality of N output terminals. The second circuit is configured, during operation, to deliver a second on / off signal at each of its output terminals, a function of the corresponding first signal from the first circuit. Each of the output terminals of the second circuit is connected to the input terminal of one of the N switches, so that one of the second signals controls the switching state of the corresponding switch Ti.

[0087] In the example in Figure 4, the first circuit includes a divider network comprising N+1 resistors Ri, for i between 0 and N, such that each intermediate branch carries a potential Vi, for i between 1 and N.

[0088] In the example shown in Figure 4, the second circuit comprises a network of hysteresis comparators, each connected, at its non-inverting terminal, to one of the intermediate branches. Each inverting terminal of the hysteresis comparators is connected to a common voltage source providing a reference voltage (Vref). For example, the Vref voltage is between 3.3 and 12 V. This Vref voltage is stable and has low noise.

[0089] Advantageously, each switch Ti is connected to a combination of a resistor RPULL and a capacitor Ci. The combination of the resistor RPULL with the capacitor Ci forms a delay network with a time constant RPULL*Ci. This time constant allows adjustment of the switching time of the switch Ti and therefore of the binary signal Bi that it delivers. For example, each switch Ti is a transistor wired in open-collector configuration to the associated resistor RPULL.

[0090] Figure 5 illustrates a possible example of the M1 gain modulation circuit combining the first module M100 shown in Figure 4 and the second module M1 10 is illustrated in Figure 3. In this example, the number N of stages is equal to 4. For example, in this analog embodiment, the area required for the gain modulation circuit M1 can be between 3 and 4 cm². 2 .

[0091] In this example, the current-harvesting block M21 consists of a current transformer TSENS, a diode DSENS, and a resistor RsO. The transformer ratio can range from 1:100 to 1:500 depending on the desired output power and the maximum IT current flowing in the primary circuit, and in particular, in the main TMAIN switch of the 100 switching power supply. The IT current should closely match the actual current flowing in the main TMAIN switch. Peak current mode control requires a high transformer cutoff frequency of at least 10 times the power supply's operating frequency. To ensure proper operation, this frequency should preferably be much higher.

[0092] In this example as well, resistors Rs1 to Rs4 and MOSFET transistors S1 to S4 form four gain switching networks. The resistors are chosen such that RsO <Rs1 <Rs2<Rs3<Rs4. L’ordre de grandeur de RsO est de 10 à 20 ohms.

[0093] Comparators U1 to U4 switch high when the mains voltage present on one of the intermediate branches of the first circuit (which is a divider network) exceeds Vref. The high switching causes the corresponding switch (a MOSFET transistor T1 to T4) to switch on, resulting in the rapid discharge of the corresponding connected capacitor (C1 to C4), forcing the corresponding MOSFET transistor S1 to S4 into the off state.

[0094] Comparators U1 to U4 switch low when the voltage Vi (i.e., the input voltage range) present on one of the branches of the divider network is less than VREF. Switching low causes the corresponding output transistor, T1 to T4, to switch to the off state, allowing the corresponding connected capacitor, C1 to C4, to charge at a rate Rpull*Ci. The corresponding MOSFET transistor, S1 to S4, will switch from the off state to the on state with a switching time proportional to the time constant Rpull*Ci of the corresponding delay network.

[0095] The switching of MOSFET transistors from S1 to S4 is cumulative. In other words, when transitioning to the on state, MOSFET S4 will switch first, followed by S3, then S2, and finally S1. By design, switching S4 and S2 without switching S3 is impossible. Similarly, when transitioning to the off state, S1 will switch off first, followed by S2, then S3, and finally S4.

[0096] Consequently, the modulation of the current loop gain is achieved by connecting the resistors Rs1 to Rs4, successively, in parallel with the resistor RsO.

[0097] Figure 6 illustrates the effective input impedance R seen by the main control circuit U1 at its input terminal CS, as a function of the binary word B value and the resistances Rs1 to Rs4, for an AC input voltage ranging from 85 VAC to 265 VAC. The effective input impedance R is lower than the resistance RsO, improving the noise immunity of the main control circuit U1.

[0098] Thus, according to the invention, there is no longer a continuous path between the source SOURCE and the current loop of the switching power supply device 100.

[0099] Figure 7 illustrates the time evolution of the effective input impedance R seen by the main control circuit U1 as a function of the variation of the input voltage ACIN from the source SOURCE. This effective input impedance increases as the input voltage ACIN increases and decreases as the input voltage ACIN decreases. For each voltage Vi reached by the input voltage ACIN, corresponding to a given range and a given intermediate branch of the first circuit, the value of the effective impedance R is equal to the parallel resistance of the resistors R0 to RN+1-i, for i an integer varying between 1 and N.

[0100] As shown in Figure 7, if the input voltage increases, the turn-off time of MOSFET transistors S1 to S4 is short, so the current loop gain can be updated quickly (for example, in the event of a mains overvoltage). This behavior reduces the risk of power overshoot at the power supply output. Conversely, when the input voltage decreases, the switching time to the on state of MOSFET transistors S1 to S4 is delayed, resulting in the maintenance of the previously applied gain value for a period TMaintient, and this as long as the average value of the input voltage is constant over the duration Rpull*Ci.

[0101] Indeed, the decrease in the average value of the input voltage during a period of time greater than or equal to Rpull*Ci allows the successive switching of the MOSFET transistors S1 up to S4, adjusting the loop gain to the new input voltage, and corresponding to the release phase of the current loop gain over a time period TRelâche.

[0102] In embodiments called digital embodiments, the first M100 module is a module operating in digital mode, an example of which is illustrated in Figure 8.

[0103] In some digital embodiments, the first M100 module includes a filter and a CPU microcontroller.

[0104] Advantageously, the filter is configured to filter the input voltage from the SOURCE. For example, and as illustrated in Figure 8, the filter can consist of a network of passive components such as a pair of resistors RO and R1 providing a voltage filtered by a capacitor C1. Thus, advantageously, the filter lowers and limits the noise in the voltage that will be sent to the input of the CPU microcontroller.

[0105] Advantageously, the CPU microcontroller includes: - an analog-to-digital converter (ADC) configured to receive the input voltage filtered by the filter, - a first circuit connected to the analog-to-digital converter (ADC), and configured to perform, during operation, a first logic function F1, so as to deliver at the output, a first output voltage that is a function of the filtered input voltage; and -a second circuit connected to the first circuit and comprising N output terminals, and configured to perform, in operation, a second logic function F2, so as to generate the plurality of N binary signals Bi.

[0106] As an example, the CPU microcontroller is an 8-bit microcontroller incorporating an analog-to-digital converter (ADC).

[0107] The analog-to-digital converter (ADC) converts the analog voltage value from the filter into an integer digital value. Advantageously, the conversion occurs at a readout frequency higher than the maximum frequency of the source. For example, the readout frequency will be 20 to 50 times higher than this maximum frequency. For instance, the readout frequency can be chosen between 1 kHz and 3 kHz to be compatible with main source frequencies of 50 Hz (in Europe) or 60 Hz (in North America). The readout frequency determines the response time of the gain modulation circuit M1. Figure 9 illustrates an input voltage profile at 50 Hz and the corresponding readout points of the ADC at a readout frequency of 1 kHz.

[0108] Advantageously, the resolution of the analog-to-digital converter (ADC) in bits is at least equal to the number of stages N in the gain modulation circuit M1. Preferably, this resolution is between 8 bits and Mbits. The analog-to-digital conversion is triggered automatically by the CPU microcontroller's interrupt system. The conversion result is immediately available in memory and updated at the chosen read frequency. To reduce conversion noise and improve conversion quality, averaging can be added. Averaging over 2, 4, or 8 samples can be performed by the microcontroller at each read.

[0109] As an example, the operating range of the analog-to-digital converter (ADC) is between 0 and 3.3 V. The gain of the resistive device formed by the filter resistors R0 and R1 can be chosen so that the maximum operating voltage of the switching power supply 100 corresponds to the maximum possible input voltage of the analog-to-digital converter (ADC).

[0110] In the example shown in Figure 8, the cutoff frequency of the low-pass filter formed by resistor R0 and capacitor C1 must be higher than the source frequency SOURCE. For example, this frequency is more than 100 times higher, in order to achieve a compromise between the system's response time to variations in the source SOURCE and the effectiveness of filtering the switching noise of the main switch TMAIN. To illustrate, when the source SOURCE delivers an alternating voltage, the voltage present at the input of the analog-to-digital converter ADC is a positive miniature image of this alternating voltage.

[0111] The analog-to-digital converter (ADC) is connected at its output to the input of the first circuit performing the first logic function F1, so that the input signal of the first logic function F1 is the digital result from the analog-to-digital converter (ADC).

[0112] The execution of the first logic function F1 is synchronized with the read frequency of the analog-to-digital converter (ADC), so the digital value presented at the output of the first logic function F1 is updated at the same frequency as the ADC read frequency. Advantageously, the total latency between the conversion and the availability of a new value at the output of the first logic function F1 is much lower than the chosen read frequency. For example, the total latency can be a few microseconds.

[0113] As previously stated, the first circuit delivers, in operation, a first output voltage, by performing the first logic function F1.

[0114] The first logical function F1 performs three actions which will be described below: - an initial action of extracting a maximum voltage value; - a second action to maintain said first output voltage at said maximum voltage value; - a third action of reducing said first output voltage from the maximum voltage value.

[0115] During the first operation, the first logic function F1 extracts the maximum value of the voltage read at the input of the analog-to-digital converter (ADC). The first logic function F1 returns the peak value each time the conversion result is updated by the CPU microcontroller and is greater than the previous value. The update of the peak value at the output of the first logic function F1 occurs immediately after the ADC provides the conversion result. At the output of the first Logic function F1 therefore presents at any given time the peak value of the image of the voltage across the terminals of the source SOURCE (for example, the mains voltage). Figure 10 shows, for the example of source voltage shown in Figure 9, the two peak values ​​retained by the first logic function F1.

[0116] During the second action, the first logic function F1 maintains the peak value for a predetermined duration TMaintenance. For example, the hold time TMaintenance can be between 2 and 10 times the period corresponding to the minimum frequency of the source SOURCE. For instance, the hold time could be between 20 ms and 200 ms. This value is maintained throughout this period as long as the results of subsequent conversions performed by the analog-to-digital converter (ADC) and presented as input to the first logic function F1 remain lower than the held value. Otherwise, the first logic function F1 will switch from the hold state to the first maximum value extraction action described above.

[0117] Figure 11 shows two examples of signals (left and right) from the first circuit implementing the first logic function F1, specifically the hold time TMaintient and the change in the held value as a function of the detected peak value. This change corresponds to the switch from the hold state to the maximum value extraction state of the first logic function F1.

[0118] Advantageously, during operation, the hold time eliminates the risk of oscillation in the current loop formed by the main control circuit U1, whose gain would otherwise follow all variations in the amplitude of the source voltage. Here, the gain modulation circuit M1 is very fast at increasing the current loop gain but slow at decreasing it. This asymmetrical response time immunizes the gain modulation circuit M1 and the rest of the 100-volt switching power supply from overreacting to even the slightest variations in the mains voltage.

[0119] During the third action, the first logic function F1 decreases the previously held value. This final phase begins when the value holding phase has been completed for the full programmed duration TMaintient. For example, the release time could be set between 5 and 10 times. The hold time of the hold period. The release time is the time required to transition from the maximum to the minimum value of the modulator gain. The release occurs as long as the results of subsequent conversions performed by the analog-to-digital converter (ADC) and presented at the input of the first logic function F1 remain lower than the released value. Otherwise, the first circuit will switch the first logic function F1 from the release state to the first maximum value extraction action described above.

[0120] Figure 12 shows two examples of signals from the first circuit performing the first logic function F1, and in particular the change of this signal between the holding time and the release state on the left, and the switch, on the right, from the release time to the holding time following the switch of the first logic function F1 from the release state to the maximum value extraction state.

[0121] As previously stated, in the digital embodiments, the first M100 module includes a second circuit whose operation will be described below. The second circuit comprises N output terminals and is configured to perform, during operation, a second logic function F2, so as to generate the plurality of N binary signals Bi.

[0122] The second logic function F2 performs a conversion of the signal from the first logic function F1 (in other words the value of the peak held or released) into a value to be applied to the N output terminals, thus producing the N binary signals Bi.

[0123] Advantageously, the execution of the second logic function F2 is synchronized with the reading frequency of the analog-to-digital converter ADC.

[0124] By construction, the amplitude of the binary word B formed from the N binary signals Bi is inversely proportional to the amplitude of the peak provided by the first logic function F1. Furthermore, the gain rank evolves inversely with the amplitude of the binary word B.

[0125] Figure 13 shows a possible example of a gain modulation circuit M1 combining the first module M100 of the digital embodiment illustrated on the Figure 8 and the second module M110 are shown in Figure 3. In this figure, each of the N output terminals of the second circuit of the first module M100 is connected to one of the N stages of the second module M110. For example, in this digital embodiment, the area required for the gain modulation circuit M1 can be between 1.5 and 2 cm². 2 .

[0126] Advantageously, in digital implementations, it is possible to create 2 A N+1 different payoff ranks, in other words 2 A N+1 values ​​of gain modulation amplitude.

[0127] In the example of Figure 13, each of the binary signals Bi composing the binary word B is injected, during operation, into a control gate of a transistor Si of the second module M110. The transition to the high state of the Bi signals causes the transistors Si to switch to the conducting state and the corresponding resistance Rsi to be connected in parallel with the resistance RsO.

[0128] Unlike analog implementations, the parallel connection of the branches formed by the transistors Si and the resistors Rsi is no longer cumulative. Therefore, the modulator gain can change values ​​without passing through intermediate states.

[0129] Figure 14 illustrates the effective input impedance R seen by the main control circuit U1 at its input terminal CS, in the example shown in Figure 13, as a function of the binary word B value and the resistances Rs1 to Rs4, for an AC input voltage ranging from 85 VAC to 265 VAC. The effective input impedance R is lower than the resistance RsO, improving the noise immunity of the main control circuit U1. As can be seen in this figure, the gain rank varies from 0 to 16.

[0130] Advantageously, the update of the binary word B performed by the second logic function F2 is synchronized to a PWM_TMAIN control signal from the main control circuit U1, configured to control the main switch TMAIN. The control signal is typically a pulse-width modulation (PWM) signal. This synchronization eliminates the uncertainty in the resistive value seen at the common terminal R due to the switching speed of the transistors Si. approximate, and because the update of the output values ​​of the CPU microcontroller of the first M100 module is sequential.

[0131] Thus, when, for example, the main control circuit U1 operates in peak current mode, the entire period during which the main switch TMAIN is blocked is available to update the gain value without risk to the switching power supply. During this period, the IT current flowing through the main switch TMAIN is zero, and consequently, no voltage develops at the output terminal R of the gain modulation circuit M1, and the value formed by the parallel connection of the resistors Rsi is negligible.

[0132] Advantageously, the full execution time of the first logic function F1, the second logic function F2, and the writing of the binary word B to the output ports of the CPU microcontroller is chosen so as to be less than the minimum time in the blocked state of the main TMAIN switch.

[0133] Figure 15 shows an example of the time profile of the IT current flowing through the main switch TMAIN. In this figure, we can observe the increase in IT current when the main switch TMAIN is conducting, and the drop to zero of this IT current when the main switch TMAIN is blocked (during the Toff Min period). During this Toff Min period, the binary word B can be updated.

[0134] According to an example of the numerical embodiment, for which N equals 4 and the second module M110 is that of the example in Figure 3, the resistances Rsi of the second module M110 can be chosen such that Rs0 <Rs1 <Rs2<Rs3<Rs4. Selon cet exemple, l’ordre de grandeur de RsO est de 10 à 20 ohms. Aussi, par le choix de Rs1 =Rs2 / 2=Rs3 / 4=Rs4 / 8, l’étalement des étages sur la plage de tension d’entrée de la source SOURCE est optimal, par exemple de 100Vac à 240Vac.

[0135] For the general case of digital embodiments, the resistances Rsi can be chosen such that Rs1 = Rsi / i for i between 1 and N.

[0136] One of the advantages of the M1 gain modulation circuit according to the invention lies in its simplicity of construction and its small size.

[0137] Figure 16 shows an example of the compensation of the output power P LOAD received by the load LOAD as a function of the input voltage VSOURCE. The figure shows the sawtooth profile around a constant value of this power P LOAD with the switching power supply 100 according to the invention, compared to the output power profile with a prior art switching power supply.

[0138] Figure 17 shows the influence (right) of integrating the gain modulation circuit M1 into a switched-mode power supply on the current profile ISOURCE from the source SOURCE compared to the current profile without this integration (left). The damping of fluctuations in this current can be observed when the gain modulation circuit M1 is integrated.

[0139] The 100 switching power supply device including the previously described M1 gain modulation circuit can be advantageously used to power a high-power loudspeaker.

[0140] Thus, a second aspect of the invention relates to a loudspeaker 200 incorporating a switched-mode power supply according to the first aspect of the invention. Figure 18 schematically illustrates such a loudspeaker 200 incorporating the switched-mode power supply 100.

[0141] For example, the speaker can be a high-power, amplified speaker.

[0142] In another use, the previously described 100 switching power supply device can be separated from the enclosure it powers and alternatively integrated into an external acoustic amplifier.

[0143] Thus, a third aspect of the invention relates to an acoustic amplification device 300 comprising a switching power supply 100 according to the first aspect of the invention. Figure 19 schematically illustrates such an acoustic amplification device 300 incorporating the switching power supply 100. In one example, the amplification device is external and can power one or more loudspeakers.

[0144] Although described through a number of detailed implementation examples, the proposed process and the equipment for implementing the process include various variants, modifications, and improvements that will be obvious to those skilled in the art, it being understood that these various variants, modifications, and improvements form part of the scope of the invention, as defined by the following claims. Furthermore, different aspects and features described above may be implemented together, separately, or substituted for one another, and all the different combinations and subcombinations of aspects and features form part of the scope of the invention. In addition, some systems and equipment described above may not incorporate all the modules and functions described for the preferred embodiments. Industrial application

[0145] The invention may find application particularly in the field of acoustics, but other fields of application are possible.

[0146] The invention is not limited to the examples of the gain modulation circuit M1, the first module M100 and the second module M110 described above, only by way of example, but it encompasses all the variants that a person skilled in the art may consider within the framework of the protection sought.

Claims

Demands

1. A switching power supply device (100) configured to deliver an output voltage intended to power a load from an input voltage supplied by a source, comprising: - a transformer (TRMAIN) comprising a primary winding and a secondary winding to which the load is connected; - a main switch (TMAIN) connected to the primary winding and configured to switch between an activation state in which a current flows through it and a deactivation state; - a main control circuit (U1) delivering a control signal to the main switch (TMAIN) and configured to apply a gain to the control signal so as to maintain constant output power; - a gain modulation circuit (M1) connected at input to the source and at output to said main control circuit (U1), and configured to generate at output, on the basis of a voltage from the source, a control signal configured to modulate said gain, the gain modulation circuit (M1) comprising a plurality of N stages, said voltage controlling an activation of a set of stages among the plurality of N stages, the set of stages activated determining the corresponding gain modulation amplitude which is applied, in operation, to the gain of the main control circuit (U1).

2. Switching power supply device (100) according to claim 1, characterized in that the gain modulation circuit (M1) is configured to: a. Generate, from the input voltage, a plurality of N' binary signals (Bi) encoding together a binary word (B) of N bits representing a gain rank determining the set of stages, the set of activated stages determining a gain modulation amplitude; and b. Generate the control signal from said gain modulation amplitude.

3. Switching power supply device (100) according to claim 2, characterized in that the value of the binary word (B) is a decreasing function of the input voltage.

4. Switching power supply device (100) according to claim 2 or 3, characterized in that the gain modulation circuit (M1) comprises: a. A first module (M100) configured to receive as input, in operation, said input voltage and generate as output, said plurality of N' binary signals; b. A second module (M110) configured to receive as input, in operation, the plurality of N' binary signals (Bi) and an electrical signal representative of said current (IT) flowing in said main switch (TMAIN), the second module (M110) comprising said plurality of N stages, each of the N stages being voltage controlled by one of the N' binary signals (Bi), the plurality of the N stages joining at a common terminal connected to the main control circuit (U1), so that the control signal is delivered, in operation, by said common terminal.

5. Switching power supply device (100) according to any one of the preceding claims, characterized in that each stage comprises a series association of a transistor (Si) with a resistor (Rsi).

6. Switching power supply device (100) according to claim 4, characterized in that the first module (M100) comprises a microcontroller (CPU), the microcontroller (CPU) comprising: a. an analog-to-digital converter (ADC) configured to receive a rectified voltage representing the voltage across the source terminals; b. a first circuit connected at the output of the analog-to-digital converter, and configured to perform, in operation, a first logic function (F1), so as to deliver at output, a first output voltage as a function of the rectified voltage image of the voltage across the source terminals; c. a second circuit connected at output to the first circuit and configured to perform, in operation, a second logic function (F2), so as to generate the plurality of N' binary signals (Bi).

7. Switching power supply device (100) according to the preceding claim, characterized in that the first logic function (F1) is configured to perform: a. a first action of extracting a maximum voltage value; b. a second action of maintaining said first output voltage at said maximum voltage value; c. a third action of decreasing said first output voltage from said maximum voltage value.

8. Switching power supply device (100) according to claim 6 or 7, characterized in that: - the second circuit comprises N output terminals, - The second logic function (F2) is configured to convert the first output voltage into a plurality of binary values ​​to be applied to the N” output terminals of the second circuit, so that the gain rank is between 1 and 2 N+1 .

9. Switching power supply device (100) according to any one of claims 6 to 8, characterized in that the first module (M100) is, in operation, synchronized with a control signal (PWM_TMAIN) from the main control circuit (U1), the control signal (PWM_TMAIN) being configured to control the main switch (TMAIN).

10. Switching power supply device (100) according to any one of claims 1 to 5, characterized in that the first module (M100) comprises a circuit and a network of N’” switches (Ci), the first circuit being configured to divide, in operation, the value of the input voltage in N”” ranges, so as to generate N first signals each of the first N signals being a function of a corresponding range, each switch (Ci) being configured to switch between a conducting state and a blocking state, and to deliver, in operation, a binary signal from among the plurality of N' binary signals (Bi), each first signal determining, in operation, the switching of a corresponding switch in the network of N’” switches (Ci).

11. Switching power supply device (100) according to claim 10, characterized in that the first circuit comprises a network of resistors (Ri) connected in series.

12. Switching power supply device (100) according to any one of claims 10 or 11, characterized in that the first module (M100) further comprises a comparator network (Ui), each comparator comprising a non-inverting terminal and an inverting terminal, each non-inverting terminal being configured to receive, in operation, a corresponding signal, and each inverting terminal being connected to a common voltage source delivering a voltage (Vref), each on / off signal being configured to control the switching of a corresponding switch in the network of switches (Ci).

13. Switching power supply device (100) according to claim 12, characterized in that: - the first circuit includes intermediate branches, each delivering a corresponding signal, - each comparator is connected to a branch of the corresponding intermediate branches in an ascending order of the corresponding ranges.

14. Acoustic enclosure comprising a switching power supply device according to any one of claims 1 to 13.

15. Acoustic amplification device comprising a switching power supply device according to any one of claims 1 to 13.

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