Semiconductor device

Abstract

Provided is a semiconductor device having a small occupied area. The semiconductor device has a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor has a first semiconductor layer, a first conductive layer, and a second conductive layer. The second transistor has a second semiconductor layer, a third insulating layer, and a third conductive layer. The third insulating layer is positioned on the second semiconductor layer. The third conductive layer has a region overlapping the second semiconductor layer with the third insulating layer interposed therebetween. The first insulating layer is positioned on the third insulating layer and on the third conductive layer. The first conductive layer is positioned on the first insulating layer. The second insulating layer is positioned on the first insulating layer and the first conductive layer. The second insulating layer has an end that contacts the upper surface of the first conductive layer. The second conductive layer is positioned on the second insulating layer.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. Another aspect of the present invention relates to a display device having a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] Semiconductor devices containing transistors are widely used in electronic devices. For example, in display devices, reducing the area occupied by transistors allows for a reduction in pixel size and an increase in resolution. Therefore, there is a demand for miniaturized transistors.

[0005] As devices requiring high-definition display capabilities, for example, devices for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR) are being actively developed.

[0006] As display devices, for example, light-emitting devices having organic EL (Electroluminescence) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using an organic EL element.

[0008] International Publication No. 2016 / 038508

[0009] One aspect of the present invention aims to provide a semiconductor device having a transistor of a fine size. Alternatively, it aims to provide a semiconductor device having a transistor with a short channel length. Alternatively, it aims to provide a semiconductor device having a transistor with a large on-current. Alternatively, it aims to provide a semiconductor device having a transistor with high field-effect mobility. Alternatively, it aims to provide a semiconductor device having a transistor with high saturation. Alternatively, it aims to provide a semiconductor device having a transistor with good electrical characteristics. Alternatively, it aims to provide a semiconductor device that operates at high speed. Alternatively, it aims to provide a semiconductor device with a small footprint. Alternatively, it aims to provide a semiconductor device with low wiring resistance. Alternatively, it aims to provide a semiconductor device or display device with low power consumption. Alternatively, it aims to provide a highly reliable transistor, semiconductor device, or display device. Alternatively, it aims to provide a high-definition display device. Alternatively, it aims to provide a highly productive method for manufacturing a semiconductor device or display device. Alternatively, it aims to provide a novel transistor, semiconductor device, display device, or method for manufacturing the same.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0011] One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor has a first semiconductor layer, a first conductive layer, and a second conductive layer. The second transistor has a second semiconductor layer, a third insulating layer, and a third conductive layer. The third insulating layer is located on the second semiconductor layer. The third conductive layer has a region that overlaps with the second semiconductor layer via the third insulating layer. The first insulating layer is located on the third insulating layer and the third conductive layer. The first conductive layer is located on the first insulating layer. The second insulating layer is located on the first insulating layer and the first conductive layer. The second insulating layer has an end that is in contact with the upper surface of the first conductive layer. The second conductive layer is located on the second insulating layer. The first semiconductor layer has an end in contact with the upper surface of the first conductive layer, an end in contact with the side surface of the second insulating layer, an end in contact with the side surface of the second conductive layer, and an end in contact with the upper surface of the second conductive layer.

[0012] In the semiconductor device described above, it is preferable that the first insulating layer, the second insulating layer, and the third insulating layer have openings that reach the second semiconductor layer. It is preferable that the second conductive layer has a region in contact with the second semiconductor layer at the opening.

[0013] In the semiconductor device described above, it is preferable that the first insulating layer and the third insulating layer have openings that reach the second semiconductor layer. It is preferable that the first conductive layer has a region in contact with the second semiconductor layer at the opening.

[0014] In the semiconductor device described above, it is preferable that the first insulating layer and the second insulating layer have openings that reach the third conductive layer. It is preferable that the second conductive layer has a region in contact with the third conductive layer at the opening.

[0015] In the semiconductor device described above, it is preferable that the first insulating layer has an opening that reaches the third conductive layer. It is preferable that the first conductive layer has a region in contact with the third conductive layer at the opening.

[0016] In the semiconductor device described above, it is preferable that the first semiconductor layer has a region that overlaps with the second semiconductor layer.

[0017] In the semiconductor device described above, the first transistor preferably has a fourth insulating layer and a fourth conductive layer. The fourth insulating layer is preferably located on the first semiconductor layer. The fourth conductive layer preferably has a region facing the side surface of the second insulating layer via the fourth insulating layer and the first semiconductor layer.

[0018] In the semiconductor device described above, it is preferable that the first semiconductor layer and the second semiconductor layer each contain indium and oxygen.

[0019] In the semiconductor device described above, it is preferable that the first semiconductor layer has the same material as the second semiconductor layer.

[0020] In the semiconductor device described above, it is preferable that the first semiconductor layer is made of a different material from the second semiconductor layer.

[0021] In the semiconductor device described above, the first semiconductor layer preferably contains indium oxide. The indium content in the first semiconductor layer is preferably higher than the indium content in the second semiconductor layer.

[0022] In the semiconductor device described above, the second semiconductor layer preferably contains indium oxide. The indium content in the second semiconductor layer is preferably higher than the indium content in the first semiconductor layer.

[0023] In the semiconductor device described above, it is preferable that the first semiconductor layer and the second semiconductor layer each contain indium oxide.

[0024] In the semiconductor device described above, the first semiconductor layer preferably contains indium and oxygen. The second semiconductor layer preferably contains silicon.

[0025] One aspect of the present invention can provide a semiconductor device having a transistor of a very small size. Or, a semiconductor device having a transistor with a short channel length. Or, a semiconductor device having a transistor with a large on-current. Or, a semiconductor device having a transistor with high field-effect mobility. Or, a semiconductor device having a transistor with high saturation. Or, a semiconductor device having a transistor with good electrical characteristics. Or, a semiconductor device that operates at high speed. Or, a semiconductor device with a small footprint. Or, a semiconductor device with low wiring resistance. Or, a semiconductor device or display device with low power consumption. Or, a highly reliable transistor, semiconductor device, or display device. Or, a high-definition display device. Or, a highly productive method for manufacturing a semiconductor device or display device. Or, a novel transistor, semiconductor device, display device, or method for manufacturing the same.

[0026] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0027] Figure 1A is a top view showing an example of a semiconductor device. Figures 1B and 1C are equivalent circuit diagrams of the semiconductor device. Figure 1D is a cross-sectional view showing an example of a semiconductor device. Figures 2A and 2B are cross-sectional views showing an example of a semiconductor device. Figures 3A and 3B are perspective views showing an example of a semiconductor device. Figures 4A, 4B, and 4C are cross-sectional views showing an example of a semiconductor device. Figure 5A is a cross-sectional view showing an example of a semiconductor device. Figure 5B is a top view showing an example of a semiconductor device. Figure 6A is a top view showing an example of a semiconductor device. Figure 6B is a cross-sectional view showing an example of a semiconductor device. Figures 7A and 7B are cross-sectional views showing an example of a semiconductor device. Figures 8A and 8B are perspective views showing an example of a semiconductor device. Figure 9A is a top view showing an example of a semiconductor device. Figure 9B is a perspective view showing an example of a semiconductor device. Figures 10A, 10B, and 10C are cross-sectional views showing an example of a semiconductor device. Figures 11A, 11B, and 11C are cross-sectional views showing an example of a semiconductor device. Figures 12A and 12B are cross-sectional views showing an example of a semiconductor device. Figure 13A is a top view showing an example of a semiconductor device. Figures 13B, 13C, 13D, 13E, 13F, and 13G are equivalent circuit diagrams of the semiconductor device. Figures 14A and 14B are cross-sectional views showing an example of a semiconductor device. Figure 15A is a top view showing an example of a semiconductor device. Figures 15B and 15C are equivalent circuit diagrams of the semiconductor device. Figure 15D is a cross-sectional view showing an example of a semiconductor device. Figure 16A is a top view showing an example of a semiconductor device. Figures 16B and 16C are equivalent circuit diagrams of the semiconductor device. Figures 17A and 17B are cross-sectional views showing an example of a semiconductor device. Figure 18A is a top view showing an example of a semiconductor device. Figures 18B and 18C are equivalent circuit diagrams of the semiconductor device. Figure 19 is a cross-sectional view showing an example of a semiconductor device. Figures 20A, 20B, 20C, 20D, 20E, 20F, and 20G are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 21A, 21B, 21C, and 21D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 22A, 22B, 22C, and 22D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 23A, 23B, and 23C are cross-sectional views showing an example of a semiconductor device manufacturing method.Figures 24A, 24B, and 24C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 25A is a perspective view showing an example of a display device. Figure 25B is a block diagram showing an example of a display device. Figures 26A, 26B, 26C, 26D, 26E, 26F, 26G, and 26H are diagrams showing an example of a pixel. Figures 27A, 27B, 27C, 27D, 27E, and 27F are circuit diagrams of a pixel circuit. Figures 28A, 28B, 28C, and 28D are circuit diagrams of a pixel circuit. Figures 29A and 29B are circuit diagrams of a pixel circuit. Figures 30A and 30B are circuit diagrams of a pixel circuit. Figure 31 is a circuit diagram of a pixel circuit. Figures 32A, 32B, and 32C are top views showing an example of a pixel layout. Figures 33A and 33B are top views showing an example of a pixel layout. Figure 34 is a cross-sectional view showing an example of a display device. Figure 35 is a cross-sectional view showing an example of a display device. Figures 36A and 36B are top views showing an example of a pixel layout. Figures 37A and 37B are top views showing an example of a pixel layout. Figure 38 is a top view showing an example of a pixel layout. Figures 39A and 39B are cross-sectional views showing an example of a display device. Figure 40 is a cross-sectional view showing an example of a display device. Figures 41A and 41B are cross-sectional views showing an example of a display device. Figure 42 is a cross-sectional view showing an example of a display device. Figures 43A, 43B, and 43C are cross-sectional views showing an example of a display device. Figures 44A and 44B are cross-sectional views showing an example of a display device. Figures 45A, 45B, 45C, and 45D are diagrams showing an example of an electronic device. Figures 46A, 46B, 46C, 46D, 46E, and 46F are diagrams showing an example of an electronic device. Figures 47A, 47B, 47C, 47D, 47E, 47F, and 47G show examples of electronic devices.

[0028] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0029] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0030] The position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0031] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of components and do not limit the number of components or the order of components (e.g., process order or stacking order). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, an ordinal number may be omitted in the claims.

[0032] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0033] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0034] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, depending on the situation.

[0035] The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" may be used interchangeably. Furthermore, the names of the gate and back gate of a transistor can be appropriately rephrased as gate electrode and back gate electrode, etc., depending on the context.

[0036] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0037] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0038] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0039] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0040] In this specification, unless otherwise specified, on-current refers to the drain current (also called the conduction state) when the transistor is in the on state. Unless otherwise specified, the on state refers to the state in an n-channel transistor where the voltage between the gate and source (gate voltage, also called Vg or Vgs) is equal to or greater than the threshold voltage (also called Vth), and in a p-channel transistor where it is less than or equal to the threshold voltage.

[0041] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conductive state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage between the gate and source is lower than the threshold voltage, and in a p-channel transistor where it is higher than the threshold voltage.

[0042] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0043] In this specification, the top surface shape of a component refers to the contour shape of the component when viewed from above (also called a plan view). Furthermore, a top view refers to viewing from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0044] In this specification, "matching or roughly matching top shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in this case, it may also be said that the "matching or roughly matching top shapes" apply. Furthermore, when the top shapes match or roughly match, it can also be said that the "edges match or roughly match," or "the edges are aligned or roughly aligned."

[0045] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes called the taper angle.

[0046] In this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, high-resolution metal mask) may be referred to as MM (metal mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (metal maskless) structured devices.

[0047] In this specification, a structure in which different light-emitting layers are created using light-emitting elements (also called light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure.

[0048] In this specification, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole blocking layer or electron blocking layer may be called a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable. Furthermore, a single layer may combine the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0049] In this specification, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Examples of layers in the EL layer (also called functional layers) include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer). In this specification, a photodetector (also called a photodetector device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the pair of electrodes may be referred to as a pixel electrode and the other as a common electrode.

[0050] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step).

[0051] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0052] In this specification, the sacrificial layer (which may also be called the mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0053] In this specification, a display panel, which is one form of a display device, has the function of displaying (outputting) images or the like on its display surface. Therefore, a display panel is one form of an output device.

[0054] In this specification, a display panel on which a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) is attached, or on which an IC (Integrated Circuit) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method, may be referred to as a display panel module, display module, or simply a display panel.

[0055] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, regardless of whether it is elastic or able to restore to its original shape.

[0056] For example, flexible electronic devices, flexible display devices (also called flexible displays, etc.), flexible batteries (also called flexible batteries, etc.), and flexible substrates (also called flexible substrates, etc.) can each be deformed in response to external forces. Flexible electronic devices, flexible display devices, flexible batteries, and flexible substrates can each be used fixed in a deformed state, used after repeated deformation, or used in an undeformed state. The phrase "deforms in response to external forces" above means that it can be deformed by the average adult's hand without requiring excessive force. Flexibleness can be evaluated using testing machines capable of stress-strain measurement (tensile testing machines, compression testing machines, etc.). In stress-strain measurement, the flexibility of an object can be quantified by applying an external force to the object and measuring the strain of the object caused by the resulting stress.

[0057] In this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may also have parts that are not flexible (which can be called rigid parts).

[0058] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with higher flexibility.

[0059] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to Figures 1A to 19.

[0060] One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a first insulating layer, and a second insulating layer.

[0061] The first transistor has a first semiconductor layer, a first conductive layer, and a second conductive layer. The second transistor has a second semiconductor layer, a third insulating layer, and a third conductive layer. The third insulating layer is located on the second semiconductor layer. The third conductive layer has a region that overlaps with the second semiconductor layer via the third insulating layer. The first insulating layer is located on the third insulating layer and the third conductive layer. The first conductive layer is located on the first insulating layer. The second insulating layer is located on the first insulating layer and the first conductive layer. The second insulating layer has an end that contacts the upper surface of the first conductive layer. The second conductive layer is located on the second insulating layer. The first semiconductor layer has an end that contacts the upper surface of the first conductive layer, an end that contacts the side surface of the second insulating layer, an end that contacts the side surface of the second conductive layer, and an end that contacts the upper surface of the second conductive layer.

[0062] The first transistor preferably has a fourth insulating layer and a fourth conductive layer. The fourth insulating layer is preferably located on the first semiconductor layer. The fourth conductive layer preferably has a region facing the side surface of the second insulating layer via the fourth insulating layer and the first semiconductor layer.

[0063] In the first transistor, the fourth insulating layer functions as a gate insulating layer, the fourth conductive layer functions as a gate electrode, and the first and second conductive layers function as source and drain electrodes. The channel formation region of the first transistor is located in the region in contact with the side surface of the second insulating layer. Furthermore, the channel length of the first transistor can be controlled by the thickness of the second insulating layer sandwiched between the first and second conductive layers. In other words, the channel length of the first transistor is not affected by the exposure performance of the exposure apparatus used for fabrication. Therefore, the channel length of the first transistor can be made smaller than the minimum dimension that the exposure apparatus can expose (hereinafter also referred to as the minimum dimension). By shortening the channel length, a transistor with a large on-current can be made. In addition, since the source electrode, semiconductor layer, and drain electrode of the first transistor can be stacked, the occupied area of ​​the first transistor can be reduced. Therefore, the occupied area of ​​the semiconductor device having the first transistor can be significantly reduced.

[0064] The second transistor has a different structure from the first transistor. In the second transistor, the third insulating layer functions as a gate insulating layer, and the third conductive layer functions as a gate electrode. In the second semiconductor layer, the region that overlaps with the third conductive layer via the third insulating layer functions as the channel formation region of the second transistor. The channel length of the second transistor is influenced by the performance of the exposure apparatus used for fabrication and is greater than or equal to the minimum dimensions of the exposure apparatus. Therefore, the channel length of the second transistor can be made longer than that of the first transistor. By making the channel length longer, a transistor with high saturation can be made.

[0065] In this specification, the term "high saturation" may be used to describe a transistor where the change in current in the saturation region of the Id-Vd characteristic is small.

[0066] For example, by applying the first transistor to a transistor requiring a large on-current and the second transistor to a transistor requiring high saturation, a high-performance semiconductor device can be created. Furthermore, by having the first transistor have an overlapping region with the second transistor, the occupied area of ​​the semiconductor device can be further reduced.

[0067] <Configuration Example 1> [Configuration Example 1-1] A semiconductor device according to one aspect of the present invention will be described. A top view (also called a plan view) of the semiconductor device 10 is shown in Figure 1A. Equivalent circuit diagrams of the semiconductor device 10 are shown in Figures 1B and 1C. A cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 1A is shown in Figure 1D, a cross-sectional view of the cross-section along the dashed-dotted line B1-B2 is shown in Figure 2A, and a cross-sectional view of the cross-section along the dashed-dotted line B3-B4 is shown in Figure 2B. Note that in Figure 1A, some of the components of the semiconductor device 10 (gate insulating layer, etc.) are omitted. In the top view of the semiconductor device, some of the components will be omitted in the following drawings as in Figure 1A.

[0068] The semiconductor device 10 includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 214. The semiconductor device 10 is provided on an insulating surface. Figure 1D and the like show an example configuration in which the semiconductor device 10 is provided on a substrate 102 having an insulating surface. Alternatively, an insulating layer can be provided on the substrate 102, and the semiconductor device 10 can be provided on this insulating layer.

[0069] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of the source electrode and the drain electrode, and the conductive layer 112b functions as the other. Of the semiconductor layer 108, the region in contact with the source electrode functions as the source region, and the region in contact with the drain electrode functions as the drain region. Furthermore, of the semiconductor layer 108, the region between the source region and the drain region that overlaps with the gate electrode via the gate insulating layer functions as a channel forming region.

[0070] The transistor 200 has a conductive layer 204, an insulating layer 206, a semiconductor layer 208, a conductive layer 212a, and a conductive layer 112b. In the transistor 200, the conductive layer 204 functions as a gate electrode, and the insulating layer 206 functions as a gate insulating layer. The conductive layer 212a functions as one of the source electrode and the drain electrode, and the conductive layer 112b functions as the other. Of the semiconductor layer 208, the region that overlaps with the gate electrode via the gate insulating layer functions as a channel formation region. The semiconductor layer 208 also has a pair of regions 208P that sandwich the channel formation region. One of the pair of regions 208P functions as the source region, and the other functions as the drain region. The structure of the transistor 200 is different from the structure of the transistor 100.

[0071] The conductive layer 112b functions as the other source electrode and drain electrode of transistor 100, and also functions as the other source electrode and drain electrode of transistor 200. In other words, the other source electrode and drain electrode of transistor 100 are connected to the other source electrode and drain electrode of transistor 200. The conductive layer 112b is shared by transistor 100 and transistor 200. As a result, there is no need to provide a separate conductive layer to connect the other source electrode and drain electrode of transistor 100 to the other source electrode and drain electrode of transistor 200, thus reducing the occupied area of ​​the semiconductor device. Therefore, a compact semiconductor device can be made.

[0072] As shown in Figure 1B, transistor 100 can be an n-channel type and transistor 200 can be a p-channel type. Alternatively, as shown in Figure 1C, transistors 100 and 200 can each be n-channel types. Although transistor 100 is shown as an n-channel type in Figures 1B and 1C, the present invention is not limited to this. Transistor 100 can also be a p-channel type. For example, by making one of transistors 100 and 200 an n-channel type and the other a p-channel type, a CMOS (Complementary Metal Oxide Semiconductor) circuit can be realized. By using a CMOS circuit, the degree of design freedom is increased and the occupied area of ​​the semiconductor device can be reduced. Note that in Figures 1B and 1C, etc., an example configuration is shown in which the source electrode and drain electrode of transistor 100 are connected to the source electrode and drain electrode of transistor 200, but the present invention is not limited to this. The connection relationship between transistor 100 and transistor 200 is not particularly limited.

[0073] The configuration of transistor 100 will be explained in detail.

[0074] Figure 3A shows a perspective view of transistor 100. Figure 3B shows a perspective view of Figure 3A with the conductive layer 104 and insulating layer 106 omitted. In Figures 3A and 3B, some of the insulating layers are made transparent, and the outlines are shown with dashed lines. In subsequent drawings, as with Figure 3A, some of the insulating layers are made transparent, and the outlines are shown with dashed lines. Figure 4A also shows an enlarged view of transistor 100 as shown in Figure 1D.

[0075] A conductive layer 112a is provided on an insulating layer 214, an insulating layer 110 is provided on the conductive layer 112a, and a conductive layer 112b is provided on the insulating layer 110. The conductive layer 112a has a region in contact with the insulating layer 214. The insulating layer 110 has a region in contact with the conductive layers 112a and 112b. The insulating layer 110 also has a region sandwiched between the conductive layers 112a and 112b. The conductive layer 112a has a region that overlaps with the conductive layer 112b via the insulating layer 110.

[0076] As shown in Figure 4A, the conductive layer 112a has a region where the insulating layer 110 is provided and a region where the insulating layer 110 is not provided. The side surface 77 of the insulating layer 110 has a region that is in contact with the upper surface of the conductive layer 112a. The insulating layer 110 also has an end portion 31 that is in contact with the upper surface of the conductive layer 112a. The region of the side surface 77 that is in contact with the upper surface of the conductive layer 112a corresponds to the end portion 31. It can also be said that the lower end of the side surface 77 in the region of the side surface 77 that is in contact with the conductive layer 112a is the end portion 31.

[0077] A semiconductor layer 108 is provided on the conductive layer 112a, the conductive layer 112b, and the insulating layer 110. The semiconductor layer 108 has regions that are in contact with the upper and side surfaces of the conductive layer 112b, the side surface of the insulating layer 110 (in this case, side surface 77), and the upper surface of the conductive layer 112a. The semiconductor layer 108 is connected to the conductive layer 112a and connected to the conductive layer 112b. The semiconductor layer 108 has a shape that conforms to the shape of the upper and side surfaces of the conductive layer 112b, side surface 77, and the upper surface of the conductive layer 112a. The semiconductor layer 108 is provided spanning the region on the conductive layer 112a where the insulating layer 110 is provided and the region on the conductive layer 112a where the insulating layer 110 is not provided.

[0078] The semiconductor layer 108 has a first region in contact with the conductive layer 112a, a second region in contact with the side surface 77, and a third region in contact with the conductive layer 112b. The first region is in contact with the second region, and the second region is in contact with the third region. It can also be said that the first region is continuous with the second region, and the second region is continuous with the third region. In the transistor 100, the first region functions as either the source region or the drain region, and the third region functions as the other of the source region and the drain region. The channel formation region is located in the second region.

[0079] Figure 4B shows a cross-sectional view of the cross-section along the dashed-dotted line C1-C2 shown in Figure 4A, and Figure 4C shows a cross-sectional view of the cross-section along the dashed-dotted line D1-D2. Figure 4B is a cross-sectional view of transistor 100 including the channel formation region, and Figure 4B is a cross-sectional view of transistor 100 including the source region and the other drain region.

[0080] As shown in Figures 2A, 4A to 4C, the semiconductor layer 108 has an end 33 that contacts the upper surface of the conductive layer 112a, an end 37 that contacts the side surface 77, an end 39 that contacts the side surface of the conductive layer 112b, and an end 35 that contacts the upper surface of the conductive layer 112b. End 33 is the end of the semiconductor layer 108 on the surface that contacts the upper surface of the conductive layer 112a. End 37 is the end of the semiconductor layer 108 on the surface that contacts the side surface 77. End 39 is the end of the semiconductor layer 108 on the surface that contacts the side surface of the conductive layer 112b. End 35 is the end of the semiconductor layer 108 on the surface that contacts the upper surface of the conductive layer 112b.

[0081] The insulating layer 106, which functions as a gate insulating layer for transistor 100, is provided so as to cover the semiconductor layer 108. The insulating layer 106 has a region that is in contact with the upper surface and side surfaces of the semiconductor layer 108, as well as the side surface 77. The insulating layer 106 also has a region that is in contact with the upper surface and side surfaces of the conductive layer 112a, the upper surface and side surfaces of the conductive layer 112b, the upper surface and side surfaces of the conductive layer 212a, and the upper surface of the insulating layer 214.

[0082] As shown in Figure 4B, the insulating layer 110 has a region 70 on its side surface 77 where the semiconductor layer 108 is provided, and a region 72 where the semiconductor layer 108 is not provided. In region 70, the semiconductor layer 108 is in contact with the insulating layer 110. The insulating layer 106 has a region facing the side surface 77 via the semiconductor layer 108. On the other hand, in region 72, the insulating layer 106 is in contact with the side surface 77 of the insulating layer 110.

[0083] The conductive layer 104, which functions as the gate electrode of transistor 100, is provided on the insulating layer 106 and has a region in contact with the upper surface of the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106. The conductive layer 104 also has a region that faces the side surface 77 via the insulating layer 106 and the semiconductor layer 108. The conductive layer 104 is provided so as to cover at least the region in contact with the side surface 77 of the semiconductor layer 108. As a result, this region can function as the channel formation region of transistor 100.

[0084] The conductive layer 104 can also be configured to cover the entire semiconductor layer 108. By covering the semiconductor layer 108 with the conductive layer 104, damage to the semiconductor layer 108 when a layer is formed on the transistor 100 can be suppressed.

[0085] A step is formed by the conductive layer 112a and the insulating layer 110 and conductive layer 112b, and a semiconductor layer 108, an insulating layer 106, and a conductive layer 104 are provided along this step. In the transistor 100, the source electrode and the drain electrode are located at different heights relative to the surface of the substrate 102, and the drain current flows perpendicular to the surface of the substrate 102, or approximately perpendicular. In the transistor 100, it can also be said that the drain current flows in the vertical direction. Therefore, the transistor 100, which is one aspect of the present invention, can be called a vertical channel transistor, a vertical transistor, or a VFET (Vertical Field Effect Transistor). Furthermore, in a VFET, the conductive layer 112a can be called the lower electrode, and the conductive layer 112b can be called the upper electrode.

[0086] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, transistors with a channel length shorter than the minimum exposure dimension of the exposure apparatus used to manufacture the transistors can be manufactured with high precision. Furthermore, variations in characteristics between multiple transistors are reduced. As a result, the operation of the semiconductor device 10 becomes more stable and its reliability is improved. In addition, when variations in transistor characteristics are reduced, the degree of freedom in circuit design increases, and the operating voltage of the semiconductor device can be lowered. As a result, the power consumption of the semiconductor device can be reduced.

[0087] Because VFETs allow the source electrode, semiconductor layer, and drain electrode to be stacked, they can significantly reduce the occupied area compared to so-called planar transistors, which have semiconductor layers arranged in a planar configuration.

[0088] Conductive layers 112a, 112b, and 104 can each function as wiring. The transistor 100 can be placed in the region where these wirings overlap. In other words, in a circuit having the transistor 100 and wiring, the area occupied by the transistor 100 and wiring can be reduced. Therefore, a semiconductor device with a small occupied area can be made.

[0089] Next, I will explain the configuration of transistor 200 in detail.

[0090] As shown in Figures 1D and 2B, a semiconductor layer 208 is provided on the substrate 102, an insulating layer 206 is provided on the semiconductor layer 208, and a conductive layer 204 is provided on the insulating layer 206. The conductive layer 204 has a region that overlaps with the semiconductor layer 208 via the insulating layer 206.

[0091] An insulating layer 214 is provided on the conductive layer 204 and the insulating layer 206, and a transistor 100 and an insulating layer 110 are provided on the insulating layer 214. The insulating layer 206, insulating layer 214, and insulating layer 110 have openings 247a and 247b that reach region 208P. A conductive layer 212a is provided so as to cover opening 247a. The conductive layer 212a is in contact with region 208P at opening 247a and is connected to region 208P. A conductive layer 112b is provided so as to cover opening 247b. The conductive layer 112b is in contact with region 208P at opening 247b and is connected to region 208P.

[0092] Transistor 200 is a planar transistor in which semiconductor layers 208 are arranged in a planar manner. Furthermore, transistor 200 is a so-called top-gate transistor, having a gate electrode above the semiconductor layer 208. By supplying impurities to the semiconductor layer 208 using the conductive layer 204, which functions as the gate electrode, as a mask, a self-aligned region 208P, which functions as the source region and drain region, can be formed. Transistor 200 can be described as a TGSA (Top Gate Self-Aligned) type transistor.

[0093] The channel length of transistor 200 can be controlled by the length of the conductive layer 204. Therefore, the channel length of transistor 200 will be greater than or equal to the minimum exposure dimension of the exposure apparatus used to fabricate the transistor. In other words, the channel length of transistor 200 can be made longer than that of transistor 100. By making the channel length longer, a transistor with high saturation can be made.

[0094] A transistor 100 with a channel length shorter than the minimum exposure dimension of the exposure apparatus and a transistor 200 with a longer channel length can be formed on the same substrate by sharing some of the manufacturing processes. For example, by applying transistor 100 to a transistor that requires a large on-current and transistor 200 to a transistor that requires high saturation, a high-performance semiconductor device can be created. For example, by applying a semiconductor device according to one aspect of the present invention to a display device, a high-performance display device can be created.

[0095] By having a transistor 100 with a small footprint, a semiconductor device with a small footprint can be made. For example, when a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the footprint of the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the footprint of the drive circuit can be reduced, resulting in a narrow-bezel display device.

[0096] In one embodiment of the present invention, the surface on which the VFET transistor 100 is provided is different from the surface on which the planar transistor 200 is provided. Furthermore, the VFET can be provided in a region that overlaps with the planar transistor. For example, it is preferable that the semiconductor layer 108 has a region that overlaps with the semiconductor layer 208. This makes it possible to suppress an increase in the occupied area of ​​the semiconductor device even when a planar transistor with a long channel length is provided. In addition, the channel length of the planar transistor can be increased without increasing the occupied area of ​​the semiconductor device. This makes it possible to create a transistor with high saturation even without providing a back gate electrode. By not providing a back gate electrode, the manufacturing process can be simplified, the productivity of the semiconductor device can be increased, and manufacturing costs can be reduced.

[0097] Here, we will use the TGSA type transistor as an example of a planar transistor, but the configuration of a planar transistor is not limited to this. For example, a Top Gate Top Contact (TGTC) type transistor, a Top Gate Bottom Contact (TGBC) type transistor, a Bottom Gate Top Contact (BGTC) type transistor, or a Bottom Gate Bottom Contact (BGBC) type transistor can be used as a planar transistor.

[0098] The surface on which the semiconductor layer 108 is provided is different from the surface on which the semiconductor layer 208 is provided. Furthermore, the semiconductor layer 108 and the semiconductor layer 208 can be formed using different processes. Therefore, different materials can be used for the semiconductor layer 108 and the semiconductor layer 208. This broadens the range of material selection for the semiconductor layer 108 and the semiconductor layer 208.

[0099] In this specification, "different materials" means materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0100] Here, the electrical characteristics and reliability of the transistor differ depending on the material used for the semiconductor layer. Depending on the required electrical characteristics and reliability for transistors 100 and 200, different materials can be used for semiconductor layer 108 and semiconductor layer 208. This makes it possible to create a semiconductor device that achieves both good electrical characteristics and high reliability.

[0101] Alternatively, the same material can be used for both semiconductor layer 108 and semiconductor layer 208. This allows for the use of the same equipment for depositing semiconductor layer 108 and semiconductor layer 208, thereby lowering the manufacturing cost of semiconductor devices.

[0102] The semiconductor material used for semiconductor layer 108 and semiconductor layer 208 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). These semiconductor materials may contain impurities as dopants.

[0103] The crystallinity of the semiconductor material used in semiconductor layer 108 and semiconductor layer 208 is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0104] Semiconductor layer 108 and semiconductor layer 208 can each be made of, for example, silicon. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). Transistors using amorphous silicon for the channel formation region can be fabricated at low cost on large glass substrates. Transistors using polycrystalline silicon for the channel formation region have high field-effect mobility and can operate at high speeds. Transistors using microcrystalline silicon for the channel formation region have higher field-effect mobility than transistors using amorphous silicon and can operate at high speeds. Note that transistors using silicon for the semiconductor layer are sometimes referred to as Si transistors, and transistors using LTPS for the semiconductor layer are sometimes referred to as LTPS transistors.

[0105] The semiconductor layer 108 and the semiconductor layer 208 can each be made of a metal oxide exhibiting semiconductor properties (hereinafter also referred to as an oxide semiconductor). Transistors using oxide semiconductors (hereinafter also referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have a remarkably low off-current and can retain the charge stored in a capacitor connected in series with the transistor for a long period of time. In addition, the power consumption of semiconductor devices can be reduced by applying OS transistors. When an oxide semiconductor is used for a semiconductor layer, the semiconductor layer can be called an oxide semiconductor layer or a metal oxide layer.

[0106] Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. It is preferable to use an oxide containing indium as the metal oxide. It is even more preferable that the metal oxide has a high indium content. By using a metal oxide with a high indium content in the semiconductor layer of a transistor, a transistor with a large on-current can be made. Furthermore, because transistors using a metal oxide with a high indium content in the semiconductor layer have high field-effect mobility, a large on-current can be obtained even with a small channel width. Therefore, the occupied area of ​​the transistor can be reduced, and thus the occupied area of ​​the semiconductor device can be reduced. For example, indium oxide can be suitably used as the metal oxide.

[0107] In this specification, the ratio of the number of indium atoms to the sum of the total number of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements.

[0108] The metal oxide preferably contains at least indium. Furthermore, the metal oxide preferably contains either or both indium and zinc. Additionally, the metal oxide preferably contains one or more elements selected from indium, element M, and zinc. Element M is a metallic or metalloid element with a high bond energy to oxygen; for example, a metallic or metalloid element with a higher bond energy to oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have high bonding energy with oxygen and their ionic radii are similar to those of indium or zinc. Furthermore, tin is more preferred because its tetravalent state can increase carrier mobility. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification may include metalloid elements.

[0109] The semiconductor layer 108 and the semiconductor layer 208 are, for example, indium oxide, indium zinc oxide (In-Zn oxide, also known as IZO®), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), and aluminum zinc oxide. Indium zinc oxide (Al-Zn oxide, also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc., can be used. Alternatively, silicon-containing indium tin oxide (In-Sn-Si oxide, also written as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0110] Furthermore, the metal oxide can be composed of one or more metal elements with high periodic numbers in the periodic table, either in place of indium or in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including metal elements with high periodic numbers, the field-effect mobility of the transistor can be increased. Examples of metal elements with high periodic numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, these metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0111] Metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can increase carrier concentration or reduce the band gap, potentially improving the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0112] By increasing the content of element M in the metal oxide, a metal oxide with a large band gap can be obtained. Furthermore, oxygen vacancies (V) can be added to the metal oxide. Ｏ By suppressing the formation of oxygen deficiency (V), ＯThis suppresses carrier generation caused by ), thereby preventing a shift in the transistor's threshold voltage. As a result, the drain current (hereinafter also referred to as the cutoff current) that flows when the gate voltage (Vg) is 0V can be reduced, making it possible to create a normally-off transistor. Furthermore, it is possible to create a transistor with a small off-current. In addition, fluctuations in the transistor's electrical characteristics are suppressed, improving reliability. If element M contains multiple types of elements, the sum of the ratios of the number of atoms of element M to the sum of the number of atoms of all contained metal elements can be used as the content of element M.

[0113] By increasing the zinc content in a metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities within the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and its reliability can be improved.

[0114] As mentioned above, different materials can be used for semiconductor layer 108 and semiconductor layer 208. For example, a metal oxide (e.g., indium oxide) can be used for semiconductor layer 108, and silicon (e.g., LTPS) can be used for semiconductor layer 208. In other words, transistor 100 can be an OS transistor and transistor 200 can be a Si transistor. Alternatively, transistor 100 can be an n-channel OS transistor and the other can be a p-channel Si transistor. By using n-channel and p-channel transistors, a CMOS circuit can be realized. This increases the degree of design freedom and reduces the footprint of the semiconductor device.

[0115] Metal oxides with different compositions can be used in semiconductor layer 108 and semiconductor layer 208. For example, it is preferable that the indium content in semiconductor layer 108 is higher than the indium content in semiconductor layer 208. This allows for a larger on-current of transistor 100 and a higher saturation of transistor 200. It is also preferable that the element M content in semiconductor layer 208 is higher than the element M content in semiconductor layer 108. This allows for a higher reliability of transistor 200. Typically, indium oxide can be used in semiconductor layer 108, and indium gallium zinc oxide (In-Ga-Zn oxide), indium tin zinc oxide (In-Sn-Zn oxide), or indium gallium oxide (In-Ga oxide) can be used in semiconductor layer 208.

[0116] Furthermore, the indium content in semiconductor layer 208 can be made higher than the indium content in semiconductor layer 108. This allows for a larger on-current of transistor 200. Alternatively, a larger on-current can be obtained even with a smaller channel width, thus reducing the occupied area of ​​transistor 200. In addition, the element M content in semiconductor layer 108 can be made higher than the element M content in semiconductor layer 108. For example, indium gallium zinc oxide (In-Ga-Zn oxide) or indium tin zinc oxide (In-Sn-Zn oxide) can be used for semiconductor layer 108, and indium oxide can be used for semiconductor layer 208.

[0117] Alternatively, the same material can be used for both semiconductor layer 108 and semiconductor layer 208. For example, indium oxide can be used for both semiconductor layer 108 and semiconductor layer 208. Indium gallium zinc oxide (In-Ga-Zn oxide) or indium tin zinc oxide (In-Sn-Zn oxide) with the same or substantially the same composition can be used for both semiconductor layer 108 and semiconductor layer 208.

[0118] In the following explanation, we may use a configuration in which a metal oxide is used for semiconductor layer 108 and a metal oxide or silicon is used for semiconductor layer 208 as an example.

[0119] I will now explain area 208P.

[0120] Region 208P contains impurities. By supplying impurities to the semiconductor layer 208, a region 208P with low electrical resistance can be formed. The concentration of impurities in region 208P is higher than the concentration of impurities in the channel formation region.

[0121] When using metal oxides in semiconductor layers, the elements contained in the impurities (hereinafter also referred to as the first element) can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon as the first element. Plasma ion doping or ion implantation can be suitably used to supply the impurities. These methods allow for highly precise control of the concentration profile in the depth direction by the ion acceleration voltage and dose amount. Productivity can be increased by using plasma ion doping. Furthermore, the purity of the supplied impurities can be increased by using ion implantation with mass separation.

[0122] When an element that readily bonds with oxygen is used as the first element, the first element removes oxygen from the semiconductor layer 208 and exists in a state bonded with oxygen. In addition, oxygen vacancies (V) exist in the semiconductor layer 208. Ｏ). When an element that becomes stable by bonding with oxygen is used as the first element, the first element in the semiconductor layer 208 exists stably in an oxidized state. Therefore, it is difficult to desorb due to heat applied during the manufacturing process of the semiconductor device, and the electrical resistance of the region 208P can be kept low. From this, it is preferable to use, as the first element, an element whose oxide can exist as a solid at least at the temperature during the manufacturing process. As the first element, one or both of boron and phosphorus can be preferably used.

[0123] Hydrogen supply causes oxygen vacancies (V Ｏ ) to occur in the semiconductor layer 208. Further, defects in which hydrogen enters the oxygen vacancy (V Ｏ ), hereinafter also referred to as V Ｏ H, occur. Thereby, the electrical resistance of the region 208P can be efficiently lowered. Therefore, hydrogen can be preferably used as the first element.

[0124] In the supply of impurities, it is preferable to adjust the supply conditions so that the concentration of impurities on the surface of the semiconductor layer 208 or in a region close to the surface becomes the highest.

[0125] As the raw material used for supplying impurities, for example, a gas containing the first element can be used. When supplying boron, typically, B ２ H ６ gas, or one or more of BF ３ gas can be used. When supplying phosphorus, typically, PH ３ gas can be used. Also, a gas obtained by diluting these raw material gases with a noble gas can be used.

[0126] As the raw material used for supplying impurities, for example, CH ４ , N ２ , NH ３ , AlH ３ , AlCl ３ , SiH ４ , Si ２ H ６ , F ２ , HF, H ２ , (C ５ H ５ ) ２Mg and noble gases can be used. The raw materials are not limited to gases; solids or liquids can also be heated and vaporized for use.

[0127] The supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the composition, density, and thickness of the insulating layer 206 and the semiconductor layer 208. Note that when supplying impurities to the semiconductor layer 208 via the insulating layer 206 using the conductive layer 204 as a mask, impurities may be supplied to areas of the insulating layer 206 that do not overlap with the conductive layer 204, resulting in those areas containing impurities.

[0128] The method of supplying impurities is not limited to this; for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of plasma treatment, impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, high-density plasma CVD apparatus, etc., can be used.

[0129] I will now explain the insulating layer 110.

[0130] As the insulating layer 110, either an inorganic insulating layer or an organic insulating layer, or both, can be used. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. Preferably, the insulating layer 110 has one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0131] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0132] The insulating layer 110 has a region that is in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 110 that is in contact with the semiconductor layer 108 contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, it is preferable that the region of the insulating layer 110 that is in contact with the channel-forming region of the semiconductor layer 108 contains oxygen. One or more oxides and oxiditrides can be suitably used in the region of the insulating layer 110 that is in contact with the channel-forming region of the semiconductor layer 108.

[0133] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 110 that is in contact with the semiconductor layer 108 releases oxygen when heat is applied. This supplies oxygen from the insulating layer 110 to the semiconductor layer 108, and reduces oxygen deficiencies (V) in the semiconductor layer 108. Ｏ), and V Ｏ H can be reduced.

[0134] The insulating layer 110 preferably has a laminated structure. Figure 1D and others show an example in which the insulating layer 110 has an insulating layer 110a, an insulating layer 110b on insulating layer 110a, and an insulating layer 110c on insulating layer 110b. The insulating layers 110a, 110b, and 110c can each be made from the materials listed for insulating layer 110.

[0135] When the insulating layer 110 has a laminated structure, the side surface 77 includes the side surfaces of each layer. Also, the lower end of the side surface of the layer in contact with the conductive layer 112a in the insulating layer 110 becomes the end surface 31. When the insulating layer 110 has insulating layers 110a, 110b, and 110c, the side surface 77 includes the side surface of insulating layer 110a, the side surface of insulating layer 110b, and the side surface of insulating layer 110c. The lower end of the side surface of insulating layer 110a on the conductive layer 112a becomes the end surface 31. Furthermore, as shown in Figure 1D, it is preferable that there is no step between the side surface of insulating layer 110a and the side surface of insulating layer 110b, and that they are flat (i.e., the two surfaces are flush). Similarly, it is preferable that the side surface of insulating layer 110b and the side surface of insulating layer 110c are flush. This makes it possible to improve the coverage of the layer provided on the insulating layer 110 (for example, the semiconductor layer 108). Furthermore, it is also possible to have a configuration in which these aspects are discontinuous.

[0136] The region of the semiconductor layer 108 that is in contact with the insulating layer 110b functions as the channel formation region of the transistor 100. The insulating layer 110b preferably contains oxygen, and it is preferable to use one or more of the aforementioned oxides and oxiditrides. The insulating layer 110b preferably contains, for example, silicon and oxygen. Typically, silicon oxide and silicon oxiditride, or both, can be suitably used for the insulating layer 110b.

[0137] It is more preferable to use a material that releases oxygen when heat is applied for the insulating layer 110b. The heat applied during the manufacturing process of the semiconductor device 10 causes the insulating layer 110b to release oxygen, thereby supplying oxygen to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region of the semiconductor layer 108, oxygen deficiencies (V) can be reduced. Ｏ ) is repaired, and oxygen deficiency (V Ｏ ) can be reduced. Also, V Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0138] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or by plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the upper surface of the insulating layer 110b by forming a film in an oxygen-containing atmosphere using a sputtering method. The film can then be removed. The method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 2.

[0139] The insulating layer 110b is preferably deposited using sputtering or plasma chemical vapor deposition (PECVD: Plasma Enhanced Chemical Vapor Deposition, also known as plasma CVD). In particular, by using sputtering and depositing the film without using gases containing hydrogen (for example, hydrogen gas and ammonia gas) as the deposition gas, a film with an extremely low hydrogen content can be obtained. This suppresses the supply of hydrogen to the channel formation region of the semiconductor layer 108, thereby stabilizing the electrical characteristics of the transistor.

[0140] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a and the insulating layer 214. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b and the conductive layer 212a. It is preferable that the insulating layer 110a and the insulating layer 110c each release small amounts of impurities (e.g., hydrogen and water). Furthermore, it is preferable that the insulating layer 110a and the insulating layer 110c each impose poorly on substances. It can also be said that the insulating layer 110a and the insulating layer 110c function as barrier layers. Specifically, it is preferable that the insulating layer 110a and the insulating layer 110c each impose poorly on substances. This suppresses the diffusion of impurities contained in the insulating layer 110a and the insulating layer 110c into the channel formation region of the semiconductor layer 108. Therefore, it is possible to produce a transistor that exhibits good electrical characteristics and is highly reliable.

[0141] In this specification, the term "barrier layer" refers to a membrane having barrier properties. Barrier properties refer to one or both of the following functions: a function that makes it difficult for the target substance to diffuse, thereby suppressing the permeation of the substance through the membrane (also known as low permeability); and a function that captures or fixes the substance (also known as gettering).

[0142] The barrier layer can be made of, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, an aluminum nitride, a silicon nitride, and a silicon nitride oxide. Typically, the barrier layer can be made of, for example, one or more aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0143] Furthermore, the same material can be used for insulating layer 110a and insulating layer 110c. This allows the equipment used to form insulating layer 110a and insulating layer 110c to be common, thereby lowering the manufacturing cost of semiconductor devices. Alternatively, different materials can be used for insulating layer 110a and insulating layer 110c. This broadens the range of material choices for insulating layer 110a and insulating layer 110c.

[0144] It is preferable that insulating layer 110a and insulating layer 110c are made of materials that are not permeable to oxygen. This suppresses the diffusion of oxygen contained in insulating layer 110b to the conductive layer 112a side via insulating layer 110a. Similarly, it suppresses the diffusion of oxygen contained in insulating layer 110b to the conductive layer 112b side via insulating layer 110c. This increases the amount of oxygen supplied from insulating layer 110b to the channel formation region of semiconductor layer 108, thereby reducing oxygen deficiencies (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0145] By using an oxide or oxiditride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b (or the insulating film that becomes the insulating layer 110b) when the insulating layer 110c (or the insulating film that becomes the insulating layer 110c) is formed.

[0146] One or more of the insulating layers 110a, 110b, and 110c can also be arranged in a laminated structure. For example, the insulating layer 110c can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0147] A cross-sectional view of the transistor 100 is shown in Figure 5A. The thickness T110c of the insulating layer 110c is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, more preferably 20 nm to 300 nm, more preferably 50 nm to 300 nm, more preferably 100 nm to 300 nm, and more preferably 100 nm to 200 nm. As shown in Figure 5A, the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is formed (here, the upper surface of the insulating layer 110b) and the upper surface of the insulating layer 110c in a cross-sectional view.

[0148] The thickness T110c is preferably a value that functions as a barrier layer against oxygen. The thickness T110c can be thinner than the thickness T110a. If the thickness T110c of the insulating layer 110c is thick, the amount of impurities released from the insulating layer 110c increases, and the amount of impurities that diffuse into the channel formation region of the semiconductor layer 108 may increase. On the other hand, if the thickness T110c is thin, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112b side through the insulating layer 110c, and the amount of oxygen supplied to the channel formation region may decrease. By setting the thickness T110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, and the oxygen deficiency (V) in the channel formation region can be reduced. Ｏ ) and V Ｏ H can be reduced. Note that the thickness T110c is not limited to the range mentioned above.

[0149] The thickness T110a of the insulating layer 110a is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, more preferably 20 nm to 300 nm, more preferably 50 nm to 300 nm, more preferably 100 nm to 300 nm, more preferably 100 nm to 250 nm, and more preferably 150 nm to 250 nm. As shown in Figure 5A, the thickness T110a can be the shortest distance between the surface on which the insulating layer 110a is formed (for example, the upper surface of the conductive layer 112a) and the upper surface of the insulating layer 110a in a cross-sectional view.

[0150] If the thickness T110a of the insulating layer 110a is thin, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a side through the insulating layer 110a, reducing the amount of oxygen supplied to the channel formation region of the semiconductor layer 108. On the other hand, if the thickness T110a is thick, the amount of impurities released from the insulating layer 110a increases, and the amount of impurities diffusing into the channel formation region increases. By setting the thickness T110a within the aforementioned range, the amount of oxygen supplied to the channel formation region can be increased, thereby reducing oxygen deficiency (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced. Note that the thickness T110a is not limited to the range mentioned above.

[0151] The thickness T110a can be made thicker than the thickness T110c. When the region of the semiconductor layer 108 in contact with the insulating layer 110a functions as a source region or a drain region, increasing the thickness T110a makes the distance from the source region to the gate electrode and the distance from the drain region to the gate electrode more uniform. This makes the electric field of the gate electrode acting on the channel formation region more uniform.

[0152] At least one of the regions of the semiconductor layer 108 that are in contact with the insulating layer 110a and the region that are in contact with the insulating layer 110c may be a region with lower electrical resistance compared to the channel-forming region (hereinafter also referred to as the low-resistance region). This region can also be described as a region with a higher carrier concentration or a higher oxygen vacancy density compared to the channel-forming region. By using a material that releases impurities (e.g., water and hydrogen) in the insulating layer 110a, the region of the semiconductor layer 108 in contact with the insulating layer 110a can contain impurities, making this region a low-resistance region. The semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112a (either the source region or the drain region) and the channel-forming region. Similarly, by using a material that releases impurities in the insulating layer 110c, the region of the semiconductor layer 108 in contact with the insulating layer 110c can contain impurities, making this region a low-resistance region. The semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel-forming region. The low-resistance region can function as a buffer region to mitigate the drain electric field. These low-resistance regions can also function as either the source region or the drain region.

[0153] Furthermore, impurities released from the insulating layer 110a may diffuse into the channel formation region of the semiconductor layer 108 via the insulating layer 110b, or via one of the source and drain regions of the semiconductor layer 108. Similarly, impurities released from the insulating layer 110c may diffuse into the channel formation region via the insulating layer 110b, or via the other of the source and drain regions of the semiconductor layer 108. However, since oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 in contact with the insulating layer 110b, oxygen deficiency (V) in the channel formation region occurs. Ｏ ) and V Ｏ The H value can be reduced. This suppresses the shift in the threshold voltage, allowing for a transistor that achieves both a small cutoff current and a large on-current. Therefore, a semiconductor device that achieves both low power consumption and high performance can be created.

[0154] However, if the amount of impurities released from insulating layer 110a and insulating layer 110c becomes too large, the amount of impurities contained in semiconductor layer 108 will increase. As a result, oxygen vacancies (V) will be formed in semiconductor layer 108. Ｏ ) and V Ｏ The amount of H is the oxygen deficiency (V) that is repaired by the oxygen supplied from the insulating layer 110b. Ｏ ) and V Ｏ There is a risk that the amount of H may exceed the amount of H. Even when materials that release impurities are used for the insulating layer 110a and insulating layer 110c, it is more preferable that the amount of released impurities be small.

[0155] Although the insulating layer 110 is shown here as a three-layer laminated structure, the present invention is not limited to this. Preferably, the insulating layer 110 has at least an insulating layer 110b. It is also possible to have a configuration that does not have one or both of the insulating layers 110a and 110c. Furthermore, the insulating layer 110 can be configured as a laminated structure of four or more layers.

[0156] The channel length and channel width of transistors 100 and 200 will be explained using Figures 1D, 2B, 5A, and 5B. Figure 5B is a top view of the semiconductor device 10. Here, the region in contact with the side surface of the insulating layer 110b of the semiconductor layer 108 will be described as the channel formation region of transistor 100.

[0157] In Figure 5A, the channel length L100 of transistor 100 is indicated by a dashed double arrow. The channel length L100 of transistor 100 corresponds to the length of the region in contact between the semiconductor layer 108 and the side surface of the insulating layer 110b in a cross-sectional view. In other words, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110b between the side surface of the insulating layer 110b on the semiconductor layer 108 side and the surface of the insulating layer 110b to be formed (in this case, the upper surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure apparatus, enabling the realization of minute transistors. Specifically, it is possible to realize transistors with extremely short channel lengths that could not be realized with conventional exposure apparatuses for mass production of flat panel displays (for example, with a minimum dimension of about 2 μm or 1.5 μm). Furthermore, it is possible to realize transistors with channel lengths of less than 10 nm without using the extremely expensive exposure apparatus used in state-of-the-art LSI technology.

[0158] The channel length L100 can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 can also be 100 nm or more and 1 μm or less.

[0159] By shortening the channel length L100, the on-current of the transistor 100 can be increased. Using the transistor 100, a circuit capable of high-speed operation can be fabricated. Furthermore, the circuit's occupied area can be reduced. Therefore, a compact semiconductor device can be made. For example, when a semiconductor device according to one aspect of the present invention is applied to a large display device or a high-definition display device, even when the number of wires increases, the signal delay in each wire can be reduced, and display unevenness can be suppressed. Also, because the circuit's occupied area can be reduced, the bezel of the display device can be narrowed.

[0160] The channel length L100 can be controlled by adjusting the thickness T110b and angle θ110b of the insulating layer 110b.

[0161] The thickness T110b of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.

[0162] The side surface of the insulating layer 110 facing the semiconductor layer 108 is preferably tapered. The angle θ110b is preferably less than 90 degrees. By reducing the angle θ110b, the coverage of the layer formed on the insulating layer 110 (for example, the semiconductor layer 108) can be improved. Furthermore, when the angle θ110 is 90 degrees or less, the smaller the angle θ110b, the longer the channel length L100 can be made, and the larger the angle θ110b, the shorter the channel length L100 can be made.

[0163] The angle θ110b can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and less than 90 degrees, 85 degrees or less, or 80 degrees or less. The angle θ110b can also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less.

[0164] Although Figure 5A and other figures show the angle θ110b as less than 90 degrees, the present invention is not limited to this. The angle θ110b can also be 90 degrees or approximately 90 degrees. This allows for a shorter channel length L100 and a smaller footprint for the semiconductor device.

[0165] Figure 5A and other figures show an example configuration in which the shape of the side surface 77 is a straight line in a cross-sectional view, but the present invention is not limited to this. In a cross-sectional view, the shape of the side surface 77 can be a curve. Alternatively, the side surface 77 can include both a region where it is a straight line and a region where it is a curve.

[0166] As shown in Figure 5A and other figures, it is preferable that the side surface of the conductive layer 112b facing the semiconductor layer 108 and the side surface 77 are flush. This improves the coverage of the layer (for example, the semiconductor layer 108) provided on the insulating layer 110 and the conductive layer 112b. However, it is also possible to have a configuration in which the side surface of the conductive layer 112b facing the semiconductor layer 108 and the side surface 77 are discontinuous.

[0167] In this case, if the conductive layer 112b is in contact with the side surface of the insulating layer 110b, the channel length L100 of the transistor 100 may become shorter than the length of the side surface of the insulating layer 110b, making it difficult to control the channel length L100. Therefore, it is preferable that the conductive layer 112b does not have a region in contact with the side surface of the insulating layer 110b.

[0168] For example, a conductive layer, which will become the conductive layer 112b, is formed on an insulating layer, which will become the insulating layer 110. Then, the insulating layer is removed from a region that includes a part of the side surface of the conductive layer, and from a region that overlaps with that region. This makes it possible to form an insulating layer 110 and a conductive layer 112b whose sides are flush with each other.

[0169] In Figure 5B, the channel width W100 of transistor 100 is shown by a double-headed arrow on a dashed line. The channel width W100 is the width of the overlapping region of the semiconductor layer 108 and the conductive layer 104 in a direction perpendicular to the channel length direction. Also, in Figures 1D and 5B, the channel length L200 of transistor 200 is shown by a double-headed arrow on a solid line, and in Figures 2B and 5B, the channel width W200 of transistor 200 is shown by a double-headed arrow on a double-headed line. The channel length L200 is the length of the overlapping region of the semiconductor layer 208 with the conductive layer 204 between a pair of regions 208P. The channel width W200 is the width of the overlapping region of the semiconductor layer 208 with the conductive layer 204 in a direction perpendicular to the channel length direction.

[0170] When forming semiconductor layer 108, semiconductor layer 208, conductive layer 104, and conductive layer 204 using lithography, the channel width W100, channel length L200, and channel width W200 are greater than or equal to the minimum exposure dimension of the exposure apparatus. The channel width W100, channel length L200, and channel width W200 can be, for example, 20 nm or more, 50 nm or more, 100 nm or more, 200 nm or more, 500 nm or more, or 1 μm or more, and can be less than 500 μm, 200 μm or less, 100 μm or less, 50 μm or less, 20 μm or less, 10 μm or less, or 5 μm or less. Although Figure 5B and others show an example configuration in which the channel width W100 and channel width W200 are the same, the present invention is not limited to this. The channel width W100 and channel width W200 can be different. By increasing the channel width, the on-current of the transistor can be increased.

[0171] In this explanation, we have used as an example a configuration in which the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as the channel formation region of the transistor 100, but the present invention is not limited to this. The regions of the semiconductor layer 108 in contact with the insulating layer 110a and the regions in contact with the insulating layer 110c may also function as channel formation regions of the transistor 100.

[0172] [Semiconductor Layer 108 and Semiconductor Layer 208] The metal oxides that can be used in semiconductor layer 108 and semiconductor layer 208 will be described in detail. In some cases, semiconductor layer 108 will be used as an example. For semiconductor layer 208, please refer to the description related to semiconductor layer 108.

[0173] As mentioned above, the metal oxide preferably contains at least indium.

[0174] When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, and In:M Compositions such as Zn=5:1:9, In:M:Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions near these. In this specification, "nearby composition" includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0175] The atomic ratio of In in an In-M-Zn oxide can be less than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, oxygen deficiency (V) can be reduced. Ｏ This can suppress the generation of ()

[0176] Furthermore, if element M comprises multiple elements, the sum of their atomic ratios can be used as the atomic ratio of element M.

[0177] By using a material with a high indium content in the semiconductor layer 108, the on-current or field-effect mobility of the transistor can be increased. Furthermore, the presence of element M allows for oxygen deficiency (V ＯThe generation of ) can be suppressed. The content of element M is preferably 0.1% to 25%, more preferably 0.1% to 20%, more preferably 0.1% to 10%, more preferably 0.1% to 8%, more preferably 0.1% to 6%, and more preferably 0.1% to 4%. This makes it possible to make a transistor with good electrical characteristics. For example, it is preferable to use a metal oxide in which In:M:Zn = 40:1:10 or a similar ratio. Element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, a metal oxide in which In:Sn:Zn = 40:1:10 or a similar ratio can be suitably used. Alternatively, a metal oxide in which In:Al:Zn = 40:1:10 or a similar ratio can be suitably used.

[0178] A metal oxide that does not contain element M can be applied to the semiconductor layer 108. When the metal oxide is an In-Zn oxide, examples of atomic ratios of the metal elements include In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions near these. Furthermore, it is more preferable that the atomic ratio of In is greater than or equal to the atomic ratio of Zn. By increasing the atomic ratio of indium in a metal oxide, the on-current or field-effect mobility of a transistor can be increased.

[0179] For analyzing the composition of the semiconductor layer 108, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectroscopy (ICP-AES) can be used. Alternatively, a combination of these methods can be used for analysis. XPS is sometimes referred to as ESCA (Electron Spectrometry for Chemical Analysis). It is preferable to separate the peaks of the spectrum obtained by the analysis and then identify and quantify the elements. However, for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by the analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may be below the detection limit.

[0180] For depositing metal oxide films, sputtering or atomic layer deposition (ALD) can be suitably used. However, when depositing metal oxide films by sputtering, the composition of the deposited metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the deposited metal oxide film may decrease to about 50% of the content in the sputtering target.

[0181] It is preferable to use a crystalline metal oxide for the semiconductor layer 108. Examples of crystalline metal oxide structures include single crystal, polycrystalline, CAAC (c-axis aligned crystal) structure, microcrystalline structure, and nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide, the defect level density in the semiconductor layer 108 can be reduced, resulting in a highly reliable transistor. Therefore, a highly reliable semiconductor device can be realized.

[0182] The semiconductor layer 108 preferably has high crystallinity, and is preferably polycrystalline or monocrystalline. A polycrystalline indium oxide film is preferably used as the semiconductor layer 108, and a monocrystalline indium oxide film is more preferably used.

[0183] The crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0184] Single-crystal films are particularly preferred because they do not have grain boundaries, thus suppressing carrier scattering at grain boundaries and enabling transistors with high field-effect mobility. Compared to microcrystalline and amorphous films, polycrystalline films can reduce carrier scattering and enable transistors with high field-effect mobility. When a polycrystalline film is used for semiconductor layer 108, it is preferable that the grain size of the crystal grains contained in semiconductor layer 108 is large. By using a polycrystalline film with large grain size, the number of crystal grain boundaries located in the channel formation region can be reduced, and the length of the crystal grain boundaries located in the channel formation region can be shortened, thus enabling transistors with high field-effect mobility. Furthermore, it is preferable that there are few crystal grain boundaries in the channel formation region that intersect with the direction of drain current flow (also known as the channel length direction). Note that even with a polycrystalline film, if there are no crystal grain boundaries located in the channel formation region, the same effects as a single-crystal film can be achieved.

[0185] When a polycrystalline indium oxide film is used as the semiconductor layer 108, the grain size of the crystal grains contained in the semiconductor layer 108 is preferably 0.1 μm or larger, more preferably 0.2 μm or larger, more preferably 0.3 μm or larger, more preferably 0.4 μm or larger, more preferably 0.5 μm or larger, more preferably 0.6 μm or larger, and more preferably 0.7 μm or larger. Since a larger grain size is preferable, no particular upper limit is set for the grain size. Note that the grain size of the crystal grains is not limited to the above range.

[0186] The grain size of the crystal grains contained in the semiconductor layer 108 can be analyzed, for example, by transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), or electron backscatter diffraction (EBSD or EBSP). Alternatively, a combination of these methods can be used for analysis. For example, the average grain size of multiple crystal grains can be used as the grain size. Furthermore, the grain size of a crystal grain can be defined as, for example, the diameter of a circle with the same area as the crystal grain. This diameter is sometimes called the equivalent diameter of a circle.

[0187] In this specification, a grain boundary refers to, for example, the boundary between adjacent grains with different crystal orientations. Therefore, in this specification, boundaries between adjacent grains with the same crystal orientation are not included in grain boundaries. For example, even if a boundary is observed between two grains in a TEM image, if the crystal orientations of those two grains are the same or approximately the same, the boundary may not be called a grain boundary. Also, in EBSD, if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same grain.

[0188] In this specification, space groups are denoted using the international notation (or Hermann-Mauguin notation) Short notation. In addition, space group numbers from the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be included. Furthermore, Miller indices are used to indicate crystal planes and crystal directions. In crystallography, space groups, crystal planes, and crystal directions are indicated by a bar above the number, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a bar above it. In addition, individual orientations indicating directions within a crystal are indicated by [ ], collective orientations indicating all equivalent directions are indicated by < >, individual planes indicating crystal planes are indicated by ( ), and collective planes with equivalent symmetry are indicated by {}. Note that even with the same space group number, the notation for the space group may differ depending on how the crystal axis is defined.

[0189] In addition, cubic In ２ O ３ The crystal structure of this material belongs, for example, to space group Ia-3 (space group number 206).

[0190] Alternatively, it is preferable to use CAAC-OS or nc-OS for the semiconductor layer 108. As the semiconductor layer 108, for example, an indium tin zinc oxide (In-Sn-Zn oxide) film with a CAAC structure or an nc structure, or an indium gallium zinc oxide (In-Ga-Zn oxide) film can be suitably used.

[0191] CAAC-OS has multiple layered crystals. The c-axis of the crystals is oriented in the direction normal to the surface to be formed. It is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the surface to be formed. For example, it is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the upper surface of the conductive layer 112b in the region in contact with the upper surface of the conductive layer 112b, and layered crystals that are parallel or approximately parallel to the side surface in the region in contact with the side surface of the conductive layer 112b. In particular, it is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the side surface 77, which is the surface to be formed, in the region in contact with the side surface 77 of the insulating layer 110. With this configuration, the layered crystals of the semiconductor layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, so that a transistor with a large on-current can be made.

[0192] By using a highly crystalline metal oxide in the channel formation region, the defect level density in the channel formation region can be reduced. On the other hand, by using a less crystalline metal oxide, it is possible to realize a transistor that can carry a large current.

[0193] The higher the substrate temperature during metal oxide film deposition, the more crystalline the metal oxide film can be deposited. The substrate temperature during deposition can be adjusted, for example, by the temperature of the stage on which the substrate is placed during deposition. Furthermore, the higher the ratio of oxygen gas flow rate to the total deposition gas flow rate (hereinafter also referred to as the oxygen flow rate ratio), or the higher the oxygen partial pressure in the processing chamber, the more crystalline the metal oxide film can be deposited.

[0194] When a metal oxide is used for the semiconductor layer 108, the V of the channel formation region Ｏ It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. In this way, V Ｏ To obtain a metal oxide with sufficiently reduced H content, impurities such as water and hydrogen must be removed from the metal oxide (sometimes referred to as dehydration and dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V). Ｏ It is important to repair ). ＯBy using a metal oxide with sufficiently reduced impurities such as H in the channel formation region, a transistor with stable electrical characteristics can be made. Furthermore, by supplying oxygen to the metal oxide, oxygen deficiencies (V) can be reduced. Ｏ The process of repairing this is sometimes referred to as oxygenation treatment.

[0195] OS transistors exhibit minimal fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton beams, and neutron beams).

[0196] The semiconductor layer 108 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystalline structure. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0197] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable to the channel-forming region is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) are some examples.

[0198] The semiconductor layer 108 can have a laminated structure having two or more metal oxide layers. The two or more metal oxide layers of the semiconductor layer 108 can have the same or substantially the same composition. By having a laminated structure of metal oxide layers with the same composition, for example, it can be formed using the same sputtering target, thus reducing manufacturing costs. When the two or more metal oxide layers of the semiconductor layer 108 have the same or substantially the same composition, it may not be possible to clearly identify the boundaries (interfaces) of these metal oxide layers.

[0199] [Conductive layer 112a, conductive layer 112b, conductive layer 212a, conductive layer 104, conductive layer 204] Conductive layers 112a, 112b, 212a, 104, and 204 can each be a single layer or a laminated structure of two or more layers. Materials that can be used for these conductive layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. Conductive materials with low electrical resistivity, containing one or more of copper, silver, gold, and aluminum, can be suitably used for each of these conductive layers. Copper or aluminum are particularly preferred due to their excellent mass productivity.

[0200] Conductive layers 112a, 112b, 212a, 104, and 204 can each be made of a conductive metal oxide (also called an oxide conductor). Examples of oxide conductors (OC) include indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, ITSO, Ga-Zn oxide, and In-Ga-Zn oxide.

[0201] When oxygen vacancies are formed in a metal oxide with semiconductor properties, and hydrogen is added to these vacancies, donor levels are formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0202] Conductive layers 112a, 112b, 212a, 104, and 204 can each have a laminated structure consisting of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0203] Conductive layers 112a, 112b, 212a, 104, and 204 can each be made of a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, processing can be done by wet etching, thus reducing manufacturing costs.

[0204] Note that conductive layers 112a, 112b, 212a, 104, and 204 can be made of the same material. Alternatively, at least one of them can be made of a different material.

[0205] After the conductive layers 112a and 112b are formed, a semiconductor layer 108 is provided in contact with them. When a metal oxide is used for the semiconductor layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for these conductive layers, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a or conductive layer 112b and the semiconductor layer 108, potentially hindering conductivity. Therefore, it is preferable to use conductive materials that are resistant to oxidation, conductive materials that maintain low electrical resistance even when oxidized, or oxide conductors for the conductive layers 112a and 112b. Furthermore, the conductive layer 212a can be formed by processing the same conductive film as the conductive layer 112b. Therefore, the conductive layer 212a can use the same material as the conductive layer 112b. By using a different material for the conductive layer 212a than for the conductive layer 112b, the range of material selection can be broadened.

[0206] For conductive layers 112a, 112b, and 212a, it is preferable to use materials such as titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. These are preferred because they are conductive materials that are resistant to oxidation, or materials that maintain low electrical resistance even when oxidized.

[0207] The aforementioned oxide conductors can be used for conductive layers 112a, 112b, and 212a, respectively. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, ITSO, and Ga-Zn oxide can be used. Oxide conductors containing indium are particularly suitable for use in conductive layers 112a, 112b, and 212a because they have high conductivity.

[0208] Nitride conductors can also be used for conductive layers 112a, 112b, and 212a, respectively. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0209] The conductive layer 112a, conductive layer 112b, conductive layer 212a, conductive layer 104, and conductive layer 204 can each be a single layer or a laminated structure of two or more layers.

[0210] When conductive layers 112a and 112b are arranged in a laminated structure, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor for the first conductive layer that is in contact with the semiconductor layer 108. For example, ITO or ITSO can be suitably used for the first conductive layer. On the other hand, the material used for the second conductive layer that is not in contact with the semiconductor layer 108 is not particularly limited. For example, it is preferable to use a material for the second conductive layer that has a lower electrical resistivity than the first conductive layer. This makes it possible to lower the electrical resistance of conductive layers 112a and 112b. For example, copper or tungsten can be suitably used for the second conductive layer.

[0211] [Insulating layer 106, insulating layer 206] It is preferable that insulating layer 106 and insulating layer 206 each have one or more inorganic insulating layers. Insulating layer 106 and insulating layer 206 can each be made of materials that can be used for insulating layer 110. Note that insulating layer 106 may be used as an example in the following explanation. For insulating layer 206, refer to the description relating to insulating layer 106.

[0212] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least one of the aforementioned oxides and oxiditrides is used for the film constituting the insulating layer 106 that is in contact with the semiconductor layer 108. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxiditride, or aluminum oxide can be suitably used for the insulating layer 106.

[0213] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxiditrides having aluminum and hafnium, oxides having silicon and hafnium, oxiditrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0214] Although Figure 1D and other figures show the insulating layer 106 and insulating layer 206 as single-layer structures, the present invention is not limited to this. One or both of the insulating layer 106 and insulating layer 206 can be made into a laminated structure of two or more layers.

[0215] When the insulating layer 106 has a laminated structure, it is preferable to use an oxide or oxidized nitride for the first insulating layer on the semiconductor layer 108 side. The first insulating layer can preferably be one or more of silicon oxide, silicon oxidized nitride, or aluminum oxide. Alternatively, a nitride or nitride oxide can be used for the first insulating layer. For example, aluminum nitride can preferably be used for the first insulating layer.

[0216] Preferably, one or more of the layers constituting the insulating layer 106 function as a barrier layer. By providing a barrier layer, the diffusion of metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in the layers formed on the transistor 100 into the semiconductor layer 108 via the insulating layer 106 can be suppressed. Furthermore, the diffusion of oxygen contained in the insulating layer 110b into the conductive layer 104 side via the insulating layer 106 can be suppressed. As a result, the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108 increases, reducing oxygen deficiencies (V) in the channel formation region. Ｏ ) and V ＯH can be reduced. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained. In addition, oxidation of the conductive layer 104 by oxygen contained in the insulating layer 110b and the resulting increase in the electrical resistance of these conductive layers can be suppressed. As a result, a transistor exhibiting good electrical characteristics and high reliability can be obtained. For materials that can be used for the barrier layer, refer to the above description. For example, silicon nitride, aluminum oxide, and one or more of the aluminum nitride can be suitably used for one or more of the layers constituting the insulating layer 106.

[0217] When the insulating layer 106 has a laminated structure of a first insulating layer and a second insulating layer on the first insulating layer, a barrier layer can be used as the second insulating layer. For example, silicon oxynitride can be used for the first insulating layer and silicon nitride for the second insulating layer. Alternatively, silicon oxynitride can be used for the first insulating layer and aluminum oxide for the second insulating layer. Alternatively, silicon oxynitride can be used for the first insulating layer and aluminum nitride for the second insulating layer.

[0218] When the insulating layer 106 has a laminated structure of a first insulating layer and a second insulating layer on the first insulating layer, a barrier layer can also be used as the first insulating layer. Aluminum oxide can be used for the first insulating layer and silicon oxynitride for the second insulating layer. Alternatively, aluminum oxide can be used for the first insulating layer and silicon nitride for the second insulating layer. Alternatively, aluminum nitride can be used for the first insulating layer and silicon oxynitride for the second insulating layer.

[0219] Here, an example is shown in which the insulating layer 106 has a two-layer laminated structure, but the present invention is not limited to this. The insulating layer 106 can have a three-layer or more laminated structure.

[0220] [Insulating layer 214, insulating layer 218] The insulating layer 214 and insulating layer 218 can each be made of either an inorganic insulating layer or an organic insulating layer, or both. The insulating layer 214 and insulating layer 218 can each be made of the materials listed for insulating layer 110. In addition, the insulating layer 214 and insulating layer 218 can each be made of a single layer or a laminated structure.

[0221] When silicon is used for the semiconductor layer 208, it is preferable that the insulating layer 214 has a layer that releases hydrogen when heat is applied. The insulating layer 214 can preferably be, for example, silicon oxide nitride containing hydrogen, silicon nitride oxide containing hydrogen, or silicon nitride containing hydrogen. Furthermore, it is preferable that the insulating layer 214 contains a large amount of hydrogen. It is even more preferable to perform a heat treatment in a hydrogen-containing atmosphere after forming the insulating layer 214. This supplies hydrogen from the insulating layer 214 to the semiconductor layer 208, and the dangling bonds in the semiconductor layer 208 are terminated by hydrogen (hereinafter also referred to as hydrogenation or hydrogen termination). Therefore, the amount of dangling bonds in the semiconductor layer 208 can be reduced.

[0222] Furthermore, if a high temperature is applied after hydrogen termination, hydrogen in the semiconductor layer 208 may be desorbed, potentially increasing the number of dangling bonds in the semiconductor layer 208. However, compared to Si transistors, OS transistors can be manufactured at lower process temperatures (typically below 350°C). Therefore, when transistor 200 is a Si transistor, by making the transistor 100 formed on the insulating layer 214 an OS transistor, the temperature applied to the semiconductor layer 208 during the manufacturing process of transistor 100 can be reduced, thereby suppressing the increase of dangling bonds in the semiconductor layer 208.

[0223] Here, if a hydrogen-releasing material is used for the insulating layer 214, and too much hydrogen is released from the insulating layer 214, the amount of hydrogen that diffuses into the channel-forming region of the semiconductor layer 108 may increase. When a metal oxide is used for the semiconductor layer 108, oxygen vacancies (V) are formed in the semiconductor layer 108. Ｏ ) and V ＯThe amount of H is reduced by the oxygen supplied from the insulating layer 110b, resulting in an oxygen deficiency (V Ｏ ) and V Ｏ There is a risk that the amount of hydrogen will exceed the amount of H. Therefore, when a metal oxide is used for the semiconductor layer 108 and silicon is used for the semiconductor layer 208, it is preferable to provide a barrier layer on the insulating layer 214. For example, it is preferable to provide an insulating layer 110a that functions as a barrier layer on the insulating layer 214. By providing an insulating layer 110a on the insulating layer 214 which uses a hydrogen-releasing material, it is possible to suppress the diffusion of hydrogen contained in the insulating layer 214 into the channel formation region of the semiconductor layer 108 via the insulating layer 110b. This makes it possible to obtain transistors 100 and 200 with good electrical characteristics.

[0224] When silicon is used for the semiconductor layer 208, it is preferable that the insulating layer 214 has a region with a higher hydrogen content than the insulating layer 110a. This allows for a larger amount of hydrogen to be supplied from the insulating layer 214 to the semiconductor layer 208, thereby reducing dangling bonds in the semiconductor layer 208. Secondary ion mass spectrometry (SIMS) can be used to analyze the hydrogen content of the insulating layer 214 and the insulating layer 110a. Alternatively, the insulating layer 214 and the insulating layer 110a may have the same hydrogen content, or the insulating layer 110a may have a region with a higher hydrogen content than the insulating layer 214.

[0225] A barrier layer may also be used on one or both of the insulating layer 214 and the insulating layer 218. By providing a barrier layer, the diffusion of impurities from the outside into the transistor can be suppressed, thereby improving the reliability of the semiconductor device. For details on the barrier layer, please refer to the above description.

[0226] When a metal oxide is used for the semiconductor layer 208, the insulating layer 214 functions as a barrier layer, which suppresses the detachment of oxygen contained in the semiconductor layer 208 from the insulating layer 218 through the insulating layer 206. This prevents oxygen deficiencies (V) from forming in the semiconductor layer 208. Ｏ ) and V ＯThe increase in H can be suppressed. As the insulating layer 218, for example, one or both of silicon nitride and silicon nitride oxide can be suitably used.

[0227] By using an organic insulating layer for the insulating layer 214, irregularities caused by the transistor 200 can be reduced. This improves the coverage of the layer provided on the insulating layer 214 (for example, the layer of the transistor 100), and suppresses the occurrence of defects such as step breaks or porosity in the layer. Similarly, by using an organic insulating layer for the insulating layer 218, irregularities caused by the transistors 100 and 200 can be reduced. This suppresses the occurrence of defects such as step breaks or porosity in the layer provided on the insulating layer 218 (for example, the layer of the display element). In addition, one or both of the insulating layers 214 and 218 can have a laminated structure of an inorganic insulating layer and an organic insulating layer. For example, the insulating layer 214 can have a laminated structure of an inorganic insulating layer and an organic insulating layer on the inorganic insulating layer.

[0228] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatments. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or resin substrates can be used as the substrate 102. In addition, substrates on which semiconductor elements are provided can be used as the substrate 102. A substrate with an insulating film formed on its surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited and can be circular or rectangular, for example.

[0229] A flexible substrate can be used as the substrate 102, and transistors 100 and 200 can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and transistors 100 and 200. By providing a release layer, the semiconductor device can be partially or completely completed on it, then separated from the substrate 102 and transferred to another substrate. In this case, transistors 100 and 200 can be transferred to a substrate with low heat resistance or to a flexible substrate.

[0230] The following describes a configuration example of a semiconductor device that differs in some aspects from the configuration example described above. Note that in the following, explanations of parts that overlap with the previously described configuration example may be omitted. Also, in the drawings shown below, parts having the same function as the previously described configuration example may use the same hatching pattern and may not be labeled.

[0231] [Configuration Example 1-2] Figure 6A shows a top view of a semiconductor device 10A, which is one embodiment of the present invention. Figure 6B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 6A, and Figure 7A shows a cross-sectional view of the cross-section along the dashed-dotted line B1-B2. For a cross-sectional view of the cross-section along the dashed-dotted line B3-B4 shown in Figure 6A, refer to Figure 2B. For an equivalent circuit diagram of the semiconductor device 10A, refer to Figures 1B and 1C.

[0232] The semiconductor device 10A includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 214. The semiconductor device 10A differs from the semiconductor device 10 shown in Figure 1D, etc., in that the insulating layer 110 has an opening 145.

[0233] An enlarged view of the transistor 100 shown in Figure 6B is shown in Figure 7B. A perspective view of the transistor 100 is shown in Figure 8A. A perspective view of Figure 8A with the conductive layer 104 and insulating layer 106 omitted is shown in Figure 8B.

[0234] The insulating layer 110 has an opening 145 that reaches the conductive layer 112a. The side surface 77 and the upper surface of the conductive layer 112a are exposed at the opening 145. Furthermore, as shown in Figure 7B and the like, it is preferable that there is no step between the side surface of the conductive layer 112b on the opening 145 side and the side surface 77, and that the two surfaces are flush.

[0235] For example, a first conductive layer, which will become the conductive layer 112b, is formed on a first insulating layer, which will become the insulating layer 110. Then, by removing a part of the first conductive layer and a part of the first insulating layer, the conductive layer 112b and the insulating layer 110 can be formed. At this time, by removing the first conductive layer and the first insulating layer in a region including the edge of a part of the first conductive layer, the insulating layer 110 and the conductive layer 112b, whose sides are flush with each other, can be formed.

[0236] A semiconductor layer 108 is provided so as to cover the conductive layer 112b and a portion of the opening 145. The semiconductor layer 108 has regions that are in contact with the upper surface and side surface of the conductive layer 112b, and at the opening 145, it has regions that are in contact with the side surface 77 and the upper surface of the conductive layer 112a.

[0237] Openings 145 are provided only in one of the source and drain regions of the semiconductor layer 108, and in its vicinity, while an insulating layer 110 is provided in the other region. Therefore, the area of ​​the region where the insulating layer 110 is provided can be increased. This allows for an increase in the amount of oxygen supplied from the insulating layer 110 (for example, insulating layer 110b) to the semiconductor layer 108. This reduces oxygen vacancies (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced. In addition, the unevenness caused by the difference between the region where the insulating layer 110 is provided and the region where it is not provided can be reduced. As a result, the coverage of the transistor 100 and the layer provided on the insulating layer 110 can be improved, and defects such as step breaks or porosity in the layer can be suppressed.

[0238] Figure 6A and others show an example configuration in which the top surface shape of the opening 145 is a square with rounded corners, but the present invention is not limited to this. The top surface shape of the opening 145 is not limited and can be, for example, a circle, an ellipse, a triangle, a square (including rectangles, rhombuses, and squares), a pentagon, or a polygon with rounded corners. The polygon may be either a concave polygon (a polygon in which at least one interior angle exceeds 180 degrees) or a convex polygon (a polygon in which all interior angles are 180 degrees or less). By making the top surface shape of the opening 145 circular, the processing accuracy when forming the opening 145 can be improved, and a fine-sized opening 145 can be formed. In this specification, the term "circular" is not limited to a perfect circle.

[0239] As shown in Figure 8B, the conductive layer 112b can be configured to have a notch 148 in the region overlapping with the opening 145. The side surface of the conductive layer 112b is exposed in the notch 148. The semiconductor layer 108 is provided so as to cover a part of the notch 148 and a part of the opening 145. The semiconductor layer 108 has a region in contact with the side surface 77 and the upper surface of the conductive layer 112a in the opening 145, and a region in contact with the side surface of the conductive layer 112b in the notch 148.

[0240] Figure 8B and others show an example configuration in which the conductive layer 112b has a notch 148, but the present invention is not limited to this. As shown in Figures 9A and 9B, the conductive layer 112b can also be configured without a notch 148. Figure 9A is a top view of the semiconductor device 10A. Figure 9B is a perspective view showing an excerpt of the insulating layer 110, conductive layer 112a, conductive layer 112b, and semiconductor layer 108. By configuring the conductive layer 112b without a notch 148, the width of the conductive layer 112b can be reduced, thereby reducing the occupied area of ​​the semiconductor device. On the other hand, as shown in Figure 8B and others, the wiring resistance of the conductive layer 112b can be reduced by increasing the width of the conductive layer 112b.

[0241] [Configuration Example 1-3] Figures 10A to 10C show cross-sectional views of a semiconductor device 10B, which is one embodiment of the present invention. A top view of the semiconductor device 10B can be seen in Figure 6A. Figure 10A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 6A, Figure 10B is a cross-sectional view of the section along the dashed line B1-B2, and Figure 10C is a cross-sectional view of the section along the dashed line B3-B4.

[0242] The semiconductor device 10B includes a transistor 100, a transistor 200, an insulating layer 110, an insulating layer 214, and an insulating layer 109. The semiconductor device 10B mainly differs from the semiconductor device 10A shown in Figure 6B, etc., in that it has an insulating layer 109.

[0243] The insulating layer 109 is provided between the conductive layer 112a and the insulating layer 110 and the insulating layer 214. The insulating layer 109 has a region that is in contact with the conductive layer 112a, the insulating layer 110, and the insulating layer 214. The insulating layer 109 can be made from the materials listed for the insulating layer 110.

[0244] The insulating layer 109 preferably functions as a barrier layer. It is preferable to use a material for the insulating layer 109 that prevents the diffusion of impurities (e.g., water and hydrogen) contained below the insulating layer 109. This suppresses the diffusion of impurities from below the insulating layer 109 into the transistor 100. For details regarding the barrier layer, please refer to the above description. For example, silicon nitride can be suitably used for the insulating layer 109.

[0245] As mentioned above, when silicon is used for the semiconductor layer 208, a material that releases hydrogen can be used for the insulating layer 214. If too much hydrogen is released from the insulating layer 214, the amount of hydrogen that diffuses into the channel formation region of the semiconductor layer 108 via the conductive layer 112a may increase. By providing an insulating layer 109 that functions as a barrier layer between the insulating layer 214 and the conductive layer 112a, the diffusion of hydrogen contained in the insulating layer 214 into the channel formation region of the semiconductor layer 108 via the conductive layer 112a can be suppressed. This makes it possible to obtain a transistor 100 with good electrical characteristics. Preferably, the insulating layer 109 is provided at least between the conductive layer 112a and the insulating layer 214.

[0246] When silicon is used for the semiconductor layer 208, it is preferable that the insulating layer 214 has a region with a higher hydrogen content than the insulating layer 109. This allows for a larger amount of hydrogen to be supplied from the insulating layer 214 to the semiconductor layer 208, thereby reducing dangling bonds in the semiconductor layer 208. For example, secondary ion mass spectrometry (SIMS) can be used to analyze the hydrogen content of the insulating layer 214 and the insulating layer 109. Alternatively, the insulating layer 214 and the insulating layer 109 may have the same hydrogen content, or the insulating layer 109 may have a region with a higher hydrogen content than the insulating layer 214.

[0247] The thickness T109 of the region of the insulating layer 109 that is in contact with the conductive layer 112a is preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 20 nm or more and 100 nm or less, and more preferably 20 nm or more and 50 nm or less. As shown in Figure 10B, the thickness T109 can be the shortest distance between the surface of the insulating layer 109 to be formed (in this case, the upper surface of the insulating layer 214) and the upper surface of the insulating layer 109 in a cross-sectional view.

[0248] If the thickness T109 is too thick and the amount of impurities released from the insulating layer 109 becomes too large, the amount of impurities that diffuse into the semiconductor layer 108 will increase, resulting in oxygen vacancies (V) generated by these impurities. Ｏ ) and V Ｏ The amount of H is the oxygen deficiency (V) that is repaired by the oxygen supplied from the insulating layer 110b. Ｏ ) and V Ｏ There is a risk that the amount of H will be greater than the amount of other impurities. On the other hand, if the thickness T109 is thin, the amount of impurities that diffuse into the conductive layer 112a and the semiconductor layer 108 will decrease, and there is a risk that the electrical resistance of the conductive layer 112a and the electrical resistance of either the source region or the drain region of the semiconductor layer 108 will increase. By setting the thickness T109 to the aforementioned range, oxygen vacancies (V) in the channel formation region of the semiconductor layer 108 can be reduced. Ｏ ) and V ＯThis method suppresses the increase in H and also lowers the electrical resistance of the conductive layer 112a and the electrical resistance of either the source region or the drain region of the semiconductor layer 108. Note that the thickness T109 is not limited to the aforementioned range.

[0249] The insulating layer 109 contains impurities that lower the electrical resistance of the semiconductor layer 108, and a material that releases these impurities can also be used. The impurities released from the insulating layer 109 diffuse into the region of the conductive layer 112a that is in contact with the insulating layer 109. Then, the impurities that have diffused into the conductive layer 112a diffuse into the region of the semiconductor layer 108 that is in contact with the conductive layer 112a, so that region contains impurities, and the electrical resistance of that region can be lowered. In other words, the electrical resistance of either the source region or the drain region of the transistor 100 can be lowered. Therefore, a transistor with a large on-current can be made, and a semiconductor device that operates at high speed can be made.

[0250] When a metal oxide is used for the semiconductor layer 108, it is preferable that the impurities released by the insulating layer 109 include hydrogen. Examples of such impurities include water and hydrogen. As the hydrogen contained in the insulating layer 109 diffuses into the semiconductor layer 108 via the conductive layer 112a, the region of the semiconductor layer 108 in contact with the conductive layer 112a contains hydrogen, and the carrier concentration in that region increases. In other words, the electrical resistance of one of the source region and drain region of the transistor 100 can be lowered. The insulating layer 109 preferably contains, for example, silicon and hydrogen. Typically, silicon nitride containing hydrogen can be suitably used for the insulating layer 109.

[0251] The insulating layer 109 can also be made of a material that releases impurities that lower the electrical resistance of the conductive layer 112a. The impurities released from the insulating layer 109 diffuse into the conductive layer 112a, and the conductive layer 112a contains these impurities. This lowers the electrical resistance of the conductive layer 112a.

[0252] When a metal oxide is used for the conductive layer 112a, it is preferable that the impurities released from the insulating layer 109 include hydrogen. The impurities released from the insulating layer 109 diffuse into the conductive layer 112a, and the conductive layer 112a contains these impurities. This increases the carrier concentration in the conductive layer 112a, thereby lowering its electrical resistance. Furthermore, the conductive layer 112a can function as wiring, resulting in a semiconductor device with low wiring resistance. The impurities that lower the electrical resistance of the conductive layer 112a can be the same as the impurities that lower the electrical resistance of the semiconductor layer 108. Alternatively, these impurities can have different configurations. It is more preferable that the conductive layer 112a is permeable to impurities. It is more preferable that the conductive layer 112a does not readily adsorb impurities.

[0253] The insulating layer 110a has regions that are in contact with the upper surface of the insulating layer 109, and the upper and side surfaces of the conductive layer 112a. This suppresses the diffusion of impurities contained in the insulating layer 109 into the channel formation region of the semiconductor layer 108 via the insulating layer 110b.

[0254] Furthermore, impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 112a and either the source region or the drain region of the semiconductor layer 108. However, at least the region of the semiconductor layer 108 in contact with the insulating layer 110b receives oxygen from the insulating layer 110b, thus preventing oxygen deficiency (V) in the channel formation region. Ｏ ) and V Ｏ The H value can be reduced. This suppresses the shift in the threshold voltage, allowing for a transistor that achieves both a small cutoff current and a large on-current. Therefore, a semiconductor device that achieves both low power consumption and high performance can be created.

[0255] If the insulating layer 109 contains impurities that lower the electrical resistance of one or both of the semiconductor layer 108 and the conductive layer 112a, it is preferable that the insulating layer 109 has a region in which the content of such impurities is higher than that of the insulating layer 110a. For example, it is preferable that the insulating layer 109 has a region in which the content of hydrogen is higher than that of the insulating layer 110a.

[0256] The amount of hydrogen released can be adjusted by using different film deposition conditions for insulating layer 109 and insulating layer 110a. Specifically, one or more of the following can be made different for insulating layer 109 and insulating layer 110a: film deposition power (film deposition power density), film deposition pressure, type of film deposition gas, film deposition gas flow rate ratio, film deposition temperature, and the distance between the substrate and the electrode. For example, by making the film deposition power density of insulating layer 109 lower than that of insulating layer 110a, the hydrogen content in insulating layer 109 can be increased compared to that of insulating layer 110a. This increases the amount of hydrogen released from insulating layer 109 due to the heat applied to it.

[0257] It is preferable that the deposition gas used for forming the insulating layer 109 has a higher hydrogen content than the deposition gas used for forming the insulating layer 110a. Specifically, it is preferable that the ratio of the flow rate of gas containing hydrogen to the total deposition gas used for forming the insulating layer 109 is higher than the ratio of the flow rate of gas containing hydrogen to the total deposition gas used for forming the insulating layer 110a. Typically, when forming silicon nitride films or silicon oxide nitride films as insulating layers 109 and 110a using the PECVD method, it is preferable that the ratio of the flow rate of ammonia gas to the total deposition gas used for forming the insulating layer 109 (hereinafter also referred to as the ammonia flow rate ratio) is higher than the ammonia flow rate ratio of the deposition gas used for forming the insulating layer 110a. By forming the insulating layer 109 under conditions of a high ammonia flow rate ratio, the hydrogen content in the insulating layer 109 can be increased. In addition, the amount of hydrogen released from the insulating layer 109 due to the heat applied to it can be increased.

[0258] It is more preferable that the film density of the insulating layer 110a is higher than that of the insulating layer 109. This suppresses the diffusion of hydrogen contained in the insulating layer 109 into the channel formation region of the semiconductor layer 108 via the insulating layers 110a and 110b. Film density can be evaluated using, for example, Rutherford backscattering spectrum (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using a transmission electron microscope (TEM) image of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image. Therefore, in transmission electron (TE) images, the insulating layer 110a may appear darker (darker) than the insulating layer 109. Even when the same material is applied to both the insulating layer 109 and the insulating layer 110a, the difference in film density may allow the boundary between them to be observed as a difference in contrast in the cross-sectional TEM image.

[0259] [Configuration Example 1-4] Figures 11A to 11C show cross-sectional views of a semiconductor device 10C according to one embodiment of the present invention. A top view of the semiconductor device 10C can be seen in Figure 6A. Figure 11A is a cross-sectional view of the section at the dashed line A1-A2 shown in Figure 6A, Figure 11B is a cross-sectional view of the section at the dashed line B1-B2, and Figure 11C is a cross-sectional view of the section at the dashed line B3-B4.

[0260] The semiconductor device 10C includes a transistor 100, a transistor 200A, an insulating layer 110, an insulating layer 214, and an insulating layer 109. Transistor 200A differs from transistor 200 shown in Figure 10A, etc., in that the edge of the insulating layer 206 coincides with or approximately coincides with the edge of the conductive layer 204.

[0261] The edges of the insulating layer 206 are located on the semiconductor layer 208. The edges of the insulating layer 206 are in contact with the upper surface of the semiconductor layer 208, or overlap with the semiconductor layer 108. The insulating layer 206 does not overlap with region 208P. The upper surface shape of the insulating layer 206 is said to be consistent with or roughly consistent with that of the conductive layer 204. The insulating layer 206 can be formed, for example, by processing it using a resist mask for processing the conductive layer 204.

[0262] The insulating layer 214 has regions that are in contact with the upper and side surfaces of the semiconductor layer 208, the side surfaces of the insulating layer 206, and the upper and side surfaces of the conductive layer 204. The insulating layer 214, insulating layer 109, and insulating layer 110 have openings 247a and 247b that reach region 208P.

[0263] For example, after forming the conductive layer 204, by performing plasma processing in an atmosphere containing a hydrogen-containing gas using a plasma CVD apparatus, hydrogen can be supplied as an impurity to the region of the semiconductor layer 208 that does not overlap with the conductive layer 204. This makes it possible to form region 208P. Furthermore, by using a plasma CVD apparatus for supplying impurities and forming the insulating layer 214, the supply of impurities and the formation of the insulating layer 214 can be performed continuously within the apparatus, thereby increasing productivity.

[0264] Figures 12A and 12B show configuration examples different from those shown in Figures 11A to 11C. Figures 12A and 12B are cross-sectional views of a semiconductor device 10D according to one embodiment of the present invention. A top view of the semiconductor device 10D can be found in Figure 6A. Figure 12A is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 6A, and Figure 12B is a cross-sectional view of the section along the dashed-dotted line B3-B4. A cross-sectional view of the section along the dashed-dotted line B1-B2 can be found in Figure 11B.

[0265] The semiconductor device 10D includes a transistor 100, a transistor 200B, an insulating layer 110, an insulating layer 214, and an insulating layer 109. Transistor 200B differs from transistor 200A shown in Figure 11A in that the insulating layer 206 has a region that protrudes more than the conductive layer 204.

[0266] The edges of the insulating layer 206 are located on the semiconductor layer 208, and the edges of the conductive layer 204 are located on the insulating layer 206. It can also be said that the edges of the insulating layer 206 are located outside the edges of the conductive layer 204. On the semiconductor layer 208, the insulating layer 206 has a region that overlaps with the conductive layer 204 and a region that does not overlap with the conductive layer 204. Furthermore, it can be said that the edges of the conductive layer 204 are in contact with the upper surface of the insulating layer 206, or overlap with the insulating layer 206.

[0267] The semiconductor layer 208 has a channel formation region, a pair of regions 208Q flanking the channel formation region, and a pair of regions 208P located outside of them. Region 208Q is a region of the semiconductor layer 208 that overlaps with the insulating layer 206 and does not overlap with the conductive layer 204. Region 208Q is located between the channel formation region and region 208P.

[0268] Region 208Q functions as a buffer region to mitigate the drain electric field. Since region 208Q does not overlap with the conductive layer 204, it is a region where almost no channels are formed even when a gate voltage is applied to the conductive layer 204. It is preferable that the carrier concentration in region 208Q is higher than that of the channel formation region. This allows region 208Q to function as an LDD (Lightly Doped Drain) region.

[0269] Region 208Q can also be described as a region with similar or lower electrical resistance, similar or higher carrier concentration, similar or higher oxygen defect density, and similar or higher impurity concentration compared to the channel-forming region.

[0270] Region 208Q can also be described as a region with similar or higher electrical resistance, similar or lower carrier concentration, similar or lower oxygen defect density, and similar or lower impurity concentration compared to region 208P.

[0271] The insulating layer 214 has regions that are in contact with the upper and side surfaces of the semiconductor layer 208, the upper and side surfaces of the insulating layer 206, and the upper and side surfaces of the conductive layer 204.

[0272] [Configuration Example 1-5] Figure 13A shows a top view of a semiconductor device 10E, which is one embodiment of the present invention. Figures 13B to 13G show an equivalent circuit diagram of the semiconductor device 10E. Figure 14A shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 13A, and Figure 14B shows a cross-sectional view of the cross-section along the dashed-dotted line B3-B4. For a cross-sectional view of the cross-section along the dashed-dotted line B1-B2, refer to Figure 10B.

[0273] The semiconductor device 10E includes a transistor 100, a transistor 200C, an insulating layer 110, an insulating layer 214, and an insulating layer 109. The transistor 200C differs from the transistor 200 shown in Figure 10A, etc., in that it has a conductive layer 203.

[0274] The conductive layer 203 functions as the back gate electrode of the transistor 200C. The conductive layer 203 is provided between the semiconductor layer 208 and the substrate 102. An insulating layer 207 is provided so as to cover the top and side surfaces of the conductive layer 203, and the semiconductor layer 208 is provided on the insulating layer 207. The insulating layer 207 functions as the back gate insulating layer of the transistor 200C. The conductive layer 203 has a region that overlaps with the semiconductor layer 208 via the insulating layer 207. The conductive layer 203 also has a region that overlaps with the conductive layer 204 via the insulating layer 207, the semiconductor layer 208, and the insulating layer 206. The semiconductor layer 208 is sandwiched between a pair of gate electrodes (conductive layer 204 and conductive layer 203). The conductive layer 203 can use a material that can be used for the conductive layer 204, and the insulating layer 207 can use a material that can be used for the insulating layer 206.

[0275] The insulating layer 207 can be a single-layer structure or a multilayer structure. Furthermore, it is preferable that the insulating layer 207 has a barrier layer. For materials that can be used for the barrier layer, please refer to the above description. It is preferable that the insulating layer 207 be made of a material that does not easily allow impurities contained in the substrate 151 to diffuse. This suppresses the diffusion of impurities from the substrate 151 to the transistor. This improves the reliability of the semiconductor device. For example, the insulating layer 207 can be a multilayer structure of a silicon nitride film and a silicon oxynitride film on the silicon nitride film.

[0276] As shown in Figures 13A and 14A, it is preferable that the conductive layer 203 extends beyond the edge of the region where the conductive layer 204 and the semiconductor layer 208 overlap in the channel length direction of the transistor 200C. In other words, it is preferable that the size of the conductive layer 203 is larger than the size of the region where the conductive layer 204 and the semiconductor layer 208 overlap in the channel length direction. Specifically, it is preferable that the conductive layer 203 has a region that protrudes beyond the edge of the conductive layer 204 in the channel length direction.

[0277] As shown in Figure 14B, it is preferable that the conductive layer 204 and conductive layer 203 protrude outward from the edge of the semiconductor layer 208 in the channel width direction of the transistor 200. In this case, the entire channel width direction of the semiconductor layer 208 is covered by the conductive layer 204 and conductive layer 203 via the insulating layer 206 and insulating layer 207. With this configuration, the semiconductor layer 208 can be electrically surrounded by the electric field generated by the pair of gate electrodes.

[0278] Figures 13B and 13C show an example configuration in which the conductive layer 204 and the conductive layer 203 are not connected. For example, a constant potential can be applied to one of a pair of gate electrodes, and a signal for driving the transistor 200E can be applied to the other electrode. In this case, the threshold voltage when driving the transistor 200E with the other gate electrode can be controlled by the potential applied to one gate electrode.

[0279] The back gate of transistor 200E can be connected to either the source or the drain of transistor 200E. Figures 13D and 13E show a configuration in which the back gate of transistor 200E is connected to the other of the source and drain of transistor 200E. For example, by connecting the back gate to the source, fluctuations in the threshold voltage of transistor 200E can be suppressed, thereby improving reliability.

[0280] As shown in Figures 13F and 13G, the back gate of transistor 200E can be connected to the gate of transistor 200E. By applying the same potential to conductive layer 204 and conductive layer 203, an electric field for inducing a channel in semiconductor layer 208 can be effectively applied, thereby increasing the on-current of transistor 200E. As a result, the channel width of transistor 200E can be reduced, and the occupied area of ​​transistor 200E can also be reduced. For example, by providing openings in insulating layer 206 and insulating layer 207 that reach the conductive layer 203, and forming the conductive layer 204 so as to cover these openings, the conductive layer 204 can be configured to be in contact with the conductive layer 203 at these openings.

[0281] <Configuration Example 2> Figure 15A shows a top view of a semiconductor device 20, which is one embodiment of the present invention. Figures 15B and 15C show an equivalent circuit diagram of the semiconductor device 20. Figure 15D shows a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 15A, and Figure 2A shows a cross-sectional view of the section along the dashed-dotted line B1-B2. Figure 7A can be used to refer to the cross-sectional view of the section along the dashed-dotted line B1-B2, and Figure 2B can be used to refer to the cross-sectional view of the section along the dashed-dotted line B3-B4.

[0282] The semiconductor device 20 includes a transistor 100, a transistor 200D, an insulating layer 110, and an insulating layer 214. A detailed explanation of transistor 100 is omitted as it can be found in the previous description.

[0283] Transistor 200D differs from transistor 200 shown in Figure 1D, etc., mainly in that it has a conductive layer 112a instead of a conductive layer 112b. Transistor 200D has a conductive layer 204, an insulating layer 206, a semiconductor layer 208, a conductive layer 212a, and a conductive layer 112a. In transistor 200D, the conductive layer 212a functions as one of the source electrode and the drain electrode, and the conductive layer 112a functions as the other.

[0284] The conductive layer 112a functions as one of the source and drain electrodes of transistor 100, and as the other of the source and drain electrodes of transistor 200D. In other words, one of the source and drain electrodes of transistor 100 is connected to the other of the source and drain electrodes of transistor 200D. The conductive layer 112a is shared by transistor 100 and transistor 200D. As a result, there is no need to provide a separate conductive layer to connect one of the source and drain electrodes of transistor 100 to the other of the source and drain electrodes of transistor 200D, thus enabling a compact semiconductor device.

[0285] As shown in Figure 15B, transistor 100 can be an n-channel type and transistor 200D can be a p-channel type. Alternatively, as shown in Figure 15C, transistors 100 and 200 can each be n-channel types. Note that transistor 100 can also be a p-channel type.

[0286] The insulating layer 206 and the insulating layer 214 have openings 247a and 247b that reach region 208P. A conductive layer 212a is provided so as to cover opening 247a. The conductive layer 212a is in contact with region 208P at opening 247a and is connected to region 208P. A conductive layer 112a is provided so as to cover opening 247b. The conductive layer 112a is in contact with region 208P at opening 247b and is connected to region 208P.

[0287] The conductive layer 212a can be formed by processing the same conductive film as the conductive layer 112a. Therefore, the same material as the conductive layer 112a can be used for the conductive layer 212a. For example, after forming the insulating layer 206 and insulating layer 214 having openings 247a and 247b, a conductive film can be deposited to cover the openings 247a and 247b, and the conductive layer 212a and conductive layer 112a can be formed by processing the conductive film. Note that a different material from that used for the conductive layer 112a can also be used for the conductive layer 212a. An insulating layer 110 is provided on the conductive layer 212a, conductive layer 112a, and insulating layer 214.

[0288] By configuring the conductive layer 112a, which is the lower electrode of the VFET, to be in contact with region 208P, the number of insulating layers (in this case, insulating layer 214 and insulating layer 206) on which the openings 247a and 247b are provided can be reduced. This makes it easier to form the openings 247a and 247b, thereby increasing the productivity of semiconductor devices and reducing manufacturing costs. Furthermore, it is possible to improve the manufacturing yield in forming the openings 247a and 247b.

[0289] <Configuration Example 3> Figure 16A shows a top view of a semiconductor device 30, which is one embodiment of the present invention. Figures 16B and 16C show an equivalent circuit diagram of the semiconductor device 30. Figure 17A shows a cross-sectional view of the section along the dashed-dotted line A3-A4 shown in Figure 16A, and Figure 17B shows a cross-sectional view of the section along the dashed-dotted line B5-B6. For a cross-sectional view of the section along the dashed-dotted line B1-B2, refer to Figure 7A.

[0290] The semiconductor device 30 includes a transistor 100, a transistor 200E, an insulating layer 110, and an insulating layer 214. A detailed explanation of transistor 100 is omitted as it can be found in the previous description.

[0291] Transistor 200E differs from transistor 200 shown in Figure 1D, etc., mainly in that it has a conductive layer 212b instead of a conductive layer 112b. Transistor 200E has a conductive layer 204, an insulating layer 206, a semiconductor layer 208, a conductive layer 212a, and a conductive layer 212b. In transistor 200E, the conductive layer 212a functions as one of the source electrode and the drain electrode, and the conductive layer 212b functions as the other.

[0292] The insulating layer 206, insulating layer 214, and insulating layer 110 have openings 247a and 247b that reach region 208P. A conductive layer 212a is provided so as to cover opening 247a. The conductive layer 212a is in contact with region 208P at opening 247a and is connected to region 208P. A conductive layer 212b is provided so as to cover opening 247b. The conductive layer 212b is in contact with region 208P at opening 247b and is connected to region 208P.

[0293] The insulating layer 214 and the insulating layer 110 have openings 249 that reach the conductive layer 204. The conductive layer 112b is provided so as to cover the openings 249. The conductive layer 112b has a region that contacts the conductive layer 204 at the openings 249 and is connected to the conductive layer 204.

[0294] The source and drain of transistor 100 are connected to the gate of transistor 200E. Alternatively, as shown in Figure 16B, transistor 100 can be an n-channel type and transistor 200E can be a p-channel type. Or, as shown in Figure 16C, transistors 100 and 200E can each be n-channel types. Note that transistor 100 can also be a p-channel type.

[0295] The contact between the conductive layer 112b and the conductive layer 204 connects the source and drain of transistor 100 to the gate of transistor 200E. Because the contact between the conductive layer 112b and the conductive layer 204 eliminates the need to provide a separate conductive layer to connect them, the occupied area of ​​the semiconductor device 30 can be reduced.

[0296] The conductive layers 212a and 212b can be formed by processing the same conductive film as the conductive layer 112b. Therefore, the same materials as the conductive layer 112b can be used for the conductive layers 212a and 212b. However, different materials from those used for the conductive layer 112b can also be used for the conductive layers 212a and 212b.

[0297] <Configuration Example 4> Figure 18A shows a top view of a semiconductor device 40, which is one embodiment of the present invention. Figures 18B and 18C show an equivalent circuit diagram of the semiconductor device 40. Figure 19 shows a cross-sectional view of the section along the dashed-dotted line B5-B6 shown in Figure 18A. For a cross-sectional view of the section along the dashed-dotted line A3-A4, refer to Figure 17A, and for a cross-sectional view of the section along the dashed-dotted line B1-B2, refer to Figure 7A.

[0298] The semiconductor device 40 includes a transistor 100, a transistor 200E, an insulating layer 110, and an insulating layer 214. The semiconductor device 40 differs from the semiconductor device 30 shown in Figure 16A, etc., in that the conductive layer 112a is connected to the conductive layer 204 instead of the conductive layer 112b.

[0299] Detailed explanations of transistors 100 and 200E are omitted as they can be found in the previously mentioned description.

[0300] The insulating layer 214 has an opening 245 that reaches the conductive layer 204. The conductive layer 112a is provided so as to cover the opening 245. The conductive layer 112a is in contact with the conductive layer 204 at the opening 245 and is connected to the conductive layer 204.

[0301] One of the sources and drains of transistor 100 is connected to the gate of transistor 200E. Alternatively, as shown in Figure 18B, transistor 100 can be an n-channel type and transistor 200E can be a p-channel type. Or, as shown in Figure 18C, transistors 100 and 200E can each be n-channel types. Note that transistor 100 can also be a p-channel type.

[0302] The contact between the conductive layer 112a and the conductive layer 204 connects one of the sources and drains of the transistor 100 to the gate of the transistor 200E. Because the contact between the conductive layer 112a and the conductive layer 204 eliminates the need to provide a separate conductive layer to connect the conductive layer 112a and the conductive layer 204, the occupied area of ​​the semiconductor device 40 can be reduced.

[0303] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0304] (Embodiment 2) In this embodiment, a method for manufacturing a semiconductor device according to one aspect of the present invention will be described with reference to Figures 20A to 24C. Note that the description of the materials and formation methods of each element may be omitted if it is the same as that described in Embodiment 1.

[0305] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be deposited using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods. CVD methods include PECVD and thermal CVD. One type of thermal CVD is metal-organic vapor deposition (MOCVD).

[0306] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0307] When processing thin films that constitute semiconductor devices, lithography or similar methods can be used. Alternatively, thin films can be processed by nanoimprint lithography, sandblasting, lift-off methods, etc. Furthermore, island-shaped thin films can be directly formed by deposition methods using shielding masks such as metal masks.

[0308] There are two main methods of lithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0309] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other options include ultraviolet light, KrF laser light, or ArF laser light. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of the light source. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0310] For etching thin films, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0311] Here, an example of a method for manufacturing the semiconductor device 10B shown in Figures 10A to 10C will be explained using Figures 20A to 24C. Figures 20A to 24C show cross-sectional views between the dashed lines A1 and A2 shown in Figure 6A. Here, a configuration in which a metal oxide is used for semiconductor layer 108 and low-temperature polysilicon (LTPS) is used for semiconductor layer 208 will be explained as an example. When a metal oxide is used for semiconductor layer 208, refer to the description related to the formation of semiconductor layer 108.

[0312] First, a semiconductor film 208f, which will become the semiconductor layer 208, is deposited on the substrate 102 (Figure 20A). For example, an amorphous silicon film can be used as the semiconductor film 208f. The semiconductor film 208f can be deposited using sputtering or PECVD.

[0313] Next, the semiconductor film 208f is crystallized to form a semiconductor film 208F (Figure 20B). Examples of crystallization methods include solid-phase growth and laser crystallization. Examples of solid-phase growth methods include thermal crystallization using an electric heating furnace, lamp annealing crystallization using infrared light, and crystallization using a catalytic metal. These methods can also be used in combination. For example, after crystallizing the semiconductor film 208f using solid-phase growth, further irradiation with laser light can form a semiconductor film 208F with fewer defects and high crystallinity. Examples of laser light that can be used include excimer laser light using XeCl, the second harmonic of a YAG laser, or the third harmonic.

[0314] In this example, an example is shown in which an amorphous semiconductor film 208f is crystallized to form a crystalline semiconductor film 208F, but the present invention is not limited to this. A crystalline semiconductor film 208F can also be formed on a substrate 102.

[0315] Next, p-type impurities (acceptors) or n-type impurities (donors) are added to the semiconductor film 208F (hereinafter also referred to as channel doping). Channel doping can be performed selectively on the entire semiconductor film 208F or on a portion of the semiconductor film 208F. Examples of elements contained in p-type impurities include boron, aluminum, and gallium. Examples of elements contained in n-type impurities include phosphorus and arsenic.

[0316] Next, the semiconductor film 208F is processed to form island-shaped semiconductor layers 208 (Figure 20C).

[0317] Next, an insulating film 206f is formed to cover the semiconductor layer 208 and become the insulating layer 206. The insulating film 206f can be suitably formed using the PECVD method, sputtering method, or ALD method.

[0318] Next, a conductive film is formed on the insulating layer 206, and the conductive film is processed to form a conductive layer 204 (Figure 20D). Sputtering is preferably used to form the conductive film.

[0319] Next, using the conductive layer 204 as a mask, impurities are supplied to the semiconductor layer 208 via the insulating film 206f. This forms region 208P (Figure 20E). For supplying impurities, plasma ion doping or ion implantation can be suitably used, for example. For n-channel transistors, n-type impurities (e.g., phosphorus and arsenic) are supplied. For p-channel transistors, p-type impurities (e.g., boron, aluminum, and gallium) are supplied. Although an example of supplying impurities to the conductive layer 204 as a mask has been shown, the present invention is not limited to this. The resist mask used to form the conductive layer 204 can be used as a mask to supply impurities. After that, the resist mask is removed.

[0320] In the case of transistor 200B shown in Figures 12A and 12B, impurities are supplied to region 208P without going through the insulating layer 206, and to region 208Q via the insulating layer 206. This allows for the formation of an LDD region between the channel formation region and region 208P of the semiconductor layer 208. By providing an LDD region, hot carrier degradation can be suppressed.

[0321] In the case of transistor 200A shown in Figure 11A, impurities are supplied to region 208P without going through the insulating layer 206. Plasma treatment can preferably be used to supply the impurities.

[0322] Next, it is preferable to perform an activation treatment. For the activation treatment, heat treatment or laser irradiation can be used. The activation treatment can lower the electrical resistance of region 208P, repair defects in the semiconductor layer 208 that occurred during the supply of impurities, and restore crystallinity. The activation treatment can also be combined with a subsequent heat treatment or heat-applying step. Furthermore, the activation treatment can be a combination of heat treatment and laser irradiation.

[0323] Next, an insulating film 214f, which will become the insulating layer 214, is deposited on the conductive layer 204 and the insulating film 206f (Figure 20F). The insulating film 214f ​​can be deposited using the PECVD method, sputtering method, or ALD method. When silicon is used for the semiconductor layer 208, it is preferable to deposit the insulating film 214f ​​using a deposition gas containing hydrogen.

[0324] Next, it is preferable to perform a heat treatment. This allows the hydrogen contained in the insulating film 214f ​​to diffuse into the semiconductor layer 208, and the dangling bonds of the semiconductor layer 208 can be terminated (hydrogenated, hydrogen-terminated) by the hydrogen. The heat treatment can be carried out in an atmosphere containing one or more of hydrogen, nitrogen, and noble gases. In particular, performing the heat treatment in a hydrogen-containing atmosphere is preferable because it allows for efficient hydrogen termination of the dangling bonds. This heat treatment can also be combined with a later heat treatment or a step in which heat is applied.

[0325] Next, an insulating film 109f, which will become the insulating layer 109, is deposited on the insulating film 214f ​​(Figure 20G). Sputtering or PECVD can be suitably used to deposit the insulating film 109f.

[0326] Next, a conductive film is formed on the insulating film 109f, and the conductive film is processed to form a conductive layer 112a (Figure 21A). Sputtering is preferably used to form the conductive film.

[0327] Next, an insulating film 110af, which will become the insulating layer 110a, and an insulating film 110bf, which will become the insulating layer 110b, are formed on the conductive layer 112a and the insulating film 109f (Figure 21B).

[0328] The insulating film 110af and insulating film 110bf can preferably be deposited using sputtering or PECVD. It is preferable to deposit insulating film 110bf without exposing the surface of insulating film 110af to the atmosphere after depositing insulating film 110af. This suppresses the adhesion of airborne impurities to the surface of insulating film 110af. Examples of such impurities include water and organic matter. For example, it is preferable to deposit insulating film 110bf continuously using the same apparatus after depositing insulating film 110af.

[0329] The substrate temperature during the deposition of insulating film 110af and insulating film 110bf is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. By setting the substrate temperature during the deposition of insulating film 110af and insulating film 110bf within the above range, the amount of impurities (e.g., water and hydrogen) released from the film itself can be reduced, and the diffusion of impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0330] It is preferable to perform a heat treatment after forming the insulating film 110af and insulating film 110bf. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating film 110af and from the insulating film 110bf and from its surface.

[0331] It is preferable to supply oxygen to the insulating film 110bf after it has been formed. By supplying oxygen to the insulating film 110bf (later the insulating layer 110b), oxygen can later be supplied from the insulating layer 110b to the semiconductor layer 108, thereby eliminating oxygen deficiencies and V in the semiconductor layer 108. Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0332] As a method of supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. As a plasma treatment, a device that converts a gas into plasma using high-frequency power can be suitably used. Examples of devices that convert a gas into plasma using high-frequency power include PECVD devices, plasma etching devices, and plasma ashing devices. Plasma treatment is preferably carried out in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N) ２ O), Nitrogen dioxide (NO) ２It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following: carbon monoxide and carbon dioxide. The amount of oxygen supplied can be adjusted, for example, by the power and processing time in the plasma treatment. Figure 21C schematically shows, with arrows, how oxygen is supplied to the insulating film 110bf.

[0333] It is preferable to supply nitrogen to the insulating film 110bf after the insulating film 110bf has been formed. For the method of supplying nitrogen, refer to the description of the oxygen supply method described above. Plasma treatment in a nitrogen-containing atmosphere can be suitably used as the method of supplying nitrogen. For example, nitrogen, nitrous oxide (N) ２ O), and nitrogen dioxide (NO) ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following. The amount of nitrogen supplied can be adjusted, for example, by the power and treatment time in the plasma treatment.

[0334] In the insulating layer (here, insulating film 110bf or the later insulating layer 110b), nitrogen oxides (NOx) are formed by the reaction of nitrogen and oxygen. Ｘ (where X is a real number greater than 0) is produced. For example, nitrogen oxides are produced. ２ O, NO and NO ２ For example, in the insulating layer, nitrogen oxides form energy levels, which are located within the band gap of the metal oxide. ２ The transition level at which the charge of 0 transitions between the -1 state lies within the band gap of indium oxide. Therefore, nitrogen oxides (e.g., NO) ２ When a negative charge (also called a negative fixed charge) diffuses to or near the interface between the insulating layer and the semiconductor layer having a metal oxide, that level traps electrons. As a result, a negative charge (also called a negative fixed charge) is formed at or near the interface between the insulating layer and the semiconductor layer, which can increase the threshold voltage of the transistor in the positive direction. This allows for a normally-off transistor and a semiconductor device with low power consumption.

[0335] The order in which oxygen is supplied and nitrogen is supplied is not particularly limited. Oxygen can be supplied after nitrogen. Nitrogen can be supplied after oxygen. Alternatively, oxygen and nitrogen can be supplied in the same process. For example, oxygen and nitrogen can be supplied by performing plasma treatment in an atmosphere containing nitrogen and oxygen. For example, nitrous oxide (N) ２ Plasma treatment using O) is preferable because it allows for efficient generation of nitrogen oxides.

[0336] Furthermore, it is preferable to perform the plasma treatment without exposing the surface of the insulating film 110bf to the atmosphere after the insulating film 110bf has been deposited. For example, when a PECVD apparatus is used to deposit the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can increase productivity. Specifically, after depositing the insulating film 110bf in the PECVD apparatus, it is preferable to perform the plasma treatment continuously in N ２ It can perform plasma processing.

[0337] Next, it is preferable to deposit a film 130 on the insulating film 110bf (Figure 21D). Sputtering is preferably used to deposit the film 130. By depositing the film 130 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf.

[0338] The conductivity of the film 130 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 130. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, ITO, or ITSO can be used as the film 130.

[0339] It is preferable to use an oxide containing one or more of the same elements as the semiconductor layer 108 as the film 130. In particular, it is preferable to use a metal oxide applicable to the semiconductor layer 108. This allows the equipment used for forming the semiconductor layer 108 and the film 130 to be common, thereby increasing productivity and lowering manufacturing costs.

[0340] The higher the oxygen flow rate ratio of the film-forming gas in the film formation of the film 130 or the oxygen partial pressure in the processing chamber, the more oxygen can be supplied into the insulating film 110bf. The oxygen flow rate ratio is preferably, for example, 50% or more and 100% or less, more preferably 60% or more and 100% or less, still more preferably 70% or more and 100% or less, still more preferably 80% or more and 100% or less, and still more preferably 90% or more and 100% or less. Typically, the oxygen flow rate ratio can be set to 100%. Note that the oxygen flow rate ratio can be read as the ratio of the oxygen partial pressure to the pressure in the processing chamber.

[0341] Thus, by forming the film 130 by sputtering in an oxygen-containing atmosphere, it is possible to supply oxygen to the insulating film 110bf and prevent oxygen from desorbing from the insulating film 110bf during the film formation of the film 130. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and V Ｏ H in the semiconductor layer 108 can be reduced, and a transistor having good electrical characteristics and high reliability can be obtained.

[0342] After forming the film 130, it is preferable to perform a heat treatment. By performing a heat treatment after forming the film 130, oxygen can be effectively supplied from the film 130 to the insulating film 110bf.

[0343] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, and oxygen. Dry air (CDA: Clean Dry Air) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 110af and insulating film 110bf as much as possible. Heat treatment can be carried out using an oven, a rapid thermal annealing (RTA) device, etc. Using an RTA device can shorten the heat treatment time.

[0344] After the film 130 is formed, or after the aforementioned heat treatment, oxygen can be further supplied to the insulating film 110bf via the film 130. For example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used as methods for supplying oxygen. A detailed explanation of plasma treatment is omitted here, as it can be found in the previous description.

[0345] Next, the film 130 is removed. There are no particular limitations on the method for removing the film 130, but a wet etching method can be suitably used. By using a wet etching method, etching of the insulating film 110bf during the removal of the film 130 can be suppressed. This prevents the thickness of the insulating film 110bf from becoming thinner, and the thickness of the insulating layer 110b can be made uniform.

[0346] The process of supplying oxygen to the insulating film 110bf is not limited to the methods described above. For example, oxygen can be supplied to the insulating film 110bf by ion doping, ion implantation, or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through the film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0347] Next, an insulating film 110cf, which will become the insulating layer 110c, is deposited on the insulating film 110bf (Figure 22A). For the deposition of the insulating film 110cf, refer to the description related to the deposition of the insulating film 110af.

[0348] When an oxide or oxidized nitride is used for the insulating layer 110c, oxygen can be supplied to the insulating film 110bf by depositing the insulating film 110cf in an oxygen-containing atmosphere. Sputtering is preferably used for depositing the insulating film 110cf. For example, an aluminum oxide film can be deposited as the insulating film 110cf using an aluminum target in an oxygen-containing atmosphere by sputtering. The higher the oxygen flow rate ratio of the deposition gas or the oxygen partial pressure in the processing chamber during the deposition of the insulating film 110cf, the more oxygen can be supplied to the insulating film 110bf. The oxygen flow rate ratio is preferably 50% to 100%, more preferably 60% to 100%, more preferably 70% to 100%, more preferably 80% to 100%, and more preferably 90% to 100%. Typically, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure as close to 100% as possible.

[0349] By depositing the insulating film 110cf in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf during the deposition of the insulating film 110cf, while preventing oxygen from being released from the insulating film 110bf. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0350] After forming the insulating film 110cf, a heat treatment can also be performed. By performing a heat treatment after forming the insulating film 110cf, oxygen can be effectively supplied from the insulating film 110cf to the insulating film 110bf.

[0351] Next, insulating films 206f, 214f, 109f, 110af, 110bf, and 110cf are partially removed to form openings 247a and 247b that reach region 208P (Figure 22B). This forms insulating layers 206, 214, 109, 110A, 110B, and 110C. Insulating layers 110A, 110B, and 110C later become insulating layers 110a, 110b, and 110c.

[0352] Next, a conductive film 112bf is formed to cover the insulating layer 110C, the openings 247a and 247b, and to form the conductive layer 112b and conductive layer 212a (Figure 22C). Sputtering is preferably used to form the conductive film 112bf.

[0353] Next, the conductive film 112bf is processed to form conductive layer 112B and conductive layer 212a (Figure 22D). Conductive layer 112B later becomes conductive layer 112b. Wet etching can be suitably used to form conductive layer 112B and conductive layer 212a.

[0354] Next, a resist mask 180 is formed on the insulating layer 110C, the conductive layer 212a, and the conductive layer 112B (Figure 23A). The resist mask 180 has an opening 183 in the region where the opening 145 is provided. The opening 183 is provided in a region that overlaps with a part of the edge of the conductive layer 112B.

[0355] Next, the resist mask 180 is used as a mask to process the insulating layer 110A, insulating layer 110B, insulating layer 110C, and conductive layer 112B to form an opening 145 that reaches the conductive layer 112a (Figure 23B). This forms an insulating layer 110 having insulating layers 110a, 110b, and 110c, and a conductive layer 112b. At this time, a notch 148 may be formed in the conductive layer 112b (see Figure 8B). For example, a wet etching method can be suitably used to form the conductive layer 112b. For example, a dry etching method can be suitably used to form the insulating layer 110.

[0356] Next, remove the resist mask 180.

[0357] Next, a metal oxide film 108f, which will become a semiconductor layer 108, is formed to cover the conductive layer 112a, conductive layer 112b, conductive layer 212a and insulating layer 110 (Figure 23C). The metal oxide film 108f is provided in contact with the upper surface of the conductive layer 112a, the upper and side surfaces of the conductive layer 112b, the upper and side surfaces of the conductive layer 212a, and the upper and side surfaces of the insulating layer 110.

[0358] The metal oxide film 108f is preferably deposited by sputtering using a metal oxide target. Alternatively, the metal oxide film 108f is preferably deposited by the ALD method. By using the ALD method, the metal oxide film can be deposited with high coverage on the sides of the insulating layer 110 and the conductive layer 112b. Furthermore, since the deposition rate of the ALD method is easy to control, thin films can be deposited with good yield. Therefore, the ALD method is particularly suitable when the thickness of the metal oxide film 108f is thin. In addition, the CVD method can be used to deposit the metal oxide film 108f.

[0359] It is preferable that the metal oxide film 108f be a dense film with as few defects as possible. Furthermore, it is preferable that the metal oxide film 108f is a high-purity film with as few hydrogen element impurities as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0360] It is preferable to use oxygen gas when forming the metal oxide film 108f. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or oxidizride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0361] By supplying oxygen to the insulating layer 110b, oxygen is supplied to the semiconductor layer 108 in a later process, eliminating oxygen deficiencies and V in the semiconductor layer 108. Ｏ H can be reduced.

[0362] When forming the metal oxide film 108f, a mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used. The higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas used to form the metal oxide film, the higher the crystallinity of the metal oxide film can be, resulting in a more reliable transistor. Conversely, the lower the oxygen flow rate ratio or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, resulting in a transistor with a large on-current.

[0363] The higher the substrate temperature during metal oxide film deposition, the higher the crystallinity and density of the resulting metal oxide film. This allows for the creation of highly reliable transistors. Conversely, the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the resulting metal oxide film. This allows for the creation of transistors with high on-current.

[0364] The substrate temperature during the deposition of the metal oxide film 108f is preferably between room temperature (e.g., 25°C) and 250°C, more preferably between room temperature and 200°C, and even more preferably between room temperature and 140°C. For example, setting the substrate temperature to between room temperature and 140°C is preferable as it increases productivity. Furthermore, crystallinity can be reduced by depositing the metal oxide film at room temperature or without heating the substrate.

[0365] When using the ALD method, it is preferable to use a film deposition method such as the thermal ALD method or the PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferred because it exhibits extremely high coverage. The PEALD method is preferred because, in addition to exhibiting high coverage, it allows for low-temperature film deposition.

[0366] Metal oxide films can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

[0367] For example, when depositing an indium oxide film, an indium-containing precursor can be used. When depositing an In-Ga-Zn oxide film, three precursors can be used: an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor. Alternatively, two precursors can be used: an indium-containing precursor and precursors containing both gallium and zinc.

[0368] Examples of indium precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) chloride, [3-(dimethylamino)propyl]dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

[0369] Examples of gallium-containing precursors include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0370] Examples of aluminum-containing precursors include aluminum chloride and trimethylaluminum.

[0371] Examples of tin-containing precursors include tin(IV) chloride and tetrakis(dimethylamide)tin.

[0372] Examples of zinc-containing precursors include dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid) zinc, and zinc chloride.

[0373] Examples of oxidizing agents include ozone, oxygen, hydrogen peroxide, and water.

[0374] Methods for controlling the composition of the resulting film include adjusting one or more of the type of raw material gas, the flow rate ratio of the raw material gases, the duration for which the raw material gases are flowed, and the order in which the raw material gases are flowed. By adjusting these factors, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these factors, it is also possible to deposit a metal oxide film 108f with a continuously changing composition.

[0375] Before forming the metal oxide film 108f, it is preferable to perform at least one of the following: a treatment to desorb impurities (e.g., water, hydrogen, and organic matter) adsorbed on the surface of the insulating layer 110, and a treatment to supply oxygen into the insulating layer 110. For example, a heat treatment can be performed in a reduced-pressure atmosphere at a temperature of 70°C to 200°C. Alternatively, a plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, nitrous oxide (N) can be used. ２Plasma treatment in an atmosphere containing an oxidizing gas such as 0) can supply oxygen to the insulating layer 110. Plasma treatment in an atmosphere containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 110 while supplying oxygen. After such treatment, it is preferable to continuously form a metal oxide film 108f without exposing the surface of the insulating layer 110 to the atmosphere.

[0376] Furthermore, when the semiconductor layer 108 is a stacked structure, it is preferable to deposit the metal oxide film to be deposited first, and then continuously deposit the next metal oxide film without exposing its surface to the atmosphere.

[0377] When the semiconductor layer 108 has a stacked structure, all layers constituting the semiconductor layer 108 can be deposited using the same method (for example, sputtering or ALD). Alternatively, different deposition methods can be used for each layer. For example, the first metal oxide layer can be deposited by sputtering, and the second metal oxide layer can be deposited by ALD.

[0378] Next, the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 (Figure 24A).

[0379] The semiconductor layer 108 can preferably be formed using a wet etching method. In this case, regions of the insulating layer 110, conductive layer 112a, conductive layer 112b, and conductive layer 212a that do not overlap with the semiconductor layer 108 may be etched, resulting in a reduction in their thickness.

[0380] It is preferable to perform a heat treatment after the metal oxide film 108f has been formed, or after the metal oxide film 108f has been processed into a semiconductor layer 108. The heat treatment can remove impurities (e.g., water, hydrogen, and organic matter) contained in the metal oxide film 108f or the semiconductor layer 108, or adsorbed on the surface. In addition, the heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (e.g., reduce defects or increase crystallinity).

[0381] Oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108 by heat treatment. Since the description of the heat treatment can be referred to the above description, the detailed explanation is omitted.

[0382] If the heat treatment is not necessary, it may not be performed. Also, here the heat treatment is not performed and can be combined with the heat treatment performed in a later process. Also, a process in which heat is applied in a later process (for example, a film forming process) may also serve as the heat treatment.

[0383] Subsequently, an insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the insulating layer 110 (FIG. 24B). For forming the insulating layer 106, for example, the PECVD method, the sputtering method, or the ALD method can be preferably used.

[0384] When a metal oxide is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier layer that suppresses the diffusion of oxygen. By the insulating layer 106 functioning as a barrier layer, the desorption of oxygen from the semiconductor layer 108 is suppressed, and the increase in oxygen deficiency (V Ｏ ) in the semiconductor layer 108 can be suppressed. Also, the oxygen in the semiconductor layer 108 is suppressed from diffusing to the conductive layer 104 through the insulating layer 106, and the oxidation of the conductive layer 104 can be suppressed. As a result, a transistor with good electrical characteristics and high reliability can be obtained.

[0385] By increasing the temperature during the formation of the insulating layer 106 that functions as a gate insulating layer, an insulating layer with fewer defects can be obtained. However, if the temperature during the formation of the insulating layer 106 is high, oxygen desorbs from the semiconductor layer 108, and oxygen deficiency and V in the semiconductor layer 108 ＯThere may be a case where H increases. The substrate temperature during the formation of the insulating layer 106 is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, still more preferably 250°C or higher and 450°C or lower, still more preferably 300°C or higher and 450°C or lower, and still more preferably 300°C or higher and 400°C or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced, and the desorption of oxygen from the semiconductor layer 108 can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0386] Before forming the insulating layer 106, it is preferable to perform plasma treatment on the surface of the semiconductor layer 108. By this plasma treatment, impurities such as water adsorbed on the surface of the semiconductor layer 108 can be reduced. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. In particular, it is suitable when the surface of the semiconductor layer 108 is exposed to the atmosphere from the formation of the semiconductor layer 108 to the formation of the insulating layer 106. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, etc. Also, it is preferable that the plasma treatment and the formation of the insulating layer 106 are continuously performed without being exposed to the atmosphere.

[0387] Subsequently, a conductive layer 104 is formed on the insulating layer 106 (FIG. 24C). For forming the conductive film that becomes the conductive layer 104, for example, a sputtering method, a thermal CVD method (including MOCVD method), or an ALD method can be preferably used.

[0388] Subsequently, an insulating layer 218 is formed (FIG. 10A).

[0389] Through the above steps, the semiconductor device 10B of one embodiment of the present invention can be manufactured.

[0390] (Embodiment 3) In this embodiment, an indium oxide film that can be used for the semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0391] In this specification and the like, indium oxide having at least a crystal part or a crystal region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). For example, examples of crystal IO or crystalline IO include single crystal indium oxide, polycrystalline indium oxide, microcrystalline indium oxide, and the like.

[0392] Indium oxide is a semiconductor material having physical properties completely different from those of oxide semiconductors such as In—Ga—Zn oxide (IGZO) and zinc oxide.

[0393] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO will be described.

[0394] IGZO shows a tendency that the hole mobility increases as the carrier concentration increases. On the other hand, single crystal indium oxide shows a tendency that the hole mobility increases as the carrier concentration decreases. This tendency is the same as that of silicon. That is, as the concentration of dopants (impurities) in the material decreases, impurity scattering decreases and the hole mobility increases. That is, the higher the purity and intrinsic nature of single crystal indium oxide, the higher the hole mobility. From this result, it can be said that single crystal indium oxide has physical properties similar to those of silicon, unlike IGZO. When indium oxide is non-single crystal (for example, polycrystalline), the tendency may be different from that of single crystal.

[0395] The range of the carrier concentration suitable for the channel formation region of the transistor is a range including 1×10 １５ cm −３ For example, it is a range of 1×10 １４ cm −３ or more and 1×10 １８ cm −３ or less. By sufficiently reducing the carrier concentration, it can be expected that the value of the hole mobility can be increased to about 270 cm ２ / (V·s).

[0396] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0397] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the electrical resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0398] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0399] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0400] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0401] Polycrystalline films are preferred over microcrystalline or amorphous films because they can reduce carrier scattering and exhibit high field-effect mobility. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0402] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0403] In this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel-forming region can be considered as a single crystal film.

[0404] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation in the channel length direction of the semiconductor layer (for example, cross-sectional observation including the semiconductor layer, source electrode, and drain electrode).

[0405] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0406] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0407] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0408] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0409] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0410] Indium oxide films allow hydrogen to diffuse. Hydrogen diffusing into an indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0411] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰−２１ A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0412] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) can also be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0413] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0414] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0415] Typically, indium oxide crystals have a cubic structure (bixbite type), while yttria-stabilized zirconia (YSZ) crystals have a cubic structure (fluorite type). The lattice mismatch of indium oxide crystals with respect to cubic YSZ crystals is in the range of -2% to 2%, allowing for the epitaxial growth of indium oxide single crystal films on YSZ substrates.

[0416] Note that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not have the same crystal system or crystal orientation. For example, a film having a crystal with a hexagonal crystal structure or a trigonal crystal structure can be used under an indium oxide film having a crystal with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the lower surface of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. As crystals of the hexagonal crystal system or the trigonal crystal system, for example, wurtzite structure, YbFe ２ O ４ type structure, Yb ２ Fe ３ O ７ type structure, and modified forms of these are available. As an example of a crystal having a YbFe ２ O ４ type structure or a Yb ２ Fe ３ O ７ type structure, IGZO etc. are mentioned.

[0417] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0418] (Embodiment 4) In this embodiment, a display device according to one aspect of the present invention will be described using FIGS. 25A to 47.

[0419] The display device of this embodiment can be a display device with high resolution or a large display device. Therefore, the display device of this embodiment can be used, for example, in electronic devices having a relatively large screen such as television devices, desktop or notebook computers, monitors for computers, digital signage, and large game machines such as pachinko machines, as well as in display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, and audio playback devices.

[0420] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0421] A semiconductor device according to one aspect of the present invention can be used as a display device or a module having said display device. Examples of modules having said display devices include a module to which a connector such as an FPC or TCP is attached, and a module on which ICs are mounted using a COG method or COF method.

[0422] The display device of this embodiment may also function as a touch panel. For example, the display device can be fitted with various detection elements (also called sensor elements) that can detect the proximity or contact of an object to be detected, such as a finger.

[0423] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0424] Examples of capacitance methods include surface capacitance and projected capacitance. Furthermore, projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferable because it enables simultaneous multi-point detection.

[0425] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel refers to a configuration in which electrodes constituting the sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0426] <Example of Display Device Configuration 1> Figure 25A shows a perspective view of the display device 50A.

[0427] The display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In Figure 25A, substrate 152 is shown with a dashed line.

[0428] The display device 50A includes a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, etc. Figure 25A shows an example in which the IC 173 and FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Figure 25A can also be described as a display module having the display device 50A, an IC, and an FPC.

[0429] The connection portion 140 is provided on the outside of the display unit 162. The connection portion 140 can be provided along one or more sides of the display unit 162. There can be one or more connection portions 140. Figure 25A shows an example in which the connection portion 140 is provided so as to surround all four sides of the display unit 162. The connection portion 140 connects the common electrode of the display element to the conductive layer, and can supply potential to the common electrode.

[0430] The circuit section 164 includes, for example, a scan line drive circuit (also called a gate driver). Alternatively, the circuit section 164 can be configured to include both a scan line drive circuit and a signal line drive circuit (also called a source driver).

[0431] The conductive layer 165 has the function of supplying signals and power to the display unit 162 and the circuit unit 164. These signals and power are input to the conductive layer 165 from the outside via the FPC 172, or from the IC 173.

[0432] Figure 25A shows an example in which IC 173 is mounted on the substrate 151 using the COG method. IC 173 can be an IC having, for example, one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module can be configured without an IC. Furthermore, the IC can be mounted on the FPC using the COF method or the like.

[0433] A semiconductor device according to one embodiment of the present invention can be applied to either or both of the display unit 162 and the circuit unit 164. By using a semiconductor device according to one embodiment of the present invention in the display unit 162, the occupied area of ​​the pixel circuit can be reduced, and the pixel size can be reduced, resulting in a high-definition display device. Furthermore, by using a semiconductor device according to one embodiment of the present invention in the circuit unit 164, the occupied area of ​​the circuit unit 164 can be reduced, resulting in a narrow-bezel display device. In addition, since the semiconductor device according to one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0434] The display device of this embodiment can use either or both of the OS transistor and the Si transistor.

[0435] By using OS transistors, it is possible to create a display device with low power consumption. Furthermore, by using OS transistors for all the transistors in the display device, manufacturing costs can be kept low.

[0436] To increase the luminescence brightness of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to Si transistors, OS transistors have a higher breakdown voltage between the source and drain, so a higher voltage can be applied to the source-drain of an OS transistor. Therefore, by using an OS transistor as the drive transistor in the pixel circuit, the amount of current flowing through the light-emitting element can be increased, thereby increasing the luminescence brightness of the light-emitting element.

[0437] When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage than a Si transistor. Therefore, by using an OS transistor as the driving transistor in a pixel circuit, the current flowing between the source and drain can be precisely controlled by the change in gate-source voltage, thereby allowing control of the current flowing to the light-emitting element. This allows for an increase in the number of grayscale levels in the pixel circuit.

[0438] In terms of the saturation of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be supplied to a light-emitting element even if there are variations in the current-voltage characteristics of the light-emitting element. In other words, when operating in the saturation region, OS transistors can stabilize the luminescence brightness of a light-emitting element because the change in source-drain current is small even when the source-drain voltage is changed.

[0439] The transistors in the circuit unit 164 and the transistors in the display unit 162 can have the same structure or different structures. The structures of the multiple transistors in the circuit unit 164 can all be the same or there can be two or more types. Similarly, the structures of the multiple transistors in the display unit 162 can all be the same or there can be two or more types.

[0440] All of the transistors in the display unit 162 can be OS transistors, or all of the transistors in the display unit 162 can be Si transistors. Alternatively, some of the transistors in the display unit 162 can be OS transistors and the rest can be Si transistors.

[0441] For example, by using both an LTPS transistor and an OS transistor in the display unit 162, a display device with low power consumption and high driving capability can be realized. Furthermore, a configuration combining an LTPS transistor and an OS transistor is sometimes referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used for transistors that function as switches to control conduction and non-conduction between wires, and an LTPS transistor is used for transistors that control current.

[0442] For example, one of the transistors in the display unit 162 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a drive transistor. One of the source and drain of the drive transistor is connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor for the drive transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.

[0443] On the other hand, the other transistor in the display unit 162 functions as a switch for controlling the selection and deselection of pixels, and can also be called a selection transistor. The gate of the selection transistor is connected to the gate line, and one of the source and drain is connected to the source line (signal line). It is preferable to use an OS transistor for the selection transistor. This makes it possible to maintain the gradation of pixels even when the frame frequency is significantly low (for example, 1 fps or less), and thus power consumption can be reduced by stopping the driver when displaying a still image.

[0444] The display unit 162 is the area in the display device 50A that displays images, and has a plurality of pixels 210 arranged periodically. Figure 25A shows an enlarged view of one pixel 210.

[0445] The pixel 210 shown in Figure 25A has a pixel 230R that emits red (R) light, a pixel 230G that emits green (G) light, and a pixel 230B that emits blue (B) light. Full-color display can be achieved by configuring one pixel 210 with pixels 230R, 230G, and 230B. Pixels 230R, 230G, and 230B each function as sub-pixels. Furthermore, the display device 50A shown in Figure 25A shows an example in which the sub-pixels 230R, 230G, and 230B are arranged in a stripe pattern. The number of sub-pixels that make up one pixel 210 is not limited to three, but can be four or more. For example, a configuration can be made with four sub-pixels that emit four colors of light: R, G, B, and white (W). Alternatively, a configuration can be made with four sub-pixels that emit four colors of light: R, G, B, and yellow (Y).

[0446] Each pixel 230R, pixel 230G, and pixel 230B includes a display element and a circuit that controls the driving of the display element.

[0447] Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used. Furthermore, QLEDs (Quantum-dot LEDs) using a light source and color conversion technology using quantum dot materials can be used.

[0448] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, mini-LEDs and micro-LEDs can be used as LEDs.

[0449] The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0450] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0451] Furthermore, a display device according to one aspect of the present invention may be any of the following: a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed; a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed; or a dual-emission type that emits light on both sides.

[0452] Figure 25B is a block diagram illustrating the display device 50A. The display device 50A has a display unit 162 and a circuit unit 164. The display unit 162 has a plurality of periodically arranged pixels 230 (pixels 230[1,1] to pixels 230[m,n], where m and n are each independent integers of 2 or more). The circuit unit 164 has a first drive circuit unit 231 and a second drive circuit unit 232.

[0453] The circuit included in the first drive circuit section 231 functions, for example, as a scan line drive circuit (also called a gate line drive circuit, gate driver, scan driver, or low driver). The circuit included in the second drive circuit section 232 functions, for example, as a signal line drive circuit (also called a source line drive circuit, source driver, data driver, or column driver). A circuit may be provided at a position facing the first drive circuit section 231 across the display section 162. A circuit may be provided at a position facing the second drive circuit section 232 across the display section 162.

[0454] The circuit section 164 can utilize various circuits, including shift register circuits, level shifter circuits, inverter circuits, latch circuits, analog switch circuits, demultiplexer circuits, and logic circuits. The circuit section 164 can also utilize transistors and capacitive elements. The transistors in the circuit section 164 can be formed using the same process as the transistors in the pixel 230.

[0455] The display device 50A includes wiring 236, each arranged in parallel or approximately parallel, and whose potential is controlled by a circuit included in the first drive circuit unit 231, and wiring 238, each arranged in parallel or approximately parallel, and whose potential is controlled by a circuit included in the second drive circuit unit 232. Figure 25B shows an example in which wiring 236 and wiring 238 are connected to a pixel 230. However, wiring 236 and wiring 238 are just examples, and the wiring connected to the pixel 230 is not limited to wiring 236 and wiring 238.

[0456] In Figure 25B, the direction in which wiring 236 extends is sometimes referred to as the row direction, and the direction in which wiring 238 extends is sometimes referred to as the column direction. While the horizontal direction in the drawing is generally considered the row direction and the vertical direction the column direction, this is not the only way to represent the row and column directions; they can be interchanged.

[0457] A pixel layout different from that shown in Figure 25A will be described. There are no particular limitations on the arrangement of subpixels in the display device of this embodiment, and various methods can be applied. Examples of subpixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0458] In this embodiment, the top surface shape of the subpixel shown in the figure corresponds to the top surface shape of the light-emitting region (or light-receiving region).

[0459] The top surface shape of the sub-pixels may include, for example, polygons such as triangles, quadrilaterals (including rectangles and squares), pentagons, polygons with rounded corners, ellipses, or circles.

[0460] The circuit layout that constitutes the subpixel is not limited to the subpixel area shown in the figure, but can also be arranged outside of it.

[0461] The pixel 210 shown in Figure 26A has an S-stripe array applied to it. The pixel 210 shown in Figure 26A is composed of three subpixels: subpixel 230a, subpixel 230b, and subpixel 230c.

[0462] The pixel 210 shown in Figure 26B includes sub-pixels 230a with a roughly trapezoidal or triangular top surface shape with rounded corners, sub-pixels 230b with a roughly trapezoidal or triangular top surface shape with rounded corners, and sub-pixels 230c with a roughly square or hexagonal top surface shape with rounded corners. Furthermore, sub-pixel 230b has a larger light-emitting area than sub-pixel 230a. In this way, the shape and size of each sub-pixel can be determined independently. For example, sub-pixels with more reliable light-emitting devices can be made smaller in size.

[0463] A Pentile array is applied to pixels 240a and 240b shown in Figures 26C and 26D. Figures 26C and 26D show an example in which pixels 240a having sub-pixels 230a and 230b, and pixels 240b having sub-pixels 230b and 230c are arranged alternately.

[0464] Pixels 240a and 240b shown in Figures 26E to 26G have a delta array applied. Pixel 240a has two subpixels (subpixels 230a and 230b) in the top row (1st row) and one subpixel (subpixel 230c) in the bottom row (2nd row). Pixel 240b has one subpixel (subpixel 230c) in the top row (1st row) and two subpixels (subpixels 230a and 230b) in the bottom row (2nd row).

[0465] Figure 26E shows an example where each subpixel has a roughly square top shape with rounded corners, Figure 26F shows an example where each subpixel has a circular top shape, and Figure 26G shows an example where each subpixel has a roughly hexagonal top shape with rounded corners.

[0466] In Figure 26G, each subpixel is located inside a densely arranged hexagonal region. When focusing on one subpixel, it is arranged so that it is surrounded by six other subpixels. Furthermore, subpixels that emit light of the same color are not adjacent to each other. For example, when focusing on subpixel 230a, three subpixels 230b and three subpixels 230c are arranged alternately around it.

[0467] Figure 26H shows an example where the subpixels of each color are arranged in a zigzag pattern. Specifically, in a top view, the upper edges of two subpixels aligned in the row direction (for example, subpixels 230a and 230b, or subpixels 230b and 230c) are offset.

[0468] In each pixel shown in Figures 26A to 26H, it is preferable, for example, that sub-pixel 230a be sub-pixel R that emits red light, sub-pixel 230b be sub-pixel G that emits green light, and sub-pixel 230c be sub-pixel B that emits blue light. However, the configuration of the sub-pixels is not limited to this, and the colors emitted by the sub-pixels and their order can be determined as appropriate. For example, sub-pixel 230b can be sub-pixel R that emits red light, and sub-pixel 230a can be sub-pixel G that emits green light.

[0469] In photolithography, the finer the pattern being processed, the more significant the effects of light diffraction become. This compromises the fidelity of the transfer of the photomask pattern through exposure, making it difficult to process the resist mask into the desired shape. Therefore, even if the photomask pattern is rectangular, patterns with rounded corners are likely to be formed. Consequently, the top surface shape of subpixels may be a polygon with rounded corners, an ellipse, or a circle.

[0470] Here, we have used a configuration in which each pixel has three types of subpixels as an example, but the present invention is not limited to this. A configuration in which each pixel has four types of subpixels is also possible.

[0471] <Example of Pixel Circuit Configuration> An example of the configuration of a pixel 230 is shown in Figure 27A. The pixel 230 has a pixel circuit 51A and a light-emitting element 61.

[0472] The pixel circuit 51A includes transistors 52A and 52B, and a capacitive element 53. The pixel circuit 51A is a 2Tr1C type pixel circuit having two transistors and one capacitive element. The pixel circuit applicable to the display device according to one embodiment of the present invention is not particularly limited.

[0473] The anode of the light-emitting element 61 is connected to one of the source and drain of transistor 52B. The other of the source and drain of transistor 52B is connected to one electrode of the capacitive element 53 and to wiring ANO. The gate of transistor 52B is connected to one of the source and drain of transistor 52A and to the other electrode of the capacitive element 53. The region where one of the source and drain of transistor 52A, the gate of transistor 52B, and the other electrode of the capacitive element 53 are connected functions as node FN.

[0474] The source and drain of transistor 52A are connected to wiring SL. The gate of transistor 52A is connected to wiring GL. The cathode of light-emitting element 61 is connected to wiring VCOM.

[0475] Wiring GL corresponds to wiring 236, and wiring SL corresponds to wiring 238. Wiring VCOM is a wire that provides a potential for supplying current to the light-emitting element 61. Transistor 52A has the function of controlling the conduction or non-conduction state between wiring SL and the gate of transistor 52B based on the potential of wiring GL. For example, VDD is supplied to wiring ANO, and VSS is supplied to wiring VCOM.

[0476] In this specification, the high power supply potential VDD (also simply referred to as "VDD") refers to a power supply potential that is higher than the low power supply potential VSS. The low power supply potential VSS (also simply referred to as "VSS") refers to a power supply potential that is lower than the high power supply potential VDD. Furthermore, the ground potential GND (also simply referred to as "GND") can also be used as VDD or VSS. For example, if VDD is GND, then VSS is at a lower potential than GND, and if VSS is GND, then VDD is at a higher potential than GND.

[0477] Transistor 52A functions as a selection transistor for controlling the selected state of pixel 230. By making transistor 52A conductive, an image signal is supplied from wiring SL to node FN. Subsequently, by making transistor 52A non-conductive, the image signal is held at node FN. To reliably hold the image signal supplied to node FN, it is preferable to use a transistor with a small off-current for transistor 52A. For example, it is preferable to use an OS transistor as transistor 52A.

[0478] Transistor 52B functions as a drive transistor that controls the amount of current flowing to the light-emitting element 61. Capacitive element 53 has the function of maintaining the gate potential of transistor 52B. The intensity of the light emitted by the light-emitting element 61 is controlled according to the image signal supplied to the gate (i.e., node FN) of transistor 52B.

[0479] The pixel circuit 51A shown in Figure 27A has a configuration in which an n-channel transistor is used for transistor 52A and a p-channel transistor is used for transistor 52B. However, the present invention is not limited to this, and an n-channel transistor can be used for transistor 52B, as in the pixel circuit 51A shown in Figure 27B. When an n-channel transistor is used for transistor 52B, one electrode of the capacitive element 53 can be connected to one of the source and drain of transistor 52B.

[0480] The aforementioned semiconductor device can be used in the pixel circuit 51A. This reduces the area occupied by the pixel circuit 51A, enabling a high-resolution display device. It also enables a high-speed operating display device.

[0481] By using transistor 100, which has a short channel length and a large on-current, as the transistor 52A that functions as a selection transistor, a high-speed operating display device can be created. It is preferable that the transistor 52B, which functions as a drive transistor, has high saturation and high current controllability. For example, any of transistors 200 to 200E, which have a long channel length, can be suitably used for transistor 52B. This allows for a display device with high display quality. Alternatively, transistor 100, which has a large on-current, can be used for transistor 52B. This increases the current flowing to the light-emitting element 61, resulting in a display device with high brightness.

[0482] By using multiple transistors and capacitive elements in a pixel circuit, a high-performance display device can be created. By applying a semiconductor device according to one aspect of the present invention, the occupied area can be reduced even if the number of transistors and capacitive elements increases, resulting in a high-performance and high-resolution display device. For example, a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be realized.

[0483] A semiconductor device according to one aspect of the present invention can reduce the occupied area, thereby increasing the aperture ratio of pixels in a display device with a bottom emission structure. For example, a display device with an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

[0484] In this specification, the term "aperture ratio" refers to the ratio of the area of ​​the region from which light is emitted to the area of ​​the pixel.

[0485] Figures 27C to 31 show examples of configurations different from those of the pixel 230 shown in Figures 27A and 27B.

[0486] The pixel 230 shown in Figures 27C and 27D has a pixel circuit 51B and a light-emitting element 61. The pixel circuit 51B mainly differs from the pixel circuit 51A shown in Figures 27A and 27B in that it has a transistor 52C. The pixel circuit 51B has transistors 52A, 52B, 52C, and a capacitive element 53. The pixel circuit 51B is a 3Tr1C type pixel circuit having three transistors and one capacitive element.

[0487] The pixel circuit 51B shown in Figure 27C has a configuration in which a transistor 52C is added to the pixel circuit 51A shown in Figure 27A. One of the source and drain of transistor 52C is connected to one of the source and drain of transistor 52B. The other of the source and drain of transistor 52C is connected to wiring V0. For example, a reference potential is supplied to wiring V0.

[0488] The gate of transistor 52A is connected to wiring GL1. Wiring GL1 corresponds to wiring GL shown in Figures 27A and 27B. The gate of transistor 52C is connected to wiring GL2. Transistor 52C has the function of controlling the conduction or non-conduction state between the source and drain of transistor 52B and wiring V0 based on the potential of wiring GL2. The reference potential of wiring V0 provided via transistor 52C can suppress variations in the gate-source potential of transistor 52B.

[0489] The wiring V0 can be used to obtain current values ​​that can be used to set pixel parameters. Specifically, wiring V0 can function as a monitor line to output the current flowing through transistor 52B or the current flowing through light-emitting element 61 to the outside. The current output to wiring V0 can be converted into a voltage by a source follower circuit and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter and output to the outside.

[0490] As shown in the pixel circuit 51B in Figure 27D, an n-channel transistor can be used for transistor 52B. The pixel circuit 51B shown in Figure 27D has a configuration in which transistor 52C is added to the pixel circuit 51A shown in Figure 27B. When an n-channel transistor is used for transistor 52B, one electrode of the capacitive element 53 can be connected to one of the source and drain of transistor 52B.

[0491] Figures 27C and 27D show an example configuration in which the gates of transistor 52A and transistor 52C are connected to different wirings. This allows the operation of transistor 52A and transistor 52C to be controlled independently. However, the present invention is not limited to this, and as shown in the pixel circuit 51C in Figures 27E and 27F, the gates of transistor 52A and transistor 52C can be connected to the same wiring (here, wiring GL). This reduces the number of wirings and the occupied area of ​​the pixel circuit.

[0492] The pixel 230 shown in Figures 28A and 28B has a pixel circuit 51D and a light-emitting element 61. The pixel circuit 51D mainly differs from the pixel circuit 51B shown in Figures 27C and 27D in that it has a transistor 52D. The pixel circuit 51D has transistors 52A, 52B, 52C, 52D, and a capacitive element 53. The pixel circuit 51D is a 4Tr1C type pixel circuit having four transistors and one capacitive element.

[0493] The pixel circuit 51D shown in Figure 28A has a configuration in which a transistor 52D is added to the pixel circuit 51C shown in Figure 27C. One of the source and drain of transistor 52D is connected to wiring ANO. The other of the source and drain of transistor 52D is connected to one of the source and drain of transistor 52A, the other electrode of the capacitive element 53, and the gate of transistor 52B. The region where the other of the source and drain of transistor 52D, one of the source and drain of transistor 52A, the other electrode of the capacitive element 53, and the gate of transistor 52B are connected functions as node FN.

[0494] The gate of transistor 52A is connected to wiring GL1, the gate of transistor 52C is connected to wiring GL2, and the gate of transistor 52D is connected to wiring GL3.

[0495] By making transistor 52D conduct, the source and gate of transistor 52B become at the same potential, making transistor 52B non-conductive. This allows the current flowing to the light-emitting element 61 to be forcibly interrupted. Such a pixel circuit is suitable when using a display method that alternates between display periods and off periods. It is also possible to make transistor 52C conduct at the same time as making transistor 52D conduct.

[0496] Figure 28A shows an example configuration in which a p-channel transistor is used for transistor 52B, but the present invention is not limited to this. In addition to transistor 52B, one or more p-channel transistors can also be used for transistors 52A, 52C, and 52D.

[0497] As shown in the pixel circuit 51D in Figure 28B, an n-channel transistor can be used for the transistor 52B. The pixel circuit 51D shown in Figure 28B has a configuration in which the transistor 52D is added to the pixel circuit 51B shown in Figure 27D.

[0498] The pixel 230 shown in Figures 28C and 28D has a pixel circuit 51E and a light-emitting element 61. The pixel circuit 51E mainly differs from the pixel circuit 51D shown in Figures 28A and 28B in that it has a capacitive element 53A. The pixel circuit 51E has transistors 52A, 52B, 52C, 52D, a capacitive element 53, and a capacitive element 53A. The pixel circuit 51E is a 4Tr2C type pixel circuit having four transistors and two capacitive elements.

[0499] The pixel circuit 51E shown in Figure 28C has a configuration in which a capacitive element 53A is added to the pixel circuit 51D shown in Figure 28A. One electrode of the capacitive element 53A is connected to one electrode of the source and drain of transistor 52B, and the other electrode is connected to the gate of transistor 52B. Capacitive elements 53 and 53A each function as retaining capacitors. The region where the other electrode of the source and drain of transistor 52D, one electrode of the source and drain of transistor 52A, the other electrode of the capacitive element 53, the other electrode of the capacitive element 53A, and the gate of transistor 52B are connected functions as node FN.

[0500] As shown in the pixel circuit 51E in Figure 28D, an n-channel transistor can be used for the transistor 52B. The pixel circuit 51E shown in Figure 28D has a configuration in which a capacitive element 53A is added to the pixel circuit 51D shown in Figure 28B. One electrode of the capacitive element 53A is connected to wiring ANO, and the other electrode is connected to the gate of transistor 52B.

[0501] The pixel 230 shown in Figure 29A has a pixel circuit 51F and a light-emitting element 61. The pixel circuit 51F has transistors 52A, 52B, 52C, 52D, 52E, 52F and a capacitive element 53. The pixel circuit 51F is a 6Tr1C type pixel circuit having six transistors and one capacitive element.

[0502] The anode of the light-emitting element 61 is connected to one of the source and drain of transistor 52C, one of the source and drain of transistor 52F, and one electrode of the capacitive element 53. The other source and drain of transistor 52F is connected to one of the source and drain of transistor 52A, and one of the source and drain of transistor 52B. The gate of transistor 52B is connected to one of the source and drain of transistor 52E, and the other electrode of the capacitive element 53. The other source and drain of transistor 52B is connected to the other source and drain of transistor 52E, and one of the source and drain of transistor 52D. The region where the gate of transistor 52B, one of the source and drain of transistor 52E, and the other electrode of the capacitive element 53 are connected functions as node FN.

[0503] The source and the other drain of transistor 52A are connected to wiring SL, and the gate is connected to wiring GL1. The source and the other drain of transistor 52D are connected to wiring ANO, and the gate is connected to wiring GL2. The gate of transistor 52F is connected to wiring GL3. The gate of transistor 52E is connected to wiring GL4. The source and the other drain of transistor 52C are connected to wiring V0, and the gate is connected to wiring GL4. The cathode of the light-emitting element 61 is connected to wiring VCOM.

[0504] Figure 29A shows an example configuration in which n-channel transistors are used for transistors 52A to 52F. For example, a Si transistor can be used for transistor 52B, which functions as a drive transistor, and OS transistors can be used for transistors 52A and 52C to 52F. In particular, it is preferable to use an OS transistor with a small off-current for transistor 52E in order to reliably hold the image signal supplied to node FN.

[0505] A back gate can be provided for some or all of the transistors included in the pixel circuit. When a back gate is provided, it can be configured to receive the same signal as the gate, or to receive a different signal from the gate.

[0506] As shown in Figure 29B, transistor 52B can be configured to have a back gate. The back gate of transistor 52B can be connected to the gate of transistor 52B, or to either the source or drain of transistor 52B. As shown in Figure 29B, the reliability can be improved by connecting the back gate of transistor 52B to either the source or drain of transistor 52B. Alternatively, the back gate of transistor 52B can be connected to the gate of transistor 52B. This allows for a larger on-current of transistor 52B.

[0507] Figure 30A shows a pixel circuit 51F using a p-channel transistor for transistor 52B. The pixel circuit 51F shown in Figure 30A differs from the pixel circuit 51F shown in Figure 29A in the connections of transistor 52A, transistor 52E, and the capacitive element 53. In the pixel circuit 51F shown in Figure 30A, one source and drain of transistor 52A is connected to the other source and drain of transistor 52B, and one source and drain of transistor 52D. One electrode of the capacitive element 53 is connected to the other source and drain of transistor 52D. The other source and drain of transistor 52E is connected to one source and drain of transistor 52B.

[0508] As shown in the pixel circuit 51F in Figure 30B, the transistor 52B can be configured to have a back gate. When a p-channel type transistor is used for transistor 52B, the back gate of transistor 52B can be connected to the gate of transistor 52B, or to the other of the source and drain of transistor 52B. Figure 30B shows an example in which the back gate of transistor 52B is connected to the other of the source and drain of transistor 52B.

[0509] The pixel 230 shown in Figure 31 has a pixel circuit 51G and a light-emitting element 61. The pixel circuit 51G has transistors 52A, 52B, 52C, 52D, 52E, 52F, 52G and a capacitive element 53. The pixel circuit 51G is a 7Tr1C type pixel circuit having seven transistors and one capacitive element.

[0510] The pixel circuit 51G shown in Figure 31 has a configuration in which a transistor 52G is added to the pixel circuit 51F shown in Figure 30A, and p-channel transistors are used for transistors 52B, 52D, and 52F. One of the source and drain of transistor 52G is connected to the gate of transistor 52B, one of the source and drain of transistor 52E, and the other electrode of the capacitive element 53. The other of the source and drain of transistor 52G is connected to wiring V0. The gates of transistor 52A and transistor 52C are connected to wiring GL1. The gates of transistor 52D and transistor 52F are connected to wiring GL2. The gate of transistor 52E is connected to wiring GL3. The gate of transistor 52G is connected to wiring GL4. Transistor 52G has the function of resetting the potential of node FN to the potential supplied to wiring V0, that is, resetting the gate potential of the driving transistor transistor 52B.

[0511] The transistor shown in Embodiment 1 can be used in the pixel circuit shown in Figures 27A to 31.

[0512] <Pixel Circuit Layout Example 1> An example of the layout configuration of the pixel 230 is shown in Figures 32A to 33B. Figures 32A to 33B are top views corresponding to the pixel 230 shown in Figure 27D. Note that, in order to avoid making the diagrams too complex, some of the hidden lines of the components may be omitted in Figures 32A to 33B.

[0513] Figure 32A shows transistors 52A, 52B, and 52C, and a capacitive element 53. It also shows conductive layers 104 functioning as wiring GL1, conductive layer 104K functioning as wiring GL2, conductive layer 112a functioning as wiring SL, conductive layer 112aK functioning as wiring V0, conductive layer 104M functioning as wiring ANO, and conductive layer 190 functioning as a pixel electrode of the light-emitting element 61. Figure 32B is a top view of Figure 32A with the conductive layer 190 omitted.

[0514] Transistors 52A, 52B, and 52C can be replaced with one or more of the aforementioned transistors 100 and 200 to 200E. By applying a semiconductor device according to one aspect of the present invention to a pixel circuit, a high-definition display device can be made.

[0515] Figure 34 shows a cross-sectional view of the cross-section along the dashed line G1-G2 shown in Figure 32A. Figures 32A to 34 show an example configuration in which VFETs are applied to transistors 52A and 52C, and a TGSA type transistor is applied to transistor 52B. Furthermore, the sub-pixel arrangement is the pentile arrangement shown in Figure 26D. In this configuration, the size of one sub-pixel (here, sub-pixel 230a, sub-pixel 230b, or sub-pixel 230c) can be 12.6 μm × 6.3 μm, and the size of one pixel (here, pixel 240a or pixel 240b) can be 12.6 μm × 12.6 μm. In addition, the resolution is 2016 ppi, and a high-resolution display device of 2000 ppi or more can be realized on a glass substrate without using an exposure apparatus used in LSI technology.

[0516] For transistors 52C and 52B, refer to the descriptions relating to transistors 100 and 200 shown in Figures 10A to 10C. For transistors 52A and 52B, refer to the descriptions relating to transistors 100 and 200E shown in Figures 17A and 17B. Note that the transistor configurations applicable to transistors 52A, 52B, and 52C are not particularly limited.

[0517] Transistors 52A, 52B, 52C, and capacitive element 53 are formed on the substrate 151. Transistors 52A, 52B, 52C, and capacitive element 53 can be formed by sharing some of the manufacturing processes.

[0518] An insulating layer 207 is provided on the substrate 151, and a transistor 52B is provided on the insulating layer 207. An insulating layer 214 is provided on the transistor 52B, and an insulating layer 109 is provided on the insulating layer 214. Transistors 52A and 52C are provided on the insulating layer 109, an insulating layer 218 is provided on transistors 52A and 52C, and an insulating layer 235 is provided on the insulating layer 218. A light-emitting element 61 can be provided on the insulating layer 235. Figure 34 shows an example configuration in which a conductive layer 190, which functions as a pixel electrode of the light-emitting element 61, is provided on the insulating layer 235.

[0519] The insulating layer 235 can suitably use organic materials. Examples of organic materials include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimidoamide resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins. The insulating layer 235 functions as a planarizing layer that reduces irregularities caused by transistors 52A, 52B, 52C, and capacitive elements 53. By providing the insulating layer 235, the occurrence of defects (e.g., step breaks, porosity, and etching residue) in the formation of layers provided on the insulating layer 235 (e.g., conductive layer 190) is suppressed, and the manufacturing yield can be increased. Furthermore, the insulating layer 235 can be a laminated structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer. Preferably, the uppermost layer of the insulating layer 235 functions as an etching protection layer. This suppresses the formation of recesses in the insulating layer 235 when the conductive layer 190 is formed. Alternatively, when the conductive layer 190 is formed, a portion of the insulating layer 235 may be removed, and a recess may be provided in the insulating layer 235.

[0520] The conductive layer 190 can be provided in a region that overlaps with one or more of the transistors 52A, 52B, 52C, and the capacitive element 53. This can increase the aperture ratio of the pixels. Figure 34 and others show an example configuration in which the conductive layer 190 has a region that overlaps with transistor 52A, a region that overlaps with transistor 52B, and a region that overlaps with the capacitive element 53.

[0521] The transistor 52A has a semiconductor layer 108, an insulating layer 106, a conductive layer 104, a conductive layer 112a, and a conductive layer 112b. In the transistor 52A, the insulating layer 106 functions as a gate insulating layer, and the conductive layer 112b functions as one of the source electrode and drain electrode. The conductive layer 104 functions as the gate electrode of the transistor 52A and also functions as wiring GL1. The conductive layer 112a functions as the other of the source electrode and drain electrode of the transistor 52A and also functions as wiring SL.

[0522] The transistor 52C has a semiconductor layer 108K, an insulating layer 106, a conductive layer 104K, a conductive layer 112aK, and a conductive layer 112bK. In the transistor 52C, the insulating layer 106 functions as a gate insulating layer, and the conductive layer 104K functions as a gate electrode. The conductive layer 112bK functions as one of the source electrode and drain electrode. The conductive layer 104K functions as the gate electrode of the transistor 52C and also functions as wiring GL2. The conductive layer 112aK functions as the other of the source electrode and drain electrode of the transistor 52C and also functions as wiring V0.

[0523] Transistor 52C has the same structure as transistor 52A. The semiconductor layer 108K, conductive layer 104K, conductive layer 112aK, and conductive layer 112bK of transistor 52C correspond to the semiconductor layer 108, conductive layer 104, conductive layer 112a, and conductive layer 112b of transistor 52A. Furthermore, conductive layer 112aK can be called the lower electrode of transistor 52C, and conductive layer 112bK can be called the upper electrode.

[0524] Transistor 52B has a semiconductor layer 208, an insulating layer 206, a conductive layer 204, a conductive layer 112bK, and a conductive layer 212a. In transistor 52B, the insulating layer 206 functions as a gate insulating layer, the conductive layer 204 functions as a gate electrode, the conductive layer 112bK functions as one of the source electrode and drain electrode, and the conductive layer 212a functions as the other of the source electrode and drain electrode. The conductive layer 112bK functions as one of the source electrode and drain electrode of transistor 52C, and also functions as one of the source electrode and drain electrode of transistor 52B. As a result, one of the source electrode and drain electrode of transistor 52C is connected to one of the source electrode and drain electrode of transistor 52B.

[0525] The insulating layer 106, insulating layer 218, and insulating layer 235 have openings 253 that reach the conductive layer 112bK. The conductive layer 190 is provided so as to cover the openings 253. The conductive layer 190 is in contact with the conductive layer 112bK at the openings 253 and is connected to the conductive layer 112bK.

[0526] Figure 32C is a top view from Figure 32B with conductive layer 104, conductive layer 104K, and conductive layer 104M omitted. Figure 33A is a top view from Figure 32C with conductive layer 112b, conductive layer 112bK, conductive layer 212a, semiconductor layer 108, and semiconductor layer 108K omitted. Figure 33B is a top view from Figure 33A with conductive layer 112a and conductive layer 112aK omitted. Figure 33B shows semiconductor layer 208 and conductive layer 204, and also shows the hatching of conductive layer 204 through transparency.

[0527] A semiconductor layer 208 is provided on an insulating layer 207, an insulating layer 206 is provided on the semiconductor layer 208, and a conductive layer 204 is provided on the insulating layer 206. The semiconductor layer 208 has a region 208P in a region that does not overlap with the conductive layer 204. An insulating layer 214 is provided on the insulating layer 206 and the conductive layer 204, and an insulating layer 109 is provided on the insulating layer 214.

[0528] A conductive layer 112a is provided on the insulating layer 109, and an insulating layer 110 is provided on the insulating layer 109 and the conductive layer 112a.

[0529] The insulating layer 110 preferably has a laminated structure. Figure 34 shows an example configuration in which the insulating layer 110 has insulating layer 110a, insulating layer 110b, and insulating layer 110c. Figure 34 also shows an example configuration in which the insulating layer 110a has a two-layer structure consisting of insulating layer 110a_1 and insulating layer 110a_2 on top of insulating layer 110a_1. Insulating layer 110a_1 and insulating layer 110a_2 can be made from the materials listed for insulating layer 110a, respectively.

[0530] Figure 34 shows an example of a configuration where the surface on which the conductive layer 112a is formed and the surface on which the conductive layer 112aK is formed are different. The conductive layer 112a is provided on the insulating layer 109, the insulating layer 110a_1 is provided on the insulating layer 109 and the conductive layer 112a, and the conductive layer 112aK is provided on the insulating layer 110a_1. The insulating layer 110a_2 is provided on the insulating layer 110a_1 and the conductive layer 112aK, and the insulating layer 110b is provided on the insulating layer 110a_2. The insulating layer 110c is provided on the insulating layer 110b, and the conductive layer 112b and the conductive layer 112bK are provided on the insulating layer 110c.

[0531] The insulating layers 110a_1, 110a_2, 110b, and 110c have openings 145 that reach the conductive layer 112a. The semiconductor layer 108 has regions at the openings 145 that are in contact with the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a_1, the side surface of the insulating layer 110a_2, the side surface of the insulating layer 110b, and the side surface of the insulating layer 110c. The semiconductor layer 108 also has regions that are in contact with the side surface and upper surface of the conductive layer 112b. An insulating layer 106 is provided on the semiconductor layer 108, and a conductive layer 104 is provided on the insulating layer 106. The conductive layer 104 has regions that face at least the side surface of the insulating layer 110b via the insulating layer 106 and the semiconductor layer 108.

[0532] The insulating layers 110a_2, 110b, and 110c have an opening 145K that reaches the conductive layer 112aK. The semiconductor layer 108 has a region at the opening 145 that is in contact with the upper surface of the conductive layer 112aK, the side surface of the insulating layer 110a_2, the side surface of the insulating layer 110b, and the side surface of the insulating layer 110c. The semiconductor layer 108K also has a region that is in contact with the side surface and upper surface of the conductive layer 112bK. An insulating layer 106 is provided on the semiconductor layer 108K, and a conductive layer 104K is provided on the insulating layer 106. The conductive layer 104K has a region that faces at least the side surface of the insulating layer 110b via the insulating layer 106 and the semiconductor layer 108K.

[0533] When using photolithography to form conductive layers 112a and 112aK, the process for processing the conductive film that will become conductive layer 112a and the process for processing the conductive film that will become conductive layer 112aK can be made different. Therefore, the spacing between conductive layers 112a and 112aK (hereinafter also referred to as space) can be shortened without being affected by the design rules in the photography method, and the occupied area of ​​the pixel circuit can be reduced. In Figure 34, the spacing SP between conductive layers 112a and 112aK is shown by a solid double arrow. By forming conductive layers 112a and 112aK in different processes, the spacing SP can be made smaller than the minimum spacing that the exposure apparatus can expose. This reduces the occupied area of ​​the pixel circuit and increases the resolution of the display device.

[0534] By forming the conductive layer 112a and the conductive layer 112aK using different processes, different materials can be used for the conductive layer 112a and the conductive layer 112aK. This broadens the range of materials that can be selected for the conductive layer 112a and the conductive layer 112aK.

[0535] The insulating layer 206, insulating layer 214, insulating layer 109, and insulating layer 110 have openings 247a and 247b that reach region 208P. The conductive layer 212a is provided so as to cover opening 247a. The conductive layer 212a is in contact with region 208P at opening 247a and is connected to region 208P. The conductive layer 112bK is provided so as to cover opening 247b. The conductive layer 112bK is in contact with region 208P at opening 247b and is connected to region 208P.

[0536] The insulating layer 214, insulating layer 109, and insulating layer 110 have openings 249 that reach the conductive layer 204. The conductive layer 112b is provided so as to cover the openings 249. The conductive layer 112b is in contact with the conductive layer 204 at the openings 249 and is connected to the conductive layer 204.

[0537] The insulating layer 106 has an opening 251 that reaches the conductive layer 212a. The conductive layer 104M is provided so as to cover the opening 251. The conductive layer 104M is in contact with the conductive layer 212a at the opening 251 and is connected to the conductive layer 212a.

[0538] Semiconductor layer 108 and semiconductor layer 108K can be formed by processing the same semiconductor film. Conductive layer 112b, conductive layer 112bK, and conductive layer 212a can be formed by processing the same conductive film. Conductive layer 104, conductive layer 104K, and conductive layer 104M can be formed by processing the same conductive film.

[0539] It is preferable that the VFET has a region that overlaps with the TGSA type transistor. For example, it is preferable that one or both of transistors 52A and 52C have a region that overlaps with transistor 52B. It is also preferable that one or both of semiconductor layer 108 and semiconductor layer 108K have a region that overlaps with semiconductor layer 208. Figure 34 shows an example configuration in which transistor 52A has a region that overlaps with transistor 52B, and semiconductor layer 108 has a region that overlaps with semiconductor layer 208. By providing the VFET in a region that overlaps with the TGSA type transistor, the occupied area of ​​the pixel circuit can be reduced, and the resolution of the display device can be increased.

[0540] The capacitive element 53 has a conductive layer 112bK, a conductive layer 204, an insulating layer 110, an insulating layer 109, and an insulating layer 214. In the capacitive element 53, the conductive layer 112bK functions as one of a pair of electrodes, and the conductive layer 204 functions as the other. The insulating layers 110, 109, and 214, sandwiched between the pair of electrodes (conductive layer 112bK and conductive layer 204), function as dielectrics for the capacitive element 53. Note that the configuration of the capacitive element 53 is not limited to the configuration shown in Figure 34, etc.

[0541] In Figure 33B, the channel length L52 of transistor 52B is indicated by a solid double arrow. In the configurations shown in Figures 32A to 33B, the channel length L52 is approximately 10 μm. By providing a VFET above the TGSA type transistor, the occupied area of ​​the pixel 230 can be reduced even when a TGSA type transistor with a long channel length is used. Therefore, a high-resolution display device can be made. Furthermore, the channel length of the TGSA type transistor can be increased without increasing the occupied area of ​​the pixel 230. By increasing the channel length, a transistor with high saturation can be made even without providing a back gate electrode. This makes a highly reliable display device possible. In addition, the manufacturing process can be simplified, increasing the productivity of the display device and reducing manufacturing costs.

[0542] Furthermore, a portion of the wiring connected to a pixel 230 can be shared by multiple pixels 230. Also, a portion of the transistor configuration of a pixel 230 can be shared by multiple pixels 230. This reduces the area occupied by the pixel 230 and increases the resolution. Figures 32A to 33B show an example configuration in which wiring ANO (here, conductive layer 104M), an aperture 251, a conductive layer 212a, an aperture 247a, and a semiconductor layer 208 are shared between adjacent pixels 230 in the column direction.

[0543] Figure 34 and others show an example configuration in which the conductive layer 112aK does not have a region that overlaps with the conductive layer 112a, but the present invention is not limited to this. The conductive layer 112aK may also have a region that overlaps with the conductive layer 112a. The conductive layer 112a and the conductive layer 112aK are electrically insulated by the insulating layer 110a_1. By having a region in which the conductive layer 112aK overlaps with the conductive layer 112a, the occupied area of ​​the pixel circuit can be further reduced.

[0544] The surface to which conductive layer 112a is formed and the surface to which conductive layer 112aK is formed can be the same. Figure 35 shows an example configuration in which conductive layer 112a and conductive layer 112aK are provided on insulating layer 109, and insulating layer 110 is provided on conductive layer 112a and conductive layer 112aK. Conductive layer 112a and conductive layer 112aK can be formed by depositing a conductive film on insulating layer 109 and processing the conductive film by photolithography. By forming conductive layer 112a and conductive layer 112aK in the same process, manufacturing costs can be reduced. When conductive layer 112a and conductive layer 112aK are formed in the same process, the spacing SP will be greater than or equal to the minimum spacing that the exposure apparatus can expose.

[0545] <Pixel Circuit Layout Example 2> An example of the layout configuration of the pixel 230 is shown in Figures 36A to 38. Figures 36A to 38 are top views corresponding to the pixel 230 shown in Figure 31. In order to avoid making the diagrams too complex, some of the hidden lines of the components may be omitted in Figures 36A to 38. Also, the capacitive element 53 is omitted in Figures 36A to 38.

[0546] Figure 36A shows transistors 52A, 52B, 52C, 52D, 52E, 52F, and 52G. It also shows conductive layer 104 functioning as wiring GL1, conductive layer 204D functioning as wiring GL2, conductive layer 104E functioning as wiring GL3, conductive layer 104G functioning as wiring GL5, conductive layer 180A functioning as wiring SL, conductive layer 112aC functioning as wiring V0, and conductive layer 212bD functioning as wiring ANO. Figure 36B is a top view of Figure 36A with conductive layer 180A omitted.

[0547] Transistors 52A, 52B, 52C, 52D, 52E, 52F, and 52G can be one or more of the aforementioned transistors 100 and 200 to 200E. By applying a semiconductor device according to one aspect of the present invention to a pixel circuit, a high-definition display device can be made.

[0548] Figure 39A shows a cross-sectional view of the section along the dashed-dotted line H1-H2 shown in Figure 36A, Figure 39B shows a cross-sectional view of the section along the dashed-dotted line H3-H4, and Figure 40 shows a cross-sectional view of the section along the dashed-dotted line H5-H6.

[0549] Figures 36A to 40 show an example configuration in which VFETs are applied to transistors 52A, 52C, 52E, and 52G, and TGSA type transistors are applied to transistors 52B, 52D, and 52F. Furthermore, the sub-pixel arrangement is the pentile arrangement shown in Figure 26D. In this configuration, the size of one sub-pixel (here, sub-pixel 230a, sub-pixel 230b, or sub-pixel 230c) can be 24.0 μm × 12.0 μm, and the size of one pixel (here, pixel 240a or pixel 240b) can be 24.0 μm × 24.0 μm. In addition, the resolution is 1058 ppi, and a high-resolution display device of 1000 ppi or more can be realized on a glass substrate without using an exposure device used in LSI technology.

[0550] Here, by using multiple transistors and capacitive elements in the pixel circuit, a high-performance display device can be created. By applying a semiconductor device, which is one aspect of the present invention, to the pixel circuit, the occupied area of ​​the pixel circuit can be reduced even if the number of transistors and capacitive elements increases, thereby creating a high-performance and high-definition display device.

[0551] For transistors 52A, 52C, 52E, and 52G, refer to the description relating to transistor 100 shown in Figure 15D, etc., and for transistors 52B, 52D, and 52F, refer to the description relating to transistor 200D. Note that the transistor configurations applicable to transistors 52A to 52G are not particularly limited.

[0552] Transistors 52A to 52G can be formed by sharing some of the manufacturing processes.

[0553] An insulating layer 207 is provided on the substrate 151, and transistors 52B, 52D, and 52F are provided on the insulating layer 207. An insulating layer 214 is provided on transistors 52B, 52D, and 52F, and an insulating layer 109 is provided on the insulating layer 214. Transistors 52A, 52C, 52E, and 52G are provided on the insulating layer 109, and an insulating layer 218 is provided on transistors 52A, 52C, 52E, and 52G. Conductive layers 180A, 180E, and 180M are provided on the insulating layer 218.

[0554] The transistor 52A has a semiconductor layer 108, an insulating layer 106, a conductive layer 104, a conductive layer 112a, and a conductive layer 112b. In the transistor 52A, the insulating layer 106 functions as a gate insulating layer, the conductive layer 104 functions as a gate electrode, the conductive layer 112a functions as one of the source electrode and drain electrode, and the conductive layer 112b functions as the other of the source electrode and drain electrode.

[0555] Transistors 52C, 52E, and 52G each have the same structure as transistor 52A.

[0556] The transistor 52C has a semiconductor layer 108C, an insulating layer 106, a conductive layer 104, a conductive layer 112aC, and a conductive layer 112bC. The conductive layer 112aC can be called the lower electrode of the transistor 52C, and the conductive layer 112bC can be called the upper electrode. In the transistor 52C, the insulating layer 106 functions as a gate insulating layer, the conductive layer 104 functions as a gate electrode, the conductive layer 112bC functions as one of the source electrode and drain electrode, and the conductive layer 112aC functions as the other of the source electrode and drain electrode.

[0557] The transistor 52E has a semiconductor layer 108E, an insulating layer 106, a conductive layer 104E, a conductive layer 112aE, and a conductive layer 112bE. The conductive layer 112aE can be called the lower electrode of the transistor 52E, and the conductive layer 112bE can be called the upper electrode. In the transistor 52E, the insulating layer 106 functions as a gate insulating layer, the conductive layer 104E functions as a gate electrode, the conductive layer 112bE functions as one of the source electrode and drain electrode, and the conductive layer 112aE functions as the other of the source electrode and drain electrode.

[0558] The transistor 52G has a semiconductor layer 108G, an insulating layer 106, a conductive layer 104G, a conductive layer 112aC, and a conductive layer 112bE. The conductive layer 112aC can be called the lower electrode of the transistor 52G, and the conductive layer 112bE can be called the upper electrode. In the transistor 52G, the insulating layer 106 functions as a gate insulating layer, the conductive layer 104G functions as a gate electrode, the conductive layer 112bE functions as one of the source electrode and drain electrode, and the conductive layer 112aC functions as the other of the source electrode and drain electrode.

[0559] The transistor 52B has a semiconductor layer 208, an insulating layer 206, a conductive layer 204, a conductive layer 112a, and a conductive layer 112aE. In the transistor 52B, the insulating layer 206 functions as a gate insulating layer, the conductive layer 204 functions as a gate electrode, the conductive layer 112aE functions as one of the source electrode and drain electrode, and the conductive layer 112a functions as the other of the source electrode and drain electrode.

[0560] Transistors 52D and 52F each have the same structure as transistor 52B.

[0561] The transistor 52D has a semiconductor layer 208, an insulating layer 206, a conductive layer 204D, a conductive layer 112a, and a conductive layer 212bD. In the transistor 52D, the insulating layer 206 functions as a gate insulating layer, the conductive layer 204D functions as a gate electrode, the conductive layer 112a functions as one of the source electrode and drain electrode, and the conductive layer 212bD functions as the other of the source electrode and drain electrode.

[0562] The transistor 52F has a semiconductor layer 208, an insulating layer 206, a conductive layer 204D, a conductive layer 212aF, and a conductive layer 112aE. In the transistor 52F, the insulating layer 206 functions as a gate insulating layer, the conductive layer 204D functions as a gate electrode, the conductive layer 212aF functions as one of the source electrode and drain electrode, and the conductive layer 112aE functions as the other of the source electrode and drain electrode.

[0563] Figure 37A is a top view from Figure 36B with conductive layers 104, 104E, and 104G omitted. Figure 37B is a top view from Figure 37A with conductive layers 112b, 112bC, 112bE, semiconductor layer 108, 108C, 108E, and 108G omitted. Figure 38 is a top view from Figure 37B with conductive layers 112a, 112aC, 112aE, 112aM, and 212bD omitted. Figure 38 shows semiconductor layer 208 and conductive layer 204, with the hidden lines of semiconductor layer 208 shown as solid lines and the hatching of conductive layer 204 shown as transparent.

[0564] The conductive layer 112a is shared by transistors 52A, 52B, and 52D. The conductive layer 112a functions as one of the source and drain electrodes of transistor 52A, the other of the source and drain electrodes of transistor 52B, and one of the source and drain electrodes of transistor 52D.

[0565] The conductive layer 112aC is shared by transistors 52C and 52G. The conductive layer 112aC functions as the other source electrode and drain electrode of transistor 52C, and as the other source electrode and drain electrode of transistor 52G, and also functions as wiring V0.

[0566] The conductive layer 112aE is shared by transistors 52B, 52E, and 52F. The conductive layer 112aE functions as one of the source and drain electrodes of transistor 52B, the other of the source and drain electrodes of transistor 52E, and the other of the source and drain electrodes of transistor 52F.

[0567] The conductive layer 112bE is shared by transistors 52E and 52G. The conductive layer 112bE functions as one of the source and drain electrodes of transistor 52E, and as one of the source and drain electrodes of transistor 52G.

[0568] The conductive layer 104 is shared by transistors 52A and 52C. The conductive layer 104 functions as the gate electrode of transistor 52A and the gate electrode of transistor 52C, and also functions as wiring GL1.

[0569] The conductive layer 204D is shared by transistors 52D and 52F. The conductive layer 204D functions as the gate electrode of transistor 52D and the gate electrode of transistor 52F, and also functions as wiring GL2.

[0570] The conductive layer 104E functions as wiring GL3. The conductive layer 104G functions as wiring GL4.

[0571] A semiconductor layer 208 is provided on the insulating layer 207, an insulating layer 206 is provided on the semiconductor layer 208, and a conductive layer 204 and a conductive layer 204D are provided on the insulating layer 206. The semiconductor layer 208 is shared by transistors 52B, 52D, and 52F.

[0572] The semiconductor layer 208 has a first to seventh region in that order. The second and sixth regions overlap with the conductive layer 204D, respectively. The fourth region overlaps with the conductive layer 204. The second region functions as the channel formation region for transistor 52F, the fourth region as the channel formation region for transistor 52B, and the sixth region as the channel formation region for transistor 52D.

[0573] The first, third, fifth, and seventh regions are regions that do not overlap with either the conductive layer 204 or the conductive layer 204D. The first, third, fifth, and seventh regions each correspond to the region 208P described above. The first region functions as one of the source region and drain region of transistor 52F. The third region is shared by transistors 52F and 52B. The fifth region functions as the other of the source region and drain region of transistor 52F, and as one of the source region and drain region of transistor 52B. The fifth region is shared by transistors 52B and 52D. The fifth region functions as the other of the source region and drain region of transistor 52B, and as one of the source region and drain region of transistor 52D. The seventh region functions as the other of the source region and drain region of transistor 52D.

[0574] A conductive layer 204 is provided on the insulating layer 206, and an insulating layer 214 is provided on the conductive layer 204D. An insulating layer 109 is provided on the insulating layer 214. Conductive layers 112a, 112aC, 112aE, 112aM, 212aF, and 212bD are provided on the insulating layer 109. These conductive layers can be formed in the same process.

[0575] The insulating layer 109, insulating layer 214, and insulating layer 206 have openings 247c, 247d, 247e, and 247f that reach region 208P (the first region, the third region, the fifth region, and the seventh region). The conductive layer 212aF is provided so as to cover opening 247f. The conductive layer 212aF is in contact with region 208P (the first region) at opening 247f and is connected to region 208P. The conductive layer 112aE is provided so as to cover opening 247e. The conductive layer 112aE is in contact with region 208P (the third region) at opening 247e and is connected to region 208P. The conductive layer 112a is provided so as to cover opening 247d. The conductive layer 112a is in contact with region 208P (the fifth region) at the opening 247d and is connected to region 208P. The conductive layer 212bD is provided so as to cover the opening 247c. The conductive layer 212bD is in contact with region 208P (the seventh region) at the opening 247c and is connected to region 208P.

[0576] An insulating layer 110 is provided on the insulating layer 109, conductive layer 112a, conductive layer 112aC, conductive layer 112aE, conductive layer 112aM, conductive layer 212aF, and conductive layer 212bD. A conductive layer 112b, conductive layer 112bC, and conductive layer 112bE are provided on the insulating layer 110. The insulating layer 110 has an opening 145 that reaches the conductive layer 112a, an opening 145C and an opening 145G that reach the conductive layer 112aC, and an opening 145E that reaches the conductive layer 112aE.

[0577] Semiconductor layer 108 is in contact with the side surface of the insulating layer 110 and the upper surface of the conductive layer 112a at the opening 145. Semiconductor layer 108 also has a region in contact with the upper surface and side surface of the conductive layer 112b. Semiconductor layer 108C is in contact with the side surface of the insulating layer 110 and the upper surface of the conductive layer 112aC at the opening 145C. Semiconductor layer 108C also has a region in contact with the upper surface and side surface of the conductive layer 112bC. Semiconductor layer 108E is in contact with the side surface of the insulating layer 110 and the upper surface of the conductive layer 112aE at the opening 145E. Semiconductor layer 108E also has a region in contact with the upper surface and side surface of the conductive layer 112bE. Semiconductor layer 108G is in contact with the side surface of the insulating layer 110 and the upper surface of the conductive layer 112aC at the opening 145G. Furthermore, the semiconductor layer 108G has regions that are in contact with the upper and side surfaces of the conductive layer 112bE.

[0578] An insulating layer 106 is provided on the insulating layer 110, conductive layer 112b, conductive layer 112bC, conductive layer 112bE, semiconductor layer 108, semiconductor layer 108C, semiconductor layer 108E, and semiconductor layer 108G. A conductive layer 104, conductive layer 104E, and conductive layer 104G are provided on the insulating layer 106.

[0579] The conductive layer 104 has a region at the opening 145 that faces the side surface of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108, and a region at the opening 145C that faces the side surface of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108C. The conductive layer 104E has a region at the opening 145E that faces the side surface of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108E. The conductive layer 104G has a region at the opening 145G that faces the side surface of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108G.

[0580] An insulating layer 218 is provided on the insulating layer 106, conductive layer 104, conductive layer 104E, and conductive layer 104G, and conductive layers 180A, 180E, and 180M are provided on the insulating layer 218.

[0581] The insulating layer 218 and the insulating layer 106 have openings 255a that reach the conductive layer 112b. The conductive layer 180A is provided so as to cover the openings 255a. The conductive layer 180A is in contact with the conductive layer 112b at the openings 255a and is connected to the conductive layer 112b.

[0582] The insulating layer 109 and the insulating layer 214 have openings 249a that reach the conductive layer 204. The conductive layer 112aM is provided so as to cover the openings 249a. The conductive layer 112aM is in contact with the conductive layer 204 at the openings 249a and is connected to the conductive layer 204.

[0583] The insulating layer 218, insulating layer 106, and insulating layer 110 have openings 255b that reach the conductive layer 112aM. The conductive layer 180M is provided so as to cover the openings 255b. Also, the side surface of the conductive layer 112bE is exposed at the openings 255b. The conductive layer 180M is in contact with the conductive layers 112aM and 112bE at the openings 255b and is connected to the conductive layers 112aM and 112bE. As a result, the conductive layer 204 is connected to the conductive layer 112bE via the conductive layers 112aM and 180M.

[0584] The insulating layer 218, insulating layer 106, and insulating layer 110 have openings 255c that reach the conductive layer 212aF. The conductive layer 180E is provided so as to cover the openings 255c. Also, the side surface of the conductive layer 112bC is exposed at the openings 255c. The conductive layer 180E is in contact with the conductive layers 212aF and 112bC at the openings 255c and is connected to the conductive layers 212aF and 112bC. As a result, the conductive layer 212aF is connected to the conductive layer 112bC via the conductive layer 180E. The conductive layer 180E is connected to the pixel electrodes (not shown) of the light-emitting element 61.

[0585] The openings 255a, 255b, and 255c can be formed, for example, in the same process. For the formation of these openings, it is preferable to use an etching method in which the etching rate of the insulating layer 218, insulating layer 106, and insulating layer 110 is faster than the etching rate of the conductive layer 112b, conductive layer 112aM, and conductive layer 212aF. This reduces the thickness of the conductive layer 112b, conductive layer 112aM, and conductive layer 212aF, thereby suppressing an increase in the electrical resistance of these conductive layers. Furthermore, as shown in Figure 39B, in the opening 255b, not only the side surface of the conductive layer 112bE but also the upper surface of the conductive layer 112bE can be exposed. As a result, the conductive layer 180M has regions in contact with the upper and side surfaces of the conductive layer 112bE, increasing the contact area and lowering the contact resistance. Similarly, as shown in Figure 40, in the opening 255c, the conductive layer 180E has areas that are in contact with the upper and side surfaces of the conductive layer 112bC, so that the contact area is increased and the contact resistance can be reduced.

[0586] An insulating layer 216 is provided on the insulating layer 218, conductive layer 180A, conductive layer 180E, and conductive layer 180M. The insulating layer 216 can be an inorganic insulating layer, an organic insulating layer, or both. The insulating layer 216 can be made from the materials listed for the insulating layer 110. Furthermore, the insulating layer 216 can have a single-layer structure or a laminated structure.

[0587] One electrode of the capacitive element 53 can be provided on the insulating layer 216. For example, the conductive layer 112bE can function as the other electrode of the capacitive element 53, and one electrode of the capacitive element 53 can be provided in a region overlapping with the conductive layer 112bE. The insulating layers 216, 218, and 106, sandwiched between one electrode of the capacitive element 53 and the conductive layer 112bE, function as dielectrics for the capacitive element 53. In addition, one electrode of the capacitive element 53 is connected to the conductive layer 212bD. The configuration of the capacitive element 53 is not particularly limited.

[0588] In Figure 38, the channel length L52 of transistor 52B is indicated by a solid double arrow. In the configurations shown in Figures 36A to 38, the channel length L52 is approximately 16 μm. By providing a VFET above the TGSA type transistor, the occupied area of ​​the pixel 230 can be reduced even when a TGSA type transistor with a long channel length is used. Therefo...

Claims

1. The device comprises a first transistor, a second transistor, a first insulating layer, and a second insulating layer, the first transistor comprising a first semiconductor layer, a first conductive layer, and a second conductive layer, the second transistor comprising a second semiconductor layer, a third insulating layer, and a third conductive layer, the third insulating layer located on the second semiconductor layer, the third conductive layer having a region that overlaps with the second semiconductor layer via the third insulating layer, the first insulating layer located on the third insulating layer and the third conductive layer, the first conductive layer located on the first insulating layer, the second insulating layer located on the first insulating layer and the first conductive layer, the second insulating layer having an end in contact with the upper surface of the first conductive layer, and the second conductive layer located on the second insulating layer. A semiconductor device wherein the first semiconductor layer has an end portion in contact with the upper surface of the first conductive layer, an end portion in contact with the side surface of the second insulating layer, an end portion in contact with the side surface of the second conductive layer, and an end portion in contact with the upper surface of the second conductive layer.

2. The semiconductor device according to claim 1, wherein the first insulating layer, the second insulating layer, and the third insulating layer have openings that reach the second semiconductor layer, and the second conductive layer has a region in contact with the second semiconductor layer at the opening.

3. The semiconductor device according to claim 1, wherein the first insulating layer and the third insulating layer have openings that reach the second semiconductor layer, and the first conductive layer has a region in contact with the second semiconductor layer at the opening.

4. The semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer have openings that reach the third conductive layer, and the second conductive layer has a region in contact with the third conductive layer at the opening.

5. The semiconductor device according to claim 1, wherein the first insulating layer has an opening that reaches the third conductive layer, and the first conductive layer has a region in contact with the third conductive layer at the opening.

6. A semiconductor device according to any one of claims 1 to 5, wherein the first semiconductor layer has a region that overlaps with the second semiconductor layer.

7. A semiconductor device according to any one of claims 1 to 5, wherein the first transistor comprises a fourth insulating layer and a fourth conductive layer, the fourth insulating layer being located on the first semiconductor layer, and the fourth conductive layer having a region facing the side surface of the second insulating layer via the fourth insulating layer and the first semiconductor layer.

8. A semiconductor device according to any one of claims 1 to 5, wherein the first semiconductor layer and the second semiconductor layer each comprise indium and oxygen.

9. The semiconductor device according to claim 8, wherein the first semiconductor layer is made of the same material as the second semiconductor layer.

10. The semiconductor device according to claim 8, wherein the first semiconductor layer is made of a different material from the second semiconductor layer.

11. The semiconductor device according to claim 8, wherein the first semiconductor layer has indium oxide, and the indium content in the first semiconductor layer is higher than the indium content in the second semiconductor layer.

12. The semiconductor device according to claim 8, wherein the second semiconductor layer has indium oxide, and the indium content in the second semiconductor layer is higher than the indium content in the first semiconductor layer.

13. A semiconductor device according to any one of claims 1 to 5, wherein the first semiconductor layer and the second semiconductor layer each have indium oxide.

14. A semiconductor device according to any one of claims 1 to 5, wherein the first semiconductor layer comprises indium and oxygen, and the second semiconductor layer comprises silicon.

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