Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device having micro-sized transistors. This semiconductor device has two vertical transistors (first transistor and second transistor). The first transistor and the second transistor have different structures. The second transistor is layered on the first transistor. One of either a source electrode or a drain electrode (whichever is located on the side far from a substrate surface) of the first transistor and one of either a source electrode or a drain electrode (whichever is located on the side near the substrate surface) of the second transistor are connected.

Description

Semiconductor device and method for manufacturing the same

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a display device, a display module, and an electronic device. One aspect of the present invention relates to a method for manufacturing a transistor, a method for manufacturing a semiconductor device, and a method for manufacturing a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device having these, a driving method thereof, or a manufacturing method thereof.

[0003] In the present specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip provided with an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. In addition, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device are semiconductor devices themselves and may each have a semiconductor device.

[0004] A semiconductor device having a transistor is widely applied to display devices and electronic devices, and higher integration and higher speed of semiconductor devices are required. For example, when applying a semiconductor device to a high-definition display device, a semiconductor device with a high degree of integration is required. As one means for increasing the integration degree of a semiconductor device, the development of transistors with a fine size is underway.

[0005] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitute reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproduction in order to enhance the sense of reality and immersion. Examples of such display devices include liquid crystal displays, organic EL (Electroluminescence) devices, and light-emitting devices (also called light-emitting elements) such as light-emitting diodes (LEDs).

[0006] Patent Document 1 discloses a display device for VR using an organic EL device (also called an organic EL element).

[0007] International Publication No. 2018 / 087625

[0008] One aspect of the present invention aims to provide a semiconductor device having a minutely sized transistor and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a miniature semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with a large on-current and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good electrical characteristics and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a highly integrated semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a high-resolution display device.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0010] To further increase the integration of semiconductor devices, it is effective to miniaturize the transistors in the device and to devise a better layout for them. For example, instead of arranging multiple transistors in a semiconductor device on the same plane, it is effective to stack them perpendicular to the substrate surface. This allows for higher integration of the semiconductor device without increasing the area occupied by the transistors on the substrate surface.

[0011] When stacking transistors, it is preferable that the transistors on the lower layer have a structure with fewer irregularities, or a structure in which the area occupied by irregularities is small relative to the total area of ​​the transistor. This allows the transistors on the upper layer to have a flat or substantially flat surface to be formed, thereby enabling miniaturization of the transistors. It is preferable that the transistors on the lower layer have a structure with fewer irregularities, or a structure in which the area occupied by irregularities is small relative to the total area of ​​the transistor, compared to the transistors on the upper layer.

[0012] It is preferable that the transistors placed on the upper layer are smaller in size than the transistors placed on the lower layer. This allows for the placement of many transistors on the upper layer, thus enabling miniaturization of the semiconductor device even when the number of transistors constituting the semiconductor device is large. It is preferable that the transistors placed on the upper layer have a smaller area in plan view than, at least, the transistors placed on the lower layer.

[0013] One aspect of the Future comprises a first transistor, a second transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer, wherein the first transistor comprises a first semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fourth insulating layer, and the second transistor comprises a second semiconductor layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and a fifth insulating layer, and the first insulating layer The first conductive layer is provided on the second conductive layer, the third conductive layer is provided on the first insulating layer, the first insulating layer and the third conductive layer have a first opening that reaches the second conductive layer, and within the first opening, the first semiconductor layer is provided in contact with the upper surface of the second conductive layer, the side surface of the first insulating layer and the side surface of the third conductive layer, the fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer, and the fourth conductive layer has a region that overlaps with the first opening. The semiconductor device is provided in contact with the upper surface of the fourth insulating layer, the second insulating layer is provided on the fourth conductive layer so as to fill the first opening and has a second opening that reaches the third conductive layer, the first conductive layer is provided in contact with the upper surface of the third conductive layer so as to fill the second opening, the fifth conductive layer is provided in contact with the upper surface of the first conductive layer, the third insulating layer is provided on the fifth conductive layer, the sixth conductive layer is provided on the third insulating layer, the third insulating layer and the sixth conductive layer are provided in an island-like manner so as to have a region that overlaps with the fifth conductive layer, the second semiconductor layer is provided in contact with the upper surface of the fifth conductive layer, the side surface of the third insulating layer and the side surface of the sixth conductive layer, the fifth insulating layer is provided in contact with the upper surface of the second semiconductor layer, and the seventh conductive layer is provided in contact with the upper surface of the fifth insulating layer so as to have a region that overlaps with the second semiconductor layer.

[0014] Furthermore, in the above, the first semiconductor layer and the second semiconductor layer are each oxide semiconductor layers having indium, the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the third insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have silicon and nitrogen, and the seventh insulating layer and the tenth insulating layer each have silicon and oxygen.

[0015] Furthermore, in the above, it is preferable that the second insulating layer has one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.

[0016] Furthermore, in the above, the first transistor has an eighth conductive layer, and the eighth conductive layer is provided between the second conductive layer and the third conductive layer such that it has a region that overlaps with the second conductive layer and the third conductive layer, and within the first opening, one surface of the first semiconductor layer faces the fourth conductive layer and the other surface of the first semiconductor layer faces the eighth conductive layer.

[0017] Furthermore, one aspect of the present invention comprises a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first transistor comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer, wherein the second transistor comprises a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a fifth insulating layer, wherein the first insulating layer is provided on the first conductive layer, the second conductive layer is provided on the first insulating layer, the first insulating layer and the second conductive layer have a first opening that reaches the first conductive layer, within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer, the fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer, and the third The semiconductor device comprises a conductive layer provided in contact with the upper surface of a fourth insulating layer such that it has a region overlapping with a first opening, a second insulating layer provided on a third conductive layer so as to fill the first opening, a fourth conductive layer provided in contact with the upper surface of the second insulating layer and a part of the upper surface of the third conductive layer, a third insulating layer provided on a fourth conductive layer, a fifth conductive layer provided on a third insulating layer, the third insulating layer and the fifth conductive layer provided in an island-like manner such that they have a region overlapping with the fourth conductive layer, a second semiconductor layer provided in contact with the upper surface of the fourth conductive layer, a side surface of the third insulating layer, and a side surface of the fifth conductive layer, a fifth insulating layer provided in contact with the upper surface of the second semiconductor layer, and a sixth conductive layer provided in contact with the upper surface of the fifth insulating layer such that it has a region overlapping with the second semiconductor layer.

[0018] Furthermore, in the above, the first semiconductor layer and the second semiconductor layer are each oxide semiconductor layers having indium, the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the third insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have silicon and nitrogen, and the seventh insulating layer and the tenth insulating layer each have silicon and oxygen.

[0019] Furthermore, in the above, it is preferable that the second insulating layer has one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.

[0020] Furthermore, in the above, the first transistor has a seventh conductive layer, and the seventh conductive layer is provided between the first conductive layer and the second conductive layer such that it has a region that overlaps with the first conductive layer and the second conductive layer, and within the first opening, one surface of the first semiconductor layer faces the third conductive layer and the other surface of the first semiconductor layer faces the seventh conductive layer.

[0021] Furthermore, in one aspect of the present invention, a first conductive layer, a first insulating film, and a first conductive film are formed in this order, a portion of the first insulating film and the first conductive film is removed to form a first opening reaching the first conductive layer, and a first insulating layer and a second conductive layer are formed, a first semiconductor layer is formed within the first opening in contact with the side surface of the second conductive layer, the side surface of the first insulating layer, and the upper surface of the first conductive layer, a second insulating layer is formed in contact with the upper surface of the first semiconductor layer, a third conductive layer is formed in contact with the upper surface of the second insulating layer so as to have a region overlapping with the first opening, a third insulating layer is formed on the third conductive layer so as to fill the first opening, a portion of the third insulating layer is removed to form a second opening reaching the second conductive layer This is a method for manufacturing a semiconductor device, comprising: forming a mouth portion and a fourth conductive layer in contact with the upper surface of the second conductive layer so as to fill the second opening; forming a fifth conductive layer in contact with the upper surface of the fourth conductive layer; forming a second insulating film and a second conductive film on the fifth conductive layer in this order; removing a portion of each of the second insulating film and the second conductive film to form island-shaped fourth insulating layers and sixth conductive layers having a region that overlaps with the fifth conductive layer; forming a second semiconductor layer in contact with the upper surface of the fifth conductive layer, the side surface of the fourth insulating layer, and the side surface of the sixth conductive layer, respectively; forming a fifth insulating layer in contact with the upper surface of the second semiconductor layer; and forming a seventh conductive layer in contact with the upper surface of the fifth insulating layer so as to have a region that overlaps with the second semiconductor layer.

[0022] According to one aspect of the present invention, a semiconductor device having a minutely sized transistor and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a miniature semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with a large on-current and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good electrical characteristics and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a highly integrated semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a high-definition display device can be provided.

[0023] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0024] Figure 1A is a plan view showing an example of a semiconductor device. Figure 1B is a cross-sectional view showing an example of a semiconductor device. Figure 2A is a cross-sectional view showing an example of a semiconductor device. Figures 2B and 2C are circuit diagrams illustrating a semiconductor device. Figures 3A and 3B are cross-sectional views showing an example of a semiconductor device. Figures 4A and 4B are plan views showing an example of a semiconductor device. Figure 5A is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 5B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6A is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 6B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 7A is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 7B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 8A is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 8B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 9A is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 9B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 10A is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 10B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 11A is a plan view showing an example of a semiconductor device manufacturing method. Figure 11B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 12A is a plan view showing an example of a semiconductor device manufacturing method. Figure 12B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 13A is a plan view showing an example of a semiconductor device manufacturing method. Figure 13B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 14A is a plan view showing an example of a semiconductor device manufacturing method. Figure 14B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 15A is a plan view showing an example of a semiconductor device manufacturing method. Figure 15B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 16A is a plan view showing an example of a semiconductor device manufacturing method. Figure 16B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 17A is a plan view showing an example of a semiconductor device manufacturing method. Figure 17B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 18A is a plan view showing an example of a semiconductor device manufacturing method. Figure 18B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 19 is a block diagram of a display device.Figures 20A, 20B, 20C, and 20D are circuit diagrams of pixel circuits. Figures 21A, 21B, and 21C are circuit diagrams of pixel circuits. Figures 22A, 22B, and 22C are plan views showing an example of a semiconductor device fabrication method. Figures 23A, 23B, and 23C are plan views showing an example of a semiconductor device fabrication method. Figures 24A, 24B, and 24C are plan views showing an example of a semiconductor device fabrication method. Figures 25A, 25B, and 25C are plan views showing an example of a semiconductor device fabrication method. Figures 26A, 26B, and 26C are plan views showing an example of a semiconductor device fabrication method. Figures 27A, 27B, and 27C are plan views showing an example of a semiconductor device fabrication method. Figures 28A, 28B, and 28C are plan views showing an example of a semiconductor device fabrication method. Figures 29A, 29B, and 29C are plan views showing an example of a semiconductor device manufacturing method. Figures 30A, 30B, and 30C are plan views showing an example of a semiconductor device manufacturing method. Figures 31A, 31B, and 31C are plan views showing an example of a semiconductor device manufacturing method. Figures 32A, 32B, and 32C are plan views showing an example of a semiconductor device manufacturing method. Figures 33A, 33B, and 33C are plan views showing an example of a semiconductor device. Figures 34A, 34B, and 34C are plan views showing an example of a semiconductor device. Figure 35 is a perspective view showing an example of a display device. Figure 36 is a cross-sectional view showing an example of a display device. Figure 37 is a cross-sectional view showing an example of a display device. Figure 38 is a cross-sectional view showing an example of a display device. Figure 39 is a cross-sectional view showing an example of a display device. Figures 40A, 40B, 40C, and 40D are diagrams showing an example of an electronic device. Figures 41A, 41B, 41C, 41D, 41E, and 41F show examples of electronic devices. Figures 42A, 42B, 42C, 42D, 42E, 42F, and 42G show examples of electronic devices.

[0025] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0026] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0027] The positions, sizes, and extents of each component shown in the drawings may not represent their actual positions, sizes, and extents for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the drawings.

[0028] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0029] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0030] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, etc., depending on the situation.

[0031] The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" can be used interchangeably. Furthermore, the names of the gate and back gate of a transistor can be appropriately rephrased as needed, such as gate electrode and back gate electrode.

[0032] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0033] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0034] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0035] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0036] In this specification, a structure in which at least the light-emitting layers are created separately for light-emitting devices with different emission wavelengths may be referred to as an SBS (Side By Side) structure. Because the SBS structure allows for the optimization of materials and configuration for each light-emitting device, it increases the degree of freedom in selecting materials and configurations, making it easier to improve brightness and reliability.

[0037] In this specification, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole block layer or electron block layer may be called a "carrier block layer." It should be noted that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable by their cross-sectional shape or characteristics. Furthermore, a single layer may combine the functions of two or three of these layers.

[0038] In this specification, a light-emitting device has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. The layers (also called functional layers) of the EL layer include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer).

[0039] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0040] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it refers to a shape having a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities.

[0041] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (for example, a step or other difference in height).

[0042] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0043] In this specification, "approximately matching top surface shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in these cases, it may also be said that the "top surface shapes are approximately matching."

[0044] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0045] Furthermore, in this specification, "approximately matching height" refers to a configuration in which the height from a reference surface (for example, a flat surface such as the substrate surface) is approximately equal in a cross-sectional view. For example, when a planarization treatment (typically chemical mechanical polishing (CMP) treatment) is performed, the treated surface will have approximately matching height. However, even after a planarization treatment, the height may not be exactly the same depending on the film material, but in this specification, this is also considered to be "approximately matching height".

[0046] (Embodiment 1) This embodiment describes a semiconductor device, a method for manufacturing a semiconductor device, and the like according to one aspect of the present invention.

[0047] One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer.

[0048] Both the first and second transistors are vertical transistors in which the source electrode and drain electrode are provided at different heights relative to the substrate surface, and the drain current flows in the vertical direction. Therefore, miniaturization and reduction of the occupied area can be achieved compared to planar transistors in which the source electrode and drain electrode are provided on the same plane. The above-described structure of the first and second transistors enables miniaturization and high integration of the semiconductor device.

[0049] Furthermore, the second transistor is stacked on top of the first transistor. Therefore, the semiconductor device can be miniaturized and highly integrated compared to the case where the first and second transistors are located on the same plane.

[0050] It is preferable that the first transistor and the second transistor are arranged so as to have overlapping regions. Furthermore, it is preferable that the area of ​​the overlapping region of the first transistor and the second transistor is large. This allows for a further reduction in the area occupied by the semiconductor device, thereby enabling further integration of the semiconductor device.

[0051] The first insulating layer is provided so as to have a region sandwiched between the source electrode and the drain electrode of the first transistor. The second insulating layer is provided so as to cover the first transistor and has a flat upper surface. The third insulating layer is provided so as to have a region sandwiched between the source electrode and the drain electrode of the second transistor.

[0052] The second transistor can also be described as being provided on the first transistor via a second insulating layer. The first conductive layer is provided so as to be embedded in the second insulating layer. The first conductive layer has regions that are in contact with the upper surface of one of the source or drain electrodes of the first transistor (here, the electrode located on the side furthest from the substrate surface) and the lower surface of one of the source or drain electrodes of the second transistor (here, the electrode located on the side closer to the substrate surface).

[0053] An opening is provided in either the source electrode or the drain electrode of the first transistor, and in the first insulating layer, that reaches the other source electrode or drain electrode of the first transistor (in this case, the electrode located closer to the substrate surface). The first transistor is provided with a semiconductor layer that functions as a channel forming region, in contact with the source electrode and the drain electrode, so as to encompass the opening.

[0054] The source electrode or drain electrode of the second transistor (in this case, the electrode located on the side furthest from the substrate surface), and the third insulating layer are provided in an island-like manner, having a region that overlaps with one of the source electrode or drain electrode of the second transistor. The second transistor is provided in contact with the source electrode and the drain electrode, with a semiconductor layer that functions as a channel-forming region having a region that overlaps with the side surface of the island-like structure.

[0055] Although the first insulating layer is provided with the aforementioned openings, it can be said that it has a configuration in which the area occupied by the uneven portion is smaller in proportion to the total area of ​​the layer compared to the second insulating layer which is provided in an island-like shape. Therefore, the surface on which the second transistor is formed on the first transistor can be made flat or substantially flat, and an extremely fine second transistor can be formed on the first transistor with high precision.

[0056] In the first transistor, either the source electrode or the drain electrode, and the semiconductor layer must be provided so as to enclose at least the aforementioned opening; therefore, the size of these components in plan view limits the overall size of the first transistor in plan view.

[0057] On the other hand, in the second transistor, the semiconductor layer only needs to be arranged so as to overlap with at least one of the sides of the aforementioned island-shaped structure, so the overall size of the transistor in a plan view can be significantly reduced compared to the first transistor.

[0058] Therefore, the structure composed of the second transistor and the third insulating layer, although inferior in flatness to the structure composed of the first transistor and the first insulating layer provided beneath it, can be said to be superior in terms of transistor miniaturization and high integration.

[0059] In this way, by applying vertical transistors with different structures to the first and second transistors, and combining them, it is possible to create a semiconductor device that complements each other's shortcomings while utilizing each other's advantages. For example, in the case of a semiconductor device composed of two-layer stacked transistors, a vertical transistor with superior flatness compared to the second layer (the first transistor) is applied to the first layer, and a vertical transistor smaller in size than the first layer (the second transistor) is stacked in the second layer. This prevents a significant increase in the occupied area of ​​the semiconductor device, even when there are many transistors constituting the semiconductor device, and enables miniaturization of the semiconductor device.

[0060] For example, by using a semiconductor device according to one aspect of the present invention in the pixel circuit of a display device, an extremely high-resolution display device can be realized.

[0061] In the following section, a specific example of the configuration of a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0062] <Example of Semiconductor Device Configuration 1> Figure 1A shows a plan view (also called a top view) of the semiconductor device 100. Figure 1B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 1A. Figure 2B shows an equivalent circuit diagram of the semiconductor device 100. Note that in Figure 1A, some of the components of the semiconductor device 100 (such as the insulating layer) are omitted. In subsequent drawings of semiconductor devices, some of the components will also be omitted, similar to Figure 1A.

[0063] The semiconductor device 100 is provided on a substrate 102. Although not shown in Figure 1B, etc., an insulating layer that functions as an underlay can also be provided between the substrate 102 and the semiconductor device 100. The semiconductor device 100 includes a transistor 10_1, a transistor 10_2, an insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1), an insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2), an insulating layer 192, an insulating layer 193, an insulating layer 194, and a conductive layer 115. Transistors 10_1 and 10_2 are provided superimposed in this order.

[0064] The transistor 10_1 has a conductive layer 104_1, an insulating layer 106_1, a semiconductor layer 108_1, a conductive layer 112a1, and a conductive layer 112b1. The conductive layer 104_1 functions as a gate electrode. A portion of the insulating layer 106_1 functions as a gate insulating layer. The conductive layer 112a1 functions as either a source electrode or a drain electrode. The conductive layer 112b1 functions as either a source electrode or a drain electrode. Of the semiconductor layer 108_1, the entire region that overlaps with the gate electrode via the gate insulating layer between the source electrode and the drain electrode functions as a channel forming region. Furthermore, of the semiconductor layer 108_1, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region.

[0065] The above explanation relating to transistor 10_1 can be applied to transistor 10_2 by replacing the conductive layer 104_1, insulating layer 106_1, semiconductor layer 108_1, conductive layer 112a1, and conductive layer 112b1 with conductive layer 104_2, insulating layer 106_2, semiconductor layer 108_2, conductive layer 112a2, and conductive layer 112b2, respectively.

[0066] The detailed configuration of the semiconductor device 100 will now be described.

[0067] A conductive layer 112a1 is provided on the substrate 102. An insulating layer 110a1 is provided on the conductive layer 112a1 and on the substrate 102. An insulating layer 110b1 is provided on the insulating layer 110a1. An insulating layer 110c1 is provided on the insulating layer 110b1. A conductive layer 112b1 is provided on the insulating layer 110c1. Note that insulating layers 110a1, 110b1, and 110c1 are sometimes collectively referred to as insulating layer 110_1.

[0068] The conductive layer 112a1, the insulating layer 110_1, and the conductive layer 112b1 have overlapping regions. In these regions, the insulating layer 110_1 is provided so as to be sandwiched between the conductive layer 112a1 and the conductive layer 112b1.

[0069] The insulating layer 110_1 and the conductive layer 112b1 have openings 143 that reach the conductive layer 112a1.

[0070] The top surface shape of the opening 143 can be, for example, circular or elliptical. The top surface shape of the opening 143 can also be a polygon such as a triangle, quadrilateral (including rectangle, rhombus, and square), pentagon, or a polygon with rounded corners. As shown in Figure 1A, the top surface shape of the opening 143 is preferably circular. By making the top surface shape of the opening 143 circular, the processing accuracy when forming the opening 143 can be improved, and a fine-sized opening 143 can be formed. In this specification, the term "circular" is not limited to a perfect circle.

[0071] In Figure 1B, the thickness of the conductive layer 112a1 in the region overlapping with the opening 143 is shown to be approximately equal to the thickness of the region not overlapping with the opening 143, but this is not limited to this configuration. The thickness of the conductive layer 112a1 in the region overlapping with the opening 143 can be thinner than the thickness of the region not overlapping with the opening 143. In this case, the electric field from the conductive layer 104_1 (i.e., the gate electric field of transistor 10_1) can be applied to the channel formation region near the conductive layer 112a1. Therefore, the effect of the gate electric field on carriers in the channel formation region can be strengthened compared to when the thickness of the conductive layer 112a1 is uniform.

[0072] A semiconductor layer 108_1 is provided in contact with the upper surface of the conductive layer 112a1 within the opening 143, the side surface of the insulating layer 110_1 within the opening 143, the side surface of the conductive layer 112b1 within the opening 143, and the upper surface of the conductive layer 112b1.

[0073] Although Figure 1B shows a configuration in which the semiconductor layer 108_1 has a region in contact with the upper surface of the conductive layer 112b1, this is not the only configuration. The semiconductor layer 108_1 only needs to have a region in contact with the side surface of the conductive layer 112b1 within the opening 143.

[0074] For example, by configuring the entire area of ​​the semiconductor layer 108_1 to be located within the opening 143, and the edges of the semiconductor layer 108_1 to be in contact only with the side surface of the conductive layer 112b1 within the opening 143, it is possible to suppress the occurrence of a step on the conductive layer 112b1 due to the edges of the semiconductor layer 108_1. This makes it possible to improve the coverage of the film that has the upper surface of the conductive layer 112b1 as the surface to be formed.

[0075] On the other hand, as shown in Figure 1B, by having the end of the semiconductor layer 108_1 extend to the outside of the opening 143, and configuring the semiconductor layer 108_1 to contact not only the side surface of the conductive layer 112b1 within the opening 143 but also the upper surface of the conductive layer 112b1, the contact area between the semiconductor layer 108_1 and the conductive layer 112b1 can be increased. This can suppress delamination of the semiconductor layer 108_1. In addition, the contact resistance between the semiconductor layer 108_1 and the conductive layer 112b1 becomes smaller, which may allow the on-current of the transistor 10_1 to be increased.

[0076] Here, it is preferable that the insulating layer 110b1 of the insulating layer 110_1 is an insulating layer containing oxygen. Furthermore, it is preferable that it is an insulating layer that releases oxygen when heated. This allows, for example, when a metal oxide is used for the semiconductor layer 108_1, the oxygen contained in the insulating layer 110b1 to be supplied to the metal oxide. This allows oxygen deficiencies in the metal oxide to be repaired, thereby improving the electrical characteristics and reliability of the transistor 10_1.

[0077] On the other hand, among the insulating layers 110_1, it is preferable that insulating layers 110a1 and 110c1 are insulating layers that have barrier properties against gases such as oxygen and hydrogen. This makes it possible to suppress the release of oxygen contained in insulating layer 110b1 to the outside through insulating layer 110a1 or insulating layer 110c1. Furthermore, it is possible to suppress the diffusion of hydrogen from outside the insulating layer 110_1 into insulating layer 110b1 through insulating layer 110a1 or insulating layer 110c1, and the diffusion of said hydrogen into semiconductor layer 108_1. For example, when a metal oxide is used for semiconductor layer 108_1, hydrogen in semiconductor layer 108_1 can be a factor that degrades the electrical characteristics and reliability of transistor 10_1.

[0078] In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also known as low permeability), or the function of capturing or fixing the corresponding substance (also known as gettering). Furthermore, in this specification, an insulating layer having barrier properties may be referred to as a barrier insulating layer.

[0079] An insulating layer 106_1 is provided on the semiconductor layer 108_1. The insulating layer 106_1 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108_1, the upper and side surfaces of the conductive layer 112b1, and the upper surface of the insulating layer 110c1.

[0080] A conductive layer 104_1 is provided on the insulating layer 106_1. The conductive layer 104_1 is provided in contact with the upper surface of the insulating layer 106_1 such that, in a plan view, it has a region that overlaps with the opening 143. Within the opening 143, the conductive layer 104_1 has a shape that conforms to the shapes of the semiconductor layer 108_1 and the insulating layer 106_1. That is, the conductive layer 104_1 has a recess on its upper surface that corresponds to the shape of the opening 143. Within the opening 143, the conductive layer 104_1 has a region that faces the semiconductor layer 108_1 via the insulating layer 106_1.

[0081] Furthermore, the conductive layer 104_1 can also be formed to embed the opening 143. For example, depending on the depth of the opening 143 or the size of its diameter in a plan view (specifically, when the aspect ratio of the opening 143 is small), the conductive layer 104_1 may be formed to be embedded in the opening 143. In this case, the step or unevenness formed on the upper surface of the conductive layer 104_1 in the region overlapping with the opening 143 is reduced, which is preferable because it improves the coverage of the layer formed on top of it.

[0082] An insulating layer 192 is provided on the conductive layer 104_1. The insulating layer 192 has regions that are in contact with the upper surface and side surfaces of the conductive layer 104_1, as well as the upper surface of the insulating layer 106_1.

[0083] An insulating layer 193 is provided on the insulating layer 192 so as to fill the opening 143. The insulating layer 193 has the function of filling in and flattening steps or irregularities caused by the transistor 10_1. The upper surface of the insulating layer 193 has a generally flat shape. For the insulating layer 193, it is preferable to use, for example, an organic insulating material. This makes it possible to easily and productively flatten the recesses that have formed in the conductive layer 104_1.

[0084] The upper surface of the insulating layer 193 is preferably higher than the upper surface of the highest region of the insulating layer 192 as viewed from the substrate surface. Alternatively, the upper surface of the insulating layer 193 is preferably approximately the same height as the upper surface of the highest region of the insulating layer 192 as viewed from the substrate surface. This makes it possible to form a generally flat surface on which a layer (for example, a conductive layer 112a2) is formed on the insulating layer 193, thereby improving the coverage of the layer.

[0085] An insulating layer 194 is provided on the insulating layer 193. The insulating layer 194 has a region that is in contact with the upper surface of the insulating layer 193.

[0086] It is preferable to use the same materials for insulating layer 192 and insulating layer 194 as for insulating layer 110a1 and insulating layer 110c1, respectively. This makes it possible to suppress the diffusion of impurities such as hydrogen into transistor 10_1 from the layer above transistor 10_1 via insulating layer 192. Furthermore, it is possible to suppress the diffusion of impurities such as hydrogen into transistor 10_2 from the layer below transistor 10_2 via insulating layer 194.

[0087] Furthermore, if there is no concern about the diffusion of the aforementioned impurities, the device can be configured without one or both of the insulating layers 192 and 194. In this case, the number of steps involved in the manufacturing of the semiconductor device 100 can be reduced.

[0088] The insulating layers 106_1, 192, 193, and 194 are provided with openings 145 that reach the conductive layer 112b1, and the conductive layer 115 is provided so as to fill the openings 145. The conductive layer 115 has a region that is in contact with the upper surface of the conductive layer 112b1. The upper surface of the conductive layer 115 is approximately the same height as the upper surface of the insulating layer 194. The conductive layer 115 functions as a plug that connects the conductive layer 112b1 of transistor 10_1 and the conductive layer 112a2 of transistor 10_2.

[0089] By providing a conductive layer 115 that functions as a plug within the opening 145, the surface to be formed of the transistor 10_2 (in this case, the upper surface of the insulating layer 194 and the upper surface of the conductive layer 115) can be made to have a generally flat shape. Therefore, an extremely small transistor 10_2 can be formed on this surface with high precision.

[0090] In Figure 1B, etc., a configuration is shown in which a conductive layer 112b1, which functions as the other source electrode or drain electrode of transistor 10_1, and a conductive layer 112a2, which functions as one of the source electrode or drain electrode of transistor 10_2, are connected via a conductive layer 115 that functions as a plug. However, this is not the only configuration. For example, after forming openings 145 in insulating layers 106_1, 192, 193, and 194, a conductive film that will become the conductive layer 112a2 is formed on the insulating layer 194 so as to fill the openings 145. Subsequently, the conductive film can be processed to form the conductive layer 112a2. In this case, since the conductive layer 112b1 and the conductive layer 112a2 are in contact within the opening 145, it becomes unnecessary to provide the conductive layer 115, and the number of steps involved in the manufacture of the semiconductor device 100 can be reduced.

[0091] A conductive layer 112a2 is provided on the conductive layer 115 and the insulating layer 194. The conductive layer 112a2 is provided so as to have a region that overlaps with the conductive layer 115. The lower surface of the conductive layer 112a2 (the surface on the substrate 102 side) has a region that is in contact with the upper surface of the conductive layer 115.

[0092] It is preferable that the conductive layer 112a2 is provided such that it has a region that overlaps with the opening 143. This allows the transistor 10_2 to be formed superimposed on the transistor 10_1, thereby reducing the area occupied on the substrate surface of the semiconductor device 100.

[0093] An insulating layer 110a2 is provided on the conductive layer 112a2 and the insulating layer 194. An insulating layer 110b2 is provided on the insulating layer 110a2. An insulating layer 110c2 is provided on the insulating layer 110b2. A conductive layer 112b2 is provided on the insulating layer 110c2. Note that insulating layers 110a2, 110b2, and 110c2 are sometimes collectively referred to as insulating layer 110_2.

[0094] It is preferable to use the same materials for insulating layers 110a2, 110b2, and 110c2 as those used for insulating layers 110a1, 110b1, and 110c1, respectively. This allows, for example, when a metal oxide is used for the semiconductor layer 108_2, to supply oxygen from the insulating layer 110b2 to the metal oxide. It also prevents oxygen from the insulating layer 110b2 from being released to the outside via the insulating layer 110a2 or the insulating layer 110c2. Furthermore, it prevents hydrogen from diffusing into the insulating layer 110b2 from outside the insulating layer 110_2 via the insulating layer 110a2 or the insulating layer 110c2, and prevents that hydrogen from diffusing into the semiconductor layer 108_2.

[0095] When hydrogen diffuses into the semiconductor layer 108_2, the hydrogen contained in the semiconductor layer 108_2 reacts with oxygen bonded to metal atoms to form water, creating oxygen vacancies (V) in the semiconductor layer 108_2. Ｏ In some cases, an oxygen vacancy may be formed. Furthermore, a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V) may form. Ｏ (Denoted as H.) Hydrogen functions as a donor, and electrons, which are carriers, may be generated. Therefore, when hydrogen diffuses into the semiconductor layer 108_2, the transistor 10_2 is prone to normally-on characteristics, and its reliability may deteriorate. Accordingly, by having insulating layer 110_2 with insulating layer 110a2 and insulating layer 110c2, the above-mentioned problems in transistor 10_2 can be suppressed.

[0096] The conductive layer 112a2, the insulating layer 110_2, and the conductive layer 112b2 have overlapping regions. In these regions, the insulating layer 110_2 is provided so as to be sandwiched between the conductive layer 112a2 and the conductive layer 112b2.

[0097] The insulating layer 110_2 and the conductive layer 112b2 are provided in an island-like manner on the insulating layer 194 such that they overlap with the conductive layer 112a2. In a plan view, the edges of the insulating layer 110_2 and the conductive layer 112b2 coincide or roughly coincide. In Figures 1A and 1B, the space between adjacent insulating layers 110_2 and conductive layers 112b2 provided in an island-like manner is shown as a groove 144.

[0098] In Figure 1A, an example is shown where the distance between the two island-shaped insulating layers 110_2 and conductive layer 112b2 facing each other across the groove 144 is constant. However, this is not limited to this configuration, and the distance can vary depending on the location. Also, in Figure 1A, an example is shown where the sides of the two island-shaped insulating layers 110_2 and conductive layer 112b2 facing each other across the groove 144 are straight. However, this is not limited to this configuration, and some or all of the sides can have a curved shape.

[0099] In Figure 1B, the thickness of the conductive layer 112a2 in the region overlapping with the groove 144 is shown to be approximately equal to the thickness of the region not overlapping with the groove 144, but this is not limited to this configuration. Similar to the description of the conductive layer 112a1 and the opening 143 above, the conductive layer 112a2 can also be configured such that the thickness of the region overlapping with the groove 144 is thinner than the thickness of the region not overlapping with the groove 144.

[0100] A semiconductor layer 108_2 is provided such that it has a region that overlaps with the side surface of at least one of the two island-shaped insulating layers 110_2 and conductive layer 112b2 facing each other across the groove 144, the side surface of the insulating layer 110_2 and the conductive layer 112b2 facing the groove 144. The semiconductor layer 108_2 has a region that is in contact with the upper surface of the conductive layer 112a2 within the groove 144, the side surface of the insulating layer 110_2 within the groove 144, the side surface of the conductive layer 112b2 within the groove 144, and the upper surface of the conductive layer 112b2.

[0101] Although Figure 1B shows a configuration in which the semiconductor layer 108_2 has a region in contact with the upper surface of the conductive layer 112b2, this is not the only configuration. Similar to the above description of the semiconductor layer 108_1 and the conductive layer 112b1, the semiconductor layer 108_2 only needs to have a region in contact with the side surface of the conductive layer 112b2 within the groove 144.

[0102] An insulating layer 106_2 is provided on the semiconductor layer 108_2. The insulating layer 106_2 is provided so as to cover the island-shaped insulating layers 110_2 and conductive layer 112b2, as well as the semiconductor layer 108_2. The insulating layer 106_2 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108_2, the upper and side surfaces of the conductive layer 112b2, the upper surface of the conductive layer 112a2, the side surfaces of the insulating layer 110_2, and the upper surface of the insulating layer 194.

[0103] A conductive layer 104_2 is provided on the insulating layer 106_2. The conductive layer 104_2 is provided in contact with the upper surface of the insulating layer 106_2. In Figures 1A and 1B, an example is shown in which the conductive layer 104_2 is provided so as to cover both ends of the groove 144, but this is not limited to this. The conductive layer 104_2 only needs to be provided such that, in a plan view, it has a region that overlaps with the respective sides of the insulating layer 110_2 and conductive layer 112b2 on the side where the semiconductor layer 108_2 is provided, of the two island-shaped insulating layers 110_2 and conductive layer 112b2 that face each other across the groove 144. Within the groove 144, the conductive layer 104_2 has a shape that conforms to the shape of the semiconductor layer 108_2 and the insulating layer 106_2. The conductive layer 104_2 has a region within the groove 144 that faces the semiconductor layer 108_2 via the insulating layer 106_2.

[0104] As shown in Figures 1A and 1B, in transistor 10_1, a semiconductor layer 108_1 that functions as a channel formation region is provided in contact with the entire side surface of the insulating layer 110_1 within the opening 143, whereas in transistor 10_2, a semiconductor layer 108_2 that functions as a channel formation region is provided in contact with only one side surface of the two insulating layers 110_2 facing the groove 144. Therefore, in some cases, transistor 10_2 can be made smaller in size in a plan view than transistor 10_1.

[0105] On the other hand, the insulating layer 110_1 on which transistor 10_1 is provided has superior flatness over the entire substrate surface compared to the multiple island-shaped insulating layers 110_2 on which transistor 10_2 is provided, as described above. Therefore, in the case of a configuration in which multiple transistors are stacked, such as in the semiconductor device 100, transistor 10_1 is more suitable than transistor 10_2 as a transistor to be placed in the lower layer.

[0106] In Figures 1A and 1B, an example is shown in which the semiconductor layer 108_2 is provided in contact with only one side of the two insulating layers 110_2 facing the groove 144, but this is not limited to this configuration. The semiconductor layer 108_2 can also be provided extending toward A2 so as to contact the side opposite to the side in question. In this case, transistors that can function as channel formation regions can be formed in two locations (each side of the two insulating layers 110_2 facing the groove 144), so the number and integration density of transistors in the semiconductor device 100 can be increased without increasing the occupied area of ​​the semiconductor device 100.

[0107] Furthermore, the conductive layer 104_2 can also be formed to embed the groove 144. For example, depending on the depth of the groove 144 or the width of the groove 144 in a plan view (specifically, when the aspect ratio of the groove 144 is small), the conductive layer 104_2 may be formed to be embedded in the groove 144. In this case, the step or unevenness formed on the upper surface of the conductive layer 104_2 in the region overlapping with the groove 144 becomes smaller, which is preferable because it can improve the coverage of the layer formed on top of it.

[0108] In transistor 10_1, the source electrode and drain electrode are positioned at different heights relative to the surface of the substrate 102, which is the surface to be formed, and the drain current flows perpendicular to or approximately perpendicular to the surface of the substrate 102. Similarly, in transistor 10_2, the source electrode and drain electrode are positioned at different heights relative to the surface of the insulating layer 194, which is the surface to be formed, and the drain current flows perpendicular to or approximately perpendicular to the surface of the insulating layer 194, which is the surface to be formed. In other words, in transistors 10_1 and 10_2, the drain current can also be said to flow in the vertical direction. Therefore, a transistor according to one aspect of the present invention can be called a vertical transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor).

[0109] Since both transistors 10_1 and 10_2 can have their source and drain electrodes stacked on top of each other, they can be miniaturized compared to so-called planar transistors where the source and drain electrodes are arranged on the same plane. Furthermore, the area occupied by the transistors on the substrate can be significantly reduced.

[0110] Furthermore, in one embodiment of the present invention, the semiconductor device 100 has a configuration in which a transistor 10_2 is provided superimposed on a transistor 10_1 whose gate electrode recess, formed by the insulating layer 193, is substantially flattened. As a result, the area occupied by the transistors on the substrate surface can be significantly reduced compared to a configuration in which these two transistors are arranged on the same plane, thereby enabling miniaturization and high integration of the semiconductor device. For example, by using the semiconductor device according to one embodiment of the present invention in the pixel circuit of a display device using an organic EL device, an extremely high-resolution display device can be realized.

[0111] The channel length and channel width of transistor 10_1 will be described below.

[0112] In the semiconductor layer 108_1, the region in contact with the conductive layer 112a1 functions as either the source region or the drain region, the region in contact with the conductive layer 112b1 functions as either the source region or the drain region, and the region between the source region and the drain region functions as the channel-forming region.

[0113] The channel length of transistor 10_1 is the distance between the source region and the drain region. In Figure 1B, the channel length L10_1 of transistor 10_1 is shown by a dashed double arrow. In Figure 1B, the distance along the semiconductor layer 108_1 in the region between the conductive layer 112a1 and the conductive layer 112b1 is shown as the channel length L10_1 of transistor 10_1.

[0114] In addition, the channel length L10_1 of transistor 10_1 may be the thickness of the insulating layer 110_1 in the region sandwiched between the upper surface of the conductive layer 112a1 and the lower surface of the conductive layer 112b1. Alternatively, the channel length L10_1 of transistor 10_1 may be the thickness of the insulating layer 110b1. Or, the channel length L10_1 of transistor 10_1 may be the depth of the opening 143 (here, this corresponds to the sum of the thickness of the insulating layer 110_1 on the conductive layer 112a2 and the thickness of the conductive layer 112b1).

[0115] Here, the channel length L10_1 of transistor 10_1 is determined by the thickness of the insulating layer 110_1, the angle θ110_1 between the surface of the semiconductor layer 108_1 within the opening 143 (here, the side surface of the insulating layer 110_1 and the side surface of the conductive layer 112b1) and the surface of the insulating layer 110_1 (here, the upper surface of the conductive layer 112a1), etc., and is not affected by the performance of the exposure apparatus used to manufacture the transistor. Therefore, the channel length L10_1 can be set to a value smaller than the limiting resolution of the exposure apparatus, and a transistor of a very small size can be realized.

[0116] The channel length L10_1 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L10_1 can also be 100 nm or more and 1 μm or less. By shortening the channel length L10_1, the on-current of transistor 10_1 can be increased.

[0117] The thickness of the insulating layer 110_1 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less.

[0118] The angle θ110_1 can be, for example, 30 degrees or more and less than 90 degrees, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, 60 degrees or more and 80 degrees or less, 65 degrees or more and 80 degrees or less, or 70 degrees or more and 80 degrees or less. The angle θ110_1 can also be 90 degrees. A smaller angle θ110_1 is preferable because it improves the coverage of the layer (semiconductor layer 108_1, etc.) formed along the side wall of the opening 143. On the other hand, a value closer to 90 degrees is preferable because it reduces the area occupied by the transistor on the substrate surface.

[0119] The channel width of transistor 10_1 is the length of the source region or the drain region in a plan view (Figure 1A). In other words, the channel width of transistor 10_1 is the length of the region where the semiconductor layer 108_1 and the conductive layer 112a1 are in contact, or the length of the region where the semiconductor layer 108_1 and the conductive layer 112b1 are in contact, in a plan view. Alternatively, the channel width of transistor 10_1 may be an intermediate value between the length of the region where the semiconductor layer 108_1 and the conductive layer 112a1 are in contact, and the length of the region where the semiconductor layer 108_1 and the conductive layer 112b1 are in contact, in a plan view.

[0120] Here, the channel width of transistor 10_1 is described as the circumference of the region where the semiconductor layer 108_1 and the side surface of the conductive layer 112b1 on the side of the opening 143 are in contact. In Figure 1A, the channel width W10_1 of transistor 10_1 is shown by a solid double arrow. The channel width W10_1 can also be said to be the circumference of the opening 143 in a plan view.

[0121] The channel width W10_1 is determined by the shape of the top surface of the aperture 143, etc. The diameter of the aperture 143 refers to the shortest side of the smallest rectangle that circumscribes the aperture 143 in a plan view. When the aperture 143 is formed using photolithography, the diameter of the aperture 143 is greater than or equal to the limiting resolution of the exposure apparatus. This diameter is, for example, 0.20 μm or more and less than 5.0 μm. As shown in Figure 1A, if the top surface shape of the aperture 143 is circular, this diameter corresponds to the diameter of the aperture 143, and the channel width W10_1 is the value obtained by multiplying this diameter by pi (π).

[0122] Next, the channel length and channel width of transistor 10_2 will be described.

[0123] The channel length of transistor 10_2 can be determined by appropriately substituting each component of the transistor (for example, replacing the last number "1" of each symbol with "2"). In Figure 1B, the channel length L2 of transistor 10_2 is shown by a dashed double arrow. The angle between the surface of the semiconductor layer 108_2 within the groove 144 (here, the side surface of the insulating layer 110_2 and the side surface of the conductive layer 112b2) and the surface of the insulating layer 110_2 (here, the top surface of the conductive layer 112a2) is shown as angle θ110_2.

[0124] The channel width of transistor 10_2 is the length of the region where the semiconductor layer 108_2 and the conductive layer 112a2 are in contact, or the length of the region where the semiconductor layer 108_2 and the conductive layer 112b2 are in contact, in a plan view. Alternatively, the channel width of transistor 10_2 may be an intermediate value between the length of the region where the semiconductor layer 108_2 and the conductive layer 112a2 are in contact, and the length of the region where the semiconductor layer 108_2 and the conductive layer 112b2 are in contact, in a plan view.

[0125] Here, the channel width of transistor 10_2 is described as the length of the side in the region where the semiconductor layer 108_2 and the side surface of the conductive layer 112b2 on the groove 144 side are in contact. In Figure 1A, the channel width W10_2 of transistor 10_2 is shown by the double-headed arrow of the dashed line.

[0126] Note that while Figure 1A shows an example where the channel width W10_2 of transistor 10_2 has a linear shape in plan view, this is not always the case. Depending on the shape of the edges of the island-shaped insulating layer 110_2 and conductive layer 112b2, the channel width W10_2 of transistor 10_2 may have a curved shape in plan view.

[0127] The following describes the materials that can be used for each component of semiconductor devices.

[0128] [Semiconductor layer 108_1, semiconductor layer 108_2] The semiconductor material that can be used for semiconductor layer 108_1 and semiconductor layer 108_2 is not particularly limited. For example, a single semiconductor or a compound semiconductor can be used. As a single semiconductor, for example, silicon or germanium can be used. As a compound semiconductor, for example, gallium arsenide and silicon germanium can be used. As a compound semiconductor, an organic substance having semiconductor properties or a metal oxide (also called an oxide semiconductor) having semiconductor properties can be used. These semiconductor materials may also contain impurities that function as dopants (for example, when silicon is used as the semiconductor material, typical examples include elements such as phosphorus and boron).

[0129] The crystallinity of the semiconductor material used in semiconductor layer 108_1 and semiconductor layer 108_2 is not particularly limited, and either an amorphous semiconductor or a crystalline semiconductor (single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a crystalline semiconductor is preferable because it can suppress the degradation of transistor characteristics.

[0130] Semiconductor layer 108_1 and semiconductor layer 108_2 can be made of silicon. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

[0131] Transistors using amorphous silicon for semiconductor layers 108_1 and 108_2 can be formed on large glass substrates and manufactured at low cost. Transistors using polycrystalline silicon for semiconductor layers 108_1 and 108_2 have high field-effect mobility and can operate at high speeds. Furthermore, transistors using microcrystalline silicon for semiconductor layers 108_1 and 108_2 have higher field-effect mobility than transistors using amorphous silicon and can operate at high speeds.

[0132] The semiconductor layer 108_1 and semiconductor layer 108_2 preferably have a metal oxide (oxide semiconductor) having semiconductor properties. Examples of metal oxides that can be used in the semiconductor layer 108_1 and semiconductor layer 108_2 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, element M is preferably one or more selected from aluminum, gallium, yttrium, and tin. Gallium is more preferred for element M.

[0133] For semiconductor layer 108_1 and semiconductor layer 108_2, for example, indium oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also written as IWO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide containing silicon can be used.

[0134] For the formation of metal oxides, sputtering or atomic layer deposition (ALD) can be suitably used. However, when forming metal oxides by sputtering, the atomic ratio of the target material may differ from that of the metal oxide. In particular, with zinc, the atomic ratio of the metal oxide may be lower than that of the target material. Specifically, it may be between 40% and 90% of the zinc content in the target material.

[0135] When forming semiconductor layers 108_1 and 108_2 by ALD, it is preferable to use a film deposition method such as thermal ALD or PEALD (Plasma Enhanced ALD). Thermal ALD is preferred because it exhibits extremely high step coverage. PEALD is also preferred because, in addition to exhibiting high step coverage, it allows for low-temperature film deposition.

[0136] The composition of the metal oxides in semiconductor layer 108_1 and semiconductor layer 108_2 significantly affects the electrical characteristics and reliability of transistors 10_1 and 10_2, respectively.

[0137] For example, by increasing the indium content of the metal oxide, a transistor with a large on-current can be realized. Also, for example, by using a metal oxide that does not contain gallium or has a low gallium content in semiconductor layer 108_1 and semiconductor layer 108_2, a transistor with high reliability against positive bias application can be made. Also, for example, by applying a metal oxide with a low content of element M to semiconductor layer 108_1 and semiconductor layer 108_2, a transistor with high reliability against positive bias application can be made. Also, for example, by increasing the content of element M in the metal oxide, a transistor with high reliability against light can be made.

[0138] Details regarding the composition of the metal oxides in semiconductor layer 108_1 and semiconductor layer 108_2 will be described later.

[0139] It is preferable to use crystalline metal oxide layers for semiconductor layer 108_1 and semiconductor layer 108_2. For example, metal oxide layers having a CAAC (C-Axis Aligned Crystal) structure, polycrystalline structure, microcrystalline structure, nanocrystalline (nc: nano-crystal) structure, etc., can be used. By using crystalline metal oxide layers for semiconductor layer 108_1 and semiconductor layer 108_2, the defect level density in semiconductor layer 108_1 and semiconductor layer 108_2 can be reduced, and a highly reliable transistor can be realized. The CAAC structure is a crystalline structure in which multiple nanocrystals (typically multiple IGZO nanocrystals) have c-axis orientation, and in the a-b plane, the multiple nanocrystals are linked without orientation. In the CAAC structure, the grain boundaries (grains) are not as clearly visible in the a-b plane as in the polycrystalline structure, thus enabling the realization of a highly reliable transistor.

[0140] The higher the crystallinity of the metal oxide layers used in semiconductor layers 108_1 and 108_2, the lower the defect level density in semiconductor layers 108_1 and 108_2 can be. On the other hand, by using metal oxide layers with low crystallinity, it is possible to realize transistors that can carry large currents.

[0141] The semiconductor layer 108_1 and semiconductor layer 108_2 can also be a laminated structure of two or more metal oxide layers with different crystallinity. For example, a laminated structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer can be formed, in which the second metal oxide layer has regions with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer can have regions with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers in semiconductor layer 108_1 and semiconductor layer 108_2 can also have the same or approximately the same composition. By forming a laminated structure of metal oxide layers with the same composition, for example, they can be formed using the same sputtering target, thereby reducing manufacturing costs. For example, by using the same sputtering target and varying the ratio of the flow rate of oxygen gas to the total film deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), a laminated structure of two or more metal oxide layers with different crystallinity can be formed. Furthermore, the two or more metal oxide layers in semiconductor layer 108_1 and semiconductor layer 108_2 may have different compositions from each other.

[0142] The film thickness of semiconductor layer 108_1 and semiconductor layer 108_2 is preferably 3 nm to 100 nm, more preferably 5 nm to 100 nm, more preferably 10 nm to 100 nm, more preferably 10 nm to 70 nm, more preferably 15 nm to 70 nm, more preferably 15 nm to 50 nm, more preferably 20 nm to 50 nm, more preferably 20 nm to 40 nm, and more preferably 25 nm to 40 nm.

[0143] Here, we will explain the oxygen vacancies that may be formed in semiconductor layer 108_1 and semiconductor layer 108_2.

[0144] As described above, when oxide semiconductors are used for semiconductor layer 108_1 and semiconductor layer 108_2, hydrogen contained in the oxide semiconductor may react with oxygen bonded to metal atoms to form water, creating oxygen vacancies in the oxide semiconductor. Furthermore, a defect called V can form when hydrogen is added to the oxygen vacancy. ＯH can function as a donor, and electrons that are carriers may be generated. Also, a part of hydrogen may combine with oxygen that binds to metal atoms to generate electrons that are carriers. Therefore, a transistor using an oxide semiconductor rich in hydrogen tends to have normally-on characteristics. Also, since hydrogen in the oxide semiconductor is likely to move due to stresses such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate.

[0145] V Ｏ H can function as a donor of the oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, it may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, carrier concentration assuming a state where no electric field is applied may be used instead of donor concentration. That is, the "carrier concentration" described in this specification and the like may be able to be paraphrased as "donor concentration".

[0146] As described above, when an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, V in the semiconductor layer 108_1 and the semiconductor layer 108_2 Ｏ It is preferable to reduce H as much as possible to achieve high-purity intrinsic or substantially high-purity intrinsic. Thus, V Ｏ To obtain an oxide semiconductor with sufficiently reduced V H, it is necessary to remove impurities such as water and hydrogen in the oxide semiconductor (which may be described as dehydration and dehydrogenation treatment), and supply oxygen to the oxide semiconductor to repair oxygen vacancies (V Ｏ ). It is important to repair). V Ｏ By using an oxide semiconductor with sufficiently reduced defects such as V H in the channel formation region of the transistor, stable electrical characteristics can be imparted. Note that supplying oxygen to the oxide semiconductor to repair oxygen vacancies (V Ｏ ) may be referred to as an oxygen addition treatment.

[0147] When an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the carrier concentration of the oxide semiconductor in the region that functions as the channel formation region is 1×10 １８ cm−３ The following is preferable: 1 × 10 １７ cm −３ It is more preferable that it be less than 1 × 10 １６ cm −３ It is even more preferable that it be less than 1 × 10 １３ cm −３ It is even more preferable that it be less than 1 × 10 １２ cm −３ It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration of the oxide semiconductor in the region that functions as a channel-forming region, but for example, 1 × 10 −９ cm −３ It can be done this way.

[0148] Transistors using oxide semiconductors (hereinafter referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors exhibit remarkably low source-drain leakage current (hereinafter also called off-current) in the off state, allowing them to retain charge stored in a capacitor connected in series with the transistor for extended periods. Additionally, applying OS transistors to semiconductor devices can reduce the power consumption of those devices.

[0149] OS transistors can be applied to display devices. To increase the luminescence brightness of a light-emitting device included in the pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to silicon transistors (hereinafter referred to as Si transistors), OS transistors have a higher breakdown voltage between the source and drain, so a higher voltage can be applied between the source and drain of an OS transistor. Therefore, by applying an OS transistor to the drive transistor of a pixel circuit, the amount of current flowing through the light-emitting device can be increased, and the luminescence brightness of the light-emitting device can be increased.

[0150] When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage than a Si transistor. Therefore, by using an OS transistor as the driving transistor in a pixel circuit, the current flowing between the source and drain can be precisely controlled by the change in gate-source voltage, thus allowing for precise control of the current flowing to the light-emitting device. This allows for an increase in the number of grayscale levels in the pixel circuit.

[0151] In terms of the saturation characteristics of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be supplied to a light-emitting device, for example, even if there are variations in the current-voltage characteristics of the light-emitting device. In other words, when operating in the saturation region, the source-drain current remains almost unchanged even when the source-drain voltage is increased, thus stabilizing the luminescence brightness of the light-emitting device.

[0152] As described above, by using OS transistors in the drive transistors included in the pixel circuit, it is possible to achieve "suppression of black level floating," "increase in luminescence brightness," "multi-gradation," and "suppression of variations in light-emitting devices."

[0153] OS transistors exhibit small fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0154] [Insulating Layer] In a transistor according to one aspect of the present invention, and in a semiconductor device, display device, etc. to which a transistor according to one aspect of the present invention is applied, an inorganic insulating material or an organic insulating material can be used as the insulating layer (insulating layer 110_1, insulating layer 110_2, insulating layer 106_1, insulating layer 106_2, insulating layer 192, insulating layer 193, and insulating layer 194). Furthermore, a laminated structure of an inorganic insulating material and an organic insulating material can also be used as the insulating layer.

[0155] As the inorganic insulating material, one or more oxides, oxidized nitrides, nitride oxides, and nitrides can be used.

[0156] In this specification, the term "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content. The term "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, silicon oxide-nitride refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride oxide refers to a material in which the nitrogen content is greater than the oxygen content.

[0157] For the analysis of oxygen and nitrogen content, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing elemental content, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0158] Furthermore, for evaluating the film density of insulating layers, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR) can be used. Differences in film density can also sometimes be evaluated using a cross-sectional transmission electron microscope (TEM) image. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a lighter (brighter) transmission electron (TE) image. Even when the same material is used for the insulating layer, differences in film density can sometimes be observed as differences in contrast at the boundaries between these densities in the cross-sectional TEM image.

[0159] The nitrogen content of an insulating layer can be confirmed, for example, by energy-dispersive X-ray spectroscopy (EDX). For example, when silicon nitride, silicon oxynitride, etc. are used for the insulating layer, the nitrogen content can be evaluated using the ratio of the peak height of nitrogen to the peak height of silicon. In EDX, the peak of a given element refers to the point where the count number of that element reaches its maximum value in a spectrum where the energy of the characteristic X-ray is shown on the horizontal axis and the count number (detection value) of the characteristic X-ray is shown on the vertical axis. Alternatively, the difference in nitrogen content can be confirmed by using the count number at the characteristic X-ray energy specific to that element and comparing it with the count number of nitrogen to the count number of silicon. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0160] The hydrogen concentration in the insulating layer can be evaluated, for example, using SIMS.

[0161] When hydrogen diffuses into semiconductor layer 108_1 and semiconductor layer 108_2, it reacts with oxygen atoms contained in the oxide semiconductor to form water, creating oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2. Ｏ) may be formed. Furthermore, V Ｏ H is formed, and the carrier concentration in semiconductor layer 108_1 and semiconductor layer 108_2 may become high. By using a barrier film that suppresses hydrogen diffusion as an insulating layer in contact with semiconductor layer 108_1 and semiconductor layer 108_2, or as an insulating layer located around semiconductor layer 108_1 and semiconductor layer 108_2, oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2 can be suppressed. Ｏ ) and V Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0162] Oxygen vacancies (V) in the channel formation regions of transistors 10_1 and 10_2 Ｏ ) and V Ｏ H is preferably low. In particular, when the channel length is short, oxygen deficiency (V) in the channel formation region is preferable. Ｏ ) and V Ｏ The effect of H on the electrical characteristics and reliability of transistors 10_1 and 10_2 becomes significant. For example, if V flows from the source region or drain region to the channel formation region... Ｏ When H diffuses, the carrier concentration in the channel formation region increases, which may cause fluctuations in the threshold voltage of transistors 10_1 and 10_2, or a decrease in reliability. Ｏ The effect of H diffusion on the electrical characteristics and reliability of transistors 10_1 and 10_2 increases as the channel length decreases. Semiconductor layer 108_1, semiconductor layer 108_2, in particular oxygen vacancies (V) in the channel formation region. Ｏ ) and V Ｏ By reducing H, it is possible to realize transistors with short channel lengths that have good electrical characteristics and high reliability.

[0163] By using an insulating layer that releases oxygen as an insulating layer in contact with semiconductor layer 108_1 and semiconductor layer 108_2 (for example, insulating layer 106_1, insulating layer 106_2, insulating layer 110b1, insulating layer 110b2), oxygen can be supplied from the insulating layer to semiconductor layer 108_1 and semiconductor layer 108_2. By supplying oxygen to the channel formation region of semiconductor layer 108_1 and semiconductor layer 108_2, oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2 can be reduced. Ｏ ) and V Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable. Other methods for supplying oxygen to semiconductor layers 108_1 and 108_2 include heating in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere.

[0164] It is preferable that the insulating layer in contact with semiconductor layer 108_1 and semiconductor layer 108_2, or the insulating layer located around semiconductor layer 108_1 and semiconductor layer 108_2, releases little impurities (e.g., water and hydrogen) from itself. The impurities referred to here are those that diffuse into semiconductor layer 108_1 and semiconductor layer 108_2, causing oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2. Ｏ ) and V Ｏ This refers to substances that can adversely affect the electrical characteristics of a transistor, such as by generating hydrogen (H). By reducing the release of impurities, the diffusion of these impurities into semiconductor layers 108_1 and 108_2 is suppressed, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0165] In some cases, oxygen may be removed from semiconductor layers 108_1 and 108_2 due to heat applied in processes after the formation of semiconductor layers 108_1 and 108_2. However, oxygen is supplied to semiconductor layers 108_1 and 108_2 from the insulating layer in contact with them, thus preventing oxygen deficiencies (V) in semiconductor layers 108_1 and 108_2. Ｏ ) and V ＯThis makes it possible to suppress the increase in H. Furthermore, it is possible to increase the degree of freedom in the processing temperature in the process after the formation of semiconductor layer 108_1 and semiconductor layer 108_2. Specifically, the processing temperature can be increased even in the process after the formation of semiconductor layer 108_1 and semiconductor layer 108_2. Therefore, it is possible to form transistors that exhibit good electrical characteristics and are highly reliable.

[0166] [Insulating layer 110_1, insulating layer 110_2] Insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) and insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) can be made of inorganic insulating material or organic insulating material. Insulating layer 110_1 and insulating layer 110_2 can also be made of a laminated structure of inorganic insulating material and organic insulating material.

[0167] Inorganic insulating materials can be suitably used as insulating layer 110_1 and insulating layer 110_2. One or more oxides, oxidized nitrides, nitride oxides, and nitrides can be used as inorganic insulating materials. For example, one or more silicon oxide, silicon oxidized nitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride can be used as insulating layer 110_1 and insulating layer 110_2.

[0168] The insulating layer 110_1 and insulating layer 110_2 can also be arranged in a laminated structure of two or more layers. In Figure 1B, etc., insulating layer 110_1 has a laminated structure of insulating layer 110a1, insulating layer 110b1 on insulating layer 110a1, and insulating layer 110c1 on insulating layer 110b1, and insulating layer 110_2 has a laminated structure of insulating layer 110a2, insulating layer 110b2 on insulating layer 110a2, and insulating layer 110c2 on insulating layer 110b2. Note that the insulating layers 110a1, 110b1, 110c1, 110a2, 110b2, and 110c2 can be made of the same material or different materials.

[0169] It is preferable that insulating layers 110_1 and 110_2 release very little impurities (e.g., water and hydrogen) from themselves.

[0170] The film thickness of insulating layer 110b1 and insulating layer 110b2 can be made thicker than the film thickness of insulating layer 110a1 and insulating layer 110a2, and the film thickness of insulating layer 110c1 and insulating layer 110c2. As mentioned above, insulating layer 110b1 and insulating layer 110b2 are insulating layers that contain oxygen to be supplied to semiconductor layer 108_1 and semiconductor layer 108_2, respectively. Therefore, by making the film thickness of insulating layer 110b1 and insulating layer 110b2 the thickest among the three insulating layers constituting insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) and the three insulating layers constituting insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2), the amount of oxygen that can be contained in the entire insulating layer 110_1 and the entire insulating layer 110_2 can be increased. It is preferable that the deposition rate of insulating layer 110b1 and insulating layer 110b2 is faster than the deposition rates of insulating layer 110a1 and insulating layer 110a2, and insulating layer 110c1 and insulating layer 110c2. By increasing the deposition rate of thicker films, productivity can be increased.

[0171] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, each function as a barrier film that suppresses the detachment of gas (e.g., oxygen) from the insulating layers 110b1 and 110b2, respectively. It is preferable to use materials that do not easily allow gas to diffuse for the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, respectively. It is preferable that the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, each have regions with a higher film density than the insulating layers 110b1 and 110b2, respectively. By increasing the film density of the insulating layers, the barrier properties against gas can be improved. By slowing down the film deposition rate of the insulating layers, the film density can be increased, and the barrier properties against gas can be improved.

[0172] It is preferable to use oxides or oxidized nitrides as insulating layers 110b1 and 110b2. It is preferable to use films that release oxygen upon heating as insulating layers 110b1 and 110b2. For example, silicon oxide or silicon oxidized nitride can be suitably used as insulating layers 110b1 and 110b2.

[0173] The insulating layers 110b1 and 110b2 release oxygen, allowing oxygen to be supplied from insulating layer 110b1 to semiconductor layer 108_1 and from insulating layer 110b2 to semiconductor layer 108_2, respectively. It is preferable that insulating layers 110b1 and 110b2 have high oxygen diffusion coefficients. By increasing the oxygen diffusion coefficient, oxygen can diffuse more easily through insulating layer 110b1 and insulating layer 110b2, allowing oxygen to be efficiently supplied to semiconductor layer 108_1 and semiconductor layer 108_2, respectively. Furthermore, as described above, by making the film thickness of insulating layer 110b1 and insulating layer 110b2 thicker than the film thickness of insulating layer 110a1 and insulating layer 110c1, and insulating layer 110a2 and insulating layer 110c2, respectively, more oxygen can be supplied to semiconductor layer 108_1 and semiconductor layer 108_2.

[0174] The insulating layer 110_1 and insulating layer 110_2 are preferably formed by a film deposition method such as sputtering, ALD, or plasma CVD.

[0175] In particular, by using the sputtering method and a deposition method that does not use a hydrogen-containing gas as the deposition gas, it is possible to create a film with an extremely low hydrogen content. Therefore, the supply of hydrogen to semiconductor layer 108_1 and semiconductor layer 108_2 can be suppressed, and the electrical characteristics of transistor 10_1 and transistor 10_2 can be stabilized. When depositing silicon oxide by sputtering, for example, the film can be deposited using a silicon target in an atmosphere containing an oxygen-containing gas. Similarly, when depositing silicon nitride by sputtering, for example, the film can be deposited using a silicon target in an atmosphere containing a nitrogen-containing gas. Furthermore, when depositing aluminum oxide by sputtering, for example, the film can be deposited using an aluminum target in an atmosphere containing an oxidizing gas.

[0176] Furthermore, silicon oxide and silicon nitride can be deposited using, for example, the PEALD method. Aluminum oxide and hafnium oxide can also be deposited using, for example, the thermal ALD method. By depositing an insulating layer using the PEALD method and the thermal ALD method, a dense insulating film can be formed, thereby improving barrier properties against oxygen and hydrogen.

[0177] The insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, can be made of materials with a higher nitrogen content than insulating layers 110b1 and 110b2, respectively. By increasing the nitrogen content of the insulating layers, the barrier properties against oxygen and hydrogen can be enhanced.

[0178] Furthermore, insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, may each have regions where the hydrogen concentration in the film is lower than that of insulating layer 110b1 and insulating layer 110b2, respectively.

[0179] It is preferable that insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, are impermeable to oxygen. Furthermore, it is preferable that insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, are impermeable to hydrogen. Insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, respectively, function as barrier films that suppress the diffusion of hydrogen from outside the transistor to semiconductor layers 108_1 and 108_2 via insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, respectively. Preferably, the film densities of insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, are higher than the film densities of insulating layers 110b1 and 110b2, respectively. Increasing the film density of the insulating layers can improve the barrier properties against oxygen and hydrogen. When silicon oxide or silicon oxide nitride is used for insulating layers 110b1 and 110b2, silicon nitride or silicon nitride oxide can be used for insulating layers 110a1, 110c1, 110a2, and 110c2, respectively. Furthermore, hafnium oxide or aluminum oxide can preferably be used as insulating layers 110a1, 110c1, 110a2, and 110c2.

[0180] Furthermore, the insulating layers 110a1, 110c1, 110a2, and 110c2 can be constructed by laminating two or more materials selected from silicon nitride, silicon oxide nitride, hafnium oxide, and aluminum oxide, respectively.

[0181] If the oxygen contained in insulating layers 110b1 and 110b2 diffuses downward (towards the substrate 102), the amount of oxygen supplied from insulating layers 110b1 and 110b2 to semiconductor layers 108_1 and 108_2, respectively, may decrease. By providing insulating layers 110a1 and 110a2 below insulating layers 110b1 and 110b2, respectively, the diffusion of oxygen contained in insulating layers 110b1 and 110b2 downward can be suppressed. Furthermore, by providing insulating layers 110c1 and 110c2 on top of insulating layers 110b1 and 110b2, respectively, it is possible to suppress the diffusion of oxygen contained in insulating layers 110b1 and 110b2 upwards. Consequently, the amount of oxygen supplied from insulating layers 110b1 and 110b2 to semiconductor layers 108_1 and 108_2 increases, and oxygen deficiencies (V) in semiconductor layers 108_1 and 108_2 are reduced. Ｏ ) and V Ｏ H can be reduced.

[0182] Furthermore, by providing insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, the diffusion of hydrogen into semiconductor layers 108_1 and 108_2 is suppressed, respectively, and oxygen vacancies (V) in semiconductor layers 108_1 and 108_2 are reduced. Ｏ ) and V Ｏ H can be reduced.

[0183] It is preferable that insulating layers 110a1 and 110c1, and insulating layers 110a2 and 110c2, each have a thickness that functions as a barrier film for oxygen and hydrogen. If the film thickness is too thin, the barrier function may be reduced. On the other hand, if the film thickness is too thick, the areas of semiconductor layers 108_1 and 108_2 that are in contact with insulating layers 110b1 and 110b2, respectively, become narrower, and the amount of oxygen supplied to semiconductor layers 108_1 and 108_2 may decrease. The film thickness of insulating layer 110a1, insulating layer 110c1, insulating layer 110a2, and insulating layer 110c2 is preferably 1 nm to 200 nm, 1 nm to 100 nm, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 2 nm to 5 nm, respectively.

[0184] [Insulating layer 106_1, insulating layer 106_2] Insulating layers 106_1 and 106_2, which function as gate insulating layers, preferably have a low defect density. A low defect density in insulating layers 106_1 and 106_2 allows for the creation of a transistor with good electrical characteristics. Furthermore, insulating layers 106_1 and 106_2 preferably have a high dielectric breakdown voltage. A high dielectric breakdown voltage in insulating layers 106_1 and 106_2 allows for the creation of a highly reliable transistor.

[0185] Furthermore, it is preferable that insulating layers 106_1 and 106_2 are insulating layers containing oxygen. It is also preferable that they are insulating layers that release oxygen upon heating. This allows, for example, when metal oxides are used for semiconductor layers 108_1 and 108_2, the oxygen contained in insulating layers 106_1 and 106_2 to be supplied to the respective metal oxides. This allows oxygen deficiencies in the metal oxides to be repaired, thereby improving the electrical characteristics and reliability of transistors 10_1 and 10_2.

[0186] For insulating layers 106_1 and 106_2, one or more insulating oxides, oxidized nitrides, nitride oxides, and nitrides can be used. For insulating layers 106_1 and 106_2, one or more silicon oxides, silicon oxidized nitrides, silicon nitrides, aluminum oxides, aluminum oxidized nitrides, aluminum nitrides, hafnium oxide, hafnium oxidized nitrides, gallium oxide, gallium oxidized nitrides, yttrium oxide, yttrium oxidized nitride, and Ga-Zn oxides can be used. Insulating layers 106_1 and 106_2 can be single layers or laminated layers. Insulating layers 106_1 and 106_2 can also have a laminated structure of oxides and nitrides, for example.

[0187] In miniature transistors, if the thickness of the gate insulating layer becomes too thin, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to lower the voltage during transistor operation while maintaining the physical thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0188] It is preferable that insulating layers 106_1 and 106_2 release little impurities (e.g., water and hydrogen) from themselves. By reducing the release of impurities from insulating layers 106_1 and 106_2, the diffusion of these impurities into semiconductor layers 108_1 and 108_2, respectively, is suppressed, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0189] Since insulating layers 106_1 and 106_2 are formed on semiconductor layer 108_1 and semiconductor layer 108_2, respectively, it is preferable that the films be formed under conditions that minimize damage to semiconductor layer 108_1 and semiconductor layer 108_2. For example, it is preferable to form them under conditions where the deposition rate (also called the deposition rate) is sufficiently slow. For example, when forming insulating layers 106_1 and 106_2 by plasma CVD, forming them under low power conditions can reduce the damage to semiconductor layer 108_1 and semiconductor layer 108_2.

[0190] Here, we will take a configuration in which metal oxides are used for semiconductor layers 108_1 and 108_2 as an example and explain the insulating layers 106_1 and 106_2 in detail.

[0191] To improve the interfacial properties with semiconductor layer 108_1 and semiconductor layer 108_2, it is preferable to use one or more oxides and oxidized nitrides on at least the side of insulating layer 106_1 that contacts semiconductor layer 108_1, and on at least the side of insulating layer 106_2 that contacts semiconductor layer 108_2. For insulating layer 106_1 and insulating layer 106_2, for example, one or more silicon oxide and silicon oxidized nitride can be suitably used. Furthermore, it is even more preferable to use films that release oxygen upon heating for insulating layer 106_1 and insulating layer 106_2.

[0192] Furthermore, insulating layers 106_1 and 106_2 can also be arranged in a laminated structure. Insulating layers 106_1 and 106_2 can each be arranged in a laminated structure consisting of an oxide film or oxynitride film on the side in contact with semiconductor layers 108_1 and 108_2, and a nitride film on the side in contact with conductive layers 104_1 and 104_2, respectively. For example, silicon oxide and silicon oxynitride can be suitably used as the oxide film or oxynitride film. For example, silicon nitride can be suitably used as the nitride film.

[0193] It is even more preferable that the film thickness of insulating layer 106_1 and insulating layer 106_2 be between 1 nm and 100 nm. It is sufficient that insulating layer 106_1 and insulating layer 106_2 have regions with the above-mentioned film thickness in at least a portion of their respective areas.

[0194] [Conductive layer 112a1, conductive layer 112b1, conductive layer 112a2, conductive layer 112b2] Conductive layers 112a1 and 112b1, and conductive layers 112a2 and 112b2, which function as source and drain electrodes, can each be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the aforementioned metals. Conductive layers 112a1 and 112b1, and conductive layers 112a2 and 112b2 can preferably use low-resistance conductive materials containing one or more of copper, silver, gold, or aluminum, respectively. Copper or aluminum are particularly preferred due to their excellent mass-producibility.

[0195] A metal oxide film (also called an oxide conductor) can be used for conductive layers 112a1 and 112b1, and conductive layers 112a2 and 112b2, respectively. Examples of oxide conductors (OC) include In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide.

[0196] Here, we will explain oxide conductors (OCs). For example, when an oxygen vacancy is formed in a metal oxide with semiconductor properties, and hydrogen is added to the oxygen vacancy, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0197] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2, can each be a laminated structure of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0198] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2 can each be coated with a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, processing can be performed by wet etching, which makes it possible to reduce manufacturing costs.

[0199] Furthermore, conductive layers 112a1 and 112b1 can be made of the same material or different materials. The same applies to conductive layers 112a2 and 112b2.

[0200] Here, we will take a configuration in which metal oxides are used for semiconductor layers 108_1 and 108_2 as an example and specifically explain conductive layers 112a1 and 112b1, and conductive layers 112a2 and 112b2.

[0201] When oxide semiconductors are used for semiconductor layers 108_1 and 108_2, the oxygen contained in semiconductor layers 108_1 and 108_2 may oxidize conductive layers 112a1 and 112b1, as well as conductive layers 112a2 and 112b2, potentially increasing their resistance. The oxygen contained in insulating layers 110_1 and 110_2 may oxidize conductive layers 112a1 and 112b1, as well as conductive layers 112a2 and 112b2, potentially increasing their resistance. Furthermore, the oxidation of conductive layers 112a1 and 112b1, as well as conductive layers 112a2 and 112b2 by the oxygen contained in semiconductor layers 108_1 and 108_2 can lead to oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2. Ｏ In some cases, the amount of oxygen supplied from insulating layer 110_1 and insulating layer 110_2 to semiconductor layer 108_1 and semiconductor layer 108_2 may increase. This can occur because the conductive layer 112a1 and conductive layer 112b1, and conductive layer 112a2 and conductive layer 112b2 are oxidized by the oxygen contained in insulating layer 110_1 and insulating layer 110_2, respectively.

[0202] It is preferable to use materials that are resistant to oxidation for conductive layers 112a1 and 112b1, and conductive layers 112a2 and 112b2. It is preferable to use oxide conductors for conductive layers 112a1 and 112b1, and conductive layers 112a2 and 112b2. For example, In-Sn oxide (ITO) or In-Sn-Si oxide (ITSO) can be suitably used. Nitride conductors can also be used for conductive layers 112a1 and 112b1, and conductive layers 112a2 and 112b2. Examples of nitride conductors include tantalum nitride and titanium nitride. Conductive layers 112a1 and 112b1, and conductive layers 112a2 and 112b2 can also have a laminated structure of the aforementioned materials.

[0203] By using materials that are resistant to oxidation for conductive layers 112a1 and 112b1, and conductive layers 112a2 and 112b2, it is possible to suppress oxidation caused by oxygen contained in semiconductor layer 108_1 and semiconductor layer 108_2, or oxygen contained in insulating layer 110_1 and insulating layer 110_2, which can increase resistance. Furthermore, oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2 can be suppressed. Ｏ This suppresses the increase in ), and also increases the amount of oxygen supplied from insulating layer 110_1 and insulating layer 110_2 to semiconductor layer 108_1 and semiconductor layer 108_2, respectively.

[0204] [Conductive layer 104_1, conductive layer 104_2] The conductive layers 104_1 and 104_2, which function as gate electrodes, can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or alloys composed of one or more of the aforementioned metals. Furthermore, the conductive layers 104_1 and 104_2 can also be made from the same materials used for conductive layers 112a1 and 112b1, and conductive layers 112a2 and 112b2.

[0205] Although Figure 1B and other figures show conductive layers 104_1 and 104_2 as single-layer structures, this is not limited to this configuration. For example, conductive layers 104_1 and 104_2 can be arranged in a laminated structure of two or more layers. For instance, when conductive layers 104_1 and 104_2 are arranged in a two-layer laminated structure, the first conductive layer (the conductive layer on the insulating layer 106_1 side and the conductive layer 106_2 side, respectively) can be made of nitride or oxide, and the second conductive layer can be made of one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy composed of one or more of the aforementioned metals. Furthermore, for example, when conductive layer 104_1 and conductive layer 104_2 are arranged in a three-layer laminated structure, the first conductive layer (the conductive layer on the insulating layer 106_1 side and the conductive layer on the insulating layer 106_2 side, respectively) can be an alloy composed of one or more of the above-mentioned metals, or a nitride of said metal or alloy. The second conductive layer can be an alloy composed of one or more of the above-mentioned metals, and the third conductive layer can be an alloy composed of one or more of the above-mentioned metals, or a nitride of said metal or alloy.

[0206] [Insulating layer 192, insulating layer 194] It is preferable to use insulating materials that do not easily allow impurities to diffuse for the insulating layer 192 that covers transistor 10_1 and the insulating layer 194 that is provided as a lower layer of transistor 10_2. By providing insulating layers 192 and 194, it is possible to effectively suppress the diffusion of impurities from the outside into transistors 10_1 and 10_2, thereby improving the reliability of transistors 10_1 and 10_2. Examples of impurities include water and hydrogen. Insulating layer 192 and insulating layer 194 can each be an insulating layer having an inorganic insulating material or an insulating layer having an organic insulating material. It is preferable to use inorganic insulating materials for insulating layer 192 and insulating layer 194. Specific examples of inorganic insulating materials that can be used for insulating layer 192 and insulating layer 194 include the inorganic insulating materials that can be used for insulating layer 110a1, insulating layer 110c1, insulating layer 110a2, and insulating layer 110c2 mentioned above. For example, it is preferable to use silicon nitride, silicon oxide nitride, hafnium oxide, aluminum oxide, etc. for the insulating layer 192 and the insulating layer 194, respectively.

[0207] [Insulating layer 193] The insulating layer 193, which fills the opening 143 and flattens the upper surface of the transistor 10_1, can be made of either an organic insulating material or an inorganic insulating material, or both. It is preferable to use an organic insulating material for the insulating layer 193. For example, by using an organic insulating material for the insulating layer 193, a film with excellent flatness can be easily formed at a relatively low temperature on a surface to be formed on that has steps.

[0208] Specific examples of organic insulating materials that can be used in the insulating layer 193 include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimidoamide resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins. Photosensitive materials can also be used as organic insulating materials. Here, photosensitivity refers to the property of being sensitive to ultraviolet light, far ultraviolet light, electron beams, X-rays, etc. This property is used to form a resist pattern by exposure. For exposure of silicon-containing resists, ultraviolet light is mainly used, and more preferably far ultraviolet light. The raw material monomer used at this time may be aromatic, but in order to increase sensitivity, it is more desirable to have a structure that does not contain aromatic rings. For example, polyimide resin is preferably used for the insulating layer 193.

[0209] Inorganic insulating materials can also be used for the insulating layer 193. Specific examples of inorganic insulating materials that can be used for the insulating layer 193 include the inorganic insulating materials that can be used for the insulating layer 110_1 and insulating layer 110_2 mentioned above. For example, it is preferable to use silicon oxide, silicon oxynitride, silicon oxide nitride, silicon nitride, etc., for the insulating layer 193.

[0210] [Conductive layer 115] The conductive layer 115, which functions as a plug, can be made from the same material that can be used for the conductive layers 112a1, 112b1, 112a2, and 112b2 described above, or from the same material that can be used for the conductive layers 104_1 and 104_2 described above.

[0211] Although Figure 1B and other figures show the conductive layer 115 as a single-layer structure, this is not limited to this, and it can also be a laminated structure of two or more layers. For example, when the conductive layer 115 is a two-layer laminated structure, the first conductive layer can be made of an oxidation-resistant material such as the aforementioned oxide conductor (e.g., ITO, ITSO, etc.) or nitride conductor (e.g., tantalum nitride, titanium nitride, etc.), and the second conductive layer can be made of a low-resistance conductive material containing one or more of copper, silver, gold, or aluminum.

[0212] In this case, it is preferable that the first conductive layer is provided in contact with the upper surface of the conductive layer 112b1, the side surface of the insulating layer 106_1, the side surface of the insulating layer 192, the side surface of the insulating layer 193, and the side surface of the insulating layer 194, respectively, within the openings 145 provided in the insulating layers 106_1, 192, 193, and 194, and that the second conductive layer is provided on the first conductive layer so as to fill the openings 145. This makes it possible to suppress, for example, the diffusion of oxygen contained in the semiconductor layer 108_1, etc., into the conductive layer 115, which would increase the resistance of the conductive layer 115.

[0213] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or organic resin substrates can be used as the substrate 102. In addition, substrates on which semiconductor elements are provided can also be used as the substrate 102. The shape of the semiconductor substrate and insulating substrate can be circular or rectangular.

[0214] A flexible substrate can be used as the substrate 102, and the semiconductor device 100, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the semiconductor device 100, etc. The release layer can be used to separate the semiconductor device from the substrate 102 after it has been partially or completely completed on it, and to transfer it to another substrate. In this case, the semiconductor device 100, etc., can be transferred to a substrate with poor heat resistance or to a flexible substrate.

[0215] [Composition of metal oxides in semiconductor layer 108_1 and semiconductor layer 108_2] The composition of metal oxides in semiconductor layer 108_1 and semiconductor layer 108_2 is described below.

[0216] The composition of the metal oxides in semiconductor layer 108_1 and semiconductor layer 108_2 significantly affects the electrical characteristics and reliability of transistors 10_1 and 10_2, respectively.

[0217] For example, by increasing the indium content of the metal oxide, it is possible to realize a transistor with a large on-current.

[0218] When using In-Zn oxide for semiconductor layer 108_1 and semiconductor layer 108_2, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, metal oxides with atomic ratios of metal elements of In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or close to these, can be used.

[0219] When using In-Sn oxide for semiconductor layer 108_1 and semiconductor layer 108_2, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than that of tin. For example, metal oxides with atomic ratios of metal elements of In:Sn = 1:1, In:Sn = 2:1, In:Sn = 3:1, In:Sn = 4:1, In:Sn = 5:1, In:Sn = 7:1, or In:Sn = 10:1, or close to these, can be used.

[0220] When using In-M-Zn oxide for semiconductor layer 108_1 and semiconductor layer 108_2, a metal oxide can be applied in which the atomic ratio of indium to the atomic number of metal elements is higher than the atomic ratio of element M. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M. For example, in semiconductor layer 108_1 and semiconductor layer 108_2, the atomic ratios of metal elements can be In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M: Metal oxides with the following ratios can be used: Zn = 6:1:6, In:M:Zn = 10:1:3, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, or near these ratios.

[0221] Furthermore, if element M contains multiple metallic elements, the sum of the atomic ratios of those metallic elements can be used as the atomic ratio of element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as elements M, the sum of the atomic ratios of gallium and aluminum can be used as the atomic ratio of element M. It is also preferable that the atomic ratios of indium, element M, and zinc are within the aforementioned ranges. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as elements M, the sum of the atomic ratios of gallium and tin can be used as the atomic ratio of element M. It is also preferable that the atomic ratios of indium, element M, and zinc are within the aforementioned ranges.

[0222] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the total number of metal elements contained in the metal oxide is 30 atomic% to 100 atomic%, preferably 30 atomic% to 95 atomic%, more preferably 35 atomic% to 95 atomic%, more preferably 35 atomic% to 90 atomic%, more preferably 40 atomic% to 90 atomic%, more preferably 45 atomic% to 90 atomic%, more preferably 50 atomic% to 80 atomic%, more preferably 60 atomic% to 80 atomic%, and more preferably 70 atomic% to 80 atomic%. For example, when using In-Ga-Zn oxide for semiconductor layer 108_1 and semiconductor layer 108_2, it is preferable that the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms is within the aforementioned range.

[0223] In this specification, the ratio of indium atoms to the total number of atoms of other metal elements may be referred to as the indium content. The same applies to other metal elements.

[0224] By increasing the indium content of the metal oxide, a transistor with a high on-current can be created. Applying this transistor to a transistor requiring a high on-current results in a semiconductor device with excellent electrical characteristics.

[0225] For the analysis of the composition of metal oxides, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, a combination of these methods can be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by the analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or the content of element M may not be detected.

[0226] In this specification, the term "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when describing an atomic ratio of In:M:Zn = 4:2:3 or a composition near that, it includes cases where the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Also, when describing an atomic ratio of In:M:Zn = 5:1:6 or a composition near that, it includes cases where the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is 5 or more and 7 or less. Furthermore, when describing an atomic ratio of In:M:Zn = 1:1:1 or a composition near that, it includes cases where the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is greater than 0.1 and 2 or less.

[0227] <Example of semiconductor device configuration 2> Figure 2A shows an example of a semiconductor device 100A with a different configuration from the semiconductor device 100 shown in Figure 1B. Figure 2A is a cross-sectional view of the semiconductor device 100A corresponding to the dashed line A1-A2 in the plan view of the semiconductor device 100 shown in Figure 1A. Figure 2C shows the equivalent circuit diagram of the semiconductor device 100A.

[0228] The semiconductor device 100A includes a transistor 10A_1, a transistor 10A_2, an insulating layer 110_1, an insulating layer 110_2, an insulating layer 191, an insulating layer 192, and an insulating layer 193.

[0229] The semiconductor device 100A differs from the semiconductor device 100 mainly in that it does not have a conductive layer 115, and that the conductive layer 104_1 and the conductive layer 112a2 are connected.

[0230] In the semiconductor device 100A, an insulating layer 191 is provided on the conductive layer 104_1 so as to fill the opening 143. The upper surface of the insulating layer 191 has a flat or substantially flat shape. The same material as the insulating layer 193 can be used for the insulating layer 191.

[0231] A conductive layer 112a2 is provided on the transistor 10A_1, in contact with the upper surface of the insulating layer 191 and a portion of the upper surface of the conductive layer 104_1.

[0232] An insulating layer 192 is provided on the transistor 10A_1 and the conductive layer 112a2, in contact with the upper and side surfaces of the conductive layer 112a2, the side surfaces of the conductive layer 104_1, and the upper surface of the insulating layer 106_1.

[0233] An insulating layer 193 is provided on the insulating layer 192. The upper surface of the insulating layer 193 has a flat or substantially flat shape. The upper surface of the insulating layer 193 and a part of the upper surface of the insulating layer 192 (specifically, the upper surface of the region of the insulating layer 192 that overlaps with the conductive layer 112a2) are substantially the same in height. An insulating layer 110_2 is provided on the insulating layer 193 and the insulating layer 192.

[0234] In semiconductor device 100, as shown in Figures 1B and 2B, the other source electrode or drain electrode (conductive layer 112b1) of transistor 10_1 is connected to one source electrode or drain electrode (conductive layer 112a2) of transistor 10_2. In contrast, in semiconductor device 100A, as shown in Figures 2A and 2C, the gate electrode (conductive layer 104_1) of transistor 10A_1 is connected to one source electrode or drain electrode (conductive layer 112a2) of transistor 10A_2.

[0235] Thus, in one embodiment of the present invention, various connection relationships can be applied between two stacked vertical transistors, thereby broadening the range of applications to which the semiconductor device can be applied. For example, when applying one embodiment of the present invention to the pixel circuit of a display device, the semiconductor device can be applied to various locations constituting the pixel circuit (locations where two transistors have a connection relationship with each other). Specific circuit examples of display devices to which one embodiment of the present invention can be applied will be described in Embodiment 3.

[0236] Regarding semiconductor device 100A, other than the points mentioned above, you can refer to the content described for semiconductor device 100.

[0237] <Example of Semiconductor Device Configuration 3> Figure 3A shows an example of a semiconductor device configuration different from the semiconductor device 100 shown in Figure 1B and the semiconductor device 100A shown in Figure 2A. Note that in Figure 3A, only the first layer transistor (transistor 10B_1) of the semiconductor device is shown. The cross-sectional view shown in Figure 3A is a cross-sectional view of transistor 10B_1 corresponding to the dashed line A1-A2 in the plan view of the semiconductor device 100 shown in Figure 1A.

[0238] The transistor 10B_1 differs from the transistor 10_1 shown in Figure 1B and the transistor 10A_1 shown in Figure 2A mainly in that it has a conductive layer 114_1 that functions as a second gate electrode (also called a back gate electrode) and an insulating layer 110s1 that functions as a second gate insulating layer (also called a back gate insulating layer), and that the insulating layer 110_1 is composed of six layers: insulating layer 110d1, insulating layer 110e1, insulating layer 110f1, insulating layer 110g1, insulating layer 110h1, and insulating layer 110i1.

[0239] In transistor 10B_1, the insulating layer 110_1 is composed of six layers: insulating layer 110d1 on the conductive layer 112a1 and on the substrate 102, insulating layer 110e1 on insulating layer 110d1, insulating layer 110f1 on insulating layer 110e1, insulating layer 110g1 on insulating layer 110f1, insulating layer 110h1 on insulating layer 110g1, and insulating layer 110i1 on insulating layer 110h1. A conductive layer 114_1 is provided between insulating layer 110f1 and insulating layer 110g1. The conductive layer 112a1, insulating layer 110d1, insulating layer 110e1, insulating layer 110f1, conductive layer 114_1, insulating layer 110g1, insulating layer 110h1, insulating layer 110i1, and insulating layer 112b1 have regions that overlap each other.

[0240] In transistor 10B_1, the opening 143 that reaches the conductive layer 112a1 is provided in the insulating layer 110d1, insulating layer 110e1, insulating layer 110f1, conductive layer 114_1, insulating layer 110g1, insulating layer 110h1, insulating layer 110i1, and insulating layer 112b1.

[0241] Within the opening 143, an insulating layer 110s1 is provided in contact with the upper surface of the conductive layer 112a1, the side surfaces of the insulating layer 110d1, the side surfaces of the insulating layer 110e1, the side surfaces of the insulating layer 110f1, the side surfaces of the conductive layer 114_1, the side surfaces of the insulating layer 110g1, the side surfaces of the insulating layer 110h1, the side surfaces of the insulating layer 110i1, and the side surfaces of the conductive layer 112b1. The upper end of the insulating layer 110s1 has a curved shape.

[0242] A semiconductor layer 108_1 is provided in contact with the upper surface of the conductive layer 112a1 within the opening 143, the surface of the insulating layer 110s1 on the opening 143 side, the curved portion of the insulating layer 110s1, and the upper surface of the conductive layer 112b1.

[0243] In transistor 10B_1, one surface of semiconductor layer 108_1 within the opening 143 faces the conductive layer 104_1 via the insulating layer 106_1, and the other surface of semiconductor layer 108_1 within the opening 143 faces the conductive layer 114_1 via the insulating layer 110s1. As described above, the conductive layer 114_1 functions as the second gate electrode of transistor 10B_1. The insulating layer 110s1 also functions as the second gate insulating layer of transistor 10B_1.

[0244] The transistor 10B_1 has two gate electrodes positioned on either side of the semiconductor layer 108_1, allowing a gate electric field to be applied to the carriers in the channel formation region from both sides of the semiconductor layer 108_1. Therefore, it can achieve a larger on-current than transistors 10_1 and 10A_1, which have only one gate electrode (conductive layer 104_1). It can also achieve a smaller off-current. Furthermore, the threshold voltage can be shifted to the normally off side. In addition, the saturation characteristics of the current flowing when operating in the saturation region can be improved (i.e., the magnitude of the drain current hardly changes with increasing drain voltage).

[0245] The insulating layer 110s1, which functions as the second gate insulating layer of transistor 10B_1, is preferably formed from a material that contains oxygen and releases oxygen through heat treatment or the like. For example, the insulating layer 110s1 can be made from the same material that can be used for the insulating layers 110b1 and 110b2 mentioned above. This allows, for example, when a metal oxide is used for the semiconductor layer 108_1, to supply oxygen from the insulating layer 110s1 to the metal oxide. This repairs oxygen deficiencies in the metal oxide, thereby improving the electrical characteristics and reliability of transistor 10B_1.

[0246] The conductive layer 114_1, which functions as the second gate electrode of transistor 10B_1, can be made from the same material that can be used for the conductive layers 104_1 and 104_2 described above.

[0247] Of the six insulating layers constituting the insulating layer 110_1, insulating layer 110d1, insulating layer 110f1, insulating layer 110g1, and insulating layer 110i1 can be made from materials that can be used for insulating layers 110a1, 110c1, 110a2, and 110c2 as described above. In addition, insulating layer 110e1 and insulating layer 110h1 can be made from materials that can be used for insulating layers 110b1 and 110b2 as described above.

[0248] As a result, for example, when a metal oxide is used for the semiconductor layer 108_1, oxygen present in the insulating layers 110e1 and 110h1 can be supplied to the semiconductor layer 108_1 via the insulating layer 110s1. This allows for the repair of oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistor 10B_1. Furthermore, it is possible to suppress the diffusion of oxygen present in the insulating layer 110e1 to the conductive layer 112a1 side via the insulating layer 110d1 and to the conductive layer 114_1 side via the insulating layer 110f1. Similarly, it is possible to suppress the diffusion of oxygen present in the insulating layer 110h1 to the conductive layer 114_1 side via the insulating layer 110g1 and to the conductive layer 112b1 side via the insulating layer 110i1.

[0249] Regarding transistor 10B_1, other than the points mentioned above, you can refer to the explanations given for transistors 10_1 and 10A_1.

[0250] <Example of semiconductor device configuration 4> Figure 3B shows an example of a transistor configuration (transistor 10C_1) different from transistor 10B_1 shown in Figure 3A. The cross-sectional view shown in Figure 3A is a cross-sectional view of transistor 10C_1 corresponding to the dashed line A1-A2 in the plan view of semiconductor device 100 shown in Figure 1A.

[0251] Transistor 10C_1 differs from transistor 10B_1 shown in Figure 3A mainly in that it has an insulating layer 116 that covers the conductive layer 114_1 and functions as a barrier film for oxygen and hydrogen, and that its insulating layer 110_1 is composed of three layers: insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1. In addition, the shape of the insulating layer 110a1 differs from that of transistor 10_1 shown in Figure 1B and transistor 10A_1 shown in Figure 2A.

[0252] In transistor 10C_1, the end of the insulating layer 110a1 on the side of the opening 143 has a shape that protrudes more than the side of the insulating layer 110b1 on the side of the opening 143, the side of the insulating layer 110c1 on the side of the opening 143, and the side of the conductive layer 112b1 on the side of the opening 143.

[0253] Furthermore, a conductive layer 114_1 is provided on the insulating layer 110a1 so as to overlap with the insulating layer 110b1, insulating layer 110c1, and conductive layer 112b1. An insulating layer 116 is provided in contact with the upper surface and side surface of the conductive layer 114_1. An insulating layer 110s1 is provided in contact with the upper surface of the insulating layer 110a1 within the opening 143, the surface of the insulating layer 116 on the opening 143 side, the side surface of the insulating layer 110b1 on the opening 143 side, the side surface of the insulating layer 110c1 on the opening 143 side, and the side surface of the conductive layer 112b1 on the opening 143 side. The upper end of the insulating layer 110s1 has a curved shape.

[0254] Unlike transistor 10B_1, transistor 10C_1 has a configuration in which the insulating layer 110s1 does not come into contact with the conductive layer 112a1. Therefore, it is possible to suppress problems such as a decrease in the on-current of transistor 10C_1 caused by oxygen in the insulating layer 110s1 diffusing to the conductive layer 112a1 side and causing the conductive layer 112a1 to oxidize and increase its resistance.

[0255] A semiconductor layer 108_1 is provided in contact with the upper surface of the conductive layer 112a1 within the opening 143, the side surface of the insulating layer 110a1 on the opening 143 side, the surface of the insulating layer 110s1 on the opening 143 side, the curved portion of the insulating layer 110s1, and the upper surface of the conductive layer 112b1.

[0256] In transistor 10C_1, one surface of semiconductor layer 108_1 within the opening 143 faces the conductive layer 104_1 via insulating layer 106_1, and the other surface of semiconductor layer 108_1 within the opening 143 faces the conductive layer 114_1 via insulating layer 110s1 and insulating layer 116. As described above, conductive layer 114_1 functions as a second gate electrode. Insulating layer 110s1 also functions as a second gate insulating layer. Insulating layer 116 in the region sandwiched between conductive layer 114_1 and insulating layer 110s1 can also function as a second gate insulating layer.

[0257] The insulating layer 116 is preferably formed of a material that functions as a barrier film for oxygen and hydrogen. For example, the insulating layer 116 can be made of the same material that can be used for the insulating layers 110a1, 110c1, 110a2, and 110c2 mentioned above. By covering the top and sides of the conductive layer 114_1 with an insulating layer 116 made of the said material, as shown in Figure 3B, it is possible to suppress problems such as oxygen from the insulating layers 110s1 and 110b1 diffusing into the conductive layer 114_1, which would reduce the conductivity of the conductive layer 114_1.

[0258] Here, the insulating layer 116 can be formed by a film deposition method such as plasma CVD or sputtering, but for example, the insulating layer 116 covering the top and sides of the conductive layer 114_1 can also be formed by oxidizing the surface of the conductive layer 114_1 by plasma treatment in an oxygen atmosphere. In this case, an insulating layer 116 having the same function as the insulating layer 110a1 and insulating layer 110c1 can be formed without using film deposition methods such as plasma CVD or sputtering, so the number of times the above film deposition method is applied can be reduced and productivity can be increased. For example, productivity can be increased compared to a transistor 10B_1 having six insulating layers constituting the insulating layer 110_1. In this case, it is preferable to use a material that is easily oxidized by plasma treatment in an oxygen atmosphere for the conductive layer 114_1. For example, it is preferable to use aluminum. Also, in this case, the insulating layer 116 will be an insulating layer made of an oxide of the element contained in the conductive layer 114_1. For example, if aluminum is used as the material for the conductive layer 114_1, the insulating layer 116 will be aluminum oxide.

[0259] Regarding transistor 10C_1, other than the points mentioned above, you can refer to the content explained for transistor 10B_1.

[0260] Although Figures 3A and 3B illustrate a configuration example focusing only on the first layer transistor of the two transistors in a semiconductor device according to one aspect of the present invention, this configuration example can also be applied to the second layer transistor of the semiconductor device according to one aspect of the present invention.

[0261] <Example of Semiconductor Device Configuration 5> Figure 4A shows an example of a semiconductor device configuration different from the semiconductor device 100 shown in Figure 1B and the semiconductor device 100A shown in Figure 2A. Note that in Figure 4A, only the second layer transistor (transistor 10D_2) of the semiconductor device is shown. The plan view shown in Figure 4A is a plan view of transistor 10D_2, which corresponds to the plan view of semiconductor device 100 shown in Figure 1A.

[0262] The transistor 10D_2 differs from transistor 10_2 shown in Figure 1B and transistor 10A_2 shown in Figure 2A mainly in the formation region of the semiconductor layer 108_2.

[0263] As shown in Figure 4A, the transistor 10D_2 has a configuration in which the semiconductor layer 108_2 is provided so as to overlap with one of the corners of the island-shaped insulating layer 110_2 and conductive layer 112b2. Note that Figure 4A shows an example in which the interior angle of the corner in a plan view is 90 degrees, but this is not limited to this. The interior angle can be acute (greater than 0 degrees and less than 180 degrees) or obtuse (greater than 180 degrees and less than 360 degrees). Furthermore, the corner can have a rounded shape.

[0264] Because transistor 10D_2 has the above-described configuration, the semiconductor layer 108_2 has a region that contacts the two side surfaces that constitute the corner of the insulating layer 110_2. For this reason, in transistor 10D_2, the region of the semiconductor layer 108_2 that contacts the two side surfaces can function as a channel formation region.

[0265] In transistor 10D_2, in a plan view, the lengths of the two sides that overlap with the semiconductor layer 108_2 correspond to the channel width (channel width W10D_2). Therefore, the channel width of the second layer transistor can be increased without increasing the occupied area of ​​the semiconductor device. Consequently, transistor 10D_2 may be able to have a higher on-current than transistors 10_2 and 10A_2.

[0266] In transistor 10D_2, the semiconductor layer 108_2 overlaps with only one corner of the island-shaped insulating layer 110_2 and conductive layer 112b2 in a plan view, but this is not limited to this configuration. In one embodiment of the present invention, the semiconductor layer 108_2 can also overlap with the corner adjacent to the aforementioned corner (the corner overlapping with the conductive layer 104_2) of the island-shaped insulating layer 110_2 and conductive layer 112b2 in a plan view. This makes it possible to increase the channel width of the transistor without changing the size of each electrode constituting the transistor (source electrode, drain electrode, and gate electrode) in a plan view, and thus increase the on-current of the transistor.

[0267] Regarding transistor 10D_2, for details other than those mentioned above, please refer to the explanations for transistors 10_2 and 10A_2.

[0268] <Semiconductor device configuration example 6> Figure 4B shows a configuration example of a transistor (transistor 10E_2) different from the transistor 10D_2 shown in Figure 4A. The plan view shown in Figure 4B is a plan view of transistor 10E_2, which corresponds to the plan view of semiconductor device 100 shown in Figure 1A.

[0269] The formation region of the semiconductor layer 108_2 in transistor 10E_2 is different from that of transistor 10D_2 shown in Figure 4A.

[0270] As shown in Figure 4B, in transistor 10E_2, the insulating layer 110_2 and conductive layer 112b2, which are arranged in an island shape, have a concave polygonal shape (a polygon in which at least one interior angle exceeds 180 degrees), and in a plan view, the semiconductor layer 108_2 is provided in a region that overlaps with the three corners of the insulating layer 110_2 and conductive layer 112b2 (one corner in a plan view whose interior angle is greater than 180 degrees and less than 360 degrees, and two corners in a plan view whose interior angles are greater than 0 degrees and less than 180 degrees). Note that the above corners can also be rounded.

[0271] Because transistor 10E_2 has the above-described configuration, the semiconductor layer 108_2 has a region that contacts the four side surfaces that constitute the corners of the insulating layer 110_2. For this reason, in transistor 10E_2, the region of the semiconductor layer 108_2 that contacts the four side surfaces can function as a channel formation region.

[0272] In transistor 10E_2, in a plan view, the lengths of the four sides that overlap with the semiconductor layer 108_2 correspond to the channel width of the transistor (channel width W10E_2). Therefore, the channel width of the second layer transistor can be increased without increasing the occupied area of ​​the semiconductor device. Consequently, transistor 10E_2 may be able to have a higher on-current than transistors 10_2, 10A_2, and 10D_2.

[0273] In Figure 4B, the semiconductor layer 108_2 is shown overlapping with the three corners of the insulating layer 110_2 and conductive layer 112b2, which have a concave polygonal shape in plan view, but this is not limited to this configuration. For example, the semiconductor layer 108_2 can be configured to overlap with only one corner whose interior angle in plan view is greater than 180 degrees and less than 360 degrees.

[0274] Regarding transistor 10E_2, for details other than those mentioned above, please refer to the explanation for transistor 10D_2.

[0275] <Example of Semiconductor Device Manufacturing Method> Below, an example of a semiconductor device manufacturing method according to one aspect of the present invention will be described with reference to the drawings. Here, the semiconductor device 100 shown in Figures 1A and 1B will be used as an example.

[0276] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and atomic layer deposition (ALD).

[0277] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0278] CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. Furthermore, depending on the source gas used, they can be divided into metal CVD (MCCVD) and metal-organic CVD (MOCVD).

[0279] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices can become charged by receiving charge from the plasma. This accumulated charge can damage the wiring, electrodes, or components in the semiconductor device. In contrast, thermal CVD, which does not use plasma, avoids this plasma damage, resulting in a higher yield for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0280] As ALD methods, thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants, can be used.

[0281] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that provide good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable, for example, for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as the CVD method, which has a faster deposition rate.

[0282] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the source gases. For example, in the CVD method, by changing the flow rate ratio of the source gases while deposition is occurring, films with continuously changing compositions can be deposited. When deposition is performed while changing the flow rate ratio of the source gases, the deposition time can be shortened compared to deposition using multiple deposition chambers, because time required for transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0283] Furthermore, the ALD method allows for the deposition of films of any composition by using multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, films of any composition can be deposited by controlling the number of cycles for each precursor.

[0284] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0285] Thin films constituting semiconductor devices can be processed using methods such as photolithography. In addition, thin films can also be processed using nanoimprint lithography, sandblasting, and lift-off methods. Furthermore, island-like thin films can be directly formed using deposition methods that utilize shielding masks such as metal masks.

[0286] Photolithography typically involves two main methods. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, followed by exposure and development, to process the thin film into the desired shape.

[0287] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0288] For etching thin films, methods such as dry etching, wet etching, or sandblasting can be used.

[0289] For planarization of thin films, polishing methods such as the CMP method are typically suitable. Alternatively, a reflow method, which involves heat treatment of the conductive layer to fluidize it, can also be suitably used. Furthermore, a combination of the reflow method and the CMP method can be employed.

[0290] Furthermore, a process can be used in which a planarization film is formed on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching (e.g., dry etching) on ​​the planarization film, or a process in which a planarization film and a photoresist are formed in this order on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching on the planarization film and the photoresist, thereby filling only the planarization film into the depressions and flattening the entire top surface (these processes are sometimes called etch-back processes). When using an etch-back process, high-temperature heating (e.g., around 800°C) like that used in reflow methods is not required, so there is no need to worry about damage to the device during fabrication caused by such heating. In addition, an etch-back process is suitable because it can be applied to devices on large substrates that are difficult to process with the CMP method due to the effects of bending, etc.

[0291] Other thin film planarization processes that can be used include dry etching and plasma treatment. Polishing, dry etching, and plasma treatment can be performed multiple times, or they can be combined. When combining these processes, the order of the steps is not particularly limited and can be appropriately set according to the surface irregularities of the workpiece.

[0292] To precisely process a thin film to a desired thickness, for example, the CMP method can be used. In this method, first, the thin film is polished at a constant processing speed until a portion of its upper surface is exposed. Then, by polishing at a slower processing speed until the thin film reaches the desired thickness, high-precision processing becomes possible.

[0293] Methods for detecting the end point of polishing include optical methods that involve irradiating the surface of the workpiece with light and detecting changes in the reflected light, physical methods that involve detecting changes in the polishing resistance that the processing equipment receives from the workpiece, and methods that use changes in magnetic field lines caused by eddy currents generated when magnetic field lines are applied to the workpiece.

[0294] After the upper surface of the thin film is exposed, the thickness of the thin film can be precisely controlled by performing a polishing process at a slow processing speed while monitoring its thickness using an optical method such as a laser interferometer. If necessary, the polishing process can be repeated multiple times until the thin film reaches the desired thickness.

[0295] Figures 5A to 18B illustrate the method for manufacturing the semiconductor device 100. Figure (A) in each figure shows a plan view corresponding to Figure 1A. Figure (B) in each figure shows a cross-sectional view along the dashed line A1-A2 in the plan view shown in Figure 1A.

[0296] First, a conductive film that will become the conductive layer 112a1 is formed on the substrate 102, and the conductive layer 112a1 is formed by removing a portion of the conductive film (Figures 5A and 5B). For example, sputtering can be used to form the conductive film. In addition, either or both of the wet etching method and the dry etching method can be used to process the conductive film.

[0297] Next, insulating films 110a1f, 110b1f, and 110c1f are formed on the conductive layer 112a1 and the substrate 102 in this order.

[0298] For the insulating film 110a1f, any material that can be used for the insulating layer 110a1 described above can be used as appropriate.

[0299] As the insulating film 110a1f, for example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide can be suitably used.

[0300] Specifically, as the insulating film 110a1f, silicon nitride can be deposited using, for example, a sputtering method. Alternatively, silicon nitride can be deposited using, for example, a PEALD method. Alternatively, aluminum oxide can be deposited using, for example, a sputtering method.

[0301] Furthermore, for example, a configuration in which aluminum oxide and silicon nitride are layered can be used. For instance, aluminum oxide deposited using the sputtering method and silicon nitride deposited using the PEALD method can be used in a layered configuration.

[0302] The insulating film 110b1f can be made from any material that can be used for the insulating layer 110b1 described above.

[0303] For example, silicon oxide, silicon oxide, silicon nitride, and the like can be suitably used as the insulating film 110b1f.

[0304] Specifically, as the insulating film 110b1f, silicon oxide can be deposited using, for example, a sputtering method. Alternatively, silicon oxide can be deposited using, for example, a PECVD method. Alternatively, silicon oxynitride can be deposited using, for example, a PECVD method.

[0305] Furthermore, for example, silicon oxide deposited using the sputtering method and silicon oxide or silicon oxidnitride deposited using the PECVD method can be used in a layered configuration.

[0306] The insulating film 110b1f can also be subjected to heat treatment after it has been formed. By performing heat treatment, water and hydrogen can be removed from the surface and within the insulating film 110b1f.

[0307] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can also be used as the atmosphere containing nitrogen or oxygen. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a content of hydrogen, water, etc. kept to a minimum, it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 110b1f as much as possible. Heat treatment can be performed using, for example, an oven or a rapid thermal annealing (RTA) device. Using an RTA device can shorten the heat treatment time.

[0308] After the above heat treatment, a step of supplying oxygen to the insulating film 110b1f can also be performed. For example, after the insulating film 110b1f is formed, a metal oxide layer can be formed on the insulating film 110b1f to supply oxygen to the insulating film 110b1f. Alternatively, the heat treatment can be performed after the formation of the metal oxide layer. By performing the heat treatment after the formation of the metal oxide layer, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110b1f, and oxygen can be contained in the insulating film 110b1f. The oxygen supplied to the insulating film 110b1f is supplied to the semiconductor layer 108_1 in a later step, thereby eliminating oxygen vacancies (V) in the semiconductor layer 108_1. Ｏ ) and V Ｏ H can be reduced.

[0309] After forming the metal oxide layer, or after the aforementioned heat treatment, oxygen can be further supplied to the insulating film 110b1f through the metal oxide layer. As a method of supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. As the plasma treatment, a device that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of devices that convert gas into plasma using high-frequency power include plasma etching devices and plasma ashing devices.

[0310] The metal oxide layer can be an insulating layer or a conductive layer. For example, the metal oxide layer can be aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0311] It is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108_1 as the metal oxide layer. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108_1. This allows the metal oxide layer to be formed using the same sputtering target as the semiconductor layer 108_1, thereby reducing manufacturing costs.

[0312] When using a metal oxide material containing indium and gallium in the metal oxide layer, a material with a higher gallium composition (content) than the semiconductor layer 108_1 can be used. By using a material with a higher gallium composition (content) in the metal oxide layer, the barrier properties against oxygen can be further enhanced. This is preferable because it can suppress the detachment of oxygen contained in the insulating film 110b1f to the outside.

[0313] The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferable to form it by sputtering in an atmosphere containing oxygen. This allows for a suitable supply of oxygen to the insulating film 110b1f during the formation of the metal oxide layer.

[0314] Next, the metal oxide layer is removed. For example, a wet etching method can be suitably used to remove the metal oxide layer.

[0315] The process of supplying oxygen to the insulating film 110b1f is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc., can be supplied to the insulating film 110b1f by ion doping, ion implantation, plasma treatment, etc. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110b1f, and then oxygen can be supplied to the insulating film 110b1f through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used.

[0316] For the insulating film 110c1f, any material that can be used for the insulating layer 110c1 described above can be used as appropriate.

[0317] For materials and film formation methods that can be used for the insulating film 110c1f, refer to the description of materials and film formation methods that can be used for the insulating film 110a1f mentioned above.

[0318] Next, a conductive film 112b1f is formed on the insulating film 110c1f (Figures 6A and 6B). The conductive film 112b1f can be made from any of the materials previously used for the conductive layer 112b1. Furthermore, for the formation of the conductive film 112b1f, for example, sputtering can be used.

[0319] Next, a conductive layer 112b1e is formed by removing a portion of the conductive film 112b1f (Figures 7A and 7B). Either a wet etching method or a dry etching method, or both, can be used to form the conductive layer 112b1e. The conductive layer 112b1e is formed to have a region that overlaps with the conductive layer 112a1.

[0320] Next, a process is performed to remove a portion of each of the conductive layer 112b1e, insulating film 110c1f, insulating film 110b1f, and insulating film 110a1f to form an opening 143 that reaches the conductive layer 112a1. For example, a dry etching method can be suitably used for this process. This process forms the conductive layer 112b1, insulating layer 110c1, insulating layer 110b1, and insulating layer 110a1, each having an opening (Figures 8A and 8B).

[0321] Next, a semiconductor film that will become the semiconductor layer 108_1 is formed in contact with the upper surface of the conductive layer 112a1 within the opening 143, the side surfaces of the insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) within the opening 143, the side surfaces of the conductive layer 112b1 within the opening 143, and the upper surface of the conductive layer 112b1. After that, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108_1 (Figures 9A and 9B). The semiconductor layer 108_1 is provided so as to have a region that overlaps with the opening 143. In addition, the semiconductor layer 108_1 is provided so that its edges have a region that is in contact with the conductive layer 112b1.

[0322] For the semiconductor film that will become the semiconductor layer 108_1, any material that can be used for the semiconductor layer 108_1 as described above can be used as appropriate.

[0323] For example, sputtering can be used to form the semiconductor film that will become the semiconductor layer 108_1. For example, when a metal oxide is used for the semiconductor layer 108_1, it can be formed by sputtering using a metal oxide target. Using the sputtering method is preferable because it allows for the relatively easy formation of films with low hydrogen content.

[0324] Furthermore, when a metal oxide is used for the semiconductor layer 108_1, it can also be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0325] For example, when forming In-Ga-Zn oxide, three precursors can be used: an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor. Alternatively, two precursors can be used: an indium-containing precursor and precursors containing both gallium and zinc.

[0326] Indium-containing precursors that can be used include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, and indium(III) chloride.

[0327] Furthermore, gallium-containing precursors such as trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, and diethylchlorogallium can be used.

[0328] Furthermore, zinc-containing precursors such as dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid) zinc, and zinc chloride can be used.

[0329] For example, ozone, oxygen, and water can be used as oxidizing agents.

[0330] Methods for controlling the composition of the resulting film include adjusting the flow ratio of the source gases, the duration of the source gas flow, and the order in which the source gases are flowed. By adjusting these factors, it is also possible to deposit films with continuously changing compositions. Furthermore, it becomes possible to deposit films with different compositions in succession.

[0331] Using the ALD method to form the semiconductor film that will become the semiconductor layer 108_1 is preferable because it allows the semiconductor layer 108_1 to be formed with a uniform thickness on the side surface of the insulating layer 110_1.

[0332] After forming the semiconductor film that will become the semiconductor layer 108_1, a heat treatment can also be performed. This heat treatment reduces the amount of water and hydrogen contained in the semiconductor film and allows oxygen to be supplied to the semiconductor film from the insulating layer 110_1. Note that the heat treatment can also be performed after processing the semiconductor film.

[0333] The substrate temperature (stage temperature) during the formation of the semiconductor layer 108_1 is preferably between room temperature (25°C) and 200°C, and more preferably between room temperature and 130°C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when using a large-area glass substrate.

[0334] The higher the substrate temperature during the formation of the metal oxide layer, the more crystalline the metal oxide layer can be formed. Furthermore, the higher the oxygen flow rate ratio, the more crystalline the metal oxide layer can be formed.

[0335] Next, the semiconductor layer 108_1, the conductive layer 112b1, and the insulating layer 110c1 are covered to form an insulating layer 106_1 (Figures 10A and 10B). The insulating layer 106_1 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108_1, the upper and side surfaces of the conductive layer 112b1, and the upper surface of the insulating layer 110c1.

[0336] The insulating layer 106_1 can be made from the materials described above as appropriate.

[0337] For example, the ALD method can be used to form the insulating layer 106_1. Using the ALD method is preferable because it allows for good coverage of the insulating layer 106_1 formed over the semiconductor layer 108_1 that covers the opening 143. However, if the semiconductor layer 108_1 can be sufficiently covered, methods other than the ALD method can be used to form the insulating layer 106_1. For example, the PECVD method or sputtering method can be used. This allows for a faster deposition rate of the insulating layer 106_1 than when using the ALD method, thereby increasing productivity.

[0338] Next, a conductive film that will become the conductive layer 104_1 is formed on the insulating layer 106_1, and a portion of the conductive film is removed to form the conductive layer 104_1 (Figures 11A and 11B). For forming the conductive film, sputtering, CVD, molecular beam epitaxy (MBE), PLD, ALD, etc., can be used as appropriate. Here, it is preferable that the conductive film is formed in contact with the insulating layer 106_1 that faces the side surface of the insulating layer 110_1 within the opening 143. Therefore, it is preferable to use a formation method that has good covering or embedding properties for forming the conductive film, and it is more preferable to use the CVD or ALD method. In addition, one or both of the wet etching method and the dry etching method can be used for processing the conductive film. The conductive layer 104_1 is formed to have a region that overlaps with the opening 143.

[0339] This forms transistor 10_1.

[0340] Next, an insulating layer 192 is formed on the conductive layer 104_1 and the insulating layer 106_1. The insulating layer 192 is provided in contact with the upper and side surfaces of the conductive layer 104_1 and the upper surface of the insulating layer 106_1. For forming the insulating layer 192, for example, the ALD method, the PECVD method, or the sputtering method can be used.

[0341] Next, an insulating layer 193 is formed on the insulating layer 192. The insulating layer 193 is formed to fill the opening 143. Furthermore, the height of the upper surface of the insulating layer 193 is formed to be higher than the height of the upper surface in any region of the insulating layer 192. For example, when an organic insulating material such as polyimide resin is used as the insulating layer 193, an insulating layer 193 with a generally flat upper surface can be easily formed by a method such as spin coating. Alternatively, after forming the insulating film that will become the insulating layer 193, an insulating layer 193 with a generally flat upper surface can be formed by performing an etch-back treatment on the insulating film.

[0342] Next, an insulating layer 194 is formed on the insulating layer 193 (Figures 12A and 12B). For forming the insulating layer 194, for example, the ALD method, PECVD method, sputtering method, etc., can be used.

[0343] Next, openings 145 reaching the conductive layer 112b1 are formed in the insulating layer 106_1, insulating layer 192, insulating layer 193, and insulating layer 194, and the conductive layer 115 is formed to fill the openings 145 (Figures 13A and 13B). For example, after forming the openings 145, a conductive film that will become the conductive layer 115 is formed on the insulating layer 194 and the conductive layer 112b1 using a sputtering method, CVD method, MBE method, PLD method, ALD method, etc. Next, the conductive film is processed using a CMP method, etch-back treatment, etc. until the upper surface of the insulating layer 194 is exposed, and the conductive layer 115 embedded in the openings 145 can be formed.

[0344] Next, a conductive film that will become the conductive layer 112a2 is formed on the conductive layer 115 and the insulating layer 194, and the conductive layer 112a2 is formed by removing a portion of the conductive film (Figures 14A and 14B). For example, sputtering can be used to form the conductive film. In addition, either or both of the wet etching method and the dry etching method can be used to process the conductive film. The conductive layer 112a2 is formed to have a region that overlaps with the conductive layer 115. Furthermore, it is preferable that the conductive layer 112a2 is formed to have a region that overlaps with the opening 143.

[0345] Next, insulating films 110a2f, 110b2f, 110c2f, and conductive film 112b2f are formed on the conductive layer 112a2 and the insulating layer 194 in this order (Figures 15A and 15B). For materials and formation methods that can be used for insulating films 110a2f, 110b2f, 110c2f, and conductive film 112b2f, refer to the descriptions above for insulating films 110a1f, 110b1f, 110c1f, and conductive film 112b1f, respectively.

[0346] Next, the conductive film 112b2f, insulating film 110c2f, insulating film 110b2f, and insulating film 110a2f are processed to form grooves 144 that reach the conductive layer 112a2. For example, a dry etching method can be suitably used for this process. This process forms island-shaped conductive layers 112b2 and insulating layers 110_2 (insulating layer 110c2, insulating layer 110b2, and insulating layer 110a2) (Figures 16A and 16B). The insulating layer 110_2 and conductive layer 112b2 are formed to have regions that overlap with the conductive layer 112a2.

[0347] Next, a semiconductor film that will become the semiconductor layer 108_2 is formed in contact with the upper surface of the conductive layer 112a2 within the groove 144, the side surface of the insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) within the groove 144, the side surface of the conductive layer 112b2 within the groove 144, and the upper surface of the conductive layer 112b2. After that, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108_2 (Figures 17A and 17B). The semiconductor layer 108_2 is provided such that, in a plan view, it has a region that overlaps with at least one side wall of the groove 144 (the side surface of the insulating layer 110_2 and the side surface of the conductive layer 112b2).

[0348] Regarding materials and formation methods that can be used for the semiconductor film that will become semiconductor layer 108_2, refer to the description of materials and formation methods that can be used for the semiconductor film that will become semiconductor layer 108_1 mentioned above.

[0349] Next, the semiconductor layer 108_2, the conductive layer 112a2, the conductive layer 112b2, and the insulating layer 110_2 are covered to form an insulating layer 106_2 (Figures 18A and 18B). The insulating layer 106_2 has regions that are in contact with the top and side surfaces of the semiconductor layer 108_2, the top surface of the conductive layer 112a2, the top and side surfaces of the conductive layer 112b2, and the side surfaces of the insulating layer 110_2. For materials that can be used for the insulating layer 106_2, and for the formation method, etc., refer to the description of materials that can be used for the insulating layer 106_1 described above.

[0350] Next, a conductive film that will become the conductive layer 104_2 is formed on the insulating layer 106_2, and a portion of the conductive film is removed to form the conductive layer 104_2. For materials that can be used for the conductive film, forming methods, processing methods, etc., refer to the description above for materials that can be used for the conductive film that will become the conductive layer 104_1. The conductive layer 104_2 is formed to have a region that overlaps with the groove 144 and the semiconductor layer 108_2.

[0351] This forms transistor 10_2.

[0352] By following the above steps, the semiconductor device 100 can be manufactured (Figures 1A and 1B).

[0353] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0354] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0355] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0356] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0357] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0358] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single-crystal indium oxide.

[0359] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0360] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0361] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0362] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. It is especially preferable to use elements in which the oxide is conductive or semiconducting.

[0363] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0364] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at the grain boundaries can be suppressed, enabling the realization of a transistor exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by the grain boundaries.

[0365] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0366] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0367] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0368] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0369] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0370] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include group 13 elements of the periodic table such as gallium and aluminum, and group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0371] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0372] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0373] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0374] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0375] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Additionally, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10 −２１ A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0376] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This can improve the crystallinity of the indium oxide film. A substrate (for example, a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0377] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0378] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0379] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0380] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified forms. YbFe ２ O４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0381] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0382] (Embodiment 3) A semiconductor device according to one aspect of the present invention can be applied to a display device, for example. In this embodiment, a circuit, layout, etc. applicable to the display device will be described.

[0383] Figure 19 is a block diagram illustrating a display device 300 to which a semiconductor device according to one aspect of the present invention can be applied. The display device 300 has a display unit 435, a first drive circuit unit 431, and a second drive circuit unit 432.

[0384] The display unit 435 has a plurality of pixels 230 arranged in a matrix of m rows (where m is an integer of 1 or more) and n columns (where n is an integer of 1 or more).

[0385] The display unit 435 corresponds, for example, to the display unit 168 in Figure 35 described in Embodiment 4, and the pixels 230 correspond, for example, to the sub-pixels 11R, 11G, 11B, and 210 in Figure 35 described in Embodiment 4.

[0386] In Figure 19, the pixel 230 in the 1st row and nth column is shown as pixel 230[1,n], the pixel 230 in the mth row and 1st column is shown as pixel 230[m,1], and the pixel 230 in the mth row and nth column is shown as pixel 230[m,n]. In addition, any pixel 230 included in the display unit 435 may be shown as pixel 230[r,s]. r is an integer between 1 and m, and s is an integer between 1 and n.

[0387] The circuit included in the first drive circuit section 431 functions, for example, as a scan line drive circuit. The circuit included in the second drive circuit section 432 functions, for example, as a signal line drive circuit. It is also possible to provide some circuit at a position facing the first drive circuit section 431 across the display section 435. Similarly, it is possible to provide some circuit at a position facing the second drive circuit section 432 across the display section 435. The circuits included in the first drive circuit section 431 and the second drive circuit section 432 are collectively referred to as the peripheral drive circuit 433.

[0388] The peripheral drive circuit 433 can utilize various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit. A semiconductor device 100 according to one aspect of the present invention can be used in the peripheral drive circuit 433. Furthermore, the transistors in the peripheral drive circuit and the transistors included in the pixel 230 can be formed in the same process.

[0389] Furthermore, the display device 300 has m wires 436, each arranged in roughly parallel directions and whose potential is controlled by a circuit included in the first drive circuit section 431, and n wires 437, each arranged in roughly parallel directions and whose potential is controlled by a circuit included in the second drive circuit section 432.

[0390] Note that Figure 19 shows an example where wiring 436 and wiring 437 are connected to pixel 230. However, wiring 436 and wiring 437 are just examples, and the wiring connected to pixel 230 is not limited to wiring 436 and wiring 437.

[0391] <Example of Pixel Circuit Configuration> Figures 20A to 21C show an example of the configuration of a pixel 230. The pixel 230 has a pixel circuit 51 (pixel circuit 51A, pixel circuit 51B, pixel circuit 51C, pixel circuit 51D, pixel circuit 51E, pixel circuit 51F, or pixel circuit 51G) and a light-emitting element 61.

[0392] The light-emitting element described in this embodiment refers to a self-emissive display element such as an organic EL element (also called an OLED (Organic LED)). The light-emitting element connected to the pixel circuit can be a self-emissive light-emitting element such as an LED, microLED, QLED (Quantum-dot LED), or semiconductor laser.

[0393] The pixel circuit 51A shown in Figure 20A is a 2Tr1C type pixel circuit having transistors 52A and 52B, and a capacitor 53.

[0394] One of the sources or drains of transistor 52A is connected to wiring SL, and the gate of transistor 52A is connected to wiring GL. The other of the sources or drains of transistor 52A is connected to the gate of transistor 52B and one terminal of capacitor 53. One of the sources or drains of transistor 52B is connected to wiring ANO. The other of the sources or drains of transistor 52B is connected to the other terminal of capacitor 53 and the anode of light-emitting element 61. The cathode of light-emitting element 61 is connected to wiring VCOM. The region where the other of the sources or drains of transistor 52A, the gate of transistor 52B, and one terminal of capacitor 53 are connected functions as node ND.

[0395] Wiring GL corresponds to wiring 436, and wiring SL corresponds to wiring 437. Wiring VCOM is a wire that provides a potential for supplying current to the light-emitting element 61. Transistor 52A has the function of controlling the conduction state (a state in which current can flow) or non-conduction state between wiring SL and the gate of transistor 52B based on the potential of wiring GL. For example, VDD is supplied to wiring ANO, and VSS is supplied to wiring VCOM. Transistor 52A can also be called a selection transistor because it functions as a switch for controlling the selection and deselection of the pixel 230.

[0396] By turning transistor 52A ON, an image signal is supplied from wiring SL to node ND. Subsequently, by turning transistor 52A OFF, the image signal is held at node ND. To ensure reliable retention of the image signal supplied to node ND, it is preferable to use a transistor with a small off-current for transistor 52A. For example, it is preferable to use an OS transistor as transistor 52A.

[0397] Transistor 52B has the function of controlling the amount of current flowing to the light-emitting element 61. Transistor 52B can also be called a driving transistor. Capacitor 53 has the function of maintaining the gate potential of transistor 52B. The intensity of the light emitted by the light-emitting element 61 is controlled according to the image signal supplied to the gate (node ​​ND) of transistor 52B.

[0398] For example, the semiconductor device 100A shown in Embodiment 1 (see Figures 2A and 2C) can be applied to the pixel circuit 51A. In this case, transistor 10A_1 can be applied to transistor 52B, and transistor 10A_2 can be applied to transistor 52A.

[0399] The pixel circuit 51B shown in Figure 20B is a 3Tr1C type pixel circuit having transistors 52A, 52B, 52C, and a capacitor 53. The pixel circuit 51B shown in Figure 20B has a configuration in which transistor 52C is added to the pixel circuit 51A shown in Figure 20A.

[0400] One source or drain of transistor 52C is connected to the other source or drain of transistor 52B. The other source or drain of transistor 52C is connected to wiring V0. For example, wiring V0 is supplied with a reference potential. The gate of transistor 52C is connected to wiring GL.

[0401] Transistor 52C has the function of controlling the conduction or non-conduction state between the source or drain of transistor 52B and the wiring V0 based on the potential of the wiring GL. Wiring V0 is a wiring that provides a reference potential. When an n-channel transistor is used for transistor 52B, the reference potential of wiring V0 provided via transistor 52C can suppress variations in the gate-source voltage of transistor 52B.

[0402] Furthermore, the wiring V0 can be used to obtain current values ​​that can be used to set pixel parameters. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through transistor 52B or the current flowing through light-emitting element 61 to the outside. The current output to wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the outside.

[0403] For example, the semiconductor device 100 shown in Embodiment 1 (see Figures 1A, 1B, and 2B) can be applied to the pixel circuit 51B. In this case, transistor 10_1 can be applied to transistor 52B, and transistor 10_2 can be applied to transistor 52C. Alternatively, transistor 10_1 can be applied to transistor 52C, and transistor 10_2 can be applied to transistor 52B.

[0404] For example, the semiconductor device 100A shown in Embodiment 1 (see Figures 2A and 2C) can be applied to the pixel circuit 51B. In this case, transistor 10A_1 can be applied to transistor 52B, and transistor 10A_2 can be applied to transistor 52A.

[0405] The pixel circuit 51C shown in FIG. 20C is a configuration in the pixel circuit 51A shown in FIG. 20A when the transistor 52B has a back gate. The back gate of the transistor 52B is connected to the other of the source or drain of the transistor 52B, the other terminal of the capacitor 53, and the anode of the light-emitting element 61. By connecting the back gate of the transistor 52B to the other of the source or drain of the transistor 52B, the operation of the transistor 52B can be made more stable.

[0406] For example, in the semiconductor device 100A (see FIGS. 2A and 2C) shown in Embodiment 1, a configuration in which the transistor 10A_1 is replaced with the transistor 10B_1 (see FIG. 3A) or the transistor 10C_1 (see FIG. 3B) can be applied to the pixel circuit 51C. In this case, the transistor 10B_1 or the transistor 10C_1 can be applied to the transistor 52B, and the transistor 10A_2 can be applied to the transistor 52A, respectively.

[0407] Note that in the pixel circuit 51C, only the transistor 52B has a back gate, but this is not the limit. A configuration in which either one or both of the transistors 52A and 52B have a back gate can also be adopted.

[0408] The pixel circuit 51D shown in FIG. 20D is a configuration in the pixel circuit 51B shown in FIG. 20B when the transistor 52B has a back gate and the wirings connected to the gates of the transistors 52A and 52C are independent of each other.

[0409] The back gate of the transistor 52B is connected to the other of the source or drain of the transistor 52B, one of the source or drain of the transistor 52C, the other terminal of the capacitor 53, and the anode of the light-emitting element 61. As described above for the pixel circuit 51C shown in FIG. 20C, by connecting the back gate of the transistor 52B to the other of the source or drain of the transistor 52B, the operation of the transistor 52B can be made more stable.

[0410] Furthermore, the gate of transistor 52A is connected to wiring GL1, and the gate of transistor 52C is connected to wiring GL2. Unlike the pixel circuit 51B shown in Figure 20B, by providing separate wiring for the gate of transistor 52A and wiring for the gate of transistor 52C, it is possible to apply different potentials to the gates of the two transistors, thereby allowing the two transistors to operate independently.

[0411] For example, in the semiconductor device 100 shown in Embodiment 1 (see Figures 1A, 1B, and 2B), a configuration in which transistor 10_1 is replaced with transistor 10B_1 (see Figure 3A) or transistor 10C_1 (see Figure 3B) can be applied to the pixel circuit 51D. In this case, transistor 10B_1 or transistor 10C_1 can be replaced with transistor 52B, and transistor 10_2 can be replaced with transistor 52C.

[0412] Furthermore, for example, in the semiconductor device 100A shown in Embodiment 1 (see Figures 2A and 2C), a configuration in which transistor 10A_1 is replaced with transistor 10B_1 (see Figure 3A) or transistor 10C_1 (see Figure 3B) can be applied to the pixel circuit 51D. In this case, transistor 10B_1 or transistor 10C_1 can be replaced with transistor 52B, and transistor 10A_2 can be replaced with transistor 52A.

[0413] In the pixel circuit 51D, only transistor 52B has a back gate, but this is not limited to this configuration. It is also possible to have one or more of transistors 52A to 52C have a back gate.

[0414] The pixel circuit 51E shown in Figure 21A has a configuration in which a transistor 52D is added to the pixel circuit 51B shown in Figure 20B. The pixel circuit 51E shown in Figure 21A is a 4Tr1C type pixel circuit having transistors 52A, 52B, 52C, 52D, and a capacitor 53.

[0415] One of the sources or drains of transistor 52D is connected to node ND, and the other source or drain is connected to wiring V0.

[0416] Wirings GL1, GL2, and GL3 are connected to the pixel circuit 51E. Wiring GL1 is connected to the gate of transistor 52A, wiring GL2 is connected to the gate of transistor 52C, and wiring GL3 is connected to the gate of transistor 52D. In this embodiment, wirings GL1, GL2, and GL3 are sometimes collectively referred to as wiring GL. Therefore, there may be more than one wiring GL.

[0417] By simultaneously making transistors 52C and 52D conduct, the source and gate of transistor 52B become at the same potential, making transistor 52B non-conducting. This allows the current flowing to the light-emitting element 61 to be forcibly interrupted. Such a pixel circuit is suitable when using a display method that alternates between display periods and off periods.

[0418] The pixel circuit 51F shown in Figure 21B is an example of the pixel circuit 51E shown in Figure 21A with the addition of a capacitor 53A. The capacitor 53A functions as a retaining capacitor. The pixel circuit 51E shown in Figure 21A is a 4Tr1C type pixel circuit. The pixel circuit 51F shown in Figure 21B is a 4Tr2C type pixel circuit.

[0419] For example, the semiconductor device 100 shown in Embodiment 1 (see Figures 1A, 1B, and 2B) can be applied to the pixel circuit 51E and the pixel circuit 51F, respectively. In this case, transistor 10_1 can be applied to transistor 52B, and transistor 10_2 can be applied to transistor 52C. Alternatively, transistor 10_1 can be applied to transistor 52C, and transistor 10_2 can be applied to transistor 52B.

[0420] Alternatively, transistor 10_1 can be replaced with transistor 52A, and transistor 10_2 can be replaced with transistor 52D. Alternatively, transistor 10_1 can be replaced with transistor 52D, and transistor 10_2 can be replaced with transistor 52A.

[0421] For example, the semiconductor device 100A shown in Embodiment 1 (see Figures 2A and 2C) can be applied to the pixel circuit 51E and the pixel circuit 51F, respectively. In this case, transistor 10A_1 can be applied to transistor 52B, and transistor 10A_2 can be applied to transistor 52A.

[0422] Although the pixel circuits 51E and 51F are configured so that neither transistor has a back gate, this is not limited to this configuration. One or more of transistors 52A to 52D may have a back gate.

[0423] The pixel circuit 51G shown in Figure 21C is a 6Tr1C type pixel circuit having transistors 52A, 52B, 52C, 52D, 52E, 52F, and a capacitor 53.

[0424] One source or drain of transistor 52A is connected to wiring SL, and the gate of transistor 52A is connected to wiring GL2. One source or drain of transistor 52D is connected to wiring ANO, and the gate of transistor 52D is connected to wiring GL1. The other source or drain of transistor 52D is connected to one source or drain of transistor 52B. The other source or drain of transistor 52B is connected to the other source or drain of transistor 52A, and to one source or drain of transistor 52F. The gate of transistor 52F is connected to wiring GL3.

[0425] One source or drain of transistor 52E is connected to the other source or drain of transistor 52D, and one source or drain of transistor 52B. The other source or drain of transistor 52E is connected to the gate of transistor 52B and one terminal of capacitor 53. The other terminal of capacitor 53 is connected to the other source or drain of transistor 52F, the anode of light-emitting element 61, and one source or drain of transistor 52C. The gates of transistor 52E and transistor 52C are connected to wiring GL4. The other source or drain of transistor 52C is connected to wiring V0. The region to which the other source or drain of transistor 52E, the gate of transistor 52B, and one terminal of capacitor 53 are connected functions as node ND.

[0426] For example, the semiconductor device 100 shown in Embodiment 1 (see Figures 1A, 1B, and 2B) can be applied to the pixel circuit 51G. In this case, transistor 10_1 can be applied to transistor 52A, and transistor 10_2 can be applied to transistor 52B. Alternatively, transistor 10_1 can be applied to transistor 52B, and transistor 10_2 can be applied to transistor 52A.

[0427] Alternatively, transistor 10_1 can be replaced with transistor 52B, and transistor 10_2 can be replaced with transistor 52D. Alternatively, transistor 10_1 can be replaced with transistor 52D, and transistor 10_2 can be replaced with transistor 52B.

[0428] Alternatively, transistor 10_1 can be replaced with transistor 52B, and transistor 10_2 can be replaced with transistor 52E. Alternatively, transistor 10_1 can be replaced with transistor 52E, and transistor 10_2 can be replaced with transistor 52B.

[0429] Alternatively, transistor 10_1 can be replaced with transistor 52D, and transistor 10_2 can be replaced with transistor 52E. Alternatively, transistor 10_1 can be replaced with transistor 52E, and transistor 10_2 can be replaced with transistor 52D.

[0430] Alternatively, transistor 10_1 can be replaced with transistor 52A, and transistor 10_2 can be replaced with transistor 52F. Alternatively, transistor 10_1 can be replaced with transistor 52F, and transistor 10_2 can be replaced with transistor 52A.

[0431] Alternatively, transistor 10_1 can be replaced with transistor 52B, and transistor 10_2 can be replaced with transistor 52F. Alternatively, transistor 10_1 can be replaced with transistor 52F, and transistor 10_2 can be replaced with transistor 52B.

[0432] Alternatively, transistor 10_1 can be replaced with transistor 52C, and transistor 10_2 can be replaced with transistor 52F. Alternatively, transistor 10_1 can be replaced with transistor 52F, and transistor 10_2 can be replaced with transistor 52C.

[0433] For example, the semiconductor device 100A shown in Embodiment 1 (see Figures 2A and 2C) can be applied to the pixel circuit 51G. In this case, transistor 10A_1 can be applied to transistor 52B, and transistor 10A_2 can be applied to transistor 52E.

[0434] In the pixel circuit 51G, none of the transistors have back gates, but this is not limited to this configuration. One or more of the transistors 52A to 52F may have back gates.

[0435] Furthermore, since the semiconductor device 100 has a configuration in which transistors 10_1 and 10_2 are connected in series (either the source or drain is connected to the other), for example, the semiconductor device 100 itself can be used as a drive transistor (transistor 52B) in each of the pixel circuits 51A to 51G. In this way, the drive transistor can be considered to have a configuration in which two transistors are connected in series. Consequently, it is possible to have a drive transistor with better current saturation (i.e., the change in current in the saturation region in the drain current (Id) - drain voltage (Vd) characteristic of the transistor is small) than in the case of a configuration with only one transistor.

[0436] Furthermore, as mentioned above, the transistor 10_2 located on the upper side of the semiconductor device 100 can be smaller in size than the transistor 10_1 located on the lower side. Therefore, without increasing the area occupied on the substrate surface, a vertical transistor with the same structure as transistor 10_2 can be placed adjacent to transistor 10_2 on the upper side of the semiconductor device 100. For example, by connecting either the source electrode or drain electrode of the vertical transistor and transistor 10_2 to each other, a structure can be formed in which the vertical transistor, transistor 10_2, and transistor 10_1 are connected in series.

[0437] For example, by applying the above structure to the drive transistors (transistors 52B) of each of the pixel circuits 51A to 51G, the current saturation of the drive transistors can be further improved.

[0438] Note that, among the three transistors included in the above-described structure, only the two transistors (transistor 10_2 and the vertical transistor having the same structure as the transistor 10_2 adjacent thereto) arranged on the upper layer side can be applied as the transistor 52B. Even in this case, compared with the case where only the transistor 10_2 is applied as the transistor 52B, the current saturation of the transistor 52B can be enhanced without increasing the occupation area on the substrate surface. Also, in this case, for the remaining one transistor (transistor 10_1) arranged on the lower layer side, for example, it can be applied as the transistor 52C of the pixel circuit 51B, pixel circuit 51D, pixel circuit 51E, or pixel circuit 51F. Also, for example, it can be applied as the transistor 52D or transistor 52F of the pixel circuit 51G.

[0439] Hereinafter, a specific layout example of the aforementioned pixel circuit and an example of its manufacturing method to which the semiconductor device according to an aspect of the present invention can be applied will be described with reference to FIGS. 22A to 34C. (A) of each figure shows an example of the layout of the pixel circuit 51G shown in FIG. 21C, and (B) and (C) of each figure show examples of the layout of the pixel circuit 51E shown in FIG. 21A, respectively.

[0440] Note that hereinafter, regarding the four transistors (transistors 52A to 52D) included in the pixel circuit 51E, it is assumed that they are arranged in two layers in groups of two, with the transistors 52C and 52D arranged in the first layer and the transistors 52A and 52B arranged in the second layer. Also, regarding the six transistors (transistors 52A to 52F) included in the pixel circuit 51G, it is assumed that they are arranged in two layers in groups of three, with the transistors 52A, 52C, and 52F arranged in the first layer and the transistors 52B, 52D, and 52E arranged in the second layer.

[0441] Furthermore, for (A) and (B) in each figure, the line and spacing of the pattern in each layer is formed with a design value of 1.5 μm, while for (C) in each figure, the line and spacing of the pattern in each layer is formed with a design value of 1.0 μm.

[0442] First, a conductive layer 112a1 is formed (Figures 22A to 22C). For details on how to form the conductive layer 112a1, please refer to the description in Figures 5A and 5B in the <Example of Semiconductor Device Manufacturing Method>.

[0443] Next, an insulating film (not shown) which will become the insulating layer 110_1, and a conductive layer which will become the conductive layer 112b1 are formed on the conductive layer 112a1 in this order. Then, the conductive layer is processed to form the conductive layer 112b1e (Figures 23A to 23C). For details on how to form the conductive layer 112b1e, etc., refer to the description in Figures 6A to 7B in <Examples of Semiconductor Device Manufacturing Methods>.

[0444] Next, the insulating layer that will become the insulating layer 110_1 and a portion of the conductive layer 112b1e are removed to form an opening 143 that reaches the conductive layer 112a1, and the insulating layer 110_1 (not shown) and the conductive layer 112b1 are formed (Figures 24A to 24C). For details on how to form the opening 143, etc., refer to the description in Figures 8A and 8B in <Examples of Semiconductor Device Manufacturing Methods>.

[0445] Next, a semiconductor layer 108_1 is formed on the conductive layer 112b1 such that it has a region that overlaps with the opening 143 (Figures 25A to 25C). For details on how to form the semiconductor layer 108_1, please refer to the description in Figures 9A and 9B in <Examples of Semiconductor Device Manufacturing Methods>.

[0446] Next, an insulating layer 106_1 (not shown) and a conductive film that will become the conductive layer 104_1 are formed on the semiconductor layer 108_1 in that order, and then the conductive film is processed to form the conductive layer 104_1 (Figures 26A to 26C). For information on how to form the conductive layer 104_1 and the like, refer to the description in Figures 10A to 11B in <Examples of Semiconductor Device Manufacturing Methods>.

[0447] As a result, in Figure 26A, transistors 52A, 52C, and 52F are formed, respectively. In Figure 26B, transistors 52C and 52D are formed, respectively. In Figure 26C, transistors 52C and 52D are formed, respectively. The aforementioned transistors are transistors that are placed in the first layer of pixel circuit 51E and pixel circuit 51G, respectively.

[0448] Next, insulating layers 192, 193, and 194 (none of which are shown) are formed in this order on each transistor shown in Figures 26A to 26C. Then, an opening 145 is formed in the region of the insulating layer that overlaps with the conductive layer 112b1. Next, a conductive layer 115 is formed to fill the opening 145 (Figures 27A to 27C). For information on how to form the conductive layer 115, etc., refer to the description in Figures 12A to 13B in <Examples of Semiconductor Device Manufacturing Methods>.

[0449] The following steps concern the fabrication of the transistors located in the second layer of the pixel circuit 51E and the pixel circuit 51G, respectively. For clarity, only the structural components formed in the second layer will be shown in the following diagrams.

[0450] Next, a conductive layer 112a2 is formed on the conductive layer 115 and the insulating layer 194 (Figures 28A to 28C). For details on how to form the conductive layer 112a2, please refer to the description in Figures 14A and 14B in the <Example of Semiconductor Device Manufacturing Method>. Figures 28B and 28C show an example in which a conductive layer 112a3 is formed using a separate mask after the conductive layer 112a2 has been formed. The conductive layer 112a3 is, for example, a conductive layer that becomes wiring ANO in the pixel circuit 51E. The conductive layer 112a3 can be formed using the same method as the wiring 112a2, using a material that can be used for the wiring 112a2.

[0451] Next, an insulating film (not shown) which will become the insulating layer 110_2, and a conductive layer which will become the conductive layer 112b2 are formed in this order on the conductive layer 112a2 (and on the conductive layer 112a3). These are then processed to form island-shaped insulating layers 110_2 (not shown) and conductive layers 112b2 (Figures 29A to 29C). For information on how to form the conductive layer 112b2, etc., refer to the description in Figures 15A to 16B in <Examples of Semiconductor Device Manufacturing Methods>.

[0452] Next, a semiconductor layer 108_2 is formed on the conductive layer 112b2 such that it has a region that overlaps with at least one side surface of the conductive layer 112b2 (Figures 30A to 30C). For details on how to form the semiconductor layer 108_2, please refer to the description in Figures 17A and 17B in the <Example of Semiconductor Device Manufacturing Method>.

[0453] Next, an insulating layer 106_2 (not shown) and a conductive film that will become the conductive layer 104_2 are formed on the semiconductor layer 108_2 in that order, and then the conductive film is processed to form the conductive layer 104_2 (Figures 31A to 31C). For information on how to form the conductive layer 104_2 and the like, refer to the description in Figures 18A and 18B in <Examples of Semiconductor Device Manufacturing Methods>.

[0454] As a result, in Figure 31A, transistors 52B, 52D, and 52E are formed, respectively. In Figure 31B, transistors 52A and 52B are formed, respectively. In Figure 31C, transistors 52A and 52B are formed, respectively. The aforementioned transistors are transistors that are placed in the second layer of pixel circuit 51E and pixel circuit 51G, respectively.

[0455] Figure 32A shows a layout in which the second layer of the pixel circuit 51G shown in Figure 31A is superimposed on the first layer of the pixel circuit 51G shown in Figure 26A. Figure 32B shows a layout in which the second layer of the pixel circuit 51E shown in Figure 31B is superimposed on the first layer of the pixel circuit 51E shown in Figure 26B. Figure 32C shows a layout in which the second layer of the pixel circuit 51E shown in Figure 31C is superimposed on the first layer of the pixel circuit 51E shown in Figure 26C.

[0456] Figures 33A to 33C show only semiconductor layer 108_1 and semiconductor layer 108_2 extracted from the layout shown in Figures 32A to 32C, respectively.

[0457] In Figure 33A, according to one aspect of the present invention, it can be seen that two of the six transistors in the pixel circuit 51G are superimposed (specifically, transistor 52A and transistor 52B above it). Also, in Figure 33B, according to one aspect of the present invention, it can be seen that two of the four transistors in the pixel circuit 51E are superimposed (specifically, transistor 52C and transistor 52B above it). Also, in Figure 33C, according to one aspect of the present invention, it can be seen that the four transistors in the pixel circuit 51E are superimposed in pairs at two locations (specifically, transistor 52D and transistor 52A above it, and transistor 52C and transistor 52B above it).

[0458] Figures 34A to 34C show, respectively, only the semiconductor layer 108_1, semiconductor layer 108_2, conductive layer 112b1, conductive layer 112a2, and conductive layer 115 of the two superimposed transistors from the layout shown in Figures 32A to 32C.

[0459] As shown in Figures 34A to 34C, in each layout, the conductive layer 112b1 of the first layer transistor and the conductive layer 112a2 of the second layer transistor are connected by the conductive layer 115. In other words, in each layout, the semiconductor device 100 shown in Embodiment 1 (see Figures 1A, 1B, and 2B) can be applied to the locations where two transistors overlap. In this case, the transistor placed in the first layer of each layout corresponds to transistor 10_1, and the transistor placed in the second layer corresponds to transistor 10_2.

[0460] Furthermore, when the layout shown in Figure 32A is applied to the pixel circuit 51G, which consists of six transistors, a resolution of 1500 ppi or higher can be achieved. Similarly, when the layout shown in Figure 32B is applied to the pixel circuit 51E, which consists of four transistors, a resolution of 2000 ppi or higher can be achieved. And when the layout shown in Figure 32C is applied to the pixel circuit 51E, which consists of four transistors, a resolution of 3000 ppi or higher can be achieved.

[0461] As described above, by using a semiconductor device according to one embodiment of the present invention in the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced. Therefore, the resolution of the display device can be increased. For example, a display device can be realized with a resolution of 1,000 ppi or more and 10,000 ppi or less, preferably 2,000 ppi or more and 9,000 ppi or less, more preferably 3,000 ppi or more and 8,000 ppi or less, even more preferably 4,000 ppi or more and 8,000 ppi or less, even more preferably 5,000 ppi or more and 8,000 ppi or less, and even more preferably 6,000 ppi or more and 8,000 ppi or less.

[0462] Furthermore, by reducing the area occupied by the pixel circuit, the number of pixels in the display device can be increased (higher resolution). For example, it becomes possible to realize display devices with extremely high resolutions such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K2K (3840 x 2160 pixels), or 8K4K (7680 x 4320 pixels).

[0463] Therefore, by using a semiconductor device according to one aspect of the present invention in the pixel circuit of a display device, the display quality of the display device can be improved. Furthermore, in a bottom-emission type display device using an EL element, the aperture ratio of the pixels can be increased. Pixels with a high aperture ratio can emit light with the same brightness as pixels with a low aperture ratio, but with a lower current density. Therefore, the reliability of the display device can be improved.

[0464] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0465] (Embodiment 4) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 35 to 39.

[0466] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television equipment, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices.

[0467] Furthermore, the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, and as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0468] A semiconductor device according to one aspect of the present invention can be used as a display device or a module having said display device. Examples of modules having said display devices include a module to which a connector such as a Flexible Printed Circuit (FPC) or TCP (Tape Carrier Package) is attached, and a module on which an Integrated Circuit (IC) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method.

[0469] [Display device 50A] Figure 35 shows a perspective view of the display device 50A.

[0470] The display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In Figure 35, substrate 152 is shown with a dashed line.

[0471] The display device 50A includes a display unit 168, a connection unit 140, a circuit unit 164, wiring 165, etc. Figure 35 shows an example in which IC 173 and FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Figure 35 can also be described as a display module having the display device 50A, an IC, and an FPC.

[0472] The connection portion 140 is provided on the outside of the display unit 168. The connection portion 140 can be provided along one or more sides of the display unit 168. There may be one or more connection portions 140. Figure 35 shows an example in which the connection portion 140 is provided so as to surround all four sides of the display unit. The connection portion 140 connects the common electrode of the display element to the conductive layer, and can supply potential to the common electrode.

[0473] The circuit section 164 includes, for example, a scan line drive circuit (also called a gate driver). Alternatively, the circuit section 164 can be configured to include both a scan line drive circuit and a signal line drive circuit (also called a source driver).

[0474] The wiring 165 has the function of supplying signals and power to the display unit 168 and the circuit unit 164. These signals and power are input to the wiring 165 from an external source via the FPC 172, or from the IC 173.

[0475] Figure 35 shows an example in which IC 173 is provided on the substrate 151 using the COG method or COF method. For example, IC 173 can be an IC having one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module can also be configured without an IC. Furthermore, the IC can be mounted on the FPC using the COF method or the like.

[0476] One embodiment of the present invention can be applied, for example, to one or both of the display unit 168 and the circuit unit 164 of a display device 50A.

[0477] For example, when a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the occupied area of ​​the drive circuit can be reduced, resulting in a narrow-bezel display device. Furthermore, because the semiconductor device according to one aspect of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0478] The display unit 168 is the area in the display device 50A that displays images, and has a plurality of periodically arranged pixels 210. Figure 35 shows an enlarged view of one pixel 210.

[0479] There are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0480] The pixel 210 shown in Figure 35 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light.

[0481] Each sub-pixel 11R, sub-pixel 11G, and sub-pixel 11B includes a display element and a circuit that controls the driving of the display element.

[0482] Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used. Furthermore, QLEDs using a light source and color conversion technology with quantum dot materials can also be used.

[0483] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0484] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs, OLEDs, and semiconductor lasers. For example, mini-LEDs and micro-LEDs can be used as LEDs.

[0485] Examples of light-emitting materials for light-emitting devices include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0486] The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0487] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0488] In this embodiment, the explanation will mainly be given using the case where a light-emitting element is used as the display element.

[0489] Furthermore, a display device according to one aspect of the present invention may be configured as any of the following: a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed; a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed; or a dual-emission type that emits light on both sides.

[0490] Figure 36 shows an example of a cross-section obtained by cutting a portion of the display device 50A, including the FPC 172, a portion of the circuit section 164, a portion of the display section 168, a portion of the connection section 140, and a portion of the end section.

[0491] The display device 50A shown in Figure 36 has transistors 205D, 205R, 205G, 205B, 206R, 206G, 206B, light-emitting elements 130R, 130G, 130B, etc. between substrates 151 and 152. Light-emitting element 130R is a display element of a sub-pixel 11R that emits red light, light-emitting element 130G is a display element of a sub-pixel 11G that emits green light, and light-emitting element 130B is a display element of a sub-pixel 11B that emits blue light.

[0492] An insulating layer 197 is provided on the substrate 151. Transistors 205D, 205R, 205G, and 205B are provided on the insulating layer 197.

[0493] It is preferable to use a material for the insulating layer 197 that does not easily absorb impurities such as water and hydrogen. This allows the insulating layer 197 to function as a barrier layer, effectively suppressing the diffusion of impurities from the substrate 151 to the transistor. Therefore, the reliability of the display device can be improved.

[0494] The display device 50A employs an SBS structure. The SBS structure allows for the optimization of materials and configurations for each light-emitting element, thus increasing the freedom in selecting materials and configurations, and making it easier to improve brightness and reliability.

[0495] Furthermore, the display device 50A is a top-emission type. In the top-emission type, transistors and the like can be arranged overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type.

[0496] Transistors 205D, 205R, 205G, and 205B are all formed on the substrate 151. These transistors can be manufactured using the same materials and processes.

[0497] In this embodiment, an example is shown in which OS transistors are used for transistors 205D, 205R, 205G, 205B, 206R, 206G, and 206B. For example, transistor 10_1 according to one aspect of the present invention can be used for transistors 205D, 205R, 205G, and 205B. Also, for example, transistor 10_2 according to one aspect of the present invention can be used for transistors 206R, 206G, and 206B. Transistor 10_2 according to one aspect of the present invention can also be used for transistor 205D. In other words, the display device 50A has either or both of transistors 10_1 or 10_2 according to one aspect of the present invention in both the display unit 168 and the circuit unit 164. By using a semiconductor device according to one embodiment of the present invention (shown in Figure 36 as the semiconductor device 100 in Figures 1A and 1B) in which transistors 10_1 and 10_2 are superimposed on the display unit 168, the pixel size can be reduced, and higher resolution can be achieved. Furthermore, by using at least one of transistors 10_1 or 10_2 according to one embodiment of the present invention in the circuit unit 164, the occupied area of ​​the circuit unit 164 can be reduced, and a narrower bezel can be achieved. For details on transistors 10_1 and 10_2 according to one embodiment of the present invention, refer to the description of the previous embodiment.

[0498] Specifically, transistors 205D, 205R, 205G, and 205B each have a conductive layer 104_1 that functions as a gate electrode, an insulating layer 106_1 that functions as a gate insulating layer, a conductive layer 112a1 that functions as one of the source electrode or drain electrode, a conductive layer 112b1 that functions as the other of the source electrode or drain electrode, and a semiconductor layer 108_1 having a metal oxide.

[0499] Furthermore, transistors 206R, 206G, and 206B each have a conductive layer 104_2 that functions as a gate electrode, an insulating layer 106_2 that functions as a gate insulating layer, a conductive layer 112a2 that functions as one of the source electrode or drain electrode, a conductive layer 112b2 that functions as the other of the source electrode or drain electrode, and a semiconductor layer 108_2 having a metal oxide.

[0500] Furthermore, the transistors in the display device of this embodiment are not limited to those of one aspect of the present invention. For example, a configuration combining the transistors of one aspect of the present invention with transistors of other structures is also possible.

[0501] The display device of this embodiment may also have a configuration that includes, for example, one or more of a planar transistor, a staggered transistor, or an inverse staggered transistor. The transistors in the display device of this embodiment may be either top-gate or bottom-gate type. Alternatively, the device may have a configuration in which gates are provided above and below the semiconductor layer in which the channel is formed.

[0502] Furthermore, the display device of this embodiment may also have a transistor (Si transistor) that uses silicon in the channel formation region.

[0503] Examples of silicon include single-crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, transistors having an LTPS semiconductor layer (hereinafter also referred to as LTPS transistors) can be used. LTPS transistors have high field-effect mobility and good frequency characteristics.

[0504] To increase the luminescence brightness of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to Si transistors, OS transistors have a higher breakdown voltage between the source and drain, so a higher voltage can be applied to the source-drain of an OS transistor. Therefore, by using an OS transistor as the drive transistor in the pixel circuit, the amount of current flowing through the light-emitting element can be increased, thereby increasing the luminescence brightness of the light-emitting element.

[0505] Furthermore, when the transistor operates in the saturation region, OS transistors exhibit smaller changes in source-drain current in response to changes in gate-source voltage compared to Si transistors. Therefore, by using OS transistors as driving transistors in the pixel circuit, the current flowing between the source and drain can be precisely controlled by changes in gate-source voltage, thereby allowing control of the current flowing to the light-emitting element. This allows for an increase in the number of grayscale levels in the pixel circuit.

[0506] Furthermore, in terms of the saturation characteristics of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be supplied to a light-emitting element even if there are variations in the current-voltage characteristics of the light-emitting element. In other words, when operating in the saturation region, the source-drain current remains almost unchanged even when the source-drain voltage is changed, thus stabilizing the luminescence brightness of the light-emitting element.

[0507] The transistors in the circuit unit 164 and the transistors in the display unit 168 can have the same structure or different structures. The structures of the multiple transistors in the circuit unit 164 can all be the same or there can be two or more types. Similarly, the structures of the multiple transistors in the display unit 168 can all be the same or there can be two or more types.

[0508] All of the transistors in the display unit 168 can be OS transistors, all of the transistors in the display unit 168 can be Si transistors, and some of the transistors in the display unit 168 can be OS transistors and the rest can be Si transistors.

[0509] For example, by using both an LTPS transistor and an OS transistor in the display unit 168, a display device with low power consumption and high driving capability can be realized. Furthermore, a configuration combining an LTPS transistor and an OS transistor is sometimes referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used for a transistor that functions as a switch to control conduction and non-conduction between wires, and an LTPS transistor is used for a transistor that controls current.

[0510] For example, one of the transistors in the display unit 168 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a drive transistor. Either the source or the drain of the drive transistor is connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor for the drive transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.

[0511] On the other hand, the other transistor in the display unit 168 functions as a switch for controlling the selection and deselection of pixels, and can also be called a selection transistor. The gate of the selection transistor is connected to the gate line, and either the source or the drain is connected to the source line (signal line). It is preferable to use an OS transistor for the selection transistor. This makes it possible to maintain the gradation of pixels even when the frame frequency is significantly reduced (for example, 1 fps or less), and thus power consumption can be reduced by stopping the driver when displaying a still image.

[0512] An insulating layer 195 is provided so as to cover transistors 206R, 206G, and 206B.

[0513] The insulating layer 195 preferably functions as a protective layer for the transistor. Similar to the insulating layer 197, it is preferable to use a material for the insulating layer 195 that does not easily absorb impurities such as water and hydrogen. This allows the insulating layer 195 to function as a barrier layer, effectively suppressing the diffusion of impurities from above the transistor into the transistor.

[0514] In this way, by providing an insulating layer 197 below (on the substrate 151 side) transistors 205D, 205R, 205G, 205B, 206R, 206G, and 206B, and an insulating layer 195 above them, the transistors can be sandwiched between upper and lower barrier layers. This effectively suppresses the diffusion of impurities into the transistors from the outside, further improving the reliability of the display device.

[0515] An insulating layer 235 is provided on the insulating layer 195. Preferably, the insulating layer 235 functions as a planarizing layer that fills in any steps or irregularities formed on the transistors 205R, 205G, and 205B, and flattens the upper surface.

[0516] Furthermore, it is preferable that the outermost layer of the insulating layer 235 functions as an etching protection layer. This makes it possible to suppress the formation of recesses in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Alternatively, the insulating layer 235 can be configured to have recesses when processing the pixel electrodes 111R, 111G, 111B, etc.

[0517] A light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B are provided on the insulating layer 235.

[0518] The light-emitting element 130R has a pixel electrode 111R on an insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 135 on the EL layer 113R. The light-emitting element 130R shown in Figure 36 emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0519] The light-emitting element 130G has a pixel electrode 111G on an insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 135 on the EL layer 113G. The light-emitting element 130G shown in Figure 36 emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0520] The light-emitting element 130B has a pixel electrode 111B on an insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 135 on the EL layer 113B. The light-emitting element 130B shown in Figure 36 emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0521] In Figure 36, EL layers 113R, 113G, and 113B are all shown with the same film thickness, but this is not the only option. The film thicknesses of EL layers 113R, 113G, and 113B can also be different. For example, it is preferable to set the film thicknesses of EL layers 113R, 113G, and 113B to thicknesses corresponding to the optical path length that intensifies the light emitted by each layer. This enables the realization of a microcavity structure and improves the color purity of the light emitted from each light-emitting element.

[0522] The pixel electrode 111R is connected to the conductive layer 112a2 of transistor 206R via openings provided in the insulating layers 110_2, 106_2, 195, and 235 located on the conductive layer 112a2. Furthermore, since the conductive layer 112a2 of transistor 206R and the conductive layer 112b1 of transistor 205R are connected via the conductive layer 115, the pixel electrode 111R is also connected to the conductive layer 112b1 of transistor 205R.

[0523] Similarly, the pixel electrode 111G is connected to the conductive layer 112a2 of transistor 206G and the conductive layer 112b1 of transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112a2 of transistor 206B and the conductive layer 112b1 of transistor 205B.

[0524] The ends of the pixel electrodes 111R, 111G, and 111B are covered by an insulating layer 237. The insulating layer 237 functions as a partition (also called a bank or spacer). The insulating layer 237 can be provided in a single-layer or multi-layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the insulating layer 237 can be made of a material that can be used for the insulating layer 235. The insulating layer 237 electrically insulates the pixel electrodes from the common electrode. In addition, the insulating layer 237 electrically insulates adjacent light-emitting elements from each other.

[0525] The common electrode 135 is a continuous film provided in common to the light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B. The common electrode 135, which is shared by multiple light-emitting elements, is connected to a conductive layer 123 provided at the connection portion 140. It is preferable to use a conductive layer for the conductive layer 123 that is made of the same material and formed by the same process as the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B.

[0526] In a display device according to one aspect of the present invention, among the pixel electrodes and common electrodes, the electrode that extracts light is preferably made of a conductive film that transmits visible light. Furthermore, it is preferable that the electrode that does not extract light is made of a conductive film that reflects visible light.

[0527] Furthermore, a conductive film that transmits visible light can also be used on the electrode that does not extract light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer can be reflected by the reflective layer and extracted from the display device.

[0528] As the material for forming the pair of electrodes of the light-emitting element, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. Other examples of such materials include indium tin oxide (ITO), In-Si-Sn oxide (ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Furthermore, such materials include aluminum-containing alloys (aluminum alloys) such as aluminum, nickel, and lanthanum alloys (Al-Ni-La), as well as silver-magnesium alloys and silver-containing alloys such as silver-palladium-copper alloys (Ag-Pd-Cu, also written as APC). Other materials include elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys containing these in appropriate combinations, graphene, and the like.

[0529] It is preferable that the light-emitting element has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes in the light-emitting element is a semitransmitting / semi-reflective electrode that transmits and reflects visible light, and the other is a reflective electrode that reflects visible light. By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting element.

[0530] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a visible light transmittance (light with a wavelength of 400 nm or more and less than 750 nm) of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transparent and semi-reflective electrodes shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes shall be 1 × 10⁻⁶ −２ A value of Ωcm or less is preferable.

[0531] The EL layers 113R, 113G, and 113B are each provided in an island-like configuration. In Figure 36, the edges of adjacent EL layers 113R and 113G overlap, the edges of adjacent EL layers 113G and 113B overlap, and the edges of adjacent EL layers 113R and 113B overlap. When forming island-like EL layers using a fine metal mask, the edges of adjacent EL layers may overlap as shown in Figure 36, but this is not the only case. In other words, adjacent EL layers can not overlap and can be configured to be separated from each other. Furthermore, in a display device, it is possible to have a configuration in which both adjacent EL layers overlap and adjacent EL layers do not overlap and are separated from each other.

[0532] Each of the EL layers 113R, 113G, and 113B has at least one light-emitting layer. The light-emitting layer has one or more types of light-emitting materials. As the light-emitting material, a material that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red can be used as appropriate. In addition, a material that emits near-infrared light can also be used as the light-emitting material.

[0533] Examples of luminescent materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0534] The light-emitting layer may also consist of one or more types of organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). The one or more types of organic compounds may include one or both of materials with high hole transport properties (hole transport materials) and materials with high electron transport properties (electron transport materials). Furthermore, bipolar materials (materials with high electron and hole transport properties) or TADF materials may be used as the one or more types of organic compounds.

[0535] The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that exhibits emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration simultaneously achieves high efficiency, low-voltage operation, and a long lifespan for the light-emitting element.

[0536] The EL layer may have, in addition to the light-emitting layer, one or more of the following: a layer containing a material with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking properties (electron blocking layer), a layer containing a material with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking properties (hole blocking layer). Furthermore, the EL layer may also have a configuration that includes either or both a bipolar material and a TADF material.

[0537] The light-emitting element can use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0538] A light-emitting element can be configured as either a single structure (having only one light-emitting unit) or a tandem structure (having multiple light-emitting units). Each light-emitting unit has at least one light-emitting layer. In a tandem structure, multiple light-emitting units are connected in series via a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By using a tandem structure, a light-emitting element capable of high-brightness emission can be created. Furthermore, compared to a single structure, a tandem structure can reduce the current required to obtain the same brightness, thereby improving reliability. The tandem structure can also be called a stacked structure.

[0539] In Figure 36, when using a tandem light-emitting element, it is preferable that the EL layer 113R has a structure having multiple light-emitting units that emit red light, the EL layer 113G has a structure having multiple light-emitting units that emit green light, and the EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0540] A protective layer 131 is provided on the light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B. The protective layer 131 and the substrate 152 are bonded together via an adhesive layer 149. A light-shielding layer 117 is provided on the substrate 152. For sealing the light-emitting element, for example, a solid sealing structure or a hollow sealing structure can be applied. In Figure 36, the space between the substrate 152 and the substrate 151 is filled with the adhesive layer 149, and a solid sealing structure is applied. Alternatively, the space can be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure can be applied. In this case, the adhesive layer 149 can be configured to be provided in a frame shape so as not to overlap with the light-emitting element. Furthermore, the space can be filled with a resin different from the adhesive layer 149 provided in a frame shape.

[0541] The protective layer 131 is provided at least on the display section 168, and preferably so as to cover the entire display section 168. It is preferable that the protective layer 131 covers not only the display section 168, but also the connection section 140 and the circuit section 164. Furthermore, it is preferable that the protective layer 131 extends to the end of the display device 50A. On the other hand, in the connection section 204, there is a portion where the protective layer 131 is not provided in order to connect the FPC 172 and the conductive layer 167.

[0542] By providing a protective layer 131 on the light-emitting element 130R, on the light-emitting element 130G, and on the light-emitting element 130B, the reliability of the light-emitting element can be improved.

[0543] The protective layer 131 can be a single layer or a laminated structure of two or more layers. Furthermore, the conductivity of the protective layer 131 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.

[0544] The presence of an inorganic film in the protective layer 131 prevents oxidation of the common electrode 135 and suppresses the intrusion of impurities that induce degradation of the light-emitting element (e.g., water, oxygen, etc.), thereby suppressing degradation of the light-emitting element and improving the reliability of the display device.

[0545] For example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxidogenic nitride insulating films, and nitride oxide insulating films can be used for the protective layer 131. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably has a nitride insulating film or a nitride oxide insulating film, and more preferably has a nitride insulating film.

[0546] Furthermore, the protective layer 131 may also be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO. The inorganic film is preferably highly resistive, and more specifically, it is preferably more resistive than the common electrode 135. The inorganic film may also contain nitrogen.

[0547] When the light emitted from a light-emitting element is extracted via a protective layer 131, it is preferable that the protective layer 131 has high transmittance to visible light. For example, ITO, IGZO, and aluminum oxide are preferred because they are inorganic materials with high transmittance to visible light.

[0548] As the protective layer 131, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used. By using this laminated structure, it is possible to suppress the intrusion of impurities (e.g., water, oxygen, etc.) that can induce degradation of the light-emitting element into the EL layer.

[0549] Furthermore, the protective layer 131 can also have an organic film. For example, the protective layer 131 can have both an organic film and an inorganic film.

[0550] A connection portion 204 is provided in the region of substrate 151 where substrate 152 does not overlap. At the connection portion 204, wiring 165 is connected to FPC 172 via conductive layer 166, conductive layer 167, and connection layer 242. The wiring 165 is shown as an example of a single-layer conductive layer obtained by processing the same conductive film as conductive layer 112a1. The conductive layer 166 is shown as an example of a single-layer conductive layer obtained by processing the same conductive film as conductive layer 112b2. The conductive layer 167 is shown as an example of a single-layer conductive layer obtained by processing the same conductive film as pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B. On the upper surface of the connection portion 204, the conductive layer 167 is exposed. This allows the connection portion 204 and FPC 172 to be connected via the connection layer 242.

[0551] The display device 50A is of the top-emission type. The light emitted by the light-emitting element is emitted towards the substrate 152. It is preferable to use a material with high transmittance to visible light for the substrate 152. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 135) contains a material that transmits visible light.

[0552] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 that faces the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in connection parts 140, in circuit parts 164, etc.

[0553] Furthermore, a colored layer, such as a color filter, can be provided on the surface of the substrate 152 facing the substrate 151, or on the protective layer 131. By placing a color filter on top of the light-emitting element, the color purity of the light emitted from the pixel can be increased.

[0554] Furthermore, various optical components can be placed on the outside of the substrate 152 (the side opposite to the substrate 151). Examples of optical components include polarizing plates, phase difference plates, light diffusion layers (such as diffusion films), anti-reflective layers, and light-gathering films. Additionally, surface protection layers such as an antistatic film to suppress dust adhesion, a water-repellent film to make it difficult for dirt to adhere, a hard coat film to suppress the occurrence of scratches during use, and an impact absorption layer can be placed on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO₂) can be used as a surface protection layer. ｘ By providing a protective layer, surface contamination and scratching can be suppressed, which is preferable. Furthermore, DLC (diamond-like carbon), aluminum oxide (AlO2) can be used as the surface protective layer. ｘ ), polyester-based materials, or polycarbonate-based materials may be used. It is preferable to use a material with high transmittance to visible light for the surface protective layer. Furthermore, it is preferable to use a material with high hardness for the surface protective layer.

[0555] Substrates 151 and 152 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, etc., respectively. The substrate on the side that extracts light from the light-emitting element should be made of a material that transmits the light. If flexible materials are used for substrates 151 and 152, the flexibility of the display device can be increased, and a flexible display can be realized. In addition, a polarizing plate can be used as at least one of substrates 151 and 152.

[0556] Substrates 151 and 152 can be made from polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrates 151 and 152 can also be made of glass of a thickness sufficient to provide flexibility.

[0557] Furthermore, when a circular polarizing plate is superimposed on a display device, it is preferable to use a substrate with high optical isotropy for the substrate of the display device. A substrate with high optical isotropy has low birefringence (or a small amount of birefringence). Examples of films with high optical isotropy include triacetylcellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.

[0558] As the adhesive layer 149, various types of curing adhesives can be used, such as UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0559] As the connecting layer 242, an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like can be used.

[0560] [Display Device 50B] The display device 50B shown in Figure 37 differs from the display device 50A in that each sub-pixel of each color uses a light-emitting element having a common EL layer 113 and a coloring layer (such as a color filter). In the following description of the display device, parts that are the same as those described earlier may be omitted.

[0561] The display device 50B shown in Figure 37 has transistors 205D, 205R, 205G, 205B, 206R, 206G, 206B, light-emitting elements 130R, 130G, 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, a colored layer 132B that transmits blue light, etc., between substrates 151 and 152.

[0562] The light-emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 135 on the EL layer 113. The light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0563] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 135 on the EL layer 113. The light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0564] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 135 on the EL layer 113. The light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0565] The light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B each have a common EL layer 113 and a common electrode 135. Providing a common EL layer 113 for each sub-pixel of each color reduces the number of manufacturing steps compared to providing a different EL layer for each sub-pixel of each color.

[0566] For example, the light-emitting elements 130R, 130G, and 130B shown in Figure 37 emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, respectively, to obtain light of a desired color.

[0567] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When obtaining white light emission using two light-emitting layers, the light-emitting layers should be selected such that their emission colors are complementary. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration that emits white light as a whole can be obtained. Also, when obtaining white light emission using three or more light-emitting layers, the emission colors of the three or more light-emitting layers should combine to produce white light as a whole.

[0568] The EL layer 113 preferably has, for example, an emissive layer having a light-emitting material that emits blue light, and an emissive layer having a light-emitting material that emits visible light with a longer wavelength than blue. The EL layer 113 preferably has, for example, an emissive layer that emits yellow light and an emissive layer that emits blue light. Alternatively, the EL layer 113 preferably has, for example, an emissive layer that emits red light, an emissive layer that emits green light, and an emissive layer that emits blue light.

[0569] For light-emitting elements that emit white light, a tandem structure is preferable. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and a light-emitting unit that emits blue light in that order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and red light and a light-emitting unit that emits blue light in that order. For example, the number of layers and color order of the light-emitting unit can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, B, or a three-layer structure of B, X, B. The number of layers and color order of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, G, or a three-layer structure of R, G, R. It is also possible to have a configuration in which other layers are provided between the two light-emitting layers.

[0570] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in Figure 37 emit blue light. In this case, the EL layer 113 has one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. In addition, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, by providing a color conversion layer between the light-emitting element 130R or 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or 130G can be converted into longer wavelength light, and red or green light can be extracted. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. Some of the light emitted by the light-emitting elements may be transmitted directly without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer via the colored layer, the colored layer absorbs light of colors other than the desired color, thereby increasing the color purity of the light exhibited by the subpixel.

[0571] [Display device 50C] The display device 50C shown in Figure 38 differs from the display device 50B mainly in that it is a bottom-emission type display device.

[0572] The light emitted by the light-emitting element is emitted towards the substrate 151. It is preferable to use a material with high transmittance to visible light for the substrate 151. On the other hand, the light transmittance of the material used for the substrate 152 is not a requirement.

[0573] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistors. Figure 38 shows an example in which a light-shielding layer 117 is provided on the substrate 151, an insulating layer 153 is provided on the light-shielding layer 117, and transistors 205D, 205R (not shown), 205G, 205B, etc. are provided on the insulating layer 153. In addition, a colored layer 132R (not shown), a colored layer 132G, and a colored layer 132B are provided on the insulating layer 195, and an insulating layer 235 is provided on the colored layer 132R, a colored layer 132G, and a colored layer 132B.

[0574] The light-emitting element 130G, which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 135.

[0575] The light-emitting element 130B, which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 135.

[0576] The pixel electrodes 111G and 111B are made of materials with high transmittance to visible light. It is preferable to use a material that reflects visible light for the common electrode 135. In a bottom-emission type display device, a metal with low resistance can be used for the common electrode 135, which suppresses voltage drops caused by the resistance of the common electrode 135 and enables the realization of high display quality.

[0577] A transistor according to one aspect of the present invention can be miniaturized and have a reduced occupied area, which allows for an increase in the aperture ratio of pixels or a reduction in the size of pixels in a display device with a bottom emission structure.

[0578] [Display Device 50D] The display device 50D shown in Figure 39 is an example of a display device to which an MML (metal maskless) structure is applied. In other words, the display device 50D has a light-emitting element manufactured without using a fine metal mask. Note that the laminated structure from the substrate 151 to the insulating layer 235 and the laminated structure from the protective layer 131 to the substrate 152 are the same as those of the display device 50A, so their explanation is omitted.

[0579] In Figure 39, light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 235.

[0580] The light-emitting element 130R includes a conductive layer 124R on an insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 134 on the layer 133R, and a common electrode 135 on the common layer 134. The light-emitting element 130R shown in Figure 39 emits red light (R). Layer 133R has a light-emitting layer that emits red light. In the light-emitting element 130R, layer 133R and the common layer 134 can be collectively called the EL layer. In addition, one or both of the conductive layer 124R and the conductive layer 126R can be called the pixel electrode.

[0581] The light-emitting element 130G includes a conductive layer 124G on an insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 134 on the layer 133G, and a common electrode 135 on the common layer 134. The light-emitting element 130G shown in Figure 39 emits green light (G). Layer 133G has a light-emitting layer that emits green light. In the light-emitting element 130G, layer 133G and the common layer 134 can be collectively called the EL layer. In addition, one or both of the conductive layer 124G and the conductive layer 126G can be called the pixel electrode.

[0582] The light-emitting element 130B includes a conductive layer 124B on an insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 134 on the layer 133B, and a common electrode 135 on the common layer 134. The light-emitting element 130B shown in Figure 39 emits blue light (B). Layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, layer 133B and the common layer 134 can be collectively called the EL layer. In addition, one or both of the conductive layers 124B and 126B can be called the pixel electrode.

[0583] In this specification, among the EL layers of a light-emitting element, layers provided in an island-like manner for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer common to multiple light-emitting elements is referred to as common layer 134. In this specification, the common layer 134 may be omitted, and layers 133R, 133G, and 133B may be referred to as island-like EL layers, island-shaped EL layers, etc.

[0584] Layers 133R, 133G, and 133B are separated from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0585] Note that in Figure 39, layers 133R, 133G, and 133B are all shown with the same film thickness, but this is not the only option. The film thicknesses of layers 133R, 133G, and 133B can also be different.

[0586] The conductive layer 124R is connected to the conductive layer 112a2 of transistor 206R through openings provided in the insulating layers 110_2, 106_2, 195, and 235 located on the conductive layer 112a2. Furthermore, since the conductive layer 112a2 of transistor 206R and the conductive layer 112b1 of transistor 205R are connected via the conductive layer 115, the pixel electrode 111R is also connected to the conductive layer 112b1 of transistor 205R.

[0587] Similarly, conductive layer 124G is connected to conductive layer 112a2 of transistor 206G and conductive layer 112b1 of transistor 205G, and conductive layer 124B is connected to conductive layer 112a2 of transistor 206B and conductive layer 112b1 of transistor 205B.

[0588] The conductive layer 124R, conductive layer 124G, and conductive layer 124B are formed to cover openings provided in the insulating layer 110_2, insulating layer 106_2, insulating layer 195, and insulating layer 235, which are located on the conductive layer 112a2, respectively. Layer 128 is embedded in the recesses of the conductive layer 124R, conductive layer 124G, and conductive layer 124B, respectively.

[0589] Layer 128 has the function of flattening the recesses of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B, which are connected to conductive layers 124R, 124G, and 124B, are provided on conductive layer 124R, conductive layer 124G, conductive layer 124B, and layer 128, respectively. Therefore, the regions that overlap with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixels. It is preferable to use conductive layers that function as reflective electrodes for conductive layer 124R and conductive layer 126R.

[0590] Layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used for layer 128 as appropriate. In particular, it is preferable that layer 128 be formed using an insulating material, and especially preferable that it be formed using an organic insulating material. For example, an organic insulating material that can be used for the insulating layer 237 described above can be applied to layer 128.

[0591] Figure 39 shows an example in which the upper surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited. The upper surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0592] Furthermore, the height of the upper surface of layer 128 and the height of the upper surface of the conductive layer 124R can be the same or approximately the same, or they can be different. For example, the height of the upper surface of layer 128 can be lower or higher than the height of the upper surface of the conductive layer 124R.

[0593] The end of the conductive layer 126R can be aligned with the end of the conductive layer 124R, or it can cover the side surface of the end of the conductive layer 124R. Preferably, the ends of both the conductive layer 124R and the conductive layer 126R have a tapered shape. Specifically, preferably, the ends of both the conductive layer 124R and the conductive layer 126R have a tapered shape with a taper angle of less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By making the side surface of the pixel electrode tapered, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0594] Since conductive layers 124G and 126G, and conductive layers 124B and 126B are the same as conductive layers 124R and 126R, a detailed explanation is omitted.

[0595] The top and sides of the conductive layer 126R are covered by layer 133R. Similarly, the top and sides of the conductive layer 126G are covered by layer 133G, and the top and sides of the conductive layer 126B are covered by layer 133B. Therefore, the entire regions where conductive layers 126R, 126G, and 126B are provided can be used as light-emitting regions for light-emitting elements 130R, 130G, and 130B, respectively, thereby increasing the aperture ratio of the pixels.

[0596] The upper surfaces and sides of layers 133R, 133G, and 133B are covered by insulating layers 125 and 127, respectively. A common layer 134 is provided on layer 133R, layer 133G, layer 133B, insulating layer 125, and insulating layer 127, and a common electrode 135 is provided on the common layer 134. The common layer 134 and the common electrode 135 are both continuous films provided in common to multiple light-emitting elements.

[0597] In Figure 39, the insulating layer 237 shown in Figure 36, etc., is not provided between the conductive layer 126R and layer 133R. In other words, the display device 50D does not have an insulating layer (also called a partition, bank, spacer, etc.) that is in contact with the pixel electrodes and covers the upper edges of the pixel electrodes. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made. In addition, a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.

[0598] As described above, layers 133R, 133G, and 133B each have an emissive layer. Preferably, layers 133R, 133G, and 133B each have an emissive layer and a carrier transport layer (electron transport layer or hole transport layer) on the emissive layer. Alternatively, preferably layers 133R, 133G, and 133B each have an emissive layer and a carrier block layer (hole block layer or electron block layer) on the emissive layer. Alternatively, preferably layers 133R, 133G, and 133B each have an emissive layer, a carrier block layer on the emissive layer, and a carrier transport layer on the carrier block layer. Since the surfaces of layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, providing one or both of the carrier transport layer and the carrier block layer on the emissive layer suppresses exposure of the emissive layer to the outermost surface and reduces damage to the emissive layer. This can improve the reliability of the light-emitting element.

[0599] The common layer 134 may have, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 134 may have a configuration in which an electron transport layer and an electron injection layer are stacked, or a configuration in which a hole transport layer and a hole injection layer are stacked. The common layer 134 is shared by the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B.

[0600] Each side of layer 133R, layer 133G, and layer 133B is covered by the insulating layer 125. The insulating layer 127 covers each side of layer 133R, layer 133G, and layer 133B via the insulating layer 125.

[0601] The sides (and even a portion of the top surface) of layers 133R, 133G, and 133B are covered by at least one of the insulating layers 125 and 127. This prevents the common layer 134 (or common electrode 135) from coming into contact with the pixel electrode and the sides of layers 133R, 133G, and 133B, thereby suppressing short circuits in the light-emitting element. This improves the reliability of the light-emitting element.

[0602] The insulating layer 125 is preferably in contact with the respective sides of layers 133R, 133G, and 133B. By configuring the insulating layer 125 to be in contact with layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, thereby improving the reliability of the light-emitting element.

[0603] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses of the insulating layer 125. Preferably, the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.

[0604] By providing insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, thereby reducing the large height differences and irregularities on the surface of layers formed on the island-shaped layers (e.g., carrier injection layers, common electrodes, etc.), making it flatter. Consequently, the coverage of carrier injection layers, common electrodes, etc. can be improved.

[0605] The common layer 134 and common electrode 135 are provided on layer 133R, layer 133G, layer 133B, insulating layer 125, and insulating layer 127. Before the insulating layer 125 and insulating layer 127 are provided, a step difference occurs due to the region where the pixel electrode and island-shaped EL layer are provided and the region where the pixel electrode and island-shaped EL layer are not provided (the region between light-emitting elements). In one embodiment of the present invention, the presence of the insulating layer 125 and insulating layer 127 can flatten this step difference and improve the coverage of the common layer 134 and common electrode 135. Therefore, connection failures due to step breaks in the common layer 134 or common electrode 135 can be suppressed. In addition, it is possible to suppress the local thinning of the common electrode 135 due to the step difference and the resulting increase in electrical resistance.

[0606] The upper surface of the insulating layer 127 is preferably flatter. The upper surface of the insulating layer 127 can also be configured to have at least one of a flat surface, a convex surface, and a concave surface. For example, the upper surface of the insulating layer 127 is preferably flat and has a smooth convex surface shape.

[0607] The insulating layer 125 can be an insulating layer having an inorganic material. For example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxidogenic nitride insulating films, and nitride oxide insulating films can be used for the insulating layer 125. Specific examples of these inorganic insulating films are as described above. The insulating layer 125 can be a single-layer structure or a laminated structure. In particular, aluminum oxide is preferred because it has a high selectivity ratio with the EL layer during etching and has the function of protecting the EL layer in the formation of the insulating layer 127, which will be described later. In particular, by applying an inorganic insulating film such as an aluminum oxide film, hafnium oxide film, or silicon oxide film formed by the ALD method to the insulating layer 125, an insulating layer 125 with few pinholes and excellent function in protecting the EL layer can be formed. The insulating layer 125 can also be a laminated structure of a film formed by the ALD method and a film formed by the sputtering method. For example, the insulating layer 125 can be a laminated structure of an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.

[0608] Preferably, the insulating layer 125 functions as a barrier insulating layer against at least one of water and oxygen. Furthermore, preferably, the insulating layer 125 has the function of suppressing the diffusion of at least one of water and oxygen. Also, preferably, the insulating layer 125 has the function of capturing or fixing (also called gettering) at least one of water and oxygen.

[0609] The insulating layer 125 has the function of a barrier insulating layer or a gettering function, thereby suppressing the diffusion of impurities (substances that can induce degradation of the light-emitting elements; typically, at least one of water and oxygen) that could diffuse from the outside to each light-emitting element. This configuration makes it possible to provide a highly reliable light-emitting element and, furthermore, a highly reliable display device.

[0610] Furthermore, it is preferable that the insulating layer 125 has a low impurity concentration. This suppresses the diffusion of impurities from the insulating layer 125 to the EL layer, thereby preventing the deterioration of the EL layer. In addition, by lowering the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration and a sufficiently low carbon concentration, preferably both.

[0611] The insulating layer 127, provided on the insulating layer 125, has the function of flattening the large height differences and irregularities in the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface forming the common electrode 135.

[0612] As the insulating layer 127, an insulating layer having an organic material can be suitably used. Preferably, a photosensitive organic resin is used as the organic material; for example, a photosensitive resin composition containing an acrylic resin is preferred. In this specification, the term "acrylic resin" does not refer only to polymethacrylate esters or methacrylic resins, but may refer to acrylic polymers in a broad sense.

[0613] Furthermore, as the insulating layer 127, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimidoamide resin, silicone resin, si...

Claims

It comprises a first transistor, a second transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer. The first transistor has a first semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fourth insulating layer. The second transistor comprises a second semiconductor layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and a fifth insulating layer. The first insulating layer is provided on the second conductive layer, The third conductive layer is provided on the first insulating layer, The first insulating layer and the third conductive layer have a first opening that reaches the second conductive layer. Within the first opening, the first semiconductor layer is provided in contact with the upper surface of the second conductive layer, the side surface of the first insulating layer, and the side surface of the third conductive layer. The fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer, The fourth conductive layer is provided in contact with the upper surface of the fourth insulating layer such that it has a region that overlaps with the first opening. The second insulating layer is provided on the fourth conductive layer so as to fill the first opening and has a second opening that reaches the third conductive layer. The first conductive layer is provided in contact with the upper surface of the third conductive layer so as to fill the second opening, The fifth conductive layer is provided in contact with the upper surface of the first conductive layer, The third insulating layer is provided on the fifth conductive layer, The sixth conductive layer is provided on the third insulating layer, The third insulating layer and the sixth conductive layer are provided in an island-like manner, having regions that overlap with the fifth conductive layer. The second semiconductor layer is provided in contact with the upper surface of the fifth conductive layer, the side surface of the third insulating layer, and the side surface of the sixth conductive layer, The fifth insulating layer is provided in contact with the upper surface of the second semiconductor layer, The seventh conductive layer is provided in contact with the upper surface of the fifth insulating layer such that it has a region that overlaps with the second semiconductor layer. Semiconductor equipment. 　 In claim 1, The first semiconductor layer and the second semiconductor layer are each an oxide semiconductor layer containing indium. The first insulating layer comprises a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer. The third insulating layer comprises a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer. The sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each contain silicon and nitrogen. The seventh insulating layer and the tenth insulating layer each contain silicon and oxygen, respectively. Semiconductor equipment. 　 In claim 1 or claim 2, The second insulating layer comprises one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. Semiconductor equipment. 　 In claim 1 or claim 2, The first transistor has an eighth conductive layer, The eighth conductive layer is provided between the second conductive layer and the third conductive layer such that it has an area that overlaps with each of the second conductive layer and the third conductive layer. Within the first opening, one surface of the first semiconductor layer faces the fourth conductive layer, and the other surface of the first semiconductor layer faces the eighth conductive layer. Semiconductor equipment. 　 It comprises a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer. The second transistor comprises a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a fifth insulating layer. The first insulating layer is provided on the first conductive layer, The second conductive layer is provided on the first insulating layer, The first insulating layer and the second conductive layer have a first opening that reaches the first conductive layer. Within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer. The fourth insulating layer is provided in contact with the upper surface of the first semiconductor layer, The third conductive layer is provided in contact with the upper surface of the fourth insulating layer such that it has a region that overlaps with the first opening. The second insulating layer is provided on the third conductive layer so as to fill the first opening, The fourth conductive layer is provided in contact with the upper surface of the second insulating layer and a portion of the upper surface of the third conductive layer. The third insulating layer is provided on the fourth conductive layer, The fifth conductive layer is provided on the third insulating layer, The third insulating layer and the fifth conductive layer are provided in an island-like manner, having regions that overlap with the fourth conductive layer. The second semiconductor layer is provided in contact with the upper surface of the fourth conductive layer, the side surface of the third insulating layer, and the side surface of the fifth conductive layer, The fifth insulating layer is provided in contact with the upper surface of the second semiconductor layer, The sixth conductive layer is provided in contact with the upper surface of the fifth insulating layer such that it has a region that overlaps with the second semiconductor layer. Semiconductor equipment. 　 In claim 5, The first semiconductor layer and the second semiconductor layer are each an oxide semiconductor layer containing indium. The first insulating layer comprises a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer. The third insulating layer comprises a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer. The sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each contain silicon and nitrogen. The seventh insulating layer and the tenth insulating layer each contain silicon and oxygen, respectively. Semiconductor equipment. 　 In claim 5 or claim 6, The second insulating layer comprises one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. Semiconductor equipment. 　 In claim 5 or claim 6, The first transistor has a seventh conductive layer, The seventh conductive layer is provided between the first conductive layer and the second conductive layer such that it has an area that overlaps with the first conductive layer and the second conductive layer, Within the first opening, one surface of the first semiconductor layer faces the third conductive layer, and the other surface of the first semiconductor layer faces the seventh conductive layer. Semiconductor equipment. 　 The first conductive layer, the first insulating film, and the first conductive film are formed in this order. A portion of the first insulating film and the first conductive film is removed to form a first opening that reaches the first conductive layer, and a first insulating layer and a second conductive layer are formed. Within the first opening, a first semiconductor layer is formed in contact with the side surface of the second conductive layer, the side surface of the first insulating layer, and the upper surface of the first conductive layer. A second insulating layer is formed in contact with the upper surface of the first semiconductor layer. A third conductive layer is formed in contact with the upper surface of the second insulating layer, having a region that overlaps with the first opening. A third insulating layer is formed on the third conductive layer so as to fill the first opening. A portion of the third insulating layer is removed to form a second opening that reaches the second conductive layer. A fourth conductive layer is formed in contact with the upper surface of the second conductive layer so as to fill the second opening. A fifth conductive layer is formed in contact with the upper surface of the fourth conductive layer. A second insulating film and a second conductive film are formed on the fifth conductive layer in this order. By removing a portion of the second insulating film and the second conductive film, an island-shaped fourth insulating layer and a sixth conductive layer are formed, having a region that overlaps with the fifth conductive layer. A second semiconductor layer is formed in contact with the upper surface of the fifth conductive layer, the side surface of the fourth insulating layer, and the side surface of the sixth conductive layer, respectively. A fifth insulating layer is formed in contact with the upper surface of the second semiconductor layer. A seventh conductive layer is formed in contact with the upper surface of the fifth insulating layer, such that it has a region that overlaps with the second semiconductor layer. Method for manufacturing semiconductor devices.

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