Semiconductor device

Abstract

By forming a gate lead-out part (232) so as to cover a position (P3) that is at the furthest distance within an inner end portion (241a) of a field insulation film (24) from a contact region (20), electrical field concentration when generating a displacement current is reduced, and dV / dt capability is increased.

Description

Semiconductor equipment Cross-references to related applications

[0001] This application is based on Japanese Patent Application No. 2024-206399, filed on 27 November 2024, the contents of which are incorporated herein by reference.

[0002] This disclosure relates to a semiconductor device having a vertical semiconductor element such as a vertical MOSFET, and is particularly suitable when silicon carbide (hereinafter referred to as SiC) is used as the semiconductor material.

[0003] The iC semiconductor device that constitutes a power semiconductor has a configuration that includes a cell region on which semiconductor elements such as MOSFETs are formed, as well as a peripheral region surrounding the cell region, which is equipped with a connecting section where gate wiring and other elements are arranged, and a peripheral voltage-bearing structure. A thin interlayer insulating film is used in the cell region, and a thick interlayer insulating film is used in the wiring region (see Patent Document 1).

[0004] One of the challenges in power semiconductors is the malfunction or destruction of semiconductor devices caused by the demand for low-loss power semiconductors. When a power semiconductor switches, the terminal voltage of the power semiconductor, for example, the drain-source voltage of a MOSFET, changes rapidly during the switching transient or due to its influence. The amount of voltage change over time is called dV / dt, and in recent years, the demand for low-loss power semiconductors has increased dV / dt in order to reduce switching losses, which can lead to malfunction or destruction of semiconductor devices depending on the operating conditions.

[0005] To address this, efforts are being made to improve the tolerance to increases in dV / dt (hereinafter referred to as dV / dt tolerance). For example, a structure has been proposed in which the p-type layer formed at the junction between the breakdown voltage region and the cell region in the semiconductor is made low-resistance, and multiple rows of contact regions connected to the source electrode are formed, with each row of contact regions separated and spaced apart. In addition, a structure has been proposed in which the p-type layer formed at the junction is made low-density and shallow to make the p-type layer high-resistance. There is also a structure that shortens the distance from the displacement current generation point to the hole extraction point.

[0006] Japanese Patent Publication No. 2023-27528

[0007] However, in response to the need for even faster driving of semiconductor devices, the inventors conducted experiments on use at dV / dt > 100kV / μs and found that even with the above-mentioned structure designed to improve withstand voltage, dielectric breakdown occurred at the outer edge of the cell region.

[0008] The purpose of this disclosure is to provide a semiconductor device that can suppress dielectric film breakdown.

[0009] A first aspect of the present disclosure is a semiconductor device having a cell region on which a vertical semiconductor element is formed, and an outer peripheral region surrounding the cell region, the outer peripheral region having an outer peripheral breakdown structure and a connecting portion located between the outer peripheral breakdown structure and the cell region, the semiconductor device having a semiconductor element having a gate electrode layer formed on the cell region, the gate electrode layer including a plurality of stripe-shaped gate electrodes extending in one direction as the longitudinal direction, and an outer peripheral breakdown structure formed on the outer peripheral breakdown structure, the semiconductor substrate having an outer peripheral breakdown structure formed on the semiconductor substrate at the connecting portion, a field insulating film formed surrounding the cell region, a gate lead portion formed on the outer peripheral region from the longitudinal tip of the gate electrode layer and riding up on the field insulating film, and an interlayer insulating film having a first contact hole formed that covers the gate lead portion and the field insulating film while exposing a part of the gate lead portion, The device comprises a gate wiring formed on the interlayer insulating film and connected to the gate lead portion through the first contact hole, wherein a second conductivity type contact region is formed on the semiconductor substrate in the cell region, the interlayer insulating film is also formed on the semiconductor substrate in the cell region, and a second contact hole is formed to expose the contact region, and the gate lead portion covers the inner end of the field insulating film on the cell region side at the position furthest from the contact region.

[0010] In this way, by covering the position of the inner edge of the field insulating film that is furthest from the contact region with the gate lead portion, the electric field concentration when a displacement current is generated is mitigated, making it possible to improve the dV / dt withstand voltage and suppress the breakdown of the insulating film.

[0011] This is a plan view of a semiconductor device according to the first embodiment. This is a perspective cross-sectional view of region RA in Figure 1, viewed from direction II. This is a cross-sectional view along line III-III in Figure 1. This is a cross-sectional view along line IV-IV in Figure 1. This is a diagram showing the top layout of each part provided in the semiconductor device. This is a cross-sectional view explaining the displacement current generated during recovery. This is a diagram showing the layout of a reference semiconductor device and the carrier flow during recovery. This is a diagram showing the layout of a semiconductor device according to the first embodiment and the carrier flow during recovery. This is a diagram showing the gate lead-out section in sections A-A, B-B, and C-C in Figure 7A.

[0012] The embodiments of this disclosure will be described below with reference to the drawings. In each embodiment, including the other embodiments described below, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0013] (First Embodiment) The semiconductor device according to the first embodiment will be described with reference to the drawings. Here, the case in which SiC is used as the semiconductor material will be given as an example, but other compound semiconductors, such as gallium nitride (GaN), gallium oxide (GaO), etc., can also be used.

[0014] As shown in Figure 1, the semiconductor device of this embodiment has a rectangular chip containing a cell region 1 in which the element operates and an outer peripheral region 2 surrounding the cell region 1. Below the cell region 1 in Figure 1, in addition to the gate pad 3a for controlling the semiconductor element provided in the cell region 1, various pads 3 for temperature detection and the like are formed.

[0015] As shown in Figure 2, the outer peripheral region 2 has a configuration that includes a guard ring portion 2a corresponding to the outer peripheral pressure-resistant structure and a connecting portion 2b located inside the guard ring portion 2a, that is, between the cell region 1 and the guard ring portion 2a.

[0016] Cell region 1 is equipped with a trench gate structure n-channel vertical MOSFET as a semiconductor element, as shown in Figures 2 to 4. The details of the vertical MOSFET will be described below, but in this description, one direction in the plane direction of the semiconductor substrate 10 will be referred to as the X-axis direction, the direction intersecting one direction in the plane direction of the semiconductor substrate 10 will be referred to as the Y-axis direction, and the direction intersecting the X-axis direction and the Y-axis direction will be referred to as the Z-axis direction. Here, the X-axis direction, Y-axis direction and Z-axis direction are considered to be mutually orthogonal axes. In addition, the Z-axis direction in this embodiment corresponds to the thickness direction of the semiconductor substrate 10, which will be described later, and also corresponds to the stacking direction of the substrate 11 and the low-density layer 13, which will be described later. The Y-axis direction is, for example, the <11-20> direction.

[0017] The semiconductor substrate 10 is formed by creating the semiconductor portion of a vertical MOSFET. The semiconductor substrate 10 is made of n ＋ The device is constructed by forming various semiconductor layers made of SiC on a substrate 11 of a specific type. In this embodiment, the substrate 11 is, for example, having an off-angle of 0 to 8° with respect to the (0001) Si plane, and having an n-type impurity concentration of 1.0 × 10¹⁶ such as nitrogen and phosphorus. １９ / cm ３ It is said that a substrate with a thickness of approximately 300 μm is used. In the case of a vertical MOSFET, the substrate 11 constitutes the drain region.

[0018] An n-type buffer layer 12 made of SiC is formed on the surface of the substrate 11 as needed. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The n-type impurity concentration of the buffer layer 12 is set to a concentration between that of the substrate 11 and the low-concentration layer 13 described later.

[0019] On the surface of the buffer layer 12, for example, the n-type impurity concentration is 5.0 × 10 １５ ~2.0 x 10 １６ / cm ３ It is said that the n is made of SiC with a thickness of about 7 to 15 μm. －A low-concentration layer 13 of a certain type is formed. The low-concentration layer 13 may have a constant impurity concentration in the Z-axis direction, but it is preferably inclined in the concentration distribution so that the side of the low-concentration layer 13 closer to the substrate 11 has a higher concentration than the side farther from the substrate 11. In this embodiment, the low-concentration layer 13 corresponds to the first impurity region.

[0020] In the surface layer portion of the low-concentration layer 13 in the cell region 1, a JFET layer 14 composed of an n-type layer with a higher impurity concentration than the low-concentration layer 13 and a first deep layer 15 composed of a p-type layer are formed. In this embodiment, the JFET layer 14 and the first deep layer 15 each extend along the X-axis direction and have linear portions arranged alternately and repeatedly in the Y-axis direction. That is, the JFET layer 14 and the first deep layer 15 are each in a stripe shape extending along the X-axis direction when viewed from the Z-axis direction, and they are configured in a layout where they are arranged alternately along the Y-axis direction.

[0021] The JFET layer 14 is of n-type with an impurity concentration higher than that of the low-concentration layer 13, and its thickness is 0.3 to 1.5 μm. In this embodiment, the JFET layer 14 has an n-type impurity concentration of 5.0×10 １６ ~1.0×10 １７ / cm ３ or so. The first deep layer 15 has a p-type impurity concentration of about 2.0×10 １７ ~2.0×10 １８ / cm ３ or so.

[0022] Regarding the first deep layer 15, it may be at the same depth as the JFET layer 14, deeper or shallower than the JFET layer 14. In this embodiment, the first deep layer 15 is formed shallower than the JFET layer 14. That is, the first deep layer 15 is formed such that its bottom is located within the JFET layer 14. Thereby, the spread of the depletion layer into the JFET layer 14 between the first deep layers 15 is suppressed, and the on-resistance is reduced.

[0023] On the other hand, the surface layer of the low-concentration layer 13 in the guard ring portion 2a of the outer peripheral region 2 is provided with multiple p-shaped guard rings 16 as an outer peripheral pressure-resistant structure, surrounding the cell region 1. For example, the upper surface layout of the guard rings 16 is such that, when viewed from the Z-axis direction, it is a square or circular shape with rounded corners.

[0024] Furthermore, a p-type bonding layer 15a is provided on the surface of the low-concentration layer 13 in the bonding portion 2b of the outer peripheral region 2. The bonding layer 15a is positioned so that its inner edge surrounds the cell region 1, and its outer edge extends to the boundary with the guard ring portion 2a. The bonding layer 15a is formed by extending the first deep layer 15 to the bonding portion 2b, and has the same depth and the same p-type impurity concentration as the first deep layer 15.

[0025] In addition, a JFET layer 14 is formed on a part of the connecting portion 2b of the outer peripheral region 2, specifically on the cell region 1 side of the connecting portion 2b, and no JFET layer 14 is formed outside of that, but the JFET layer 14 may be formed further outwards.

[0026] Furthermore, a base layer 18, a source region 19, a contact region 20, and the like are formed on the JFET layer 14 and the first deep layer 15 in the cell region 1.

[0027] The base layer 18 is p-type and is formed on the JFET layer 14 and the first deep layer 15. Therefore, the first deep layer 15 is connected to the base layer 18. The base layer 18 has, for example, a p-type impurity concentration of 5.0 × 10⁻¹⁶. １６ ~2.0 x 10 １９ / cm ３ It is said to have a thickness of approximately 2.0 μm.

[0028] Source region 19 is n ＋ It is a type formed on the surface of the base layer 18 and has a higher impurity concentration than the low-concentration layer 13 and the JFET layer 14. The contact region 20 is p ＋It is a type and is formed on the surface of the base layer 18, and is composed of a higher impurity concentration than the base layer 18. Specifically, the source region 19 is formed to be in contact with the side surface of the trench 21, which will be described later, and the contact region 20 is formed on the opposite side of the trench 21, which will be described later, with the source region 19 in between. In this embodiment, the source region 19 has an n-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0 × 10⁻⁶. １８ / cm ３ It is said that the thickness is about 0.3 μm. The contact region 20 has a p-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0 × 10 ２１ / cm ３ It is said that the thickness is approximately 0.3 μm. In this embodiment, the source region 19 corresponds to the second impurity region.

[0029] In the connecting portion 2b of the outer peripheral region 2, the low-concentration layer 13, JFET layer 14, first deep layer 15, and the base layer 18, contact region 20, and surface portion of the low-concentration layer 13 are formed on the connecting layer 15a. On the inner edge side of the connecting portion 2b, the base layer 18 and contact region 20 are formed on the connecting layer 15a and extend from the cell region 1. On the outer edge side of the connecting portion 2b, the base layer 18 and contact region 20 are not formed, and the surface portion of the low-concentration layer 13 is formed. In other words, in this embodiment, the base layer 18 and contact region 20 in the outer peripheral region 2 extend from the cell region 1 and are formed up to a certain point in the connecting portion 2b, but are not formed in the connecting portion 2b and guard ring portion 2a further out. Furthermore, from the boundary between the cell region 1 and the outer peripheral region 2 up to the middle of the connecting portion 2b, the entire surface of the connecting portion 2b is designated as the contact region 20, and beyond that, the entire surface of both the connecting portion 2b and the guard ring portion 2a is designated as the low-concentration layer 13.

[0030] As described above, in the present embodiment, the semiconductor substrate 10 is configured to include a substrate 11, a buffer layer 12, a low-concentration layer 13, a JFET layer 14, a first deep layer 15, a base layer 18, a source region 19, a contact region 20, and the like. Further, in the present embodiment, on the inner edge side of the cell region 1 or the connecting portion 2b, one surface 10a of the semiconductor substrate 10 is formed of the source region 19, the contact region 20, etc., and the other surface 10b of the semiconductor substrate 10 is formed of the substrate 11.

[0031] Note that the JFET layer 14, the first deep layer 15, the connecting layer 15a, the guard ring 16, the base layer 18, the source region 19, and the contact region 20 are formed of ion implantation layers formed by ion implantation in the present embodiment.

[0032] Further, in the cell region 1, a trench 21 penetrating the source region 19, the base layer 18, etc. of the semiconductor substrate 10 and reaching the JFET layer 14 and the first deep layer 15 from the one surface 10a side is formed. The trench 21 corresponds to a gate trench, and the bottom surface is set to a depth located within the JFET layer 14 and the first deep layer 15, and the width is, for example, 0.4 to 0.8 μm.

[0033] Further, a plurality of trenches 21 are extended along the Y-axis direction with the Y-axis direction as the longitudinal direction, and are formed in a stripe shape by being arranged at equal intervals with an interval B1 in the X-axis direction as shown in FIG. 3. That is, in the present embodiment, the trenches 21 are formed such that the longitudinal direction intersects the longitudinal direction of the first deep layer 15. In the present embodiment, as shown in FIG. 2, the tips of adjacent ones of the trenches 21 arranged in a stripe shape are connected in an arc shape, but the trenches 21 may be constituted only by the stripe-shaped portions.

[0034] At the bottom of the trench 21, a second deep layer 30 serving as an electric field relaxation layer is formed so as to contact the bottom surface of the trench 21. In the present embodiment, the second deep layer 30 is composed of a p-type layer having a lower impurity concentration than that of the first deep layer 15 and is electrically connected to the base layer 18 via the first deep layer 15. Specifically, the second deep layer 30 is formed along the longitudinal direction of the trench 21. That is, the second deep layer 30 extends along the Y-axis direction intersecting the first deep layer 15. Further, the second deep layer 30 of the present embodiment is formed so as to penetrate the JFET layer 14 and the first deep layer 15 and reach the low-concentration layer 13 at the bottom surface.

[0035] By forming the second deep layer 30 along the bottom surface of the trench 21, it is possible to suppress the intrusion of an electric field into the gate insulating film 22, which will be described later, located at the bottom of the trench 21, and suppress dielectric breakdown. Further, by forming the second deep layer 30 so as to contact the bottom surface of the trench 21, it is possible to reduce the capacitance between the gate electrode 231 and the lower electrode 29, which will be described later, that is, the feedback capacitance, and improve the switching speed. Furthermore, since the second deep layer 30 is formed so as to penetrate the JFET layer 14 and the first deep layer 15 and reach the low-concentration layer 13 at the bottom surface, the creeping up of the electric field to the JFET layer 14 disposed between the second deep layers 30 is suppressed, and the breakdown voltage can be improved. In addition, since breakdown is likely to occur in the second deep layer 30 that protrudes downward when an overvoltage is applied, breakdown is likely to occur in the cell region 1, and the avalanche withstand voltage can be improved.

[0036] Furthermore, a gate insulating film 22 is formed on one surface 10a of the semiconductor substrate 10, including the inner wall surface of the trench 21. A gate electrode layer 23 is formed on the gate insulating film 22, with the portion located within the trench 21 forming the gate electrode 231, and the portion extending outside the trench 21 forming the gate lead-out portion 232. The trench 21, the gate insulating film 22, and the gate electrode 231 constitute a trench gate structure, and a gate voltage can be applied to the gate electrode 231 through the gate lead-out portion 232. The gate insulating film 22 is formed by thermal oxidation of one surface 10a of the semiconductor substrate 10, including the inner wall surface of the trench 21, or by depositing an insulating film by CVD (chemical vapor deposition). For example, the thickness of the gate insulating film 22 is approximately 100 nm on both the side and bottom sides of the trench 21. The gate electrode layer 23 is made of doped poly-Si or the like, which is doped with impurities, and extends to the junction 2b. The detailed structure of this gate electrode layer 23, including its layout, will be described later.

[0037] In cell region 1, a contact hole 22a is formed in the gate insulating film 22, exposing the source region 19 and the contact region 20. In Figure 2, the portion above the source region 19 and the contact region 20, that is, above one surface 10a of the semiconductor substrate 10, is omitted from the illustration.

[0038] As shown in Figures 3 and 4, a field insulating film 24 is formed on one surface 10a of the semiconductor substrate 10 so as to surround the outer edge of the cell region 1. The field insulating film 24 is composed of, for example, an oxide film and is formed by a method such as CVD, and is thicker than the gate insulating film 22. The detailed structure of this field insulating film 24, including its layout, will be described later.

[0039] Furthermore, an interlayer insulating film 25 is formed to cover the gate electrode layer 23, the gate insulating film 22, and the field insulating film 24, etc. The interlayer insulating film 25 is made of BPSG (abbreviation for Borophosphosilicate Glass) or the like and is thicker than the gate insulating film 22.

[0040] As shown in Figure 3, the interlayer insulating film 25 has contact holes 251 formed in the cell region 1 that expose the source region 19 and the contact region 20 together with the contact hole 22a. Furthermore, as shown in Figure 4, the interlayer insulating film 25 has contact holes 252 formed that expose the portion of the gate electrode layer 23 that extends to the connecting portion 2b. Among the contact holes 251, the contact hole 251a located outside the multiple gate electrodes 231 is wider than the contact hole 251b located between the gate electrodes 231. This contact hole 251a is for extracting carriers moving from the outer peripheral region 2, and the contact region 20 is exposed. Hereinafter, the portion of this contact region 20 located outside the multiple gate electrodes 231 and exposed by the contact hole 251a will be called the outermost contact 20a. Also, the portion of the contact region 20 located inside the outermost contact 20a and exposed by the contact hole 251b will be called the inner contact 20b.

[0041] An upper electrode 26 is formed on the interlayer insulating film 25, which is electrically connected to the source region 19 and the contact region 20 through contact holes 22a and 251. The upper electrode 26 is designed to allow electrical connection to the outside. In this embodiment, the upper electrode 26 corresponds to the first electrode. In addition, a gate wiring 27 is formed on the interlayer insulating film 25, which is electrically connected to the gate electrode layer 23 through contact hole 252. The detailed structure of this gate wiring 27, including its layout, will be described later.

[0042] Furthermore, a protective film 28 made of polyimide or the like is formed to cover the connecting portion 2b and the guard ring portion 2a. In this embodiment, the protective film 28 is formed from the outer peripheral region 2 to the outer edge of the cell region 1 in order to protect the wiring and suppress the occurrence of creepage discharge between the upper electrode 26 and the lower electrode 29, which will be described later. Specifically, in the cell region 1, the protective film 28 is formed to cover the portion of the upper electrode 26 on the outer peripheral region 2 side while exposing the portion of the upper electrode 26 on the inner edge side.

[0043] A lower electrode 29 is formed on the other side 10b of the semiconductor substrate 10, which is electrically connected to the substrate 11. In this embodiment, the lower electrode 29 corresponds to the second electrode.

[0044] This structure constitutes a semiconductor device in which a trench gate structure MOSFET, which is an inverted type of n-channel MOSFET according to this embodiment, is formed.

[0045] The above describes the configuration of the semiconductor device in this embodiment. In this embodiment, n － type, n type, n ＋ The type corresponds to the first conductivity type, p-type, p ＋ The type corresponds to the second conductivity type. Next, the detailed structure, including the layout of the field insulating film 24, the gate lead portion 232 of the gate gate electrode layer 23, and the gate wiring 27, will be described.

[0046] Figure 5 shows the top layout of the field insulating film 24, gate lead-out portion 232, and gate wiring 27. For clarity, the field insulating film 24 and gate electrode layer 23 are shown with hatching.

[0047] The field insulating film 24 has an outer edge portion 241, a pad lower portion 242, and a central portion 243. The outer edge portion 241 is a portion formed along the outer edge of the chip constituting the semiconductor device. The outer edge portion 241 has an inner end portion 241a that is on the cell region 1 side and an outer end portion 241b that is on the opposite side of the cell region 1 as its ends. A stepped portion is formed by the field insulating film 24 at these inner end portion 241a and outer end portion 241b, and the position of the stepped portion at the inner end portion 241a in particular is a place where the insulating film is prone to breaking. More specifically, the inner end portion 241a has a first portion 241c that extends in a direction intersecting the longitudinal direction of the gate electrode 231, a second portion 241d that extends along the longitudinal direction of the gate electrode 231, and a corner portion 241e that connects the first portion 241c and the second portion 241d. The first portion 241c is arranged at a predetermined distance from the tips of a plurality of gate electrodes 231. The second portion 241d is positioned at a predetermined distance from the outermost of the multiple gate electrodes 231. The corner portion 241e is rounded in an arc shape.

[0048] The lower part of the pad 242 is the portion formed below each type of pad 3. The lower part of the pad 242 is rectangular in shape, with two opposing short sides 242a and 242b and one long side 242c forming stepped ends. The part of the lower part of the pad 242 opposite to the long side 242c is connected to the outer edge 241.

[0049] The central portion 243 is a part that extends linearly in the center of the cell region 1 and is formed to connect with the outer edge portion 241 and the long side 242c of the lower part of the pad 242. The ends 243a and 243b on both sides of the central portion 243 are also stepped portions.

[0050] As shown in Figure 1, the gate wiring 27 has a line 271 extending vertically on the left and right sides of Figure 1, a line 272 overlapping with the central portion 243, and a line 273 extending horizontally at the bottom of Figure 5. Line 271 is formed to connect all the corresponding positions to each end of the multiple gate electrodes 231. Line 272 is formed to connect the longitudinal centers of the multiple gate electrodes 231 and is connected to the gate pad 3a. Line 273 is formed outside the cell region 1 beyond each pad 3, as the portion connecting line 271 to the gate pad 3a. Each of these lines 271 to 273 is formed on the corresponding portion of the field insulating film 24 and is connected to the gate lead portion 232 through contact holes 252 formed in the field insulating film 24.

[0051] Although not shown in Figure 5, the gate electrode 231 portion of the gate electrode layer 23 has the same layout as the trench 21, with multiple gate electrodes extending along the Y-axis direction, and arranged at equal intervals in the X-axis direction to form a stripe pattern.

[0052] The gate lead-out portion 232 of the gate electrode layer 23 is led out from each tip of the multiple gate electrodes 231 to the outside of the gate electrodes 231 and is formed to ride on the gate insulating film 22 and the field insulating film 24, as shown in Figure 4. As shown in Figure 5, the gate lead-out portion 232 is formed to cover the inner end 241a of the outer edge portion 241, the ends 243a and 243b on both sides of the central portion 243, and the two short sides 242a and 242b of the lower part of the pad 242 located on the left and right sides in Figure 5. Note that the gate wiring 27 is not formed on the portion of the outer edge portion 241 that extends to the left and right on the upper side of Figure 5. In other words, the gate wiring 27 is not arranged on the gate lead-out portion 232 that covers the second portion 241d of the outer edge portion 241 of the field insulating film 24 that is located on the opposite side of the pad 3. For this reason, although the gate wiring 27 is not arranged on the upper side of Figure 5, the gate electrode layer 23 is formed to ride on the outer edge portion 241. By not arranging the gate wiring 27 in this way, it is possible to increase the active rate for the element to operate as a cell region 1.

[0053] In a semiconductor device in which a vertical semiconductor element is formed as in this embodiment, a step exists between the portion where the field insulating film 24 is formed and the portion where it is not formed. Experiments revealed that insulator film breakdown occurs with increasing dV / dt in the portion of the step that is composed of the inner end portion 241a, particularly near the corner portion 241e located outside the area in the cell region 1 where multiple trenches 21 are arranged.

[0054] Therefore, in addition to the gate lead portion 232 being formed at the location corresponding to the tip of each gate electrode 231, it is also formed outside the range in which the multiple gate electrodes 231 are arranged in the direction of the arrangement of the multiple gate electrodes 231. Specifically, the gate lead portion 232 is formed to cover not only the first portion 241c but also the corner portion 241e. Furthermore, in this embodiment, the gate lead portion 232 is also placed in the second portion 241d of the outer edge portion 241 that is along the longitudinal direction of the multiple trenches 21, so that the periphery of the cell region 1 is surrounded by the gate lead portion 232.

[0055] Furthermore, in the X-axis direction, in the cell region 1 other than the portion where the lower pad 242 is located, that is, the portion above the lower pad 242 in Figure 5, the trench 21 and gate electrode 231 are formed up to a predetermined distance from the inner end 241a, including the lower part of the central portion 243. On the other hand, in the X-axis direction, in the portion where the lower pad 242 is located, the trench 21 and gate electrode 231 are not formed below the lower pad 242, but are formed between the inner end 241a and the lower pad 242, up to a predetermined distance from both. For this reason, the gate lead-out portion 232 is formed over the two sides 242a and 242b of the lower pad 242 located on the left and right sides in Figure 5.

[0056] Although the gate lead-out portion 232 is not formed on the long side 242c of the lower part 242 of the pad so as to ride on the field insulating film 24, it may be formed there as well.

[0057] [Operation of the semiconductor device] Next, the operation of the semiconductor device of this embodiment will be described. First, in the off state of the semiconductor device, before a gate voltage is applied to the gate electrode 231, no inversion layer is formed in the base layer 18. Therefore, even if a positive voltage, for example 1600V, is applied to the lower electrode 29, electrons do not flow from the source region 19 into the base layer 18, and no current flows between the upper electrode 26 and the lower electrode 29.

[0058] Furthermore, before a gate voltage is applied to the gate electrode 231, an electric field is present between the drain and gate, which can cause electric field concentration at the bottom of the gate insulating film 22. However, in the semiconductor device described above, the first deep layer 15 and the JFET layer 14 are located deeper than the trench 21. As a result, the depletion layer formed between the first deep layer 15 and the JFET layer 14 suppresses the rise of equipotential lines due to the influence of the drain voltage, making it difficult for high electric fields to penetrate the gate insulating film 22. Moreover, since a second deep layer 30, which acts as an electric field relaxation layer, is provided at the bottom of the trench 21, it becomes even more difficult for high electric fields to penetrate the gate insulating film 22. Therefore, the destruction of the gate insulating film 22 can be suppressed.

[0059] Furthermore, when a predetermined gate voltage is applied to the gate electrode 231, a channel is formed on the surface of the base layer 18 that is in contact with the trench 21. As a result, electrons injected from the upper electrode 26 pass through the channel formed in the base layer 18 from the source region 19, then through the JFET layer 14 to the low-concentration layer 13, and then through the substrate 11, which acts as the drain layer, to the lower electrode 29. This causes a current to flow between the upper electrode 26 and the lower electrode 29, turning on the semiconductor device. In this embodiment, since electrons that have passed through the channel pass through the JFET layer 14 and the low-concentration layer 13 to the substrate 11, it can be said that a drift layer 17 having the JFET layer 14 and the low-concentration layer 13 is configured.

[0060] Here, the gate lead portion 232 is arranged in the above-described layout relative to the field insulating film 24. This configuration improves the switching withstand capability when turning the vertical MOSFET on and off based on the application of a gate voltage. This switching withstand capability will be explained below.

[0061] Figure 6 shows the displacement current A1 in a cross-section along the Y-axis passing through the outermost contact 20a.

[0062] During recovery when a vertical MOSFET is high-speed switched, a displacement current A1 flows as shown by the dashed arrow in Figure 6. Specifically, in the outer peripheral region 2, the displacement current A1 proceeds from the lower electrode 29 through the substrate 11, the low-concentration layer 13, and the JFET layer 14 to the bridging layer 15a, and then to the base layer 18 and the contact region 20. Then, within the contact region 20, the displacement current A1 flows to the upper electrode 26 while moving in the planar direction of the semiconductor substrate 10. The displacement current A1 at this time is proportional to the high voltage dV / dt generated during switching. Furthermore, the higher the impurity concentration of the p-type and n-type layers constituting the pn junction in the outer peripheral region 2, the larger the source-drain capacitance becomes, thus increasing dV / dt and thus the displacement current A1.

[0063] The generation of dV / dt causes a displacement current A1 to flow through the pn junction capacitance between the drain and base of the vertical MOSFET, and a voltage drop occurs due to this displacement current A1 and the internal resistance of the base. When this voltage becomes large, and the base-emitter voltage of the parasitic npn transistor formed by the drain, base, and source increases, the parasitic npn transistor turns on, a latch-up phenomenon occurs, and the device is destroyed.

[0064] To solve this, it is necessary to increase the dV / dt withstand capability. For example, this can be achieved by modifying the concentration of the base layer 18 or the trench gate structure, or by reducing the concentration of p-type impurities in the connecting portion 2b. It is also possible to improve the dV / dt withstand capability by shortening the distance from the point where the displacement current A1 is generated to the outermost contact 20a, which becomes the hole extraction portion.

[0065] However, when high-speed switching experiments were conducted on the semiconductor device with the reference structure shown in Figure 7A to address the need for even higher speed driving, it was found that dielectric film breakdown occurred in the semiconductor device with the reference structure.

[0066] In the reference semiconductor device, compared to the semiconductor device of this embodiment, the gate lead portion 232 is formed only in the range corresponding to the tip positions of the multiple trenches 21, and is not formed outside that range. Also, in the reference semiconductor device, the distance to the outermost contact 20a is longer compared to the semiconductor device of this embodiment.

[0067] First, experiments were conducted on the semiconductor device of the reference structure for use at dV / dt > 100kV / μs. As a result, electric field concentration occurred in the path of the displacement current A1 due to a step in the field insulating film 24, specifically the inner end 241a on the cell region 1 side of the field insulating film 24, which sometimes caused the gate insulating film 22 and the field insulating film 24 to break down. The locations where dielectric breakdown occurred had characteristic features: (i) position P1 in Figure 7A, that is, a location where the distance from the step to the outermost contact 20a is large, and (ii) position P2, that is, a location where the gate lead-out portion 232 that extends over the step is interrupted.

[0068] Regarding (i), this can be solved by shortening the distance from the stepped portion to the outermost contact 20a, but there are limitations due to process tolerances and reliability. Process tolerances include, for example, mask misalignment, and the layout design must take into account a margin that takes mask misalignment into account. Also, if the overlap between the gate electrode 231 embedded in the trench 21 of the gate electrode layer 23 and the gate lead portion 232 at the tip of the trench 21 becomes too small, the gate current per unit area flowing through the overlap portion of the two will increase. This will cause a phenomenon similar to electromigration, leading to fracture and compromising reliability. Therefore, it is not possible to shorten the distance from the stepped portion to the outermost contact 20a to an infinitesimally small amount.

[0069] Regarding (ii), when we actually performed CAE (Computer-Aided Engineering) to check the electric field distribution, we confirmed that an electric field concentration occurred at position P2 where the gate lead-out section 232 over the stepped section is interrupted. This is presumed to be because a shape anomaly occurs in the part over the stepped section where the gate lead-out section 232 is interrupted in the arrangement direction of the multiple trenches 21, causing an electric field concentration at that location. States A, B, and C in Figure 8 show the A-A, B-B, and C-C cross sections in Figure 7A. As in state A in Figure 8, the shape of the gate lead-out section 232 is stable even at the stepped section at positions corresponding to each tip of the multiple gate electrodes 231, but as in state B, the shape at the stepped section is unstable at the terminal position of the gate lead-out section 232. For this reason, it is thought that an electric field concentration occurs at position P2.

[0070] Therefore, in this embodiment, as shown in Figure 7B, the range of the gate pull-out portion 232 that extends over the stepped portion is widened, and the gate pull-out portion 232 is formed outside the range in which the multiple trenches 21 are arranged in the direction of the arrangement of the multiple trenches 21.

[0071] The holes H and arrows shown in Figures 7A and 7B indicate the recovery operation at the corners of the cell region 1, specifically the right corner of the chip in Figure 1. During recovery, a displacement current A1 is generated when the remaining carriers, the holes H, escape through the contact region 20 to the upper electrode 26. Between each trench 21, the holes escape from the contact region 20 formed between them, but outside the cell region 1 in the direction of arrangement of the multiple trenches 21, the holes H escape through the outermost contact 20a.

[0072] In this case, in the reference structure, a strong electric field is applied at position P1, which is the furthest distance from the outermost contact 20a on the inner end 241a of the field insulating film 24, and in this case, at the bent portion located at the chip corner of the field insulating film 24, which can cause the insulating film to break. However, in reality, the insulating film breakdown occurred at position P2, which is where the gate lead portion 232 is interrupted and intersects with the inner end 241a. This position P2 is a place where shape abnormalities of the gate lead portion 232 are likely to occur, and it is thought that this caused electric field concentration, leading to the insulating film breakdown.

[0073] In contrast, in the semiconductor device of this embodiment, the gate lead portion 232 is formed up to the corner portion 241e, which is a bent portion located at the chip corner, within the inner end portion 241a of the field insulating film 24. Therefore, since the inner end portion 241a, which is farther from the outermost contact 20a, can be covered by the gate lead portion 232, the occurrence of shape abnormalities in the gate lead portion 232 within that range can be suppressed. Consequently, the electric field concentration when the displacement current A1 is generated is mitigated. This makes it possible to improve the dV / dt withstand voltage and suppress the breakdown of the insulating film.

[0074] In addition, a gate lead-out portion 232 is also provided in the second portion 241d of the inner end portion 241a of the outer edge portion 241, that is, the portion located in the upper part of the plane of the paper in Figure 5. As a result, electric field concentration can be mitigated even in the portion of the outer edge portion 241 that is along the longitudinal direction of the multiple trenches 21, making it possible to further suppress the breakdown of the insulating film.

[0075] In this embodiment of the semiconductor device, the inner contact 20b of the contact region 20 is formed linearly between a plurality of trenches 21. In Figure 7B, the tips of the outermost contact 20a and the inner contact 20b are semicircular, and the corner portion 241e, which is the bending point of the inner end portion 241a of the field insulating film 24, is designed with an arc corresponding to the arc of the tip of the outermost contact 20a. In other words, the center of the arc of the bending point of the inner end portion 241a is aligned with the semicircular portion of the tip of the outermost contact 20a. Therefore, the position P3, which is the longest distance between the outermost contact 20a and the inner end portion 241a, is between the outermost contact 20a and the inner contact 20b that is closest to the outermost contact 20a. At least this position P1 is covered by the gate lead portion 232, so that electric field concentration can be mitigated and insulating film breakdown can be suppressed.

[0076] As described above, in the semiconductor device of this embodiment, the gate lead portion 232 is formed to cover the position P3, which is the furthest distance from the contact region 20, on the inner end 241a of the field insulating film 24. Therefore, the electric field concentration when the displacement current A1 is generated is mitigated, the dV / dt withstand capability is improved, and the breakdown of the insulating film can be suppressed. Consequently, the switching withstand capability can be improved, and the switching speed of the vertical MOSFET can be increased. For example, by forming the gate lead portion 232 on the corner portion 241e located at the chip corner of the inner end 241a of the field insulating film 24, the position P3, which is the furthest distance from the contact region 20, can be covered.

[0077] Furthermore, for semiconductor devices with this structure, only the mask used when forming the gate electrode layer 23 needs to be different from that of the reference structure. This makes it possible to simplify the manufacturing process.

[0078] (Other Embodiments) While this disclosure has been described in accordance with the embodiments described above, it is not limited to those embodiments and includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, are also within the scope and concept of this disclosure.

[0079] For example, the layout of the portion of the gate lead-out portion 232 that rides onto the field insulating film 24 may be changed from the above embodiment. For example, although the gate lead-out portion 232 is formed to cover the inner end portion 241a of the field insulating film 24, the step portion caused by the field insulating film 24 also occurs in other parts, such as the outer end portion 241b and the long side portion 242c of the lower part of the pad 242. Although these locations are not places where insulating film breakdown is likely to occur, it is possible for it to occur, so by arranging the gate lead-out portion 232 to cover at least one of these locations, it is possible to further suppress insulating film breakdown. For this reason, the gate lead-out portion 232 may cover only a part of the end of the field insulating film 24, or it may cover the entire end.

[0080] Furthermore, in the above embodiment, the design aligns the arc of the tip of the outermost contact 20a with the arc of the corner portion 241e. As a result, the position P3 that is the furthest distance from the contact area 20 on the inner end portion 241a is not at the corner portion 241e, but depending on the design, the corner portion 241e may be the furthest distance. In that case as well, by forming the gate lead-out portion 232 up to the corner portion 241e, the stepped portion at the furthest distance position P3 can be covered by the gate lead-out portion 232.

[0081] Furthermore, although a MOSFET was used as an example in the above embodiment, other semiconductor elements such as IGBTs (isolated gate bipolar transistors) or diodes may also be used. Also, although a trench-type switching element with a trench gate structure was given as an example of a vertical semiconductor element in the above embodiment, a planar type may also be used. In other words, any switching element is acceptable as long as it has a gate lead portion 232 that extends over the field insulating film 24 so as to allow the gate electrode 231 to be formed on the gate insulating film 22 in contact with the base layer 18. In that case, the portion of the gate electrode layer 23 that is arranged in a stripe shape used for transistor operation becomes the gate electrode 231, and the portion that extends from there becomes the gate lead portion 232.

[0082] Furthermore, in the above embodiment, the outer peripheral region 2 does not have a contact region 20 that contacts the upper electrode 26 outside the gate wiring 27, but it is also possible to have a structure that includes such a contact region. However, if the contact region 20 is provided outside the gate wiring 27, the area of ​​the cell region 1 will decrease when considering the same chip area. Therefore, it is more advantageous for increasing the area of ​​the cell region 1 to provide the contact region 20 only on the cell region 1 side of the gate wiring 27.

[0083] (Perspective of this disclosure) The above disclosure can be understood, for example, from the following perspectives. [First perspective] A semiconductor device having a cell region (1) on which a vertical semiconductor element is formed, and an outer peripheral region (2) surrounding the cell region, which is provided with an outer peripheral breakdown structure (2a) and a connecting portion (2b) located between the outer peripheral breakdown structure and the cell region, the semiconductor device having a substrate (11) made of silicon carbide of a first conductivity type or a second conductivity type, and a first impurity region (13) of a first conductivity type formed on the substrate and having a lower impurity concentration than the substrate, wherein the semiconductor element has a gate electrode layer (23) formed on the cell region, which includes a plurality of stripe-shaped gate electrodes (231) extending in one direction as the longitudinal direction, and an outer peripheral breakdown structure (16) formed on the outer peripheral breakdown structure, and on the semiconductor substrate in the connecting portion, a field insulating film (24) formed surrounding the cell region, A semiconductor device comprising: a portion of the gate electrode layer that is drawn out from the longitudinal tip of the gate electrode to the outer peripheral region and formed to ride up on the field insulating film; an interlayer insulating film (25) having a first contact hole (252) that covers the gate draw-out portion and the field insulating film while exposing a part of the gate draw-out portion; and a gate wiring (27) formed on the interlayer insulating film and connected to the gate draw-out portion through the first contact hole, wherein a second conductivity type contact region (20) is formed on the semiconductor substrate in the cell region, the interlayer insulating film is also formed on the semiconductor substrate in the cell region, and a second contact hole (251) that exposes the contact region is formed, and the gate draw-out portion covers the inner end (241a) of the field insulating film, which is the end on the cell region side, at the position (P3) furthest from the contact region.[Second viewpoint] The semiconductor device according to the first viewpoint, wherein the inner end includes a first portion (241c) extending in a direction intersecting the longitudinal direction of the gate electrode, a second portion (241d) extending along the longitudinal direction of the gate electrode, and a corner portion (241e) connecting the first portion and the second portion, and the gate lead portion covers the first portion and the corner portion of the inner end of the field insulating film. [Third viewpoint] Of the outer peripheral region, a pad (3) including a gate pad (3a) connected to the gate wiring is arranged outside the plurality of gate electrodes in the arrangement direction of the plurality of gate electrodes, the field insulating film has a pad lower portion (242) located below the pad, and the second portion includes one second portion connected to the pad lower portion and another second portion located on the opposite side of the plurality of gate electrodes from the one second portion, and the gate lead portion also covers the other second portion. [Fourth viewpoint] The semiconductor device according to the third viewpoint, wherein the gate wiring is not located on the portion of the gate lead that covers the other second portion. [Fifth viewpoint] The lower part of the pad has, in addition to the portion connected to the one second portion, two sides (242a, 242b) that intersect the longitudinal direction of the gate electrode, and a side (242c) located on the opposite side of the two sides from the portion connected to the one second portion, and the gate lead also covers the two sides, according to the third or fourth viewpoint.[Sixth Perspective] The cell region comprises a semiconductor element having: a base layer (18) of a second conductivity type formed on the first impurity region; a gate insulating film (22) formed in contact with the base layer; a gate electrode (231) formed on the gate insulating film; a second impurity region (19) of a first conductivity type formed on the surface of the base layer and having a higher impurity concentration than the first impurity region; a first electrode (26) formed on the interlayer insulating film and electrically connected to the second impurity region and the contact region through the second contact hole; and a second electrode (29) arranged on the back side of the substrate and electrically connected to the substrate. The contact region has a portion arranged between the plurality of gate electrodes, as well as an outermost contact (20a) arranged outside the plurality of gate electrodes in the arrangement direction of the plurality of gate electrodes, and the outermost contact is formed along the longitudinal direction and has a semicircular tip. A semiconductor device according to any one of the second to fifth aspects, wherein the corner of the field insulating film is an arc whose center coincides with the arc of the tip of the outermost contact. [Seventh aspect] A semiconductor device according to any one of the second to sixth aspects, wherein the semiconductor element is a switching element, and when the semiconductor element recovers from switching, a displacement current (A1) flows as carriers present in the outer peripheral region pass through the base layer and the outermost contact in the connecting portion to the first electrode side. [Eighth aspect] A semiconductor device according to any one of the first to seventh aspects, wherein the contact region is formed only on the cell region side of the gate wiring. [Ninth aspect] A semiconductor device according to any one of the first to eighth aspects, wherein the gate lead portion covers the entire edge of the field insulating film.

Claims

1. A semiconductor device comprising: a cell region (1) on which a vertical semiconductor element is formed; and an outer peripheral region (2) surrounding the cell region, which is provided with an outer peripheral breakdown structure (2a) and a connecting portion (2b) located between the outer peripheral breakdown structure and the cell region, wherein the semiconductor device comprises: a substrate (11) made of silicon carbide of a first conductivity type or a second conductivity type; and a first impurity region (13) of a first conductivity type formed on the substrate and having a lower impurity concentration than the substrate, wherein the semiconductor element has a gate electrode layer (23) formed on the cell region, which includes a plurality of stripe-shaped gate electrodes (231) extending in one direction as the longitudinal direction, and an outer peripheral breakdown structure (16) formed on the outer peripheral breakdown structure, wherein on the semiconductor substrate at the connecting portion, there is a field insulating film (24) formed surrounding the cell region, A semiconductor device comprising: a portion of the gate electrode layer that is drawn out from the longitudinal tip of the gate electrode to the outer peripheral region and formed to ride up on the field insulating film; an interlayer insulating film (25) having a first contact hole (252) that covers the gate draw-out portion and the field insulating film while exposing a part of the gate draw-out portion; and a gate wiring (27) formed on the interlayer insulating film and connected to the gate draw-out portion through the first contact hole, wherein a second conductivity type contact region (20) is formed on the semiconductor substrate in the cell region, the interlayer insulating film is also formed on the semiconductor substrate in the cell region, and a second contact hole (251) that exposes the contact region is formed, and the gate draw-out portion covers the inner end (241a) of the field insulating film, which is the end on the cell region side, at the position (P3) furthest from the contact region.

2. The semiconductor device according to claim 1, wherein the inner end includes a first portion (241c) extending in a direction intersecting the longitudinal direction of the gate electrode, a second portion (241d) extending along the longitudinal direction of the gate electrode, and a corner portion (241e) connecting the first portion and the second portion, and the gate lead portion covers the first portion and the corner portion of the inner end of the field insulating film.

3. In the outer peripheral region, a pad (3) including a gate pad (3a) connected to the gate wiring is arranged outside the plurality of gate electrodes in the direction of arrangement of the plurality of gate electrodes, the field insulating film has a pad lower portion (242) located below the pad, and the second portion has one second portion connected to the pad lower portion and the other second portion located on the opposite side of the plurality of gate electrodes from the one second portion, and the gate lead portion also covers the other second portion, the semiconductor device according to claim 2.

4. The semiconductor device according to claim 3, wherein the gate wiring is not arranged on the portion of the gate lead-out portion that covers the other second portion.

5. The lower part of the pad has, in addition to the portion connected to the one second portion, two sides (242a, 242b) that intersect the longitudinal direction of the gate electrode, and a side (242c) that is positioned on the opposite side of the two sides from the portion connected to the one second portion, and the gate lead-out portion covers the two sides as well, the semiconductor device according to claim 3.

6. The cell region comprises a semiconductor element having: a base layer (18) of a second conductivity type formed on the first impurity region; a gate insulating film (22) formed in contact with the base layer; a gate electrode (231) formed on the gate insulating film; a second impurity region (19) of a first conductivity type formed on the surface of the base layer and having a higher impurity concentration than the first impurity region; a first electrode (26) formed on the interlayer insulating film and electrically connected to the second impurity region and the contact region through the second contact hole; and a second electrode (29) arranged on the back side of the substrate and electrically connected to the substrate. The contact region has a portion arranged between the plurality of gate electrodes, as well as an outermost contact (20a) arranged outside the plurality of gate electrodes in the arrangement direction of the plurality of gate electrodes, and the outermost contact is formed along the longitudinal direction and has a semicircular tip. The semiconductor device according to any one of claims 2 to 5, wherein the corner of the field insulating film is an arc whose center coincides with the arc of the tip of the outermost contact.

7. The semiconductor device according to claim 6, wherein the semiconductor element is a switching element, and when the semiconductor element recovers from switching, a displacement current (A1) flows as carriers present in the outer peripheral region escape to the first electrode side through the base layer and the outermost contact in the connecting portion.

8. The semiconductor device according to claim 1, wherein the contact region is formed only on the cell region side of the gate wiring.

9. The semiconductor device according to claim 1, wherein the gate lead portion covers the entire end of the field insulating film.

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