Fully self-aligned contact between backside power and interconnect using replacement metal contact integration

Abstract

Aspects of the present disclosure provide a method of fabricating a semiconductor structure that includes a source-and-drain (S / D) contact and a metal backside contact via vertically aligned with the S / D contact. For example, the method can include providing a substrate, with an oxide layer formed on the substrate, forming over the oxide layer a fin structure that includes a stack of alternating semiconductor layers and dielectric layers, etching a portion of the oxide layer beneath the fin structure to form a backside contact via opening, forming at least one S / D contact to cover the semiconductor layers of the fin structure, and metalizing the backside contact via opening to form a metal backside contact via.

Description

240059W001FULLY SELF-ALIGNED CONTACT BETWEEN BACKSIDE POWER AND INTERCONNECT USING REPLACEMENT METAL CONTACT INTEGRATIONFIELD OF THE INVENTION

[0001] The present disclosure relates to semiconductor processing, and, in particular, to methods of fabricating a semiconductor structure that includes vertically aligned source -and- drain contact and metal backside contact via.BACKGROUND

[0002] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] In the manufacture of a semiconductor device (especially on the microscopic scale), various fabrication processes are executed such as film -forming depositions, etch mask creation, patterning, material etching and removal, and doping treatments. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors have been created in one plane, with wiring / metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other.SUMMARY

[0004] Aspects of the present disclosure provide a method of fabricating a semiconductor structure that includes a source -and-drain (S / D) contact and a metal backside contact via vertically aligned with the S / D contact. For example, the method can include providing a substrate, with an oxide layer formed on the substrate, forming over the oxide layer a fin structure that includes a stack of alternating semiconductor layers and dielectric layers, etching a portion of the oxide layer beneath the fin structure to form a backside contact via240059W001 opening, forming at least one S / D contact to cover the semiconductor layers of the fin structure, and metalizingthe backside contact via opening to form a metal backside contact via.

[0005] In an embodiment, the method can further include forming a gate structure that couples the semiconductor layers of the fin structure, wherein metalizing the backside contact via opening can include filling the backside contact via opening with a replacement metal contact material before the gate structure is formed, removing the replacement metal contact material filled in the backside contact via opening after the gate structure is formed, and metalizing the backside contact via opening. For example, forming the gate structure can include forming a replacement gate structure that couplesthe semiconductor layers of the fin structure, and performing a replacement metal gate (RMG) process to replace the replacement gate structure with the gate structure. In some embodiments, the replacement metal contact material can be formed before the RMG process is performed.

[0006] In an embodiment, etching the portion of the oxidelayer beneath the fin structure to form the backside contact via opening can include forming a gate spacer to cover the fin structure, removing a portion of the gate spacer that is formed on a topside of an end portion of the fin structure to reveal the topside of the end portion of the fin structure, and etching the end portion of the fin structure and the portion of the oxide layer beneath the end portion of the fin structure to form the backside contact via opening. In another embodiment, forming the at least one S / D contact to cover the semiconductor layers of the fin structure can include removing and recessing a portion of the dielectric layers of the fin structure, forming an inner spacer to cover the recessed dielectric layers, with the semiconductor layers uncovered, and forming the at least one S / D contact to cover the uncovered semiconductor layers of the fin structure.

[0007] In an embodiment, the method can further include forming a metal interconnect that couples the metal backside contact via to the at least one S / D contact. In another embodiment, the method can further include forming a gate structure that couples the semiconductor layers of the fin structure, wherein forming the metal interconnect can include forming an interconnect trench that connects the at least one S / D contact to the metal backside contact via, filing the interconnect trench with a gap -fill material before the gate structure is formed, removing the gap-fill material filled in the interconnect trench after the gate structure is formed, and metalizing the interconnect trench to form the metal interconnect. For example, the interconnect trench and the backside contact via opening can be metalized in a same process. In an embodiment, metalizing the backside contact via240059W001 opening can include filling the backside contact via opening with a replacement metal contact material before the interconnect trench is formed, removing the replacement metal contact material filled in the backside contact via opening after the interconnect trench is metalized, and metalizingthe backside contact via opening to form the metal backside contact via. In another embodiment, the method can further include flipping the semiconductor structure to expose a backside of the substrate opposing a frontside of the substrate where the oxide layer is formed before the replacement metal contact material is removed. In some embodiments, the method can further include forming a backside power rail connecting the metal backside contact via. In various embodiments, the method can further include filling the backside contact via opening with a metal barrier layer, wherein the metal backside contact via is formed on the metal barrier layer. For example, the metal interconnect can wrap around the at least one S / D contact.

[0008] In an embodiment, forming the at least one S / D contact can include forming a merged S / D contact that couples all of the semiconductor layers of the fin structure. In another embodiment, forming the at least one S / D contact can include forming unmerged S / D contacts, each of the S / D contacts coupling a corresponding one of the semiconductor layers of the fin structure.

[0009] In an embodiment, the method can further include forming a contact etch stop layer to cover the at least one S / D contact. In another embodiment, the method can further include forming a gate structure that couples the semiconductor layers of the fin structure, and removing the contact etch stop layer, wherein the contact etch stop layer can be formed before the gate structure is formed and is removed after the gate structure is formed.

[0010] In an embodiment, the method can further include forming a silicidation layer that covers the at least one S / D contact. In another embodiment, the method can further include forming a gate structure that couples the semiconductor layers of the fin structure, wherein the silicidation layer is formed after the gate structure is formed.

[0011] Note that this summary section does not specify every embodiment and / or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty. For additional details and / or possible perspectives of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.240059W001BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein:

[0013] FIGs. 1-10 shows show a semiconductor structure fabricated atvarious intermediate steps according to some embodiments of the present disclosure; and

[0014] FIG. 11 is a flow chart of an exemplary method of fabricating a semiconductor structure according to some embodiments of the present disclosure.DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms, such as “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0016] The order of discussion of the different steps as described herein has been presented for clarity sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein may be discussed in different places of this disclosure, it is intended that each of the concepts can be executed independently of each other or in combination with each other. Accordingly, the present invention can be embodied and viewed in many different ways.240059W001

[0017] Backside power distribution networks (PDNs) for logic semiconductor devices incorporate the ground (e.g., VSS) and / or supply power grid (e.g., VDD) on the backside of the semiconductor devices in order to provide significant area scaling to the chip as well as some margin of power and performance improvement of the chip. Typically , VDD and VSS power rails are processed on the topside of a wafer at the initial metallization layer (M0), and since they run across all standard cells without any break, they are typically sized as much as three times wider with respect to the signal tracks at the same metal layer. For example, for a 7 -track high standard cell design, the VDD and VSS tracks, which can be shared between adjacent north-south facing standard cells, comprise as much as the equivalent of 3 of the total tracks. Moving these tracks from the topside of the wafer at M0 layer down to below the semiconductor device as a backside metal layer (BSM0) potentially allows the standard cell to be reduced down to the size of just the 4 routing tracks used for signal connection. This significant reduction in standard cell area allows for a greater number of chips to be manufactured on a wafer, which in turn, can significantly reduce the overall costs for each die.

[0018] Connections between the VDD and VSS power rails and the source and drain (S / D) contacts are typically made through the incorporation of metal vias which will connect the metal tracks at M0 layer down to a metal interconnect wrapping around the S / D contact. These metal vias are typically self-aligned by means of an etch-selective dielectric cap which can be deposited overtop the recessed metal interconnect, where the cap will have some degree of etch selectivity relative to the cap deposited overtop a replacement metal gate (also called transistor) and a low-k spacer used as dielectric separation between the metal interconnect and the gate metal. The height of these metal vias can vary by integration, but are generally minimized to below 30 nm in order to minimize the resistance posed by the metal vias, as these metal vias typically will have diameters approximating the width of the metal interconnects, which can be as low as 12 nm.

[0019] The VDD and VSS power rails at the topside M0 layer are often related to the extreme north and south boundary of the standard cell so that the VDD and VSS power rails can be shared between adjacent standard cells facing each other in the north -to-south orientation; the middle of the standard cell is typically where the signal routing is wired. The placement of the topside VDD and VSS power rails to the outer north and south regions of the standard cell requires that the metal interconnect also extends out to this distance in order to make a downward connection for the metal vias. This extension of the metal interconnect in order to allow for the connection metal to the VSS and VDD power rails entails significant240059W001 fringe capacitance which can drive decreased performance and increase power consumption of the semiconductor device.

[0020] The benefit of adopting backside power connections allows for a more free sizing of the backside VDD and VSS power rails, since there could be minimal or no routing tracks on the backside of the wafer which confine the size of the backside power rails. This allows for larger width power rails in the backside which can significantly improve voltage drop across the chip and also allows for metal interconnect to not have to extend as far in order to make a direct backside connection to the VDD and VSS power. This provides for significant improvement in performance and power.

[0021] The current method of forming such metal vias that connect the backside power to the metal interconnect are done through incorporation of through -silicon vias (TSVs) and nano-through-silicon vias (nTSVs) in which the metal via is formed during the backside processing and making a connection to the metal interconnect on the topside of the wafer through flipping the wafer and processing.

[0022] The TSVs and nTSVs have no means to be fully self-aligned given that the metal interconnect and transistor metals are not exposed to the backside of the wafer in these processes, so the etch-selectivity method of self-alignment is not readily possible from the backside of the wafer in which the metal interconnect can be recessed and re-filled with etch- selective dielectric caps. Thus, the current approach of forming these metal vias suffers from an inability to provide any means of self-alignment other than to significant reduce the size of the diameters of the metal vias in order to ensure that the placement of the metal vias meets the existing edge-placement-error (EPE) and alignment capability of the lithographic exposure equipment. Another approach to allow for TSV and nTSV processing is to purposely extend the metal interconnect out by a distance in order to have to adjacent gate metal. This leads to some performance and power degradation of the semiconductor device since the metal connection is now farther away from the actual S / D contact.

[0023] Another important note concerning these TSV and nTSV structures is that they require more height compared to the conventional top-down contacts. This is attributed to the fact that the TSVs and nTSVs much pass through some amount of residual backside silicon (although this is purely optional even though it is used by the industry) and then through a shallow trench isolation (STI) layer before connecting with the metal interconnect. These distances can exceed 50 nm, placing them at much higher potential for increasing resistance, and hence further degrading performance and power for the semiconductor devices.240059W001

[0024] What is needed is what is called a backside contact (BSC) posed by Qualcomm at IEDM in 2021 in which a backside contact can be made directly under the active source and drain (S / D) contact structure to connect to the backside power. The concept from Qualcomm was to form the via connection prior to S / D contact formation through in -situ doped CVD epitaxy growth from the nanosheet ends; however, this process runs into some fundamental processing challenges in the followings: (1) the via would be filled with the S / D contact material from the CVD epitaxy process which would drive higher overall contact resistances which would potentially degrade performance / power of the device; (2) finding a method to replace the S / D contact material in the via with a suitable metal would result in a contact which could not be silicided at the metal / contact interface which would drive significant performance reduction from higher contact resistance; and (3) the overall integration is a challenge since the via would extend down into the STI which is typically composed of silicon oxide, while the interconnect would need to be etched within the field dielectric which is also typically silicon oxide.

[0025] US Patent No. 11 / 322,401 titled “Reverse contact and silicide process for three- dimensional semiconductor devices” from Tokyo Electron poses a methodology in which a replacement dielectric material can be used to memorize an interconnect structure within a field silicon oxide material. In the present disclosure, the application of this patent is extended in order to provide a means to create a fully self-aligned backside contact (BSC) via in which this via can exist directly under a S / D contact connecting to a backside power distribution network metal grid which is fully self -aligned to the interconnect and the S / D contact and have no risk of inadvertently connecting to a transistor.

[0026] The concept here is to fully self-align the via connecting the metal interconnect wrapping around the source and drain (S / D) contact to the backside VSS and / or VDD power rails. This self-alignment is crucial in order to prevent any unintentional shorting of the backside power to the transistor as this would lead to the transistor potentially always being in an “always on” or “always off’ condition.

[0027] FIGs. 1-10 show a semiconductor structure 100 fabricated at various intermediate steps according to some embodiments of the present disclosure. In an embodiment, the semiconductor structure 100 can include a via that connects a source and drain (S / D) contact to a backside power delivery network is formed prior to the growth and formation of the S / D contact. As shown in FIG. 1, the semiconductor structure 100 can include a fin structure 110 that protrudes from a bonding (or buried) oxide layer 120 formed on a substrate 130 (or a silicon-on-insulator (SOI) substrate). In an embodiment, the fin structure 110 can include a240059W001 stack of alternating semiconductor layers 111 and dielectric layers 112. For example, the semiconductor layers 11 1 can include silicon or silicon germanium and be used as channel structures (semiconductor layers 111) of a semiconductor device. The fin structure 110 may be formed by etching a stack of nanosheets of the semiconductor layers 111 and the dielectric layers 112. In an embodiment, an etch stop layer (ESL) 140 may be formed on the bonding oxide layer 120.

[0028] As shown in FIG. 2, a (low-k) gate spacer 210 can be deposited to cover the fin structure 110. Then, a portion of the gate spacer 210 that is formed on a topside of the fin structure 110 can be etched and removed, to reveal the topside of the fin structure 110. In an embodiment, an optional gap-fill layer 220 of a material such as spin-on-carbon (SoC) can be filled and recessed after the low-k gate spacer 210 is deposited in order to reveal the fin structure 110 covered by the low-k gate spacer 210. Then, the fin structure 110 can be etched away selective to the gate cap (typically, silicon nitride), the low-k gate spacer 210 (typically, some type of doped silicon oxide film), and the recessed gap -fill layer 220 to uncover a portion of the ESL 140. Then, the uncovered portion of the ESL 140 can be etched and the gap-fill layer 220 can be ashed and removed. Once the fin structure 110 is etched away outside of the transistor area, the etch can continue opening the dielectric (e.g., the ESL 140 and the bonding oxide layer 120) directly beneath and extend down to either the substrate 130 or to whatever end-point is chosen based on the integration used. This is how the via is fundamentally fully-self aligned to the S / D contact and will have no means by which to short to the adjacent gate.

[0029] As shown in FIG. 3, a portion of the dielectric layers 112 (shown in FIG. 2) can be etched and recessed, and an inner spacer 310 can be selectively deposited to cover the recessed portion of the dielectric layers 112, with the semiconductor layers 111 uncovered. Then, a small-dimension patterning (e.g., a block copolymer (BCP) patterning) can be performed and an SoC layer 320 can be deposited to cover a region outside of a transistor area 340. Then, the bonding oxide layer 120 can be etched to form a backside contact (BSC) via opening 330 for dielectric or metal materials to be filled therein.

[0030] As shown in FIG. 4, the SoC layer 320 can be ashed and removed, and a replacement metal contact (RMC) material (or a gap-fill dielectric) 410 can fill the backside contact via opening 330. In an embodiment, the gap-fill dielectric 410 will have an etch selectivity differentfrom the field silicon oxide dielectric (e.g., the bonding oxide layer 120) as well as the STI dielectric (also silicon oxide) and any wafer bonding dielectric. This will240059W001 allow for the via that connects the intended metal interconnect to the backside metal power VDD / VSS to be “memorized” during subsequent processing.

[0031] Then, S / D contacts 420 and 430 can be formed on the channel structures (semiconductor layers 111) of the fin structure 110 (shown in FIGs. 1 and 2). For example, the S / D contact 420 can be PMOS S / D contact 420, be composed of epitaxially grown silicon germanium which is in-situ doped with baron (B) or similar species, and be composed of multiple layers of silicon germanium of different compositions of germanium in order to provide some level of additional strain to the PMOS channel structures (semiconductor layers 111) of the PMOS semiconductor device. As another example, the S / D contact 430 can be NMOS S / D contact 430, be composed of epitaxially grown silicon which is in-situ doped with phosphorous (P) or arsenic (As) in order to improve the conductance of the NMOS S / D contact 430. The PMOS S / D contact 420 and / or the NMOS S / D contact 430 can be a merged S / D contact (as shown in FIG. 4) or include individual S / D contacts that correspond to the channel structures (semiconductor layers 111), respectively.

[0032] The S / D contacts 420 and 430 can be formed through either of several methods in order to maintain a narrow wrap-around contact structure which can be used for small logic standard cells heights, even with higher performance semiconductor devices which will require larger nanosheet widths. These methods for small wrap-around contact can include: (1) confined growth S / D epitaxy growth (as shown in FIG. 4) in which the initial gate spacer 210 originally existing along the sidewalls of the fin structure 110 are used to confine the lateral growth of the S / D contacts 420 and 430 to maintain a fin-shaped S / D profile; (2) directionally controlled S / D CVD epitaxial growth in which specific crystal orientation growth is favored over others such that the S / D contacts 420 and 430 can be merged in the vertical orientation between nanosheets, but minimize the lateral extension of the nanosheets in the north-south orientation which would make creating a true wrap-around contact more difficult from an integration and area perspective; and (3) utilization of the sidewall metal contact process in which only minimal volume of S / D epitaxy is in-situ doped and grown from the ends of the nanosheets (e.g., the channel structures (semiconductor layers 111)) in which the volume is in sufficient to merge; this would limit the size of the individual contacts to “stubs” extending from the nanosheets and, as such, the lateral extension of the S / D contacts 420 and 430 would not far exceed the width of the starting fin structure 110. The interconnect metal would be used to electrically merge the individual S / D contacts. In an embodiment, the gap-fill dielectric 410 will cover any silicon (or silicon germanium) below240059W001 the fin structure 110 so no CVD epitaxy growth will be seen from either the bottom silicon substrate 130 or any thinned silicon film used in SOI wafer processing.

[0033] Then, the low-k gate spacer 210 remaining along the sidewalls of the fin structure 110 (or called low-k gate spacer shoulder) can be etched and removed.

[0034] As shown in FIG. 5, a contact-etch stop layer (CESL) liner 510 can be isotopically deposited over the formed S / D contacts 420 and 430 to protect the S / D contacts 420 and 430 from any subsequent processing. In some embodiments, low-k gate spacer shoulder 210 can be removed at this time; however, it is also noted that the low-k gate spacer shoulder 210 could have been removed at an earlier step (as shown in FIG. 4) and not used for the confined growth CVD epitaxy process. In such an alternate process, the low-k gate spacer shoulder 210 could be removed prior to the gap-fill deposition of the spin -on-carbon and its subsequent recess, with the self-alignment ofthe backside contact via opening 330 (shown in FIG. 3) still being fully self-aligned. In some embodiments, the removal of the low-k gate spacer shoulder 210 ca be anisotropic, so to ensure that adequate sidewall spacer exists between the metal interconnect and metal gate, and the cap used over the initial gate structure is set to a height such that the consumption of the low-k gate spacer 210 to remove the shoulder will not create any cavities between the metal gate and metal interconnects. Then, a pre-metal dielectric 520 can be deposited over the S / D contacts 420 and 430.

[0035] As shown in FIG. 6, an interconnect pattern in a transfer (TiN) hardmask 610 can be memorized, and then an interconnect trench 620 can be patterned and self-aligned to the interconnect pattern in the transfer hardmask 610. The interconnect trench 620 can either be re-filled with silicon oxide (which would require an additional lithography exposure layer to re-open layer) or re-filled with the same gap-fill dielectric 410 in order to memorize the interconnect structure. In some integrations, one approach may be more favorable than the other. In the example shown, the interconnect trench 620 can be re-filled with silicon oxide while keeping the gap-fill dielectric 410 only within the backside contact via opening 330 (show in FIG. 3).

[0036] Then, replacement metal gate (RMG) processing can be performed to form the gate structure of the semiconductor device. After the RMG processing, the interconnect trench 620 is either re-patterned and re-opened through the silicon oxide; or in the case of a replacement metal contact (RMC) process, the gap-fill dielectric (e.g., the gap-fill dielectric 410) filled within the interconnect trench 620 can be simply isotopically removed to reveal the memorized interconnect trench 620 and / or the backside contact via opening 330 connecting down to the substrate 130, or down to an embedded etch stop layer (e.g., the ESL240059W001140) on top of the substrate 130. In an embodiment, the interconnect pattern can be repatterned and transferred down through the silicon oxide (e.g., the gap-fill dielectric 410); this can be done with the anisotropic etch reaching the base of the fin -shaped S / D contacts 420 and 430 because the S / D contacts 420 and 430 themselves are fin-shaped due to the proposed confined growth used in this example where the sidewalls of the S / D contacts 420 and 430 are confined by the low-k gate spacer shoulder 210 existing on the sides of the initial nanosheet silicon / silicon germanium fin structure 110. The CESL liner 510 (shown in FIG. 5) will protect the S / D contacts 420 and 430 from damage during the anisotropic etch process, as is normal forthe case of standard contact etches done today. For the purpose of the backside metal contacts, it is critical that the interconnect trench 620 extends down to the bottom of the S / D contacts 420 and 430 forthe case of the fin-shaped S / D contact shape. For the case of a sidewall metal contact integration, the interconnect trench 620 must extend down to the top of the backside contact via opening 330.

[0037] Once the RMG processing is done and the interconnect trench 620 is re-opened, the CESL liner 510 over the S / D contacts 420 and 430 can be removed as is typically done. For the case of a sequentially bonded wafer to form the isolation in which the backside contact via opening 330 will pass through, the CESL liner 510 must be of a material with moderate etch-selectivity compared to the ESL 140. This difference can be inherent to the material selection or can be a similar material with a difference in binding energy. It is important to note that during the silicide formation process that the top of the substrate 130 is blocked, either by the presence of the recessed etch -selective gap-fill dielectric 410 used in the replacement metal contact (RMC) process or by incorporation of a secondary gap -fill material which is recessed below the height of the S / D contacts 420 and 430 such as spin-on- carbon. It is also important to note that if an STI process is used, or if an SOI substrate is used in which a thin strip of silicon exists at the initial silicon / silicon germanium fin structure 110, this silicon can likewise be blocked during the siliciation process.

[0038] In some embodiments, a portion of the ESL 140 that is formed within the interconnect trench 620 and a slight top portion of the bonding oxide layer 120 can also be etched and removed.

[0039] As shown in FIG. 7, a silicidation layer 710 can be formed on the S / D contacts 420 and 430. Then, the interconnect trench 620 (shown in FIG. 6) can be metalized with a highly conductive metal to form the metal interconnect 720. In some embodiments, the highly conductive metal may also fill the backside contact via opening 330 (shown in FIG. 3) if the backside contact via opening 330 has already been cleared of any replacement dielectric (e.g,240059W001 the gap-fill dielectric 410). In the example shown in FIG. 7, the recessed gap-fill dielectric 410 can be maintained within the backside contact via opening 330 such that the highly conductive metal is only filling the interconnect trench 620. It is noted that this places some margin of criticality on the ability to recess this gap -fill dielectric 410 such that adequate amount exists to “memorize” the BSC via opening 330 while not blocking any of the merged S / D epitaxy in the S / D contacts 420 and 430.

[0040] As shown in FIG. 8, the interconnect trench 620 (shown in FIG. 6) may be recessed and an etch-selective cap 810 can be formed over the metal interconnect 720. In an embodiment, the etch-selective cap 810 may have etch selectivity to the silicon nitride gate cap, the silicon oxide field dielectric, and the carbon-doped silicon oxide film which typically comprises the low-k gate spacer. In some embodiments, the etch -selective cap 810 can be composed of a dielectric material such as carbon-rich silicon nitride films, or even films composed of silicon carbide or SiCN. Then, the back-end-of-line (BEOL) M0 through Ml 6 (also referred to as Mx, My and Mz layers) 820 can be formed and the semiconductor device can be effectively completed. Then, the semiconductor structure 100 can be (fusion) bonded to a carrier wafer (not shown) so that the semiconductor structure 100 can be flipped to expose the backside of the substrate 130.

[0041] As shown in FIG. 9, the substrate 130 can be removed through multiple integration processes including, but not limited to: (1) SOITEC-like delamination process; (2) back- grinding of the silicon substrate 130; (3) chemical-mechanical polishing (CMP) of the silicon substrate 130 (for SOI substrate this can be done where the silicon is removed to where the buried oxide (BOX) layer 120 is end-pointed; or in the case of a sequential backside power distribution network (BSPDN) integration the CMP can extend to end-point physically on a bottom etch stop layer (e.g., the ESL 140) which can also serve as a CMP-stop layer as well, and the etch-stop or CMP-stop layer must also be removed prior to proceeding to the next step of the integration); and (4) isotropic removal of the backside silicon through an etch or wet-etch process.

[0042] After the removal of the substrate 130, the backside contact vias opening 330 (shown in FIG. 3) will be exposed in the bonding oxide layer 120, whether this be the buried oxide from a SOI wafer, the bonding dielectric of a fusion-based sequential integration, or the STI silicon oxide from a more conventional approach. In most cases such as what is illustrated here, the backside contact via opening 330 will be filled with the gap-fill dielectric 410 used in the replacement metal contact (RMC) process or be filled with the metal used in the metal interconnectlization of the metal interconnect 720.240059W001

[0043] A separate etch stop layer (ESL) 910 covering the gap-fill dielectric 410 and the buried oxide layer 120 plus a deposition of a low-k dielectric material 920 on the ESL 910 can be done to form the low-k dielectric material 920 in which the first backside metal layer will be formed. In an embodiment, the first backside metal layer can include the VSS and / or VDD power rails. The power rails can then be patterned and transferred through the low-k dielectric material 920 by etching to stop on and then transfer through the etch stop layer (ESL) 910 which was deposited at the same time as the low-k dielectric material 920, so as to re-expose the RMC material (i.e., the gap-fill dielectric 410). In some embodiments, the gapfill dielectric 410 filled in the backside contact via opening 330 (shown in FIG. 3) can be isotopically removed in order to re-open the backside contact via opening 330.

[0044] As shown in FIG. 10, a highly conductive metal barrier layer 1010 such as ruthenium (Ru), cobalt (Co), tungsten (W) or some other metal can be filled in to not only fill the backside contact via opening 330 (shown in FIG. 3) for the metal backside contact via 1040 but to also form the metal barrier layer 1010 for the backside power rails 1020 and 1030, if the intent is to filled these backside metal layers with copper. The metal barrier layer 1010 in this case can be used to prevent the migration of copper to the active transistor and device. Alternatively, the entire backside contact via opening 330 and backside metal layer can be filled with a single highly conductive metal such as ruthenium, cobalt, tungsten or other metal, where a copper back-fill will not be used. The choice of metal for the backside metal lines depends on the size of the VSS and / or VDD tracks in terms of overall resistance and IR drop requirements, as well as on the cost of the integration process, where copper may have benefit for both provided that the size of the VSS and / or VDD lines are wide enough. The carrier wafer can be polished and removed, and the semiconductor structure 100 can be re-flipped if it is desired to have the top-side of the semiconductor structure 100 connect to a top-side power distribution network.

[0045] It is found through ring-oscillator-based performance / power assessment, that this method requires additional processing steps in the integration to drive good contact resistance (RhoC) performance due to: (1) the metal filled in the backside contact via opening 330 making an ohmic connection to the S / D contacts 420 and 430 at the interface; and (2) the metal interconnect 720 at the base of the S / D contacts 420 and 430 is not continuous and hence does not make a true wrap-around contact on the bottom of the S / D contacts 420 and 430. These issues can be resolved through additional steps in the process integration sequence.240059W001

[0046] In the processing step in which the interconnect trench 620 (shown in FIG. 6) is transferred through the silicon oxide layer 120, the current example had the trench-etch to stop on the etch stop layer 140 incorporated through the sequential bonding process to form the initial wafer stack. In order to ensure a proper full metal wrap-around of the S / D contact structure, the etch stop layer 140 can also be etched through in the interconnect transfer etch process to open the etch stop layer 140 in the area under the intended metal interconnect 720, and then the silicon oxide 120 (regardless if this is STI oxide, BOX oxide from SOI wafer process, or bonding dielectric material from the sequential approach for BSPDN) can also be partially etched in order to make a clear opened wrap-around path for the S / D contacts 420 and 430.

[0047] To prevent the ohmic contact connection of the metal filled in the backside contact via opening 330 to the S / D contacts 420 and 430, an additional backside silicide formation process may be needed after the semiconductor structure 100 is flipped over and the replacement gap -fill dielectric 410 within the backside contact via opening 330 is removed. This is to ensure a full and continuous silicide wraps around the full contact structure in order to have an optimum Schottky Barrier Height (SBH) for the metal interconnect-to-contact interface.

[0048] After making these additional changes, superior contact resistance is achieved due to the full wrap-around contact and interconnect structure as well as significant performance / power gains for the RO device due to the improved contact resistance and the fringe capacitance reduction. The overall area scaling assessments for a larger sized logic standard cell library is still being run and significantly scale the cell height can be expected as large extensions in the interconnect placement in order to make connections to the BSPDN away from the active S / D contact are no longer needed.

[0049] FIG. 11 is a flow chart of an exemplary method 1100 of fabricating a semiconductor structure (e.g., the semiconductor structure 100) according to some embodiments of the present disclosure. In various embodiments, some of the steps of the method 1100 shown can be performed concurrently or in a different order than shown, can be substituted by other method steps, or can be omitted. Additional method steps can also be performed as desired. The method 1100 can start with step SI 110, at which a substrate can be provided, with an oxide layer formed on the substrate. For example, the substrate 130 canbe provided, with the oxide layer 120 formed on the substrate 130, as shown in FIG. 1. The method 1100 can proceed to step SI 120.240059W001

[0050] At step SI 120, a fin structure that includes a stack of alternating semiconductor layers and dielectric layers can be formed over the oxide layer. For example, the fin structure 110 that includes the semiconductor layers 111 and the dielectric layers 112 can be formed over the oxide layer 120, as shown in FIG. 1. The method 1100 can proceed to step SI 130.

[0051] At step SI 130, a portion of the oxide layer beneath the fin structure can be etched to form a backside contact via. For example, a portion of the oxide layer beneath the fin structure 110 can be etched to form the backside contact via opening 330, as shown in FIG. 3. The method 1100 can proceed to step SI 140.

[0052] At step SI 140, at least one S / D contact can be formed to cover the semiconductor layers of the fin structure. For example, the S / D contacts 420 and 430 can be formed to cover the semiconductor layers 111 of the fin structure 110, as shown in FIG. 4. The method 1100 can proceed to step SI 150.

[0053] At step SI 150, the backside contact via can be metalized to form a metal backside contact via. For example, the backside contact via opening 330 canbe metalized to form the metal backside contact via 1040, as shown in FIG. 10.

[0054] In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.

[0055] Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0056] “ Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the present disclosure. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and240059W001 may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a dielectric layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying dielectric layer or overlying dielectric layer, patterned or un-pattemed, but rather, is contemplated to include any such dielectric layer or base structure, and any combination of dielectric layers and / or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.

[0057] Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the present disclosure. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.

Claims

240059W001WHAT IS CLAIMED IS:

1. A method of fabricating a semiconductor structure, the method comprising: providing a substrate, with an oxide layer formed on the substrate; forming over the oxide layer a fin structure that includes a stack of alternating semiconductor layers and dielectric layers; etching a portion of the oxide layer beneath the fin structure to form a backside contact via opening; forming at least one S / D contact to cover the semiconductor layers of the fin structure; and metalizing the backside contact via opening to form a metal backside contact via.

2. The method of claim 1, further comprising: forming a gate structure that couples the semiconductor layers of the fin structure, wherein metalizing the backside contact via opening includes filling the backside contact via opening with a replacement metal contact material before the gate structure is formed, removing the replacement metal contact material filled in the backside contact via opening after the gate structure is formed, and metalizing the backside contact via opening.

3. The method of claim 2, wherein forming the gate structure includes: forming a replacement gate structure that couples the semiconductor layers of the fin structure; and performing a replacement metal gate (RMG) process to replace the replacement gate structure with the gate structure.

4. The method of claim 3, wherein the replacement metal contact material is formed before the RMG process is performed.

5. The method of claim 1, wherein etching the portion of the oxide layer beneath the fin structure to form the backside contact via opening includes: forming a gate spacer to cover the fin structure; removing a portion of the gate spacer that is formed on a topside of an end portion of the fin structure to reveal the topside of the end portion of the fin structure; and etching the end portion of the fin structure and the portion of the oxide layer beneath the end portion of the fin structure to form the backside contact via opening.240059W0016. The method of claim 1, wherein forming the at least one S / D contact to cover the semiconductor layers of the fin structure includes: removing and recessing a portion of the dielectric layers of the fin structure; forming an inner spacer to cover the recessed portion of the dielectric layers, with the semiconductor layers uncovered; and forming the at least one S / D contact to cover the uncovered semiconductor layers of the fin structure.

7. The method of claim 1, further comprising: forming a metal interconnect that couples the metal backside contact via to the at least one S / D contact.

8. The method of claim 7, further comprising: forming a gate structure that couples the semiconductor layers of the fin structure, wherein forming the metal interconnect includes forming an interconnect trench that connects the at least one S / D contact to the metal backside contact via, filing the interconnect trench with a gap-fill material before the gate structure is formed, removing the gap -fill material filled in the interconnect trench after the gate structure is formed, and metalizing the interconnect trench to form the metal interconnect.

9. The method of claim 8, wherein the interconnect trench and the backside contact via opening are metalized in a same process.

10. The method of claim 8, wherein metalizing the backside contact via opening includes filling the backside contact via opening with a replacement metal contact material before the interconnect trench is formed, removing the replacement metal contact material filled in the backside contact via opening after the interconnect trench is metalized, and metalizing the backside contact via opening to form the metal backside contact via.

11. The method of claim 10, further comprising: flipping the semiconductor structure to expose a backside of the substrate opposing a frontside of the substrate where the oxide layer is formed before the replacement metal contact material is removed.240059W00112. The method of claim 11, further comprising: forming a backside power rail connecting the metal backside contact via.

13. The method of claim 11, further comprising: filling the backside contact via opening with a metal barrier layer, wherein the metal backside contact via is formed on the metal barrier layer.

14. The method of claim 7, wherein the metal interconnect wraps around the at least one S / D contact.

15. The method of claim 1, wherein forming the at least one S / D contact includes forming a merged S / D contact that couples all of the semiconductor layers of the fin structure.

16. The method of claim 1, wherein forming the at least one S / D contact includes forming unmerged S / D contacts, each of the S / D contacts coupling a corresponding one of the semiconductor layers of the fin structure.

17. The method of claim 1, further comprising: forming a contact etch stop layer to cover the at least one S / D contact.

18. The method of claim 17, further comprising: forming a gate structure that couples the semiconductor layers of the fin structure; and removing the contact etch stop layer, wherein the contact etch stop layer is formed before the gate structure is formed and is removed after the gate structure is formed.

19. The method of claim 1, further comprising: forming a silicidation layer that covers the at least one S / D contact.

20. The method of claim 19, further comprising: forming a gate structure that couples the semiconductor layers of the fin structure, wherein the silicidation layer is formed after the gate structure is formed.

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