Reordering dispatched instructions in graphics processing

By determining a priority order for graphics processing instructions and executing them accordingly, the method addresses GPU inefficiencies, ensuring correct ordering and enhancing parallel execution and slot utilization, thus improving graphics processing efficiency.

WO2026117327A1PCT designated stage Publication Date: 2026-06-04QUALCOMM INC
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
QUALCOMM INC
Filing Date
2025-10-14
Publication Date
2026-06-04

AI Technical Summary

Technical Problem

Existing graphics processing units (GPUs) face inefficiencies due to instruction backlogs and incorrect ordering, leading to reduced execution slot efficiency and increased synchronization overhead, which impairs the performance of graphics processing.

Method used

A method is introduced to determine a priority order for graphics processing instructions, generate an instruction queue based on this order, and execute instructions accordingly, ensuring correct ordering and reducing backlogs by allowing lower priority instructions to be executed earlier, thereby improving parallel execution and execution slot utilization.

Benefits of technology

This approach alleviates data or instruction backlogs, ensures correct instruction ordering, and enhances parallel execution and execution slot utilization at GPUs, improving overall graphics processing efficiency.

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Abstract

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain a set of instructions associated with the graphics processing. The apparatus may also determine a priority order for each of the set of instructions associated with the graphics processing. Further, the apparatus may identify at least one instruction in the set of instructions based on the priority order for each of the set of instructions. The apparatus may also execute the at least one instruction based on identification of the at least one instruction.
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