Wafer-scale synthesis and deposition of one-dimensional materials with precisely controlled intervals on thermally treated substrates

Abstract

In an approach to wafer‑scale synthesis for deposition of one-dimensional (1D) materials, a method includes selecting an annealing temperature; annealing a substrate at the selected annealing temperature for a predetermined length of time to form a plurality of one-directional substrate channels; and depositing a metal thin film on the substrate to replicate a substrate topography and to form a plurality of one-dimensional metal channels corresponding to the plurality of one-dimensional substrate channels.

Description

Atty. Docket: UA25-012PCTWAFER-SCALE SYNTHESIS AND DEPOSITION OF ONE-DIMENSIONALMATERIALS WITH PRECISELY CONTROLLED INTERVALS ON THERMALLYTREATED SUBSTRATESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of US Provisional Application Serial No. 63 / 724,970, filed November 26, 2024, which is hereby incorporated by reference in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to one-dimensional materials and, more particularly, to a method for wafer-scale synthesis and deposition of one-dimensional materials with precisely controlled intervals on thermally treated substrates.BACKGROUND

[0003] One-dimensional (ID) materials generally are defined as nanostructures characterized by two dimensions confined to the nanoscale, while the third dimension extends significantly longer. These materials may include, but are not limited to, carbon-based ID materials, such as graphene nanoribbons (GNRs) and carbon nanotubes (CNTs), transition metal trichalcogenides such as tantalum trisulfide (TaSs), and any other suitable ID materials across a wide range of compositions and structures. They have many applications, including electronics, optics, optoelectronics, energy, and biology. In many applications, such as semiconductor manufacturing, the ID materials must be aligned. Existing methods of producing these ID materials do not align the materials. There exists a need to produce aligned ID materials.Atty. Docket: UA25-012PCTBRIEF DESCRIPTION OF THE DRAWINGS

[0004] Reference should be made to the following detailed description which should be read in conjunction with the following figures, wherein like numerals represent like parts.

[0005] FIGs. 1 A and IB illustrate large-scale fabrication of a gold channel structures consistent with the present disclosure.

[0006] FIG. 1C illustrates examples of controlled topology using different substrate types consistent with the present disclosure.

[0007] FIG. ID illustrates a sapphire substrate (top image) and an SrTiCh substrate (bottom image) showing improved uniformity of channel structures on the SrTiCh substrate consistent with the present disclosure.

[0008] FIG. 2 illustrates examples of valley-to-valley distance control consistent with the present disclosure.

[0009] FIGs. 3A and 3B illustrate the wafer-scale capability of the disclosed method consistent with the present disclosure.

[0010] FIGs. 4A and 4B illustrate solution-based alignment consistent with the present disclosure.

[0011] FIGs. 5A and 5B illustrate solution-based carbon nanotube (CNT) alignment consistent with the present disclosure.

[0012] FIGs. 6A-6D illustrate annealing of sapphire substrates at various temperatures consistent with the present disclosure.

[0013] FIGs. 7A and 7B illustrates metal thin film deposition and surface topography transfer consistent with the present disclosure.

[0014] FIG. 8 illustrates an AFM image of the metal thin film surface topography transfer on the bottom side of the metal thin film consistent with the present disclosure.Atty. Docket: UA25-012PCT

[0015] FIG. 9 is a graph of the Raman shift for the synthesis of graphene nanoribbons on gold film with channels consistent with the present disclosure.

[0016] FIG. 10 illustrates an alignment of one-dimensional Tantalum Trisulfide (TaS3) on a gold film, consistent with the present disclosure.

[0017] FIGS. 11A-11D illustrate substrate images of an SrTiCh substrate pre-processed with an NH4F-HF solution according to embodiments of the present disclosure.

[0018] FIG. 12 is a flow diagram of the steps for wafer-scale synthesis and deposition of onedimensional materials with controlled intervals on thermally treated substrates consistent with the present disclosure.Atty. Docket: UA25-012PCTDETAILED DESCRIPTION

[0019] Disclosed herein is a method to enable precise control over the alignment of onedimensional (ID) materials for designing, for example, ID material-based transistors and electronics that surpasses the limitations of conventional silicon-based devices. ID materials, such as CNTs and GNRs, may be used in electronic and optoelectronic applications which may include, but are not limited to, high density field effect transistors, logic computing, sensing, and imaging.

[0020] The disclosed method uses annealing to create channel features on substrates, enabling the alignment of ID materials on a wafer-scale. By depositing metal films onto these substrates, the channel features are transferred to the metal surfaces, facilitating the alignment of ID materials. This method can be applied to both bottom-up and top-down synthesis techniques, including the precise synthesis of GNRs. The channel size can be controlled by adjusting the annealing temperature and / or substrate miscut angle. Additionally, the technique is printable, allowing for the reuse of substrates, enhancing efficiency and scalability. The disclosed method includes the creation of one-dimensional channels on metal films to provide global alignment of ID materials.

[0021] The disclosed method is a new technique that uses the surface reconstruction of substrates when annealed at high temperatures to create channel features. Although thermally treated substrates have been studied previously, their use for aligning low-dimensional materials has been limited. The disclosed method takes advantage of the surface morphology of these substrates to align various ID materials on a wafer-scale with controlled intervals, enabling global alignment at high ID materials density.

[0022] The present disclosure also provides methodologies for deposition of metal films onto thermally treated substrates. The metal films inherit the one-directional channel features from the underlying substrate morphology on both their top and bottom surfaces. The structure on the top surface can be used without further processing, and the bottom surface can be used by transferring the metal film onto another substrate. This one-directional feature on the metal surface is used to align ID materials along a specific direction. This approach of using thermally treated substrates to create metal channels has not been previously explored, and can be applied to various types of metals.Atty. Docket: UA25-012PCT

[0023] The disclosed method can be applied to both bottom-up methods, which create ID materials from molecules, and top- down methods, which reduce dimensions from bulk crystals. For instance, atomically precise GNRs are synthesized with precursor molecules on metal surfaces, growing along channel edges. The channel density and depth can be controlled by adjusting the thermal treatment temperature, thereby controlling the interval of GNRs. Additionally, ID materials synthesized beforehand can be suspended in solvent and drop-casted onto the metal films, aligning along the channel edges. This approach can also be applied to various types of materials in other fields which may include, but are not limited to, CNTs, transition metal chalcogenides, DNA, and biological molecules.

[0024] The disclosed method is printable, allowing the thermally treated substrate to be reused multiple times to create metal films with ID channel morphology. This reusability enhances the efficiency and scalability of the process.

[0025] FIGs. 1 A and IB illustrate large-scale fabrication of a gold channel structures consistent with the present disclosure. FIGs. 1A and IB illustrate the steps for fabrication of a gold step structure on a single crystalline substrate. In the example of FIGs. 1A and IB the single crystalline substrate is sapphire, but other single crystalline substrates may be used. Other single crystalline substrates may include, but are not limited to, lithium niobate (LiNbO3) and strontium titanate (SrTiO3).

[0026] In FIG. 1A, a single crystal substrate 100A is processed using the disclosed annealing method. Image 102 shows the surface of the substrate 100 A before annealing. In this example, the height variance of the surface of the substrate 100A ranges from approximately 0 nm. to 2 nm, as shown by the gradient reference graph to the right of the image 102. For the example of FIGs. 1A and IB, the single crystal substrate 100A through 100D is a sapphire crystal substrate, but other substrate materials may be used.

[0027] The right side of FIG. 1A illustrates the single crystal substrate 100B after annealing. As can be noted from the single crystal substrate 100B, substrate channel structures 103A, 103B,..., 103N are formed on the surface of the substrate after annealing. The channel structures 103A, 103B,..., 103N are formed as generally elongated and approximately parallel channels or troughs, as illustrated. Using the XYZ coordinates as a reference where the X and Y dimensionsAtty. Docket: UA25-012PCT are defined in the plane of the surface of the substrate 100B and the Z dimension is defined as normal to the surface of the substrate 100B, each channel 103A, 103B,..., 103N is defined approximately across the entire surface of the substrate 100B (in the Y dimension) and generally parallel to one another in the X dimension. In this example, the substrate 100B has been annealed at a temperature of 1700°C for a predetermined length of time, for example, one hour. Image 104 shows the surface of the substrate 100B after annealing. In the image 104, the Z depth of the channels 103A, 103B,..., 103N is on the order of 0 to 60 nm (as shown by the gradient reference graph to the right of the image 104), representing the overall height of a peak-to-valley of each channel 103A, 103B,..., 103N. The substrate channels 103A, 103B,..., 103N form a template for metal deposition, described below.

[0028] It should be noted that although the annealing temperature for the example of substrate 100B is 1700°C, other annealing temperatures may be used for different terrace sizes or different substrate materials. In an embodiment, the annealing temperature may be in the range of 300°C to 2000°C, inclusive. Such temperature may be selected, for example, to be below a melting point of the substrate and may be based on a thickness of the substrate, etc.

[0029] In FIG. IB, the single crystal substrate 100C shows the substrate 100B from FIG. 1A after metal thin film deposition. In the example of FIG. IB, the deposited metal is gold, but in other examples other metals may be used. In an embodiment, the metal may be, but is not limited to, copper, silver, titanium, chromium, or nickel.

[0030] In an embodiment, the metal is deposited by physical vapor deposition. In other embodiments, the metal may be deposited by sputtering or drop casting. In still other embodiments, any appropriate method of deposition may be used as would be known to one skilled in the art.

[0031] Image 108 shows the surface of the substrate 100C after a metal, e.g., gold, has been deposited on the surface, forming a film 106. As can be noted on the substrate 100C, the gold film 106 replicates the morphology on the top surface of the substrate 100C. In other words, the substrate channels 103A, 103B,..., 103N in the substrate provide a template to form corresponding metal channels 107 A, 107B, ..., 107N.Atty. Docket: UA25-012PCT

[0032] Substrate 100D is the substrate 1 OOC after the gold film 106 has been delaminated from the substrate 100C. Image 114 shows the gold / sapphire interface of the substrate 100D after delaminating the gold film 106. The underside 112 of the gold film 106 is also shown in FIG. IB. The underside 112 of the gold film 106 includes the metal channels.

[0033] FIG. 1C illustrates non-limiting examples of various embodiments to control the topology of the substrate using different substrate types according to various embodiments of the present disclosure. The examples of FIG. 1C illustrate substrate images after annealing. For example, substrate-1 114 is an example of miscut c-plane sapphire, substrate-2 116 is an example of m-plane sapphire, substrate-3 118 is an example of LiNbO3, and substrate-4 120 is an example of SrTiCh. As is shown in the images of FIG. 1C, the substrate -4 120 shows a greater density of substrate channels (i.e., number of channels per unit dimension), compared to substrates 1 and 3. Substrate 1 exits poorly defined channels and lower channel density compared with substrates 2, 3 and 4. In addition, substrate 4 exhibits fewer channel defects (described below) compared to substrates 2 and 3.

[0034] In an embodiment, the substrate is a miscut crystalline substrate. During the annealing process, the miscut crystalline substrate attempts to realign the crystal structure, causing the formation of the terraces on the surface of the substrate. The characteristics of the substrate channel structures, such as height and spacing, formed in the annealing process are determined both by the annealing temperature and the miscut angle of the crystalline substrate. In an embodiment, the c- plane miscut angle is in the range of greater than 0 degrees to 10 degrees (inclusive of 10 degrees). For example, a substrate may be cut with an angle of 4 degrees. The terms “miscut”, “miscut c- plane” and “m-plane” are well understood by one skilled in materials processing arts, and generally represent a crystalline angle that is offset from a surface angle. In some embodiments, the miscut angle is zero, for example in reference to an m-plane of the crystalline structure as is well known in the art.

[0035] As a general matter, as the miscut angle increases, the channel density increases, however, a larger channel density also tends to increase the number of defects in the channels (e.g., channel bunching, larger number of mis-aligned channels, etc.). Thus, the teachings of the presentAtty. Docket: UA25-012PCT disclosure provides control over the channel density by controlling annealing temperature and miscut angle to minimize the number of channel defects for a given application.

[0036] FIG. ID illustrates improved uniformity of channel structures on an SrTiCh substrate consistent with the present disclosure. Image 122 is an example of miscut m-plane sapphire substrate, which exhibits defects 124 characterized as substrate channel bunching. Image 126 shows an SrTiCh substrate, which exhibits few, if any, such defects. The channel density of the SrTiCF substrate (image 126) is similar to the channel density of the miscut m-plane sapphire substrate (image 122).

[0037] FIG. 2 illustrates examples of controlling channel-to-channel distance of a substrate consistent with the present disclosure. As shown in FIG. 2, the channel-to-channel size varies with annealing temperature. In the examples of FIG. 2, substrate- 1 202 was annealed at a temperature of 1300°C yielding an average channel-to-channel distance of 28 nm, wafer-2 204 was annealed at a temperature of 1300°C yielding average channel-to-channel distance of 62 nm, and substrate- 3 206 was annealed at a temperature of 1300°C yielding average channel-to-channel distance of 142 nm. In the examples of FIG. 2 a sapphire substrate was used.

[0038] FIGs. 3A and 3B illustrate the wafer-scale capability of the method consistent with the present disclosure. In the example of FIGs. 3A, the direction of the steps and step size are consistent across a wafer. Measurements were taken at various points across both the annealed sapphire substrate 310 as well as the backside of the gold film 320. The measurements for the four points noted in FIG. 3A, point-1 312, point-2 314, point-3 316, and point-4 318, are graphed in FIG. 3B. As shown by the consistent alignment of the steps on point-1 312, point-2 314, point-3 316, and point-4 318. both on the annealed sapphire substrate 310 and the gold film 320. the disclosed process yields consistent channel structures across the entire wafer. These channel structures are used to align the ID materials subsequently placed on the metal film.

[0039] In the graph of FIG. 3B, the channel size of the annealed sapphire substrate 310 is shown in the left bar graph of each pair of measurement points of FIG. 3A, and the channel size of the backside of gold film 320 is shown in right bar graph of each pair of measurement points of FIG. 3A. The graph of FIG. 3B illustrates that the channel structures on the backside of gold film 320Atty. Docket: UA25-012PCT closely replicates the channel structures of the annealed sapphire substrate 310 because the metal film is tightly bonded to the substrate structure.

[0040] FIGs. 4A and 4B illustrate solution-based alignment consistent with the present disclosure. In the example of FIG. 4A, ID material 406 suspended in a solution 402 (e.g., ethanol, etc.) was drop cast onto substrate 400 which contains steps or terraces 402. FIG. 4B illustrates the results after the solution 402 was dried under vibration. As shown in FIG. 4B, the ID material 406 has aligned with the metal channels 402. During experimentation, both TaS3 and CNTs were deposited by this method, although it should be noted that other ID materials may be deposited using this method as would be known to one skilled in the art. It should be noted that while ID materials may be used according to the teachings of the present disclosure, quasi ID material can be used, for example, transition metal trichalcogenides (TMTCs), DNA, and / or biological molecules.

[0041] FIGs. 5A and 5B illustrate solution-based CNT alignment consistent with the present disclosure. The graphs in FIGs. 5A and 5B demonstrate a proof-of-concept for the disclosed method. FIGs. 5A and 5B are polarized Raman spectroscopy images representing CNTs placed on a gold film deposited on an m-sapphire substrate which has been annealed by the disclosed method to form channels on the surface of the substrate and, therefore, on the gold film (FIG. 5A) as compared to CNTs placed on a gold film deposited on a mica substrate using an existing commercial growth process (FIG. 5B). As shown in graphs 402, 404, 406, and 410, the CNTs placed on the gold film deposited on an m-sapphire substrate which has been annealed by the methods of the present disclosure exhibit a high degree of alignment. The CNTs placed on a gold film deposited on a mica substrate using an existing commercial growth process (i.e., no onedirectional step structure) in graphs 412, 414, 416. 418. and 420, conversely, exhibit poor alignment.

[0042] FIGs. 6A-6D are example atomic force microscopy (AFM) images of sapphire substrates before (FIG. 6A) and after (FIGs. 6B-6D) annealing at various temperatures consistent with the present disclosure. In the examples of FIGs. 6A-6D, miscut m-plane sapphire substrates were annealed at three different temperatures: 1700°C, 1500°C, and 1275°C, each for a duration of 1 hour in air. Prior to annealing, the substrate surfaces were relatively flat (as shown by theAtty. Docket: UA25-012PCT gradient reference graph to the right of the image 602). Post-annealing, the surfaces exhibited onedirectional channels. The channel width and height varied with the annealing temperature, with channel sizes ranging from a few nanometers to hundreds of nanometers. For example, image 604 (FIG. 6B, annealed at approximately 1700°C) has a channel density of approximately 5 channels per m. and an average channel depth of approximately 27 nm., image 604’ (FIG. 6C, annealed at approximately 1500°C) has a channel density of approximately 6 channels per pm. and an average channel depth of approximately 10 nm., and image 604” (FIG. 6D, annealed at approximately 1275°C) has a channel density of approximately 20 channels per pm. and an average channel depth of approximately 1 nm.

[0043] FIGs. 7A and 7B illustrates metal thin film deposition and surface topography transfer consistent with the present disclosure. In the examples of FIGs. 7A and 7B, a 100 nm gold film was deposited onto the m-cut sapphire substrate annealed at 1700°C, as shown in FIG. 7A. The deposited gold film replicated the topography of the sapphire substrate. This channel topography remained intact after annealing the gold film at 400°C for one hour, a typical temperature for GNR synthesis (FIG. 7B). Given that GNRs grow along channel edges, GNRs according to this embodiment align along the channel edges on the metal surface created by this method.

[0044] FIG. 8 illustrates an AFM image of the metal thin film surface topography transfer on the bottom side of the metal thin film consistent with the present disclosure. As illustrated, channels are also formed at the bottom side of the deposited film, at the interface between the metal and the sapphire substrate. The gold film was delaminated, and the surface topography was measured by AFM. The morphology of the substrate surface was successfully transferred to the metal film. Notably, the same sapphire substrate can be reused for multiple metal film depositions.

[0045] FIG. 9 is a graph of the Raman shift for the synthesis of GNRs on gold film with channels consistent with the present disclosure. Here, GNR synthesis onto the gold film on the annealed sapphire substrate was performed. The synthesis of GNRs was confirmed by Raman spectroscopy. The Raman spectrum of the deposited GNRs is shown in FIG. 9. The spectrum shows the unique Raman peaks for GNRs, demonstrating the successful growth of GNRs on the gold film with the channels as formed using the teachings of the present disclosure.Atty. Docket: UA25-012PCT

[0046] FTG. 10 illustrates an alignment of one-dimensional TaS3 on a gold film with metal channels formed on the surface (as described herein), consistent with the present disclosure. FIG. 10 shows an optical image of the gold film on m-cut sapphire annealed at 1700°C after TaS3 deposition. TaS3 was sonicated in ethanol to create a solution of suspended TaS3 crystals. This solution was drop-casted onto the gold film deposited on the annealed sapphire and dried under sonication. As shown in FIG. 10. the TaS3 crystals spontaneously aligned along the channel edge direction of the gold film (as shown in the lower right zoomed-in image).

[0047] FIGS. 11A-11D illustrate substrate images of a SrTiCh substrate pre-processed with an NFUF-HF solution according to embodiments of the present disclosure. As is known in the art, substrate wafers may be processed at manufacture with an NH4F-HF solution. The SrTiCh substrate of FIGS. 11A-11D has a miscut angle of approximately 0.1°, and was annealed at approximately 900°C for approximately 8 hours. The image 1102 of FIG. 11 A shows a 20x20 pm area of the SrTiCh substrate annealed at approximately 900°C for approximately 8 hours. The image 1104 of FIG. 11B shows a 10x10 pm area of the SrTiCh substrate annealed at approximately 900°C for approximately 8 hours. The image 1106 of FIG. 11C shows a 5x5 pm area of the SrTiCh substrate annealed at approximately 900°C for approximately 8 hours. The image 1108 of FIG. 11D shows a 2x2 pm area of the SrTiCh substrate annealed at approximately 900°C for approximately 8 hours. Comparing the images of the SrTiCh substrate of FIGS. 11A-11D with the images of the sapphire substrates of FIG. 2, it is noted that the SrTiCh substrate generally provides fewer defects (e.g., channel bunching and channel discontinuities, etc.) than the sapphire substrate.

[0048] FIG. 12 is a flow diagram of the steps for a process 1100 for wafer-scale synthesis and deposition of one-dimensional materials with precisely controlled intervals on thermally treated substrates consistent with the present disclosure.

[0049] Process 1200 includes selecting a substrate annealing temperature (operation 1202). In the illustrative example of FIG. 12, a substrate annealing temperature is selected based on the selected substrate as well as the desired channel density and channel depth. In an embodiment, the annealing temperature may be in the range of 300°C to 2,000°C.

[0050] Process 1200 includes annealing the substrate at the selected temperature for a predetermined length of time (operation 1204). In an embodiment, the predetermined length ofAtty. Docket: UA25-012PCT time may be one hour. In another embodiment, other appropriate lengths of time may be chosen based on the desired characteristics of the channels and the type of substrate in use.

[0051] Process 1200 includes depositing a metal thin film to replicate the substrate channels (operation 1206). In an embodiment, the deposited metal may be gold, but in other embodiments other metals may be used. For example, the metal may be, but is not limited to, copper, silver, titanium, chromium, or nickel. In an embodiment, the metal may be deposited by physical vapor deposition. In other embodiments, the metal may be deposited by sputtering or drop casting. In still other embodiments, any appropriate method of deposition may be used as would be known to one skilled in the art.

[0052] Process 1200 may include delaminating the metal film from the substrate (optional operation 1208). In optional operation 1208, the metal film is delaminated from the substrate material, allowing the thermally treated substrate to be reused multiple times to create metal films with the step-like morphology. This reusability enhances the efficiency and scalability of the process.

[0053] According to one embodiment of the present disclosure there is thus provided a method for wafer-scale synthesis for deposition of ID materials. The method of this embodiment includes selecting an annealing temperature; annealing a substrate at the selected annealing temperature for a predetermined length of time to form a plurality of one-dimensional substrate channels; and depositing a metal thin film on the substrate to replicate a substrate topography and to form a plurality of one-dimensional metal channels corresponding to the plurality of one-dimensional substrate channels.

[0054] According to another embodiment of the present disclosure there is thus provided a method for wafer-scale synthesis and deposition of ID materials. The method of this embodiment includes selecting an annealing temperature; annealing a substrate at the selected annealing temperature for a predetermined length of time to form a plurality of one-dimensional substrate channels; depositing a metal thin fdm on the substrate to replicate a substrate topography and to form a plurality of one-dimensional metal channels corresponding to the plurality of onedimensional substrate channels; and synthesizing a ID material aligned along the one-directional metal channels.Atty. Docket: UA25-012PCT

[0055] According to another embodiment of the present disclosure there is thus provided a method for wafer-scale synthesis and deposition of ID materials. The method of this embodiment includes selecting an annealing temperature; annealing a strontium titanate (SrTiO3) substrate at the selected annealing temperature for a predetermined length of time to form a plurality of onedimensional substrate channels; depositing a metal thin fdm on the substrate to replicate a substrate topography and to form a plurality of one-dimensional metal channels corresponding to the plurality of one-dimensional substrate channels; and depositing a ID material aligned along the one-directional metal channels.

[0056] Although the methods and systems have been described relative to a specific embodiment thereof, they are not so limited. Obviously, many modifications and variations may become apparent in light of the above teachings. Many additional changes in the details, materials, and arrangement of parts, herein described and illustrated, may be made by those skilled in the art. Also, it may be appreciated that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting as such may be understood by one of skill in the art. Throughout the present disclosure, like reference characters may indicate like structure throughout the several views, and such structure need not be separately discussed. Furthermore, any particular feature(s) of a particular exemplary embodiment may be equally applied to any other exemplary embodiment(s) of this disclosure as suitable. In other words, features between the various exemplary embodiments described herein are interchangeable, and not exclusive.

[0057] As used in this application and in the claims, a list of items joined by the term “and / or” can mean any combination of the listed items. For example, the phrase “A, B and / or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. As used in this application and in the claims, a list of items joined by the term “at least one of’ can mean any combination of the listed terms. For example, the phrases “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.

[0058] Unless otherwise stated, use of the word "substantially" may be construed to include a precise relationship, condition, arrangement, orientation, and / or other characteristic, and deviations thereof as understood by one of ordinary skill in the art, to the extent that such deviations do not materially affect the disclosed methods and systems. The word “approximately” may be used to include a value at or near a stated value, for example, within engineering tolerances,Atty. Docket: UA25-012PCT measurement capabilities, etc. and should be generally construed herein as a value term that mofies a value to reflect real-world and practical limitations. Throughout the entirety of the present disclosure, use of the articles "a" and / or "an" and / or "the" to modify a noun may be understood to be used for convenience and to include one, or more than one, of the modified noun, unless otherwise specifically stated. The terms "comprising", "including" and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.

Claims

Atty. Docket: UA25-012PCTCLAIMSWhat is claimed is:

1. A method for wafer-scale synthesis for deposition of one-dimensional (ID) materials, the method comprising: selecting an annealing temperature; annealing a substrate at the selected annealing temperature for a predetermined length of time to form a plurality of one-dimensional substrate channels; and depositing a metal thin film on the substrate to replicate a substrate topography and to form a plurality of one-dimensional metal channels corresponding to the plurality of one-dimensional substrate channels.

2. The method of claim 1, wherein the substrate is a single crystalline substrate.

3. The method of claim 2. wherein the single crystalline substrate is selected from a group consisting of sapphire, lithium niobate (LiNbO3), and strontium titanate (SrTiO3).

4. The method of claim 2, wherein the single crystalline substrate is a miscut single crystalline substrate.

5. The method of claim 4, wherein the miscut single crystalline substrate is miscut at an angle of greater than zero degrees to ten degrees, inclusive of ten degrees.

6. The method of claim 1, wherein the annealing temperature is in a range of 300°C to 2000°C, inclusive.

7. The method of claim 1, wherein the metal thin film is composed of gold.

8. The method of claim 1, wherein the metal thin film is composed of a metal selected from a group consisting of copper, silver, titanium, chromium, and nickel.Atty. Docket: UA25-012PCT9. The method of claim 1 , further comprising: synthesizing a ID material aligned along the one-directional metal channels.

10. The method of claim 9, wherein the ID material is a ID carbon material.

11. The method of claim 10. wherein the ID carbon material is selected from a group consisting of graphene nanoribbons (GNRs) and carbon nanotubes (CNTs).

12. The method of claim 9, wherein the ID material is a quasi-lD material.

13. The method of claim 12, wherein the quasi- ID material is transition metal trichalcogenides (TMTCs).

14. A method for wafer-scale synthesis and deposition of one-dimensional (ID) materials, the method comprising: selecting an annealing temperature; annealing a substrate at the selected annealing temperature for a predetermined length of time to form a plurality of one-dimensional substrate channels; depositing a metal thin film on the substrate to replicate a substrate topography and to form a plurality of one-dimensional metal channels corresponding to the plurality of one-dimensional substrate channels: and synthesizing a ID material aligned along the one-directional metal channels.

15. The method of claim 14, wherein the ID material is a ID carbon material.

16. The method of claim 15, wherein the ID carbon material is selected from a group consisting of graphene nanoribbons (GNRs) and carbon nanotubes (CNTs).

17. The method of claim 14, wherein the ID material is a quasi- ID material.Atty. Docket: UA25-012PCT18. The method of claim 17, wherein the quasi- 1 D material is transition metal trichalcogenides (TMTCs).

19. The method of claim 14, wherein the substrate is a single crystalline substrate.

20. The method of claim 19, wherein the single crystalline substrate is selected from a group consisting of sapphire, lithium niobate (LiNbO3), and strontium titanate (SrTiO3).

21. The method of claim 19, wherein the single crystalline substrate is a miscut single crystalline substrate.

22. A method for wafer-scale synthesis and deposition of one-dimensional (ID) materials, the method comprising: selecting an annealing temperature; annealing a strontium titanate (SrTiO3) substrate at the selected annealing temperature for a predetermined length of time to form a plurality of one-dimensional substrate channels; depositing a metal thin film on the substrate to replicate a substrate topography and to form a plurality of one-dimensional metal channels corresponding to the plurality of one-dimensional substrate channels; and depositing a ID material aligned along the one-directional metal channels.

23. The method of claim 22, wherein the ID material is a ID carbon material.

24. The method of claim 23, wherein the ID carbon material is selected from a group consisting of graphene nanoribbons (GNRs) and carbon nanotubes (CNTs).

25. The method of claim 22, wherein the ID material is a quasi- ID material.

26. The method of claim 25, wherein the quasi- ID material is transition metal trichalcogenides (TMTCs).Atty. Docket: UA25-012PCT27. The method of claim 22, wherein the strontium titanate (SrTiO3) substrate is a miscut single crystalline substrate.

28. The method of claim 27, wherein the strontium titanate (SrTiO3) substrate has a miscut angle of approximately 0.1 degrees.

29. The method of claim 22, wherein the annealing temperature is approximately 900°C.

30. The method of claim 22, wherein the predetermined length of time is approximately 8 hours.

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