Smart card circuit board, smart IC module and smart card comprising same

Abstract

A smart card circuit board according to an embodiment comprises a substrate and a conductive pattern part disposed on the substrate, wherein the conductive pattern part includes a buffer layer disposed on the substrate and a metal layer disposed on the buffer layer, the metal layer including an alloy containing copper, nickel and zinc.

Description

Circuit board for smart card, smart IC module, and smart card including the same

[0001] The embodiment relates to a circuit board for a smart card, a smart IC module, and a smart card including the same.

[0002] A smart card is a plastic card embedded with an integrated circuit chip capable of storing and processing information. The smart card has an IC installed that stores the information required for the card, and transmits this information to a reader in the form of an electrical signal.

[0003] The above smart card is manufactured by inserting a smart IC module into the main body of the card.

[0004] The above-described smart IC module is classified into a single type or a dual type depending on the arrangement of the metal layer. In the single type, the metal layer and the plating layer are arranged only on one side of the substrate. Additionally, in the dual type, the metal layer and the plating layer are arranged on both sides of the substrate.

[0005] In addition, the smart IC module is classified into contact, contactless, hybrid, and combi cards depending on the method of card usage. The contact card transmits and receives information through physical contact. Additionally, the contactless card transmits and receives information without physical contact. Furthermore, hybrid cards and combi cards include both the contact and contactless functions.

[0006] Accordingly, the smart IC module includes a contact surface and a bonding surface. The contact surface contacts an external device, and a chip is placed on the bonding surface. The bonding surface is inserted into the interior of the card body.

[0007] The chip disposed on the bonding surface and the conductive pattern disposed on the contact surface are electrically connected by wire bonding. Accordingly, the smart IC module includes a plurality of holes. The chip and the conductive pattern are wire-bonded through the holes.

[0008] A metal layer is disposed on the contact surface. If the metal layer is exposed to the outside, the metal layer may corrode. Additionally, the metal layer may be damaged by external impact. Accordingly, a plating layer may be disposed on the metal layer on the contact surface.

[0009] The manufacturing process of the smart IC module may increase due to the plating layer mentioned above. In addition, the plating layer requires expensive materials such as gold (Au). Consequently, process costs may increase.

[0010] Therefore, a circuit board for a smart card with a new structure capable of solving the above-mentioned problems, a smart IC module, and a smart card including the same are required.

[0011] As prior art related to the above-mentioned circuit board for a smart card, it is disclosed in Korean published patent (KR10-2022-0110247).

[0012] An embodiment provides a circuit board for a smart card, a smart IC module, and a smart card including the same, wherein physical reliability and / or electrical reliability are disclosed.

[0013] In addition, the embodiment provides a circuit board for a smart card in which a surface treatment layer at the contact surface is omitted, a smart IC module, and a smart card including the same.

[0014] The technical problems to be solved in the proposed embodiments are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the proposed embodiments belong from the description below.

[0015] A circuit board for a smart card according to an embodiment comprises a substrate; and a conductive pattern portion disposed on the substrate, wherein the conductive pattern portion comprises a buffer layer disposed on the substrate and a metal layer disposed on the buffer layer, and the metal layer comprises an alloy comprising copper, nickel, and zinc.

[0016] In addition, the metal layer has a gold color.

[0017] In addition, in the metal layer, the copper content is greater than the nickel content and the zinc content, and the zinc content is greater than the nickel content.

[0018] In addition, the copper content is 50% to 80% by weight, the nickel content is 1.0% to 5.0% by weight, and the zinc content is 18% to 45% by weight.

[0019] In addition, the content of at least one metal among the copper, nickel, and zinc varies along the thickness direction of the substrate within the metal layer.

[0020] In addition, the copper content on the first surface of the metal layer in contact with the buffer layer is greater than the copper content on the second surface of the metal layer opposite to the first surface.

[0021] In addition, the nickel content on the first surface of the metal layer in contact with the buffer layer is greater than the nickel content on the second surface of the metal layer opposite to the first surface.

[0022] In addition, the zinc content on the first surface of the metal layer in contact with the buffer layer is greater than the zinc content on the second surface of the metal layer opposite to the first surface.

[0023] In addition, the alloy of the metal layer further contains manganese, and the metal layer has a gray or silver color.

[0024] In addition, in the metal layer, the copper content is greater than the nickel content, the manganese content, and the zinc content, and the nickel content is greater than the manganese content and the zinc content.

[0025] In addition, the copper content is 60% to 85% by weight, the nickel content is 10% to 40% by weight, the zinc content is 0.05% to 1.0% by weight, and the manganese content is 0.07% to 1.5% by weight.

[0026] Additionally, the buffer layer comprises a first buffer layer disposed on the substrate and a second buffer layer disposed on the first buffer layer, wherein the first buffer layer comprises a first-1 buffer layer comprising a first metal and a first-2 buffer layer comprising an oxide of the first metal, and the first-2 buffer layer comprises a first portion disposed on the lower surface of the first-1 buffer layer between the first-1 buffer layer and the substrate, and a second portion disposed on the side of the first-1 buffer layer.

[0027] In addition, the thickness of the first part of the first-2 buffer layer in the vertical direction is different from the thickness of the second part of the first-2 buffer layer in the horizontal direction.

[0028] In addition, the thickness of the second part of the first-second buffer layer in the horizontal direction is smaller than the thickness of the first part of the first-second buffer layer in the vertical direction.

[0029] A circuit board for a smart card according to an embodiment includes a metal layer forming a conductive pattern. The metal layer includes an alloy. The alloy has a color identical or similar to the color of the cover layer provided on the contact surface of a comparative example, and possesses corrosion resistance, oxidation resistance, wear resistance, and hardness of a certain level or higher.

[0030] Specifically, the metal layer may comprise a first alloy comprising copper (Cu), nickel (Ni), and zinc (Zn) in a set ratio. Alternatively, the metal layer may comprise a second alloy comprising copper (Cu), nickel (Ni), manganese (Mn), and zinc (Zn) in a set ratio. The metal layer comprising the first alloy or the second alloy has improved corrosion resistance, oxidation resistance, wear resistance, and hardness. Therefore, corrosion of the metal layer can be prevented even when the metal layer is exposed to the outside. Furthermore, damage to the metal layer due to external impact can be prevented even when the metal layer is exposed to the outside. Accordingly, a separate cover layer placed on the contact surface of the metal layer can be omitted. As a result, the thickness of the circuit board for the smart card is reduced. In addition, the process efficiency of the circuit board for the smart card is improved.

[0031] Furthermore, the embodiment can provide a conductive pattern portion having the same or similar color as the conductive pattern portion including the cover layer of the comparative example while removing the cover layer. Accordingly, the embodiment can resolve customer dissatisfaction caused by design differences resulting from the removal of the cover layer and improve customer satisfaction accordingly.

[0032] Additionally, a first buffer layer and a second buffer layer are disposed between the substrate and the metal layer. The adhesion between the metal layer and the adhesive layer can be improved by the first and second buffer layers. Specifically, the first buffer layer includes a first-1 buffer layer and a first-2 buffer layer. The first-2 buffer layer includes a first portion disposed on the lower surface of the first-1 buffer layer and a second portion disposed on the side of the first-1 buffer layer. The first portion of the first-2 buffer layer faces the adhesive layer. Accordingly, the adhesion area between the first-2 buffer layer and the adhesive layer is increased by the first portion of the first-2 buffer layer. Thus, the adhesion between the metal layer and the adhesive layer is improved. Consequently, the metal layer can be easily formed. Furthermore, the detachment of the metal layer can be prevented. Accordingly, the process efficiency and reliability of the circuit board for a smart card can be improved.

[0033] In addition, electrical reliability and appearance defects of the conductive pattern portion can be improved by the second portion of the first-2 buffer layer. For example, as a metal layer is formed, the upper cover layer is omitted, which may result in a decrease in electrical reliability due to the formation of copper chloride on the side of the first-1 buffer layer, and / or appearance defects due to the formation of rust. The second portion of the first-2 buffer layer is placed on the side of the first-1 buffer layer. Accordingly, reliability problems that may occur due to the omission of the upper cover layer can be resolved. That is, the embodiment can improve the electrical characteristics of the circuit board for a smart card and, consequently, improve the appearance defects of the circuit board for a smart card. Furthermore, the embodiment can suppress the growth of copper dendrites growing through the side of the first-1 buffer layer. Therefore, the embodiment can resolve electrical reliability problems, such as circuit shorts, that may occur due to dendrite growth.

[0034] FIG. 1 is a plan view of one side of a circuit board for a smart card according to a first embodiment.

[0035] FIG. 2 is a plan view of the other side of a circuit board for a smart card according to the first embodiment.

[0036] FIG. 3 is a cross-sectional view cut along the AA' direction of FIG. 2 according to the first embodiment.

[0037] Figure 4 is an enlarged view of the R1 region of Figure 3.

[0038] Figure 5 is an enlarged view of the R2 region of Figure 3.

[0039] FIG. 6 is a cross-sectional view showing a circuit board for a smart card according to a second embodiment.

[0040] FIG. 7 is a cross-sectional view showing a circuit board for a smart card according to a third embodiment.

[0041] FIG. 8 is a cross-sectional view showing a circuit board for a smart card according to a fourth embodiment.

[0042] FIG. 9 is a cross-sectional view showing a circuit board for a smart card according to the fifth embodiment.

[0043] FIG. 10 is a cross-sectional view showing a circuit board for a smart card according to the 6th embodiment.

[0044] FIG. 11 is a cross-sectional view showing a circuit board for a smart card according to the 7th embodiment.

[0045] FIG. 12 is a cross-sectional view showing a circuit board for a smart card according to the 8th embodiment.

[0046] FIG. 13 is a cross-sectional view showing a circuit board for a smart card according to the ninth embodiment.

[0047] FIG. 14 is a cross-sectional view showing a circuit board for a smart card according to the 10th embodiment.

[0048] FIG. 15 is a plan view showing a smart IC module according to one embodiment.

[0049] FIG. 16 is a cross-sectional view showing a smart IC module according to one embodiment.

[0050] FIG. 17 is a perspective view showing a smart card according to one embodiment.

[0051] FIG. 18 is a schematic cross-sectional view of the smart card of FIG. 17.

[0052] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0053] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a sense that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0054] Furthermore, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “and at least one of B and C (or more than one),” it may include one or more of all combinations that can be formed from A, B, and C.

[0055] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention. These terms are used merely to distinguish the components from other components and are not intended to limit the essence, order, or sequence of the components.

[0056] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0057] Additionally, where described as being formed or placed on the "top or bottom" of each component, the top or bottom includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components.

[0058] In addition, when expressed as “up” or “down,” it can include the meaning of a downward direction as well as an upward direction relative to a single component.

[0059]

[0060] Hereinafter, a circuit board for a smart card, a smart IC module, and a smart card including the same according to an embodiment will be described with reference to the drawings.

[0061]

[0062] FIG. 1 is a plan view of one side of a circuit board for a smart card according to a first embodiment, FIG. 2 is a plan view of the other side of a circuit board for a smart card according to a first embodiment, FIG. 3 is a cross-sectional view cut along the AA' direction of FIG. 2 according to a first embodiment, FIG. 4 is an enlarged view of the R1 region of FIG. 3, and FIG. 5 is an enlarged view of the R2 region of FIG. 3.

[0063] Referring to FIGS. 1 to 3, a circuit board (100) for a smart card includes a substrate (110) and a conductive pattern portion (120).

[0064] At this time, the conductive pattern portion (120) of the circuit board (100) for the smart card in the first embodiment may be a single type disposed only on one side of the substrate (110).

[0065] The substrate (110) includes a first surface (110S1) and a second surface (110S2) opposite to the first surface (110S1). It is placed on the first surface (110S1) of the substrate (110).

[0066] Here, being placed on the first surface (110S1) is not understood only as a configuration in which the conductive pattern portion (120) is in direct contact with the first surface (110S1) of the substrate (110), but can also be understood as having other configurations between the first surface (110S1) of the substrate (110) and the conductive pattern portion (120).

[0067] The first surface (110S1) of the substrate (110) and the second surface (110S2) of the substrate (110) represent opposite surfaces. The first surface (110S1) of the substrate (110) may be defined as a contact surface. For example, the first surface (110S1) of the substrate (110) may represent a surface capable of recognizing information of a smart IC module through direct or indirect contact. Additionally, the second surface (110S2) of the substrate (110) may be defined as a bonding surface. For example, the second surface (110S2) of the substrate (110) may represent a surface for bonding with a chip (described later) while the chip is mounted.

[0068] The substrate (110) includes a resin material. The substrate (110) may have a certain strength. The substrate (110) may be provided with a reinforcing member. For example, the substrate (110) may be provided as a prepreg having a reinforcing member such as glass fiber. Specifically, the substrate (110) may be provided with glass fiber and a silicone-based filler (Si filler) dispersed within an epoxy resin.

[0069] The substrate (110) may be rigid or flexible. For example, the substrate (110) may include glass or plastic. For example, the substrate (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. Alternatively, the substrate (110) may include polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) polycarbonate (PC), or sapphire.

[0070] The substrate (110) may include a photoisotropic film. For example, the substrate (110) may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), photoisotropic polycarbonate (PC), or photoisotropic polymethyl methacrylate (PMMA).

[0071] Alternatively, the above-mentioned substrate (110) may be bent while having a partially curved surface. That is, the substrate (110) may be bent while having a partially flat surface and a partially curved surface. Specifically, the end of the substrate (110) may be bent while having a curved surface. Alternatively, the substrate (110) may be bent while having a random curvature.

[0072] The substrate (110) may have a thickness within a set range. For example, the thickness of the substrate (110) may be 80 µm to 150 µm, 90 µm to 140 µm, or 100 µm to 120 µm. If the thickness of the substrate (110) is less than 80 µm, the supporting force and / or rigidity of the substrate (110) may be reduced, and thereby it may be difficult to stably place the conductive pattern portion (120). If the thickness of the substrate (110) exceeds 150 µm, the thickness of the circuit board for the smart card may increase, and thereby, the thickness of the smart card including the circuit board for the smart card (100) may increase, making it difficult to thin.

[0073] The substrate (110) has insulating properties. For example, the substrate (110) may be provided to support the conductive pattern portion (120) and to provide insulation between a plurality of electrode patterns constituting the conductive pattern portion (120). For example, the substrate (110) may prevent short circuits between the plurality of electrode patterns.

[0074] The substrate (110) may be provided with through holes. For example, the substrate (110) may include a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) spaced apart from each other along the horizontal direction. In this case, although the drawing shows that the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are provided in eight numbers, this is not limited thereto. For example, depending on the type of chip mounted on the circuit board (100) for a smart card, the number of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) provided in the substrate (110) may increase or decrease. For example, the number of terminals of a chip mounted on a circuit board (100) for a smart card may be less than 8 or more than 8, and accordingly, the number of multiple through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) provided in the substrate (110) may be less than 8 or more than 8.

[0075] A plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be areas for electrically connecting a conductive pattern portion (120) disposed on a first surface (110S1) of a substrate (110) and a terminal of a chip. Preferably, a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be areas for wire bonding between the terminal of the chip and the conductive pattern portion (120).

[0076] Each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) has a width of a set range. The width of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may refer to the diameter of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). Alternatively, the width of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be defined as the minimum distance between the inner walls of the through holes passing through the horizontal central axis of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0077] The width of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be 500 µm to 1000 µm, 600 µm to 900 µm, or 700 µm to 800 µm. If the width of at least one of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) is less than 500 µm, it may be difficult to secure a wire bonding space, and this may degrade the process characteristics in the wire bonding process. In addition, if the width of at least one of the multiple through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) exceeds 1000 μm, the planar area of ​​the substrate (110) is reduced, and consequently, the rigidity of the substrate (110) is reduced, or it may be difficult to stably place the conductive pattern portion (120) on the substrate (110).

[0078] An adhesive layer (130) may be disposed on the first surface (110S1) of the substrate (110). The adhesive layer (130) may be disposed between the first surface (110S1) of the substrate (110) and the conductive pattern portion (120). For example, the adhesive layer (130) may be disposed between the first surface (110S1) of the substrate (110) and the lower surface of the conductive pattern portion (120). As an example, the adhesive layer (130) may be disposed between the first surface (110S1) of the substrate (110) and the lower surface of the first buffer layer (122-1) constituting the conductive pattern portion (120).

[0079] An adhesive layer (130) may be provided for bonding strength between the conductive pattern portion (120) and the substrate (110). The adhesive layer (130) may be a bonding sheet. The adhesive layer (130) may be provided to bond a metal layer constituting the conductive pattern portion (120) onto the first surface (110S1) of the substrate (110).

[0080] An adhesive layer (130) may be optionally provided on the substrate (110). For example, if a conductive pattern portion (120) can be directly attached to the substrate (110) with a bonding strength of a certain level or higher, the adhesive layer (130) may be omitted.

[0081] However, to further improve the adhesion between the substrate (110) and the conductive pattern portion (120), an adhesive layer (130) may be additionally placed between the substrate (110) and the conductive pattern portion (120).

[0082] The adhesive layer (130) comprises a resin material. For example, the adhesive layer (130) may comprise at least one of epoxy resin, acrylic resin, and polyimide resin. Additionally, the adhesive layer (130) may comprise at least one additive selected from natural rubber, a plasticizer, a curing agent, and a phosphorus-based flame retardant. In this case, the flexibility of the adhesive layer (130) may be improved.

[0083] The adhesive layer (130) may have a thickness within a set range. For example, the thickness of the adhesive layer (130) may be 8 µm to 35 µm, 10 µm to 30 µm, or 12 µm to 25 µm. If the thickness of the adhesive layer (130) is less than 8 µm, the adhesive strength of the adhesive layer (130) may be reduced, and thereby, the conductive pattern portion (120) may be separated from the adhesive layer (130). Additionally, if the thickness of the adhesive layer (130) exceeds 35 µm, the thickness of the circuit board for the smart card may increase or the thickness of the smart card may increase.

[0084] At this time, a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be provided to penetrate the adhesive layer (130) together with the substrate (110). For example, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate from one side of the adhesive layer (130) to the second side (110S2) of the substrate (110). For example, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be formed through a process such as punching while the adhesive layer (130) is placed on the substrate (110), thereby allowing the substrate (110) and the adhesive layer (130) to penetrate in common.

[0085] The planar surface area of ​​the adhesive layer (130) can correspond to the planar surface area of ​​the substrate (110). For example, the adhesive layer (130) can cover the first surface (110S1) of the substrate (110) entirely. Thus, the rigidity of the substrate (110) can be further improved.

[0086] The conductive pattern portion (120) may be disposed on the first surface (110S1) of the substrate (110). The conductive pattern portion (120) may refer to a pattern disposed on the contact surface of the substrate (110).

[0087] The conductive pattern portion (120) may include a plurality of conductive patterns. For example, the conductive pattern portion (120) has a plurality of electrode patterns spaced apart from each other along the horizontal direction. For example, the conductive pattern portion (120) may include a plurality of pads. In this case, the number of the plurality of conductive patterns of the conductive pattern portion (120) may correspond to the number of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, there may be eight through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), and accordingly, the conductive pattern portion (120) may include first to eighth conductive patterns (120-1, 120-2, 120-3, 120-4, 120-5, 120-6, 120-7, 120-8) spaced apart from each other along the horizontal direction. One side of the first to eighth conductive patterns (120-1, 120-2, 120-3, 120-4, 120-5, 120-6, 120-7, 120-8) may be a contact surface that contacts or does not contact an external terminal to transmit information of the circuit board (100) for a smart card to the outside. Additionally, the other surface of the first to eighth conductive patterns (120-1, 120-2, 120-3, 120-4, 120-5, 120-6, 120-7, 120-8) may be a bonding surface that is wire-bonded to a terminal of a chip mounted on a circuit board (100) for a smart card. The first to eighth conductive patterns (120-1, 120-2, 120-3, 120-4, 120-5, 120-6, 120-7, 120-8) may be upper conductive patterns disposed on the first surface (110S1) of the substrate (110).

[0088] Each of the first to eighth conductive patterns (120-1, 120-2, 120-3, 120-4, 120-5, 120-6, 120-7, 120-8) may be provided with a plurality of layers. The first to eighth conductive patterns (120-1, 120-2, 120-3, 120-4, 120-5, 120-6, 120-7, 120-8) may have the same layer structure.

[0089] Referring to FIG. 3, the conductive pattern portion (120) is formed by a metal layer (121).

[0090] A metal layer (121) is disposed on a substrate (100). A metal layer (121) is disposed on an adhesive layer (130). The metal layer (121) comprises a metallic material. Specifically, the metal layer (121) may comprise an alloy.

[0091] More specifically, the metal layer (121) in the first embodiment may be a first alloy having a first color. Alternatively, the metal layer (121) in the second embodiment may be a second alloy having a second color different from the first color. In this case, the first color may be gold. Additionally, the second color may be gray or silver. This is described in detail below.

[0092] The metal layer (121) may have a thickness within a set range. For example, the thickness of the metal layer (121) may be 30 µm to 75 µm, 40 µm to 65 µm, or 50 µm to 60 µm. If the thickness of the metal layer (121) is less than 30 µm, the resistance of the metal layer (121) increases. Additionally, if the thickness of the metal layer (121) exceeds 75 µm, the thickness of the circuit board (100) for the smart card may increase. As a result, the size of the smart card may increase or the process efficiency may decrease.

[0093] A buffer layer (122) may be disposed between the substrate (110) and the metal layer (121). The buffer layer (122) is disposed on the substrate (100). The buffer layer (122) is disposed on the adhesive layer (130). The buffer layer (122) is disposed under the metal layer (121). For example, the buffer layer (122) is disposed between the adhesive layer (130) and the metal layer (121).

[0094] The buffer layer (122) may be provided in multiple layers. For example, the buffer layer (122) may include a first buffer layer (122-1) and a second buffer layer (122-2). The first buffer layer (122-1) is placed on the adhesive layer (130), and the second buffer layer (122-2) is placed on the first buffer layer (122-1). That is, the first buffer layer (122-1) may be placed between the substrate (110) and the second buffer layer (122-2). The second buffer layer (122-2) is placed between the first buffer layer (122-1) and the metal layer (121).

[0095] A buffer layer (122) may be provided to improve the adhesion between the adhesive layer (130) and the metal layer (121). That is, the metal layer (121) may include an alloy.

[0096] At this time, the metal layer (121) may have corrosion resistance, oxidation resistance, wear resistance, and hardness above a certain level. Accordingly, the embodiment may omit the upper cover layer or upper surface treatment layer provided to impart corrosion resistance, oxidation resistance, wear resistance, and hardness on the metal layer (121).

[0097] In the first embodiment, the metal layer (121) may have a first color. For example, the metal layer (121) may have a gold color. Specifically, the embodiment may have the same or a similar color as the conductive pattern portion (preferably, the upper cover layer) of the first comparative example, while ensuring that the metal layer (121) satisfies a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0098] For example, the conductive pattern portion of the first comparative example includes a metal layer and a first cover layer. In this case, the first cover layer forms the outer surface of the conductive pattern portion. Accordingly, the color of the conductive pattern portion of the first comparative example corresponds to the color of the first cover layer. That is, the first cover layer of the first comparative example includes gold (Au). Accordingly, the conductive pattern portion of the first comparative example has a gold color.

[0099] At this time, the first embodiment provides a conductive pattern portion (120) using a metal layer (121) corresponding to the characteristics and color of the first cover layer described above. Through this, the embodiment can provide a conductive pattern portion (120) having the same appearance as the first comparative example while removing the first cover layer.

[0100] For example, the metal layer (121) in the first embodiment is formed of a first alloy. The first alloy comprises a plurality of metals. Preferably, the first alloy may comprise copper (Cu), nickel (Ni), and zinc (Zn).

[0101] The first alloy may contain copper (Cu) having a content of 50 weight% to 80 weight%. Preferably, the content of copper (Cu) in the first alloy may be 52 weight% to 78 weight%. More preferably, the content of copper (Cu) in the first alloy may be 55 weight% to 75 weight%.

[0102] If the copper (Cu) content in the first alloy constituting the metal layer (121) is less than 50 weight%, the adhesion between the metal layer (121) and the substrate (100) may be reduced. As a result, a problem may occur where the metal layer (121) separates from the substrate (100). Additionally, if the copper (Cu) content in the first alloy is less than 50 weight%, it may be difficult for the metal layer (121) to have corrosion resistance, oxidation resistance, wear resistance, and hardness above a certain level. Furthermore, if the copper (Cu) content in the first alloy exceeds 80 weight%, the nickel (Ni) content and / or zinc (Zn) content may be reduced accordingly. As a result, it may be difficult for the nickel (Ni) content and / or zinc (Zn) content to satisfy the range described below, and the metal layer (121) may not satisfy corrosion resistance, oxidation resistance, wear resistance, and hardness above a certain level.

[0103] The first alloy may contain nickel (Ni) having a content of 1.0 wt% to 5.0 wt%. Preferably, the content of nickel (Ni) in the first alloy may be 1.2 wt% to 4.0 wt%. More preferably, the content of nickel (Ni) in the first alloy may be 1.3 wt% to 3.5 wt%.

[0104] If the nickel (Ni) content in the first alloy constituting the metal layer (121) is less than 1.0 weight%, the rate of change in surface roughness of the conductive pattern portion (120) including the metal layer (121) may increase, and the signal characteristics may be degraded accordingly. Additionally, if the nickel (Ni) content in the first alloy is less than 1.0 weight%, the corrosion resistance, oxidation resistance, wear resistance, and hardness of the metal layer (121) may be reduced. Additionally, if the nickel (Ni) content in the first alloy exceeds 5.0 weight%, the processability in the process of etching the metal layer (121) to form a pattern may be reduced. Additionally, if the nickel (Ni) content in the first alloy exceeds 5.0 weight%, the corrosion resistance, oxidation resistance, wear resistance, and hardness of the metal layer (121) may be reduced.

[0105] The first alloy may contain zinc (Zn) having a content of 18% to 45% by weight. Preferably, the content of zinc (Zn) in the first alloy may be 20% to 43% by weight. More preferably, the content of zinc (Zn) in the first alloy may be 23% to 40% by weight.

[0106] If the zinc (Zn) content in the first alloy constituting the metal layer (121) is less than 18 weight%, it may be difficult for the metal layer (121) to have a gold color or a color similar to gold. As a result, customer satisfaction may be reduced. Additionally, if the zinc (Zn) content in the first alloy constituting the metal layer (121) exceeds 45 weight%, the corrosion resistance, oxidation resistance, wear resistance, and hardness of the metal layer (121) may be reduced.

[0107] Additionally, the content of each metal element in the metal layer (121) may vary along the thickness direction. For example, the content of copper (Cu) in the metal layer (121) may vary along the thickness direction in the metal layer (121).

[0108] Preferably, the copper (Cu) content in the metal layer (121) may increase as it moves toward the substrate (100). For example, the metal layer (121) may include a lower surface in contact with the buffer layer (122) and an upper surface opposite to the lower surface. Also, the copper (Cu) content in the metal layer (121) may decrease as it moves from the lower surface toward the upper surface. Alternatively, the copper (Cu) content in the metal layer (121) may increase as it moves from the upper surface toward the lower surface. For example, the copper (Cu) content in the region adjacent to the lower surface of the metal layer (121) may be greater than the copper (Cu) content in the region adjacent to the upper surface of the metal layer (121). By doing so, the embodiment can further improve the adhesion between the metal layer (121) and the buffer layer (122), and thereby further improve the electrical reliability and / or mechanical reliability of the circuit board for the smart card.

[0109] Additionally, the nickel (Ni) content in the metal layer (121) may vary as it extends toward the buffer layer (122). For example, the nickel (Ni) content in the metal layer (121) may increase as it extends from the bottom surface toward the top surface. That is, the nickel (Ni) content in the region adjacent to the buffer layer (122) of the metal layer (121) may be lower than the nickel (Ni) content in the region adjacent to the top surface of the metal layer (121). Thus, the embodiment can improve the corrosion resistance, oxidation resistance, wear resistance, and hardness of the metal layer (121) while ensuring that the metal layer (121) has a gold color identical or similar to the color of the cover layer of the comparative example.

[0110] Additionally, the zinc (Zn) content in the metal layer (121) may vary as it extends toward the buffer layer (122). For example, the zinc (Zn) content in the metal layer (121) may increase as it extends from the bottom surface toward the top surface. That is, the zinc (Zn) content in the area adjacent to the buffer layer (122) of the metal layer (121) may be lower than the zinc (Zn) content in the area adjacent to the top surface of the metal layer (121). Thus, the embodiment can improve the corrosion resistance, oxidation resistance, wear resistance, and hardness of the metal layer (121) while ensuring that the metal layer (121) has a gold color identical or similar to the color of the cover layer of the comparative example.

[0111] In addition, in the first embodiment, a cover layer is not placed on the metal layer (121), and accordingly, even if a part of the metal layer (121) is scratched, there is no change in color. That is, conventionally, a cover layer is placed on the metal layer, and as a result, a part of the metal layer may be exposed as a result of scratching the cover layer. And the exposed part of the metal layer may be perceived as a stain. In contrast, in the embodiment, since a cover layer is not placed on the metal layer (121), even if a scratch occurs on the metal layer (121), there is no change in color, so it may not be perceived from the outside. Therefore, the embodiment can further improve product reliability and further improve customer satisfaction.

[0112] Additionally, the metal layer (121) in the second embodiment is formed from a second alloy. The second alloy comprises a plurality of metals. Preferably, the second alloy may include copper (Cu), nickel (Ni), manganese (Mn), and zinc (Zn). Specifically, the second alloy of the second embodiment may be provided as a second alloy having a color identical or similar to the color of the silver-colored cover layer of the second comparative example, while possessing a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0113] The second alloy may contain copper (Cu) having a content of 60 weight% to 85 weight%. Preferably, the content of copper (Cu) in the second alloy may be 52 weight% to 82 weight%. More preferably, the content of copper (Cu) in the second alloy may be 55 weight% to 75 weight%.

[0114] If the copper (Cu) content in the second alloy constituting the metal layer (121) is less than 60 weight%, the adhesion between the metal layer (121) and the substrate (100) may be reduced. As a result, a problem may occur where the metal layer (121) separates from the substrate (100). Additionally, if the copper (Cu) content in the second alloy is less than 60 weight%, it may be difficult for the metal layer (121) to have corrosion resistance, oxidation resistance, wear resistance, and hardness above a certain level. Furthermore, if the copper (Cu) content in the second alloy exceeds 85 weight%, the nickel (Ni), manganese (Mn), and / or zinc (Zn) content may be reduced accordingly. As a result, it is difficult to satisfy the range of nickel (Ni), manganese (Mn) and / or zinc (Zn) content described below, and the metal layer (121) may not satisfy corrosion resistance, oxidation resistance, wear resistance, and hardness above a certain level.

[0115] The second alloy may contain nickel (Ni) having a content of 10 weight% to 40 weight%. Preferably, the content of nickel (Ni) in the second alloy may be 12 weight% to 38 weight%. More preferably, the content of nickel (Ni) in the second alloy may be 15 weight% to 35 weight%.

[0116] If the nickel (Ni) content in the second alloy constituting the metal layer (121) is less than 10 weight%, the rate of change in surface roughness of the conductive pattern portion (120) including the metal layer (121) may increase, and the signal characteristics may be degraded accordingly. If the nickel (Ni) content in the second alloy constituting the metal layer (121) is less than 10 weight%, it may be difficult for the metal layer (121) to have a gray color or a silver color. In addition, if the nickel (Ni) content in the second alloy is less than 10 weight%, the corrosion resistance, oxidation resistance, wear resistance, and hardness of the metal layer (121) may be reduced. In addition, if the nickel (Ni) content in the second alloy exceeds 40 weight%, the processability in the process of etching the metal layer (121) to form a pattern may be reduced. In addition, if the nickel (Ni) content in the second alloy exceeds 40 weight%, the corrosion resistance, oxidation resistance, wear resistance, and hardness of the metal layer (121) may be reduced.

[0117] Additionally, the second alloy may contain zinc (Zn) having a content of 0.05 weight% to 1 weight%. Preferably, the content of zinc (Zn) in the second alloy may be 0.08 weight% to 0.9 weight%. More preferably, the content of zinc (Zn) in the second alloy may be 0.1 weight% to 0.8 weight%.

[0118] Additionally, the second alloy may contain manganese (Mn) having a content of 0.07 wt% to 1.5 wt%. Preferably, the content of manganese (Mn) in the second alloy may be 0.1 wt% to 1.2 wt%. More preferably, the content of manganese (Mn) in the second alloy may be 0.1 wt% to 1.0 wt%.

[0119] Manganese (Mn) and zinc (Zn) in the second alloy may be additives added to refine the structure of the second alloy and achieve solid solution strengthening.

[0120] If the above-described manganese (Mn) and / or zinc (Zn) is below the above-described range, the solid solution strengthening effect is insufficient, and consequently, the wear resistance, oxidation resistance, and corrosion resistance of the metal layer (121) may be reduced. Specifically, if the above-described manganese (Mn) and / or zinc (Zn) is below the above-described range, the metal elements do not mix well with each other during the process of manufacturing the second alloy, making it difficult to achieve crystal structuring, and as a result, a problem may occur in which the crystalline phase of the alloy becomes larger (e.g., a problem in which it is difficult to refine the crystalline phase).

[0121] Additionally, if the above-described manganese (Mn) and / or zinc (Zn) exceeds the above-described range, the resistance characteristics of the metal layer (121) increase, and the signal loss may increase accordingly.

[0122] In addition, the metal layer (121) provided as the second alloy may also have a change in the content of metal elements along the thickness direction, corresponding to the metal layer (121) provided as the first alloy.

[0123] For example, the metal layer (121) may have a copper (Cu) content in the region adjacent to the buffer layer (122) that is greater than the copper (Cu) content in the region adjacent to the upper surface of the metal layer (121). Additionally, the metal layer (121) may have a nickel (Ni) content in the region adjacent to the buffer layer (122) that is less than the nickel (Ni) content in the region adjacent to the upper surface of the metal layer (121). Additionally, the metal layer (121) may have a zinc (Zn) content in the region adjacent to the buffer layer (122) that is less than the zinc (Zn) content in the region adjacent to the upper surface of the metal layer (121). Additionally, the metal layer (121) may have a manganese (Mn) content in the region adjacent to the buffer layer (122) that is less than the manganese (Mn) content in the region adjacent to the upper surface of the metal layer (121).

[0124] Accordingly, the process efficiency of the circuit board for a smart card according to the embodiment is improved. In addition, the embodiment can remove the upper cover layer, and thereby reduce the thickness of the circuit board for a smart card.

[0125] A buffer layer (122) may be disposed between the metal layer (121) and the substrate (110) or the adhesive layer (130). The buffer layer (122) may be disposed between the lower surface of the metal layer (121) and the upper surface of the adhesive layer (130).

[0126] The buffer layer (122) may be provided in multiple layers. For example, the buffer layer (122) may include a first buffer layer (122-1) and a second buffer layer (122-2). The first buffer layer (122-1) is placed on the adhesive layer (130). The second buffer layer (122-2) is placed on the first buffer layer (122-1). That is, the second buffer layer (122-2) is placed between the first buffer layer (122-1) and the metal layer (121).

[0127] The second buffer layer (122-2) may include a metal. For example, the second buffer layer (122-2) may include nickel. The adhesion between the metal layer (121) and the first buffer layer (122-1) is improved by the second buffer layer (122-2). That is, the first buffer layer (122-1) may be directly formed on the lower surface of the metal layer (121) to improve adhesion with the adhesive layer (130). In this case, the first buffer layer (122-1) may include copper. However, if the first buffer layer (122-1) is directly formed on the lower surface of the metal layer (121), the adhesion between the metal layer (121) and the first buffer layer (122-1) may be reduced. Therefore, the second buffer layer (122-2) may be placed between the metal layer (121) and the first buffer layer (122-1). A second buffer layer (122-2) may be provided to improve the adhesion between the metal layer (121) and the first buffer layer (122-1).

[0128] The first buffer layer (122-1) may include a metal. For example, the first buffer layer (122-1) may include copper (Cu). The adhesion between the metal layer (121) and the adhesive layer (130) is enhanced by the first buffer layer (122-1).

[0129] Referring to FIG. 4, the metal content of the first buffer layer (122-1) may vary along the thickness direction or the horizontal direction. For example, the first buffer layer (122-1) contains copper, and the copper content in the first buffer layer (122-1) may vary along the thickness direction and the horizontal direction.

[0130] That is, the first buffer layer (122-1) can be divided into multiple parts based on the copper content. For example, the first buffer layer (122-1) may include a first-1 buffer layer (122-11) and a first-2 buffer layer (122-12). The first-2 buffer layer (122-12) may be provided on the lower surface and side surface of the first-1 buffer layer (122-11).

[0131] The first-1 buffer layer (122-11) and the first-2 buffer layer (122-12) are formed integrally. The first-1 buffer layer (122-11) may include a metal. That is, the first-1 buffer layer (122-11) is a metal layer. For example, the first-1 buffer layer (122-11) may include copper. For example, the first-1 buffer layer (122-11) may be a metal layer containing pure copper.

[0132] The first-2 buffer layer (122-12) may include a metal oxide. That is, the first-2 buffer layer (122-12) is a metal oxide layer. For example, the first-2 buffer layer (122-12) may include copper oxide.

[0133] Accordingly, the copper content in the first-1 buffer layer (122-11) may differ from the copper content in the first-2 buffer layer (122-12). For example, the copper content in the first-1 buffer layer (122-11) may be greater than the copper content in the first-2 buffer layer (122-12). This can solve the problem of electrical properties degrading in the region adjacent to the metal layer (121).

[0134] The first-2 buffer layer (122-12) may be an oxide layer formed by oxidizing a portion of the first buffer layer (122-1). The first-2 buffer layer (122-12) may include an oxide of the metal constituting the first buffer layer (122-1). That is, the first buffer layer (122-1) may include an unoxidized first-1 buffer layer (122-11) and an oxidized first-2 buffer layer (122-12). For example, the first-2 buffer layer (122-12) may be a blackened layer formed by blackening a portion of the first buffer layer (122-1).

[0135] The surface roughness of the first-2 buffer layer (122-12) is increased by an oxidation process. That is, the surface roughness of the first-2 buffer layer (122-12) facing the adhesive layer (130) may be greater than the surface roughness of the first-1 buffer layer (122-11).

[0136] In detail, the surface roughness of the first-2 buffer layer (122-12) may be greater than the surface roughness of the metal layer (121). Additionally, the surface roughness of the first-2 buffer layer (122-12) may be greater than the surface roughness of the first buffer layer (122-1). Furthermore, the surface roughness of the first-2 buffer layer (122-12) may be greater than the surface roughness of the cover layer (123) described below. In detail, the surface roughness of the first-2 buffer layer (122-12) may be greater than the surface roughness of the first cover layer (123-1). Additionally, the surface roughness of the first-2 buffer layer (122-12) may be greater than the surface roughness of the second cover layer (123-2). Furthermore, the surface roughness of the first-2 buffer layer (122-12) may be greater than the surface roughness of the substrate (100).

[0137] The surface roughness between one side of the first-2 buffer layer (122-12) and the adhesive layer (130) may be greater than the surface roughness between the first-1 buffer layer (122-11) and the first-2 buffer layer (122-12). Additionally, the surface roughness between one side of the first-2 buffer layer (122-12) and the adhesive layer (130) may be greater than the surface roughness between the first side (1S) of the substrate and the other side of the adhesive layer (130). Furthermore, the surface roughness between one side of the first-2 buffer layer (122-12) and the adhesive layer (130) may be greater than the surface roughness between the metal layer (121) and the first buffer layer (420).

[0138] The first-2 buffer layer (122-12) may have a plurality of parts. The first-2 buffer layer (122-12) may include a first part (122-12a) and a second part (122-12b).

[0139] The first part (122-12a) and the second part (122-12b) of the first-2 buffer layer (122-12) may be provided on different surfaces of the first-1 buffer layer (122-11). For example, the first part (122-12a) of the first-2 buffer layer (122-12) may be provided on the lower surface of the first-1 buffer layer (122-11). For example, the first part (122-12a) of the first-2 buffer layer (122-12) may be placed between the first-1 buffer layer (122-11) and the adhesive layer (130). The first part (122-12a) of the first-2 buffer layer (122-12) may be provided to improve the adhesion between the first-1 buffer layer (122-11) and the adhesive layer (130), further between the second buffer layer (122-2) and the adhesive layer (130), and further between the metal layer (121) and the adhesive layer (130).

[0140] The second part (122-12b) of the first-2 buffer layer (122-12) may be provided on the side of the first-1 buffer layer (122-11). The second part (122-12b) of the first-2 buffer layer (122-12) can resolve reliability issues occurring on the side of the first-1 buffer layer (122-11).

[0141] For example, the embodiment omits the cover layer disposed on the metal layer (121) by using the metal layer (121). In this case, the conductive pattern portion (120) may include a plurality of conductive patterns spaced apart from each other with a spaced-apart region in between. In this case, the side of the metal layer (121), the side of the first buffer layer (122-1), and the side of the second buffer layer (122-2) may be exposed in the spaced-apart region. In this case, the first buffer layer (122-1) contains copper, and accordingly, reliability issues may occur on the side of the first buffer layer (122-1) in a usage environment where a circuit board for a smart card is used. For example, in a usage environment where a circuit board for a smart card is used, copper chloride may be generated due to various factors (e.g., user's sweat or moisture, etc.), and reliability issues such as copper rust may occur as a result.

[0142] Accordingly, the embodiment can solve electrical reliability problems that may occur as the side of the first-1 buffer layer (122-11) is exposed by additionally placing the second part (122-12b) of the first-2 buffer layer (122-12) on the side of the first-1 buffer layer (122-11). Furthermore, the embodiment can prevent the occurrence of rust, etc. by using the second part (122-12b) of the first-2 buffer layer (122-12), and can improve the appearance defect of the conductive pattern part (120) accordingly.

[0143] That is, a second part (122-12b) of a first-second buffer layer (122-12) is provided on the side of each first-first buffer layer (122-11) of a plurality of conductive patterns. For example, a second part (122-12b) of a first-second buffer layer (122-12) that faces each other directly with a spaced-apart region between them may be disposed on the side of each first-first buffer layer (122-11) of adjacent first and second conductive patterns. This allows the electrical reliability of the plurality of conductive patterns to be further improved.

[0144] The adhesion between the metal layer (121) and the adhesive layer (130) can be improved by the buffer layer (122). Specifically, the buffer layer (122) includes a first-second buffer layer (122-12). A first portion (122-12a) of the first-second buffer layer (122-12) faces the adhesive layer (130). Accordingly, the adhesion area between the first-second buffer layer (122) and the adhesive layer (130) is increased by the first portion (122-12a) of the first-second buffer layer (122-12). Thus, the adhesion between the metal layer (121) and the adhesive layer (130) is improved. Therefore, the metal layer (121) can be formed easily. Additionally, the detachment of the metal layer (121) can be prevented. Accordingly, the process efficiency and reliability of the circuit board for a smart card can be improved.

[0145] Additionally, electrical reliability and appearance defects of the conductive pattern portion (120) can be improved by the second portion (122-12b) of the first-second buffer layer (122-12). For example, as the metal layer (121) is formed, the upper cover layer is omitted, which may result in a problem of reduced electrical reliability due to copper chloride formation on the side of the first-first buffer layer (122-11), and / or appearance defects due to rust formation. The second portion (122-12b) of the first-second buffer layer (122-12) is positioned on the side of the first-first buffer layer (122-11). Accordingly, reliability problems that may occur due to the omission of the upper cover layer can be resolved. That is, the embodiment can improve the electrical characteristics of the circuit board for a smart card and, consequently, improve the appearance defects of the circuit board for a smart card. Furthermore, the embodiment can suppress the growth of copper dendrites growing through the side of the first-1 buffer layer (122-11). Accordingly, the embodiment can solve electrical reliability problems, such as circuit shorts that may occur due to dendrite growth.

[0146] Referring to FIG. 5, the cover layer (123) is positioned below the metal layer (121). Specifically, the cover layer (123) is positioned on the lower surface of the metal layer (121). The cover layer (123) is positioned over an area that overlaps with the through hole (TH).

[0147] The cover layer (123) may be a bonding portion to which a wire connected to the chip is bonded. For example, the chip and the cover layer (123) are wire-bonded. By this, the chip and the metal layer (121) are electrically connected to the chip.

[0148] The cover layer (123) may include a first cover layer (123-1) and a second cover layer (123-2). The first cover layer (123-1) is disposed on the lower surface of the metal layer (121), and the second cover layer (123-2) is disposed on the lower surface of the first cover layer (123-1). That is, the first cover layer (123-1) is disposed between the metal layer (121) and the second cover layer (123-2).

[0149] The first cover layer (123-1) may include a metal. The first cover layer (123-1) may include the same material as the second buffer layer (122-2). For example, the first cover layer (123-1) may include nickel. The adhesion between the metal layer (121) and the second cover layer (123-2) can be improved by the first cover layer (123-1). That is, the first cover layer (123-1) may be a buffer layer.

[0150] The second cover layer (123-2) may include a metal. The second cover layer (123-2) may include at least one metal among gold, silver, and palladium. The cover layer (123) and the wire may be bonded by the second cover layer (123-2).

[0151] At this time, the buffer layer (122) may be partially disposed on the lower surface of the metal layer (121). For example, the buffer layer (122) may not be disposed on the lower surface of the metal layer (121) in the area overlapping with the through hole (TH) in the vertical direction.

[0152] In detail, the metal layer (121) may be divided into multiple regions. In detail, the metal layer (121) may include a first region and a second region. The first region is a non-overlapping region that does not overlap with the through hole (TH) along the vertical direction. The second region is an overlapping region that overlaps with the through hole (TH) along the vertical direction.

[0153] A buffer layer (122) is disposed on the lower surface of the first region of the metal layer (121). Additionally, a buffer layer (122) is not disposed on the lower surface of the second region of the metal layer (121). That is, the buffer layer (122) is not disposed inside the through hole (TH). By this, the cover layer (123) can come into direct contact with the metal layer (121).

[0154] The buffer layer (122) is a layer provided to improve the adhesion between the metal layer (121) and the adhesive layer (130). The metal layer (121) does not come into contact with the adhesive layer (130) in the area overlapping along the vertical direction of the through hole (TH). Therefore, even if the buffer layer (122) is removed from the lower surface of the second area of ​​the metal layer (121), the adhesion between the metal layer (121) and the adhesive layer (130) can be maintained.

[0155] Additionally, since the buffer layer (122) of the second region on the lower surface of the metal layer (121) is removed, the distance between the cover layer (123) and the metal layer (121) can be shortened. Accordingly, the signal transmitted from the chip can be easily transmitted to the metal layer (121).

[0156] Meanwhile, the second buffer layer (122-2), the first buffer layer (122-1), the first cover layer (123-1), and the second cover layer (123-2) may have a set thickness.

[0157] The thickness (T2) of the second buffer layer (122-2) may be smaller than the thickness (T1) of the first buffer layer (122-1). The thickness (T2) of the second buffer layer (122-2) may be smaller than the thickness (T3) of the first cover layer (123-1). The thickness (T2) of the second buffer layer (122-2) may be larger than the thickness (T4) of the second cover layer (123-2). Here, the thickness of the first buffer layer (122-1) may refer to the vertical distance in the vertical direction from the upper surface of the first-1 buffer layer (122-11) to the lower surface of the first-2 buffer layer (122-12). Preferably, the thickness of the first buffer layer (122-1) here may mean the vertical distance in the vertical direction from the top of the first-1 buffer layer (122-11) to the bottom of the first-2 buffer layer (122-12).

[0158] The thickness (T1) of the first buffer layer (122-1) may be the same as the thickness (T3) of the first cover layer (123-1). Alternatively, the thickness (T1) of the first buffer layer (122-1) may be greater than the thickness (T3) of the first cover layer (123-1). Alternatively, the thickness (T1) of the first buffer layer (122-1) may be smaller than the thickness (T3) of the first cover layer (123-1).

[0159] The thickness (T2) of the second buffer layer (122-2) may be 1 μm or less. For example, the thickness (T2) of the second buffer layer (122-2) may be 0.6 μm to 1 μm, 0.7 μm to 1 μm, or 0.8 μm to 1 μm.

[0160] If the thickness (T2) of the second buffer layer (122-2) is less than 0.6 μm, the adhesion between the second buffer layer (122-2) and the first buffer layer (122-1) may be reduced. As a result, the adhesion between the metal layer (121) and the buffer layer (122) may be reduced. Additionally, if the thickness (T2) of the second buffer layer (122-2) exceeds 1 μm, the process efficiency in the process of forming the buffer layer (122) may be reduced. Furthermore, the process time for removing the buffer layer (122) from the lower surface of the second region of the metal layer (121) may be increased.

[0161] The thickness (T1) of the first buffer layer (122-1) may be 3 µm to 8 µm, 3.5 µm to 7 µm, or 4 µm to 6 µm. If the thickness (T1) of the first buffer layer (122-1) is less than 3 µm, the process of forming the first-second buffer layer (122-12) may be difficult. Consequently, a surface roughness of the desired size may not be formed in the first buffer layer (122-1). Consequently, the adhesion force between the metal layer (121) and the adhesive layer (130) may be reduced. Additionally, if the thickness (T1) of the first buffer layer (122-1) exceeds 8 µm, the process efficiency of forming the buffer layer (122) may be reduced. Furthermore, the process time for removing the buffer layer (122) provided in the second region of the lower surface of the metal layer (121) may be increased.

[0162] The thickness (T3) of the first cover layer (123-1) may be 2 µm to 9 µm, 3 µm to 8 µm, or 4 µm to 7 µm. If the thickness (T3) of the first cover layer (123-1) is less than 2 µm, the adhesion force between the first cover layer (123-1) and the second cover layer (123-2) may be reduced. As a result, the adhesion force between the metal layer (121) and the cover layer (123) may be reduced. Additionally, when wire bonding the chip and the cover layer (123), the plating layer may be damaged by heat and pressure.

[0163] In addition, if the thickness (T3) of the first cover layer (123-1) exceeds 9㎛, the process efficiency of forming the cover layer (123) may be reduced.

[0164] The thickness (T4) of the second cover layer (123-2) may be 0.5 μm or less. Specifically, the thickness (T4) of the second cover layer (123-2) may be 0.1 μm to 0.5 μm, 0.15 μm to 0.4 μm, or 0.2 μm to 0.35 μm. If the thickness (T4) of the second cover layer (123-2) is less than 0.1 μm, the bonding strength between the wire and the second cover layer (123-2) may be reduced. If the thickness (T4) of the second cover layer (123-2) exceeds 0.5 μm, the process cost may increase and the process efficiency may decrease.

[0165]

[0166] Hereinafter, circuit boards for smart cards according to other embodiments will be described with reference to FIGS. 6 to 13. In the following description, descriptions identical or similar to those of the first embodiment will be omitted. Also, the same reference numerals are assigned to components identical to those of the first embodiment.

[0167] FIG. 6 is a cross-sectional view showing a circuit board for a smart card according to a second embodiment, FIG. 7 is a cross-sectional view showing a circuit board for a smart card according to a third embodiment, FIG. 8 is a cross-sectional view showing a circuit board for a smart card according to a fourth embodiment, FIG. 9 is a cross-sectional view showing a circuit board for a smart card according to a fifth embodiment, FIG. 10 is a cross-sectional view showing a circuit board for a smart card according to a sixth embodiment, FIG. 11 is a cross-sectional view showing a circuit board for a smart card according to a seventh embodiment, FIG. 12 is a cross-sectional view showing a circuit board for a smart card according to an eighth embodiment, and FIG. 13 is a cross-sectional view showing a circuit board for a smart card according to a ninth embodiment.

[0168]

[0169] According to the second embodiment with reference to FIG. 6, the first buffer layer (122-1) may include a first-1 buffer layer (122-11) and a first-2 buffer layer (122-12). The first-2 buffer layer (122-12) may include a first part (122-12a) provided on the lower surface of the first-1 buffer layer (122-11) and a second part (122-12b) provided on the side of the first-1 buffer layer (122-11).

[0170] At this time, the thickness (T5) of the first part (122-12a) of the first-2 buffer layer (122-12) may be different from the thickness (T6) of the second part (122-12b) of the first-2 buffer layer (122-12).

[0171] Here, the first part (122-12a) of the first-2 buffer layer (122-12) is provided on the lower surface of the first-1 buffer layer (122-11), and the second part (122-12b) of the first-2 buffer layer (122-12) may be provided on the side of the first-1 buffer layer (122-11).

[0172] Accordingly, the thickness (T5) of the first part (122-12a) of the first-2 buffer layer (122-12) may refer to the thickness in the vertical direction of the first part (122-12a) of the first-2 buffer layer (122-12). Additionally, the thickness (T6) of the second part (122-12b) of the first-2 buffer layer (122-12) may refer to the thickness in the horizontal direction of the second part (122-12b) of the first-2 buffer layer (122-12).

[0173] The thickness (T5) of the first part (122-12a) of the first-second buffer layer (122-12) may be greater than the thickness (T6) of the second part (122-12b) of the first-second buffer layer (122-12). This may be because the functions of the first part (122-12a) of the first-second buffer layer (122-12) and the second part (122-12b) of the first-second buffer layer (122-12) are different from each other.

[0174] That is, the thickness (T6) of the second part (122-12b) of the first-second buffer layer (122-12) is made smaller than the thickness (T5) of the first part (122-12a) of the first-second buffer layer (122-12). By doing so, electrical reliability issues that may arise when the thickness (T6) of the second part (122-12b) of the first-second buffer layer (122-12) is larger than the thickness (T5) of the first part (122-12a) of the first-second buffer layer (122-12) can be resolved. For example, if the thickness (T6) of the second part (122-12b) of the first-second buffer layer (122-12) is equal to or greater than the thickness (T5) of the first part (122-12a) of the first-second buffer layer (122-12), the spacing between adjacent conductive patterns may be reduced, and reliability issues such as electrical short circuits may occur as a result. That is, when the first buffer layer (122-1) is oxidized to form the first-second buffer layer (122-12) corresponding to the oxide layer, the horizontal width of the first buffer layer (122-1) after the oxide layer is formed may be greater than the horizontal width of the first buffer layer (122-1) before the oxide layer is formed. Accordingly, the thickness (T6) of the second part (122-12b) of the first-second buffer layer (122-12) is made smaller than the thickness (T5) of the first part (122-12a) of the first-second buffer layer (122-12), thereby maintaining the spacing between adjacent conductive patterns and solving the problem of reduced electrical reliability.

[0175]

[0176] According to the third embodiment with reference to FIG. 7, a cover layer (123) may be provided on the lower surface of the metal layer (121) in the area where the buffer layer (122) has been removed. For example, a through hole (TH) may be formed by removing the buffer layer (122) together with the substrate (110) and the adhesive layer (130). Then, the cover layer (123) may be provided on the lower surface of the metal layer (121) that overlaps along the vertical direction with the through hole (TH). At this time, the cover layer (123) may be provided by partially filling the area where the buffer layer (122) has been removed. For example, the cover layer (123) may be provided with a uniform thickness on the side of the buffer layer (122) and on the lower surface of the metal layer (121).

[0177] That is, the through hole (TH) may include a through portion formed by removing the buffer layer (122). And, the cover layer (123) may be provided with a uniform thickness along the inner wall and bottom surface of the aforementioned through portion.

[0178] Through this, according to the third embodiment, the plating thickness of the cover layer (123) can be reduced, thereby reducing manufacturing costs.

[0179]

[0180] According to the fourth embodiment with reference to FIG. 8, the buffer layer (122) can be partially removed.

[0181] In detail, the metal layer (121) may be divided into multiple regions. In detail, the metal layer (121) may include a first region and a second region. The first region is a region that does not overlap with the through hole (TH) in the vertical direction. The second region is a region that overlaps with the through hole (TH) in the vertical direction.

[0182] A buffer layer (122) is disposed on the first region. Specifically, a first buffer layer (122-1) and a second buffer layer (122-2) are disposed on the first region. Additionally, a buffer layer (122) is partially disposed on the second region. Specifically, a second buffer layer (122-2) is disposed on the second region. Additionally, a first buffer layer (122-1) is partially disposed on the second region. Specifically, the first-second buffer layer (122-12) on the second region is removed. By doing so, a second buffer layer (122-2) and a first-first buffer layer (122-11) are disposed on the second region. By doing so, the cover layer (123) can come into contact with the first-first buffer layer (122-11).

[0183] The first-2 buffer layer (122-12) is a metal oxide layer. Accordingly, the first-2 buffer layer (122-12) may have little to no electrical conductivity. Accordingly, the cover layer (123) and the metal layer (121) may be insulated by the first-2 buffer layer (122-12). Accordingly, the first-2 buffer layer (122-12) can be removed, and the metal layer (121) and the cover layer (123) can be electrically connected. For example, the first portion (122-12a) of the first-2 buffer layer (122-12) may not be provided on the lower surface of the first-1 buffer layer (122-11) in the area overlapping perpendicularly with the through hole (TH).

[0184] The buffer layer (122) is a layer for the adhesion between the metal layer (121) and the adhesive layer (130). The metal layer (121) is not adhered to the adhesive layer (130) in the area overlapping with the through hole (TH). Therefore, even if the first part (122-12a) of the first-second buffer layer (122-12) in the second area is removed, the adhesion between the metal layer (121) and the adhesive layer (130) can be maintained.

[0185] A cover layer (123) is placed over an area overlapping with a through hole (TH). The cover layer (123) is placed on a metal layer (121). In detail, the cover layer (123) is placed on a buffer layer (122). In detail, the cover layer (123) is placed on a first-1 buffer layer (122-11).

[0186] A second buffer layer (122-2) and a first-1 buffer layer (122-11) remain between the cover layer (123) and the metal layer (121).

[0187] Accordingly, the strength of the wire-bonded area can be increased. The chip and the cover layer (123) can be wire-bonded by heat and pressure. Accordingly, the cover layer (123) may be damaged during the wire-bonding process.

[0188] Accordingly, the circuit board for a smart card according to the fourth embodiment can prevent this. That is, the second buffer layer (122-2) and the first-1 buffer layer (122-11) remain between the cover layer (123) and the metal layer (121). Accordingly, the strength of the wire-bonded area can be improved. Accordingly, damage to the plating layer during the wire bonding process can be prevented. As a result, the reliability of the circuit board for a smart card can be improved.

[0189] Furthermore, as the first buffer layer (122-11) and the second buffer layer (122-2) of the first buffer layer (122-1) remain in the area overlapping vertically with the through hole (TH), the wire bonding length can be reduced, thereby further improving the wire bonding characteristics.

[0190]

[0191] Additionally, according to the fifth embodiment with reference to FIG. 9, the thickness of the first-1 buffer layer (122-11) may vary depending on the region. Specifically, the thickness (T1-1) of the first-1 buffer layer (122-11) in the first region and the thickness (T1-2) of the first-1 buffer layer (122-11) in the second region may differ. Specifically, the thickness (T1-2) of the first-1 buffer layer (122-11) in the second region may be greater than the thickness (T1-1) of the first-1 buffer layer (122-11) in the first region. Specifically, the thickness (T1-2) of the first-1 buffer layer (122-11) may be greater than the thickness (T1-1) of the first-1 buffer layer in the first region by the thickness of the first part (122-12a) of the first-2 buffer layer (122-12).

[0192] The first part (122-12a) of the first-2 buffer layer (122-12) can be formed by selective oxidation. For example, the first buffer layer (122-1) can be oxidized after masking on the second region. Accordingly, the first part (122-12a) of the first-2 buffer layer (122-12) is formed only in the first region and not in the second region.

[0193] Accordingly, the thickness of the first-1 buffer layer (122-11) varies by region. Specifically, in the second region of the first-1 buffer layer (122-11), the first part (122-12a) of the first-2 buffer layer (122-12), which is an oxide layer, is not formed. As a result, the thickness (T1-2) of the first-1 buffer layer (122-11) in the second region may be greater than the thickness (T1-1) of the first-1 buffer layer (122-11) in the first region.

[0194] Accordingly, the thickness of the wire-bonded area is increased. As a result, the strength of the wire-bonded area can be improved. Therefore, damage to the cover layer (123) during the wire bonding process can be prevented. Accordingly, the reliability of the circuit board for the smart card can be improved.

[0195]

[0196] According to the sixth embodiment with reference to FIG. 10, the buffer layer (122) includes a first buffer layer (122-1) and a second buffer layer (122-2). The first buffer layer (122-1) and the second buffer layer (122-2) may have a set thickness. Also, the buffer layer (122) may be partially removed.

[0197] In detail, the metal layer (121) may be divided into multiple regions. In detail, the metal layer (121) may include a first region and a second region. The first region is a region that does not overlap with the through hole (TH). The second region is a region that overlaps with the through hole (TH).

[0198] A buffer layer (122) is disposed on a first region of the metal layer (121). Specifically, a first buffer layer (122-1) and a second buffer layer (122-2) are disposed on the first region of the metal layer (121). Additionally, a buffer layer (122) is partially disposed on a second region of the metal layer (121). Specifically, a second buffer layer (122-2) is disposed on the second region of the metal layer (121). Additionally, the first buffer layer (122-1) is not disposed on the second region of the metal layer (121). Specifically, the first buffer layer (122-1) on the second region of the metal layer (121) is removed. As a result, only the second buffer layer (122-2) is disposed on the second region of the metal layer (121). Accordingly, one side of the second buffer layer (122-2) can be exposed in the through hole (TH). Accordingly, the cover layer (123) comes into contact with the second buffer layer (122-2).

[0199] The buffer layer (122) is a layer for the adhesion between the metal layer (121) and the adhesive layer (130). The metal layer (121) is not adhered to the adhesive layer (130) in the area overlapping with the through hole (TH). Therefore, even if the first buffer layer (122-1) in the second area is removed, the adhesion between the metal layer (121) and the adhesive layer (130) can be maintained.

[0200] The cover layer (123) is placed on an area overlapping with the through hole (TH). At this time, the cover layer (123) may include only the second cover layer (123-2). That is, the first cover layer (123-1) is omitted. The second cover layer (123-2) is placed on the metal layer (121). Specifically, the second cover layer (123-2) is placed on the second buffer layer (122-2).

[0201] The second buffer layer (122-2) may include the same or similar material as the first cover layer (123-1). Accordingly, the second cover layer (123-2) can be easily bonded to the second buffer layer (122-2).

[0202] A second buffer layer (122-2) remains between the second cover layer (123-2) and the metal layer (121). The second buffer layer (122-2) contains the same or similar material as the first cover layer (123-1). Accordingly, the second cover layer (123-2) can be easily bonded to the second buffer layer (122-2).

[0203] Therefore, when wire bonding the chip and the plating layer, the process of forming the first cover layer (123-1) can be omitted. Accordingly, the process efficiency of the circuit board for the smart card can be improved.

[0204]

[0205] According to the seventh embodiment with reference to FIG. 11, the buffer layer (122) can be partially removed.

[0206] In detail, the metal layer (121) may be divided into multiple regions. In detail, the metal layer (121) may include a first region and a second region. The first region of the metal layer (121) is a region that does not overlap with the through hole (TH). The second region of the metal layer (121) is a region that overlaps with the through hole (TH).

[0207] A buffer layer (122) is disposed on a first region of the metal layer (121). Specifically, a first buffer layer (122-1) and a second buffer layer (122-2) are disposed on the first region of the metal layer (121). Additionally, a buffer layer (122) is partially disposed on a second region of the metal layer (121). Specifically, a second buffer layer (122-2) is disposed on the second region of the metal layer (121). Additionally, the first buffer layer (122-1) is not disposed on the second region of the metal layer (121). Specifically, the first buffer layer (122-1) on the second region of the metal layer (121) is removed. As a result, only the second buffer layer (122-2) is disposed on the second region of the metal layer (121). Accordingly, one side of the second buffer layer (122-2) can be exposed in the through hole (TH).

[0208] The first-second buffer layer (122-12) is a metal oxide layer. Accordingly, the first-second buffer layer (122-12) may have little to no electrical conductivity. Accordingly, the cover layer (123) and the metal layer (121) can be insulated by the first-second buffer layer (122-12). Accordingly, the first buffer layer (122-1), which includes the first-second buffer layer (122-12) in the area overlapping along the vertical direction with the through hole (TH), is removed.

[0209] A cover layer (123) is placed over an area that overlaps with a through hole (TH). The cover layer (123) is placed on a metal layer (121). In detail, the cover layer (123) is placed on a buffer layer (122). In detail, the cover layer (123) is placed on a second buffer layer (122-2). Accordingly, the first cover layer (123-1) is in contact with the second buffer layer (122-2).

[0210] A second buffer layer (122-2) remains between the cover layer (123) and the metal layer (121). The second buffer layer (122-2) and the first cover layer (123-1) may contain the same material. For example, the second buffer layer (122-2) and the first cover layer (123-1) may contain nickel.

[0211] Accordingly, the thickness of the first cover layer (123-1) can be reduced. That is, since the first buffer layer (510) remains between the metal layer (121) and the first cover layer (123-1), the thickness of the first cover layer (123-1) can be reduced. Therefore, the process time for forming the first cover layer (123-1) can be shortened.

[0212] In addition, since the second buffer layer (122-2) and the first cover layer (123-1) contain the same material, the signal transmitted from the chip is not interfered with at the interface between the second buffer layer (122-2) and the first cover layer (123-1). Therefore, the electrical characteristics of the circuit board for the smart card can be improved.

[0213]

[0214] According to the eighth embodiment with reference to FIG. 12, the metal layer (121) and the buffer layer (122) can be partially removed.

[0215] In detail, the metal layer (121) may be divided into multiple regions. In detail, the metal layer (121) may include a first region and a second region. The first region of the metal layer (121) is a region that does not overlap with the through hole (TH). The second region of the metal layer (121) is a region that overlaps with the through hole (TH).

[0216] A buffer layer (122) is disposed on the first region of the metal layer (121). Additionally, a buffer layer (122) is not disposed on the second region of the metal layer (121). The buffer layer on the second region of the metal layer (121) is removed. Therefore, the buffer layer (122) of the metal layer (121) is not disposed inside the through hole (TH).

[0217] The buffer layer (122) is a layer for the adhesion between the metal layer (121) and the adhesive layer (130). The metal layer (121) is not adhered to the adhesive layer (130) in the area overlapping with the through hole (TH). Therefore, even if the buffer layer (122) in the second area of ​​the metal layer (121) is removed, the adhesion between the metal layer (121) and the adhesive layer (130) can be maintained.

[0218] Additionally, the second region of the metal layer (121) may be partially removed. Accordingly, the thickness (T5-1) of the first region of the metal layer (121) and the thickness (T5-2) of the second region of the metal layer (121) may differ. Specifically, the thickness (T5-1) of the first region of the metal layer (121) may be greater than the thickness (T5-2) of the second region of the metal layer (121).

[0219] Since the metal layer of the second region of the metal layer (121) is partially removed, the metal layer (121) may include a groove (R). The groove (R) is formed on the second region of the metal layer (121). The groove (R) is formed along the vertical direction in a region corresponding to the through hole (TH). The groove (R) is connected to the through hole (TH).

[0220] A cover layer (123) is placed over an area that overlaps with the through hole (TH). The cover layer (123) is placed on the metal layer (121). The cover layer (123) is formed in a portion of the through hole (TH) and inside the groove (R). The cover layer (123) is placed to fill the interior of the groove (R). Accordingly, a portion of the side of the cover layer (123) comes into contact with the metal layer (121).

[0221] The side of the cover layer (123) comes into contact with the metal layer (121). Accordingly, the contact area between the cover layer (123) and the metal layer (121) is increased. Therefore, the area through which the signal transmitted from the chip travels is increased. Consequently, the electrical characteristics of the circuit board for the smart card can be improved.

[0222] In addition, since the contact area between the cover layer (123) and the metal layer (121) is increased, the bonding strength between the cover layer (123) and the metal layer (121) can be improved.

[0223] Additionally, since the buffer layer (122) is removed in the second region of the metal layer (121), the distance between the cover layer (123) and the metal layer (121) can be shortened. Accordingly, the signal transmitted from the chip can be easily transmitted to the metal layer (121).

[0224]

[0225] In addition, according to the ninth embodiment with reference to FIG. 13, the cover layer (123) may be placed only inside the groove (R). That is, the cover layer (123) may be embedded inside the groove (G).

[0226] Accordingly, the outer surface of the cover layer (123) comes into contact with the metal layer (121) entirely. As a result, the contact area between the cover layer (123) and the metal layer (121) increases. Therefore, the electrical characteristics and bonding strength of the circuit board for the smart card can be improved.

[0227]

[0228] FIG. 14 is a cross-sectional view showing a circuit board for a smart card according to the 10th embodiment.

[0229] A circuit board for a smart card according to the 10th embodiment with reference to FIG. 14 may have a structure in which conductive pattern portions are provided on each side of a substrate (110). For example, the circuit board for a smart card may include a conductive pattern portion (120) disposed on a first surface (110S1) of the substrate (110) and described with reference to FIG. 1 to 13. In this case, the conductive pattern portion (120) described with reference to FIG. 1 to 13 may be referred to as the first conductive pattern portion (120) or the upper conductive pattern portion (120) in a dual-type circuit board for a smart card.

[0230] Additionally, the circuit board for the smart card may further include a second conductive pattern portion (150) or a lower conductive pattern portion (150) disposed on the second surface (110S2) of the substrate (110). Hereinafter, this will be described as the second conductive pattern portion.

[0231] The second conductive pattern portion (150) may be spaced apart from the first conductive pattern portion (120) with the substrate (110) in between. The second conductive pattern portion (150) may be an antenna pad for an antenna function. For example, the second conductive pattern portion (150) may be an antenna pad that electrically connects a chip mounted on a circuit board (100) for a smart card and an antenna pattern.

[0232] A second adhesive layer (140) may be provided between the second surface (110S2) of the substrate (110) and the second conductive pattern portion (150). The second adhesive layer (140) may provide adhesive force for attaching a pre-manufactured second conductive pattern portion (150) to the second surface (110S2) of the substrate (110).

[0233]

[0234] FIG. 15 is a plan view showing a smart IC module according to one embodiment, and FIG. 16 is a cross-sectional view showing a smart IC module according to an embodiment. Preferably, FIG. 16 may show a plan view of the other side of the smart IC module in a state where the molding member (1300) is not placed.

[0235] Referring to FIGS. 15 and 16, the smart IC module (1000) may include a circuit board for a smart card having the plan view of FIGS. 1 and 2. However, the embodiment is not limited thereto, and the circuit board for a smart card provided in the smart IC module (1000) may include any one of the circuit boards for a smart card selected in FIGS. 3 to 8.

[0236] The smart IC module (1000) may include a chip (1100) placed in a chip mounting area. Here, the chip mounting area may be an inner area of ​​a region surrounded by a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) on the second surface (110S2) of the substrate (110).

[0237] At this time, an adhesive member (not shown) may be disposed in the aforementioned inner region, and a chip (1100) may be attached to the aforementioned adhesive member.

[0238] The chip (1100) may include a plurality of terminals (not shown). For example, the chip (1100) may include first to eighth terminals.

[0239] Additionally, it may include a connecting member (1200) that connects the terminals of the chip (1100) and the pads of the circuit board (100) for the smart card. The connecting member (1200) may be a wire, but is not limited thereto. The connecting member (1200) may include first to eighth connecting members. For example, the connecting member (1200) may include first to eighth connecting members that connect each of the first to eighth pads (120-1, 120-2, 120-3, 120-4, 120-5, 120-6, 120-7, 120-8) exposed through a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) to each of the first to eighth terminals of the chip (1100).

[0240] At this time, the smart IC module (1000) may further include a molding member (1200). The molding member (1200) can mold the chip (1100). Additionally, the molding member (1200) can mold the connecting member (1200). Accordingly, the molding member (1200) may be provided to cover the chip (1100) and the connecting member (1200) while filling the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0241]

[0242] FIG. 17 is a perspective view showing a smart card according to an embodiment, and FIG. 18 is a cross-sectional view schematically showing the smart card of FIG. 17.

[0243] Referring to FIGS. 17 and 18, a smart card (3000) according to an embodiment may include a main body (3100), a first protective layer (3210), and a second protective layer (3220).

[0244] The main body (3100) includes a receiving portion (3110). At this time, any one of the smart IC modules (2000) according to FIGS. 1 to 14 may be manufactured, and the manufactured smart IC module (2000) may be placed inside the receiving portion (3110).

[0245] The receiving portion (3110) may have a step. For example, the inner wall of the receiving portion (3110) may have a step. Preferably, the width of the receiving portion (3110) in the area corresponding to the upper part of the smart card (3000) may be greater than the width in the area corresponding to the lower part of the smart card (3000). Accordingly, the receiving portion (3110) may include a first portion having a first width and a second portion having a second width greater than the first width. Furthermore, the second portion of the receiving portion (3110) may accommodate a chip (1100) and a molding member (1200) provided in the smart IC module, and the first portion of the receiving portion (3110) may accommodate the remaining components of the smart IC module, excluding at least a portion of the chip (1100) and the molding member (1200). Accordingly, the embodiment can further drastically reduce the thickness of the smart card and allow the chip (1100) to be inserted more stably into the smart card.

[0246] At this time, the smart IC module (1000) may be a single-type circuit board for a smart card as illustrated in FIG. 1 to 13, and in this case, an antenna pattern may not be placed on the main body (3100).

[0247] Alternatively, the smart IC module (1000) may include a dual-type circuit board for a smart card according to FIG. 14. In this case, an antenna pattern (not shown) may be disposed on the main body (3100). Specifically, the antenna pattern may be disposed in a coil shape on the edge of the main body (3100). The second portion (132, 137) of the antenna pads provided in the smart IC module (2000) may be connected to the antenna pattern disposed on the main body (3100) described above. A smart card including the smart IC module according to this is operated as a contactless card, a combination card, or a hybrid card.

[0248] The smart IC module (2000) is inserted into the interior of the receiving portion (3110). The smart IC module (2000) and the main body portion (3100) are bonded by an adhesive layer (3120). By this, the smart IC module (2000) is inserted into and fixed in the receiving portion (3110).

[0249] The first protective layer (3210) is disposed on the upper part of the main body (3100). The first protective layer (3210) may include a transparent material. The first protective layer (3210) may include a transparent resin material. The first protective layer (3210) may be disposed in at least one layer. That is, the first protective layer (3210) may include a plurality of layers.

[0250] The second protective layer (3220) is disposed on the lower part of the main body (3100). A magnetic stripe may be disposed on the second protective layer (3220). The second protective layer (3220) may include a transparent material. The second protective layer (3220) may include a transparent resin material. The second protective layer (3220) may be disposed in at least one layer. That is, the second protective layer (3220) may include a plurality of layers.

[0251]

[0252] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the present invention.

[0253] Furthermore, although the above description has focused on the embodiments, this is merely illustrative and does not limit the invention. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments may be modified and implemented. Differences related to such modifications and applications should be interpreted as being included within the scope of the invention as defined in the appended claims.

Claims

1. Recording; and It includes a conductive pattern portion disposed on the above-mentioned substrate, and The conductive pattern portion comprises a buffer layer disposed on the substrate and a metal layer disposed on the buffer layer, and A circuit board for a smart card, wherein the metal layer comprises an alloy including copper, nickel, and zinc.

2. In Paragraph 1, The above metal layer is a circuit board for a smart card having a gold color.

3. In Paragraph 1, In the above metal layer, The copper content is greater than the nickel content and the zinc content, and A circuit board for a smart card, wherein the zinc content is greater than the nickel content.

4. In Paragraph 3, The copper content is 50% to 80% by weight, and The nickel content is 1.0 weight% to 5.0 weight%, and A circuit board for a smart card, wherein the zinc content is 18% to 45% by weight.

5. In Paragraph 4, A circuit board for a smart card, wherein the content of at least one metal among the copper, nickel, and zinc varies along the thickness direction of the substrate within the metal layer.

6. In Paragraph 5, A circuit board for a smart card, wherein the copper content on the first surface of the metal layer in contact with the buffer layer is greater than the copper content on the second surface of the metal layer opposite to the first surface.

7. In Paragraph 5, A circuit board for a smart card, wherein the nickel content on the first surface of the metal layer in contact with the buffer layer is greater than the nickel content on the second surface of the metal layer opposite to the first surface.

8. In Paragraph 5, A circuit board for a smart card, wherein the zinc content on the first surface of the metal layer in contact with the buffer layer is greater than the zinc content on the second surface of the metal layer opposite to the first surface.

9. In Paragraph 1, The alloy of the metal layer further includes manganese, The above metal layer is a circuit board for a smart card having a gray or silver color.

10. In Paragraph 9, In the above metal layer, The copper content is greater than the nickel content, the manganese content, and the zinc content, and A circuit board for a smart card, wherein the nickel content is greater than the manganese content and the zinc content.

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