Variable gain amplifier

Abstract

This variable gain amplifier includes: an amplification unit for amplifying an input signal and outputting the amplified input signal; a load unit which has a first end connected to an output end of the amplification unit; and a current control unit for controlling either an amplified current flowing through the amplification unit or a load current flowing through the load unit such that one is changed at a positive rate, and the other is changed at a negative rate.

Description

Variable Gain Amplifier

[0001] The present invention relates to a variable gain amplifier. This application claims priority based on Japanese Patent Application No. 2024-218439 filed in Japan on December 13, 2024, and incorporates its content herein by reference.

[0002] Patent Document 1 discloses an exponential function generator and a variable gain amplifier using the same. This variable gain amplifier includes input means for amplifying a differential input signal and outputting a voltage signal having a limited fixed gain value, and first and second curve generation means for sampling each of the input control voltages and generating signals that change with different slopes. It also has exponential function generation means for adding the signals output from the first and second curve generation means and outputting a signal having an approximate exponential function value, control current generation means for generating an exponential control current in response to the output signal of the exponential function generation means, and at least one or more variable voltage amplification means for variably amplifying the voltage signal output from the input means in response to the exponential control current, and is implemented by a CMOS process.

[0003] Further, Patent Document 2 discloses an amplifier system including a control variable gain amplifier that limits gain variation while allowing changes in supply voltage, ambient temperature, and / or manufacturing process. In this amplifier system, the variable gain amplifier has a differential pair transistor, a degeneration element connected to the differential pair transistor, and a collector load of the same type as the degeneration element and connected to the differential pair transistor, and the gain of the variable gain amplifier is determined by the physical dimension ratio of the collector load to the degeneration element at a differential input control voltage equal to zero volts.

[0004] Japanese Patent Application Laid-Open No. 2003-198290, Japanese Patent Application Publication No. 2007-500966

[0005] In the above background art, in order to realize a variable gain amplifier with high linearity, a plurality of amplifiers are combined in parallel, and the linearity is improved by the combined output obtained by synthesizing the outputs of each amplifier. However, when a plurality of amplifiers are combined in parallel, the circuit area increases.

[0006] This invention has been made in view of the above circumstances and aims to provide a variable gain amplifier that can ensure linearity while suppressing an increase in circuit area.

[0007] A variable gain amplifier according to a first aspect of the present invention comprises an amplification unit that amplifies an input signal and outputs it, a load unit whose first end is connected to the output terminal of the amplification unit, and a current control unit that controls either the amplification current flowing through the amplification unit or the load current flowing through the load unit to change at a positive rate of change, and the other to change at a negative rate of change.

[0008] A variable gain amplifier according to a second aspect of the present invention is a variable gain amplifier according to a first aspect, wherein the current control unit increases the amplification current flowing through the amplification unit by the positive rate of change and decreases the load current flowing through the load unit by the negative rate of change.

[0009] A variable gain amplifier according to a third aspect of the present invention is a variable gain amplifier according to a first or second aspect, wherein the amplification section comprises a plurality of series-connected amplification transistors, and the load section comprises a plurality of series-connected load transistors.

[0010] A variable gain amplifier according to a fourth aspect of the present invention is a variable gain amplifier according to a third aspect, wherein the sum of the sizes of the plurality of amplification transistors is smaller than the sum of the sizes of the plurality of load transistors.

[0011] A variable gain amplifier according to a fifth aspect of the present invention is a variable gain amplifier according to a third or fourth aspect, comprising a pair of bias circuits that change the amplification current and the load current, respectively, wherein one of the pair of bias circuits is connected to the amplification transistor, and the other of the pair of bias circuits is connected to the load transistor.

[0012] A variable gain amplifier according to a sixth aspect of the present invention is a variable gain amplifier according to a third or fourth aspect, comprising a plurality of bias circuits for changing the amplification current, wherein each of the plurality of bias circuits is connected one-to-one with each of the plurality of amplification transistors.

[0013] A variable gain amplifier according to a seventh aspect of the present invention is a variable gain amplifier according to a third or fourth aspect, wherein the amplification transistor and the load transistor are n-type MOS transistors or p-type MOS transistors.

[0014] According to one aspect of the present invention, it is possible to provide a variable gain amplifier that can ensure linearity while suppressing an increase in circuit area.

[0015] This is a circuit diagram showing the configuration of a variable gain amplifier according to one embodiment of the present invention. This is a characteristic diagram showing the operation of a variable gain amplifier according to one embodiment of the present invention. This is a characteristic diagram showing the performance of a variable gain amplifier according to one embodiment of the present invention.

[0016] One embodiment of the present invention will be described below with reference to the drawings. As shown in Figure 1, the variable gain amplifier A according to this embodiment includes an input terminal Tin, a first transistor 1, a second transistor 2, a first ground terminal Tg1, a third transistor 3, a first bias circuit 4, a second bias circuit 5, a load circuit 6, a power supply terminal Td, a fourth transistor 7, a second ground terminal Tg2, a fifth transistor 8, a sixth transistor 9, a third bias circuit 10, a capacitor 11, and an output terminal Tout.

[0017] Of the first transistor 1, second transistor 2, third transistor 3, fourth transistor 7, fifth transistor 8, and sixth transistor 9, the first transistor 1, second transistor 2, and third transistor 3 are connected in series on their output sides, as shown in the figure. In addition, the fourth transistor 7, fifth transistor 8, and sixth transistor 9 are connected in series on their output sides, separately from the first transistor 1, second transistor 2, and third transistor 3.

[0018] Of the components of the variable gain amplifier A, the first transistor 1, the second transistor 2, the third transistor 3, and the load circuit 6 constitute the amplification section AM in this invention. As will be described in detail later, the amplification section AM in this embodiment functions as an inverting amplifier that inverts and amplifies the input signal (high-frequency signal) of the variable gain amplifier A and outputs it from the output terminal.

[0019] Furthermore, the fourth transistor 7, the fifth transistor 8, the sixth transistor 9, and the capacitor 11 constitute the load section LO in this invention. As will be described in more detail later, the first end (one end) of the load section LO in this embodiment is connected to the output terminal of the amplifier section AM, and functions as a load for the amplifier section AM.

[0020] Furthermore, the first bias circuit 4 and the third bias circuit 10 constitute the current control unit CC in the present invention. In the current control unit CC, the first bias circuit 4 variably controls the amplification current (DC current) that flows through the amplification unit AM, i.e., the amplification drain current Ids. Also, the third bias circuit 10 in the current control unit CC variably controls the load current (DC current) that flows through the load unit LO, i.e., the load drain current Ids2.

[0021] In variable gain amplifier A, input terminal Tin is connected to the gate terminal of the first transistor 1. Input terminal Tin is also connected to a signal source outside of variable gain amplifier A. A high-frequency signal of a predetermined frequency, for example, in the range of several to tens of GHz, is input to input terminal Tin from the signal source.

[0022] The first transistor 1 is an n-type MOS transistor, as shown in the figure. The gate terminal of the first transistor 1 is connected to the input terminal Tin, the source terminal is connected to the drain terminal of the second transistor 2, and the drain terminal is connected to the source terminal of the third transistor 3.

[0023] A high-frequency signal is input to the gate terminal of the first transistor 1 via the input terminal Tin from a signal source, and a first bias voltage (DC voltage) is applied via the input terminal Tin. With the gate voltage set by the first bias voltage, the first transistor 1 inverts and amplifies the high-frequency signal and outputs it to the drain terminal.

[0024] Alternatively, instead of setting the gate voltage of the first transistor 1 with the first bias voltage supplied from the signal source, a bias circuit for setting the gate voltage of the first transistor 1 may be added to the variable gain amplifier A. In this case, only the high-frequency signal, which is an AC component, is input to the input terminal Tin from the signal source.

[0025] The second transistor 2 is an n-type MOS transistor, similar to the first transistor 1. The gate terminal of the second transistor 2 is connected to the output terminal of the first bias circuit 4, the source terminal is connected to the first ground terminal Tg1, and the drain terminal is connected to the source terminal of the first transistor 1. The amplified drain current Ids of the second transistor 2 is set based on the second bias voltage (DC voltage) input to the gate terminal from the first bias circuit 4.

[0026] The first grounding terminal Tg1 is connected to the source terminal of the second transistor 2. Furthermore, the first grounding terminal Tg1 is connected to ground potential (GND) outside of the variable gain amplifier A. The first grounding terminal Tg1 sets the source terminal of the second transistor 2 to ground potential (GND).

[0027] The third transistor 3 is an n-type MOS transistor, similar to the first transistor 1 and the second transistor 2. The gate terminal of the third transistor 3 is connected to the output terminal of the second bias circuit 5, the source terminal is connected to the drain terminal of the first transistor 1, and the drain terminal is connected to the first terminal of the load circuit 6, the gate and drain terminals of the sixth transistor 9, and the first terminal of the capacitor 11. The operating point of the third transistor 3 is set based on the third bias voltage (DC voltage) input to the gate terminal from the second bias circuit 5.

[0028] The first transistor 1, the second transistor 2, and the third transistor 3 that constitute the amplification section AM are all amplification transistors of the same size. In other words, the first transistor 1, the second transistor 2, and the third transistor 3 are process-designed to have the same element size.

[0029] Furthermore, the combined size of the first transistor 1, the second transistor 2, and the third transistor 3 (amplifying transistors) is set to be smaller than the combined size of the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9 (load transistors) that constitute the load section LO.

[0030] In this embodiment, the first transistor 1, second transistor 2, and third transistor 3 (amplifying transistors) constituting the amplification section AM are all n-type MOS transistors of the same size. However, other types of transistors may be used for the first transistor 1, second transistor 2, and third transistor 3. For example, p-type MOS transistors may be used for the first transistor 1, second transistor 2, and third transistor 3.

[0031] The output terminal of the first bias circuit 4 is connected to the gate terminal of the second transistor 2. The first bias circuit 4 generates a second bias voltage that is variable within a predetermined voltage range and applies the second bias voltage to the gate terminal of the second transistor 2 as the gate bias voltage. The first bias circuit 4 is a variable voltage source that sets the amplified drain current Ids of the first transistor 1, the second transistor 2, and the third transistor 3, whose output sides are connected in series with each other, to a desired value using the second bias voltage.

[0032] The output terminal of the second bias circuit 5 is connected to the gate terminal of the third transistor 3. The second bias circuit 5 is a fixed voltage source that applies a fixed voltage, the third bias voltage, as the gate voltage (bias voltage) to the gate terminal of the third transistor 3. In other words, the second bias circuit 5 generates the third bias voltage that sets the operating point of the third transistor 3 and outputs it to the gate terminal of the third transistor 3.

[0033] The first bias circuit 4 and the second bias circuit 5 are multiple bias circuits that change the amplification current flowing to the amplification section AM. Each of the first bias circuit 4 and the second bias circuit 5 is connected one-to-one with each of the multiple transistors, namely the second transistor 2 and the third transistor 3 (amplifying transistors).

[0034] The load circuit 6 is a two-terminal circuit in which the first terminal is connected to the drain terminal of the third transistor 3, the gate and drain terminals of the sixth transistor 9, and the first terminal of the capacitor 11, and the second terminal (the other terminal) is connected to the power supply terminal Td. The load circuit 6 has a predetermined impedance and sets the amplification gain gm of the first transistor 1.

[0035] Here, the drain terminal of the third transistor 3, which is interconnected in the amplification unit AM, and the first terminal of the load circuit 6 are the output terminals of the amplification unit AM. That is, the output terminal of the amplification unit AM is connected to the first terminal of the load unit LO, and outputs an amplified signal, obtained by inverting and amplifying the input signal (high-frequency signal), to the load unit LO. The amplification gain gm of the amplification unit AM is varied by changing the amplification drain current Ids (amplification current) flowing through it.

[0036] The power supply terminal Td is connected to the second end of the load circuit 6. The power supply terminal Td is also connected to a DC power supply of a predetermined voltage outside the variable gain amplifier A. The power supply terminal Td supplies operating power to the first transistor 1, the second transistor 2, and the third transistor 3 via the load circuit 6.

[0037] The fourth transistor 7 is an n-type MOS transistor, similar to the first to third transistors 1 to 3. The gate terminal of the fourth transistor 7 is connected to the output terminal of the third bias circuit 10, the source terminal is connected to the second ground terminal Tg2, and the drain terminal is connected to the source terminal of the fifth transistor 8. The load drain current Ids2 of the fourth transistor 7 is set by the fourth bias voltage (DC voltage) input to the gate terminal from the third bias circuit 10.

[0038] The second grounding terminal Tg2 is connected to the source terminal of the fourth transistor 7. Furthermore, the second grounding terminal Tg2 is connected to ground potential (GND) outside of the variable gain amplifier A. The second grounding terminal Tg2 sets the source terminal of the fourth transistor 7 to ground potential (GND).

[0039] The fifth transistor 8 is an n-type MOS transistor, similar to the fourth transistor 7. The gate terminal of the fifth transistor 8 is connected to its own drain terminal and the source terminal of the sixth transistor 9, the drain terminal of the fifth transistor 8 is connected to its own gate terminal and the source terminal of the sixth transistor 9, and the source terminal is connected to the drain terminal of the fourth transistor 7. In other words, the gate terminal and drain terminal of the fifth transistor 8 are connected in common.

[0040] The sixth transistor 9 is an n-type MOS transistor, similar to the fourth transistor 7 and the fifth transistor 8. The gate terminal of the sixth transistor 9 is connected to its own drain terminal, the drain terminal of the third transistor 3, the first terminal of the load circuit 6, and the first terminal of the capacitor 11. The drain terminal of the sixth transistor 9 is connected to its own gate terminal, the drain terminal of the third transistor 3, the first terminal of the load circuit 6, and the first terminal of the capacitor 11. The source terminal is connected to the drain terminal and gate terminal of the fifth transistor 8. In other words, the gate terminal and drain terminal of the sixth transistor 9 are commonly connected, similar to the fifth transistor 8.

[0041] The fourth transistor 7, fifth transistor 8, and sixth transistor 9, which constitute the load section LO, are load transistors of the same size. That is, the fourth transistor 7, fifth transistor 8, and sixth transistor 9 are process-designed to have the same element size.

[0042] Furthermore, the combined size of the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9 (load transistors) is set to be larger than the combined size of the first transistor 1, the second transistor 2, and the third transistor 3 (amplifier transistors).

[0043] In this embodiment, n-type MOS transistors are used as the fourth transistor 7, fifth transistor 8, and sixth transistor 9 that constitute the load section LO, but other types of transistors may be used for the fourth transistor 7, fifth transistor 8, and sixth transistor 9. For example, p-type MOS transistors may be used for the fourth transistor 7, fifth transistor 8, and sixth transistor 9.

[0044] The third bias circuit 10 has its output terminal connected to the gate terminal of the fourth transistor 7. The third bias circuit 10 is a variable voltage source that applies a fourth bias voltage that can be varied within a predetermined voltage range to the gate terminal of the fourth transistor 7 as a gate voltage (bias voltage). That is, the third bias circuit 10 generates a fourth bias voltage that sets the load drain current Ids2 of the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9, whose outputs are connected in series to each other, to a desired value, and outputs it to the gate terminal of the fourth transistor 7.

[0045] Here, the third bias circuit 10 changes the load drain current Ids2 (load current) by applying a fourth bias voltage to the gate terminal of the fourth transistor 7 in the load section LO. On the other hand, the first bias circuit 4 changes the amplification drain current Ids (amplification current) by applying a second bias voltage to the gate terminal of the second transistor 2 in the amplification section AM.

[0046] That is, the first bias circuit 4 and the third bias circuit 10 are a pair of bias circuits that change the amplification current and the load current, respectively. The first bias circuit 4 is connected to the gate terminal of the second transistor 2 (amplification transistor) as one of the pair of bias circuits. The third bias circuit 10 is connected to the gate terminal of the fourth transistor 7 (load transistor) as the other of the pair of bias circuits.

[0047] The capacitor 11 has its first terminal connected to the drain terminal of the third transistor 3, the first terminal of the load circuit 6, and the gate and drain terminals of the sixth transistor 9, and its second terminal (the other terminal) is connected to the output terminal Tout. The capacitor 11 is a coupling capacitor having a predetermined capacitance, and outputs only the amplification signal (high-frequency signal), which is an AC component, among the amplification signal (high-frequency signal) and the drain voltage (DC voltage) input from the output terminal of the amplification section AM to the first terminal, to the output terminal Tout.

[0048] Here, the gate terminal and drain terminal of the sixth transistor 9 and the first end of the capacitor 11 that are interconnected correspond to the first end of the load portion LO connected to the output end of the amplification portion AM. The load portion LO functions as a load for the amplification portion AM. Also, the load drain current Ids2 is an amount that sets the degree of the load of the load portion LO with respect to the amplification portion AM.

[0049] The output terminal Tout is connected to the second end of the capacitor 11. Also, the output terminal Tout is connected to the input end of the subsequent-stage circuit outside the variable gain amplifier A. The output terminal Tout outputs the amplified signal (high-frequency signal), which is the output signal of the variable gain amplifier A, toward the subsequent-stage circuit.

[0050] Next, the operation of the variable gain amplifier A according to the present embodiment will be described in detail with reference to FIGS. 2 and 3.

[0051] In the variable gain amplifier A, an input signal (high-frequency signal) input from a signal source to the input terminal Tin is inversely amplified by the amplification portion AM to obtain an amplified signal (high-frequency signal). Then, the amplified signal (high-frequency signal) is output from the output terminal Tout toward the subsequent-stage circuit via the load portion LO.

[0052] Here, the amplification gain gm of the amplification portion AM changes according to the amplification drain current Ids (amplification current) flowing through the amplification portion AM. That is, the amplification gain gm of the first transistor 1 in the amplification portion AM is an element parameter that varies according to the amplification drain current Ids (amplification current). When the amplification drain current Ids (amplification current) increases, the amplification gain gm of the first transistor 1 also increases. As a result, the amplification gain gm of the amplification portion AM becomes high and the amplitude of the amplified signal increases.

[0053] The load portion LO functions as a load together with the load circuit 6 in the inverse amplification of the input signal (high-frequency signal) in the amplification portion AM. That is, since the first end of the load portion LO is connected to the output end of the amplification portion AM in the same manner as the first end of the load circuit 6, it acts as a part of the load in the inverse amplification of the input signal (high-frequency signal) in the first transistor 1.

[0054] In this relationship between the amplification unit AM and the load unit LO, the current control unit CC in this embodiment varies the amplification gain gm of the amplification unit AM by changing the amplification drain current Ids (amplification current) flowing through the amplification unit AM. In this configuration, CC controls either the amplification drain current Ids (amplification current) flowing through the amplification unit AM or the load drain current Ids2 (load current) flowing through the load unit LO to change at a positive rate of change, while the other changes at a negative rate of change.

[0055] In the current control unit CC, the first bias circuit 4 variably controls the second bias voltage so that the amplification current flowing through the amplification unit AM, i.e., the amplification drain current Ids, gradually increases at a positive rate of change, as shown in Figure 2, for example. On the other hand, the third bias circuit 10 in the current control unit CC variably controls the fourth bias voltage so that the load current flowing through the load unit LO, i.e., the load drain current Ids2, gradually decreases at a negative rate of change.

[0056] In other words, the first bias circuit 4 increases the amplification gain gm of the first transistor 1 by gradually increasing the amplification drain current Ids, thereby increasing the amplification gain gm of the amplification section AM. In contrast, the third bias circuit 10 gradually decreases the load on the amplification section AM by gradually decreasing the load drain current Ids2.

[0057] The variable gain amplifier A according to this embodiment has linearity as shown in the characteristic curve of Figure 3, for example. That is, the linearity of the variable gain amplifier A when the amplification gain gm is varied is improved compared to the reference example without a load section LO. In the characteristic curve of Figure 3, the improvement in linearity is not clearly visible because the horizontal axis is on a linear scale, but the improvement in linearity can be clearly seen when the horizontal axis is on a log (log) scale.

[0058] In other words, the variable gain amplifier A according to this embodiment includes an amplification unit AM that amplifies and outputs an input signal, a load unit LO whose first end is connected to the output terminal of the amplification unit AM, and a current control unit CC that controls either the amplification drain current Ids (amplification current) flowing through the amplification unit AM or the load drain current Ids2 (load current) flowing through the load unit LO to change at a positive rate of change, and the other to change at a negative rate of change.

[0059] Therefore, according to this embodiment, it is possible to provide a variable gain amplifier A that can ensure linearity while suppressing an increase in circuit area by controlling either the amplification current flowing through the amplification section AM or the load current flowing through the load section LO to change at a positive rate of change and the other to change at a negative rate of change.

[0060] Furthermore, in the variable gain amplifier A according to this embodiment, the amplification section AM comprises a plurality of amplification transistors connected in series on the output side, namely a first transistor 1, a second transistor 2, and a third transistor 3. According to this embodiment, it is possible to improve linearity compared to, for example, the case in which the amplification section AM comprises a single amplification transistor.

[0061] Furthermore, in the variable gain amplifier A according to this embodiment, the load section LO comprises a plurality of load transistors, namely the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9, whose output sides are connected in series. According to this embodiment, it is possible to improve linearity compared to, for example, the case in which the load section LO comprises a single load transistor.

[0062] Furthermore, in the variable gain amplifier A according to this embodiment, the sum of the sizes of the first transistor 1, the second transistor 2, and the third transistor 3 (amplifying transistors) is smaller than the sum of the sizes of the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9 (loading transistors). According to this embodiment, it is possible to achieve stable amplification operation with respect to the input signal (high-frequency signal).

[0063] Furthermore, in the variable gain amplifier A according to this embodiment, the amplification transistor and the load transistor are n-type MOS transistors or p-type MOS transistors. According to this embodiment, it is possible to ensure linearity while suppressing an increase in circuit area for a variable gain amplifier A using n-type MOS transistors or p-type MOS transistors as the amplification transistor and load transistor.

[0064] The present invention is not limited to the above embodiments, and the following modifications are possible, for example: (1) In the above embodiments, the case in which the amplified drain current Ids (amplification current) is increased at a positive rate of change and the load drain current Ids2 (load current) is decreased at a negative rate of change, that is, the case in which the amplification gain gm of the amplification unit AM is increased, was described with reference to Figure 3, but the present invention is not limited thereto.

[0065] In other words, the present invention is also applicable when the amplified drain current Ids (amplification current) is decreased at a negative rate of change, and the load drain current Ids2 (load current) is gradually increased at a positive rate of change, that is, when the amplification gain gm of the amplification unit AM is reduced.

[0066] (2) In the above embodiment, the number of amplification transistors and load transistors was set to three, but the present invention is not limited thereto. The number of amplification transistors and load transistors may be other than three.

[0067] For example, the third transistor 3 that constitutes the amplification section AM is an amplification transistor cascode-connected to the first transistor 1, but it may be omitted if necessary. In this case, the second bias circuit 5 is also omitted. Furthermore, the load section LO may be composed of only the sixth transistor 9.

[0068] (3) In the above embodiment, the circuit configuration of the amplification section AM was a common-source inverting amplifier, but the present invention is not limited thereto. That is, the amplification section may be configured with a circuit configuration other than a common-source inverting amplifier.

[0069] (4) In the above embodiment, the load section LO is a series circuit of the fourth transistor 7, the fifth transistor 8, and the sixth transistor 9 (load transistors), with the first end connected to the output terminal of the amplifier AM and the second end (other end) connected to ground potential. However, the present invention is not limited to this. That is, the load section LO only needs to function as a load for the amplifier AM and allow the load current to be varied independently of the amplification current.

[0070] (5) In the above embodiment, the first transistor 1, second transistor 2, third transistor 3, fourth transistor 7, fifth transistor 8, and sixth transistor 9 are unipolar transistors, specifically n-type MOS transistors or p-type MOS transistors, but the present invention is not limited thereto. For example, bipolar transistors may be used instead of unipolar transistors for the first transistor 1, second transistor 2, third transistor 3, fourth transistor 7, fifth transistor 8, and sixth transistor 9.

[0071] A... Variable gain amplifier, Tin... Input terminal, Tg1... First ground terminal, Tg2... Second ground terminal, Td... Power supply terminal, Tout... Output terminal, 1... First transistor, 2... Second transistor, 3... Third transistor, 4... First bias circuit, 5... Second bias circuit, 6... Load circuit, 7... Fourth transistor, 8... Fifth transistor, 9... Sixth transistor, 10... Third bias circuit, 11... Capacitor

Claims

1. A variable gain amplifier comprising: an amplification unit that amplifies an input signal and outputs it; a load unit whose first end is connected to the output terminal of the amplification unit; and a current control unit that controls either the amplification current flowing through the amplification unit or the load current flowing through the load unit to change at a positive rate of change, and the other to change at a negative rate of change.

2. The variable gain amplifier according to claim 1, wherein the current control unit increases the amplification current flowing through the amplification unit by the positive rate of change and decreases the load current flowing through the load unit by the negative rate of change.

3. The variable gain amplifier according to claim 1 or 2, wherein the amplification section comprises a plurality of amplification transistors connected in series, and the load section comprises a plurality of load transistors connected in series.

4. The variable gain amplifier according to claim 3, wherein the sum of the sizes of the plurality of amplification transistors is less than the sum of the sizes of the plurality of load transistors.

5. A variable gain amplifier according to claim 3 or 4, comprising a pair of bias circuits for changing the amplification current and the load current, wherein one of the pair of bias circuits is connected to the amplification transistor, and the other of the pair of bias circuits is connected to the load transistor.

6. A variable gain amplifier according to claim 3 or 4, comprising a plurality of bias circuits for changing the amplification current, wherein each of the plurality of bias circuits is connected one-to-one with each of the plurality of amplification transistors.

7. The variable gain amplifier according to claim 3 or 4, wherein the amplifying transistor and the load transistor are n-type MOS transistors or p-type MOS transistors.

Images