Manufacturing method for integrated memory chip and structure thereof

Abstract

Provided in the present invention are a manufacturing method for an integrated memory chip and a structure thereof. The method comprises manufacturing a chip having an integrated memory function, comprising: on a memory wafer, using a memory reticle set to form a plurality of basic memory arrays at a first process node, wherein each basic memory array is surrounded by a plurality of scribe lines; on a control wafer, using a control reticle set to form a plurality of control chips at a second process node, wherein the first process node is more advanced than the second process node, each of the control chips is configured to control operation of a corresponding memory chip, and the memory chip comprises at least two basic memory arrays; bonding the memory wafer and the control wafer to form a bonded wafer, wherein each of the control chips is bonded to a corresponding memory chip; and dicing the bonded wafer along part (not all) of the scribe lines to form a plurality of integrated memory chips, wherein each of the integrated memory chips comprises a non-diced scribe line.

Description

Manufacturing methods and structures of integrated memory chips

[0001] This application claims priority to the international patent application No. PCT / CN2024 / 139909, filed on December 17, 2024, entitled "Resistive Random Access Memory Using Hybrid Bonding Integration", and the Chinese patent application No. 202510565432.5, filed on April 30, 2025, entitled "Manufacturing Method and Structure of Integrated Memory Chip", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates generally to the field of semiconductor manufacturing, and more specifically to a method for manufacturing an integrated memory chip and its structure. Background Technology

[0003] Resistive variable random access memory (RRAM) is a type of non-volatile memory whose resistance can be switched between a low-resistance state (LRS) and a high-resistance state (HRS) by applying an appropriate voltage. The resistance difference between the low-resistance and high-resistance states allows for the storage of digital data "0" and "1".

[0004] In typical RRAM memory integrated circuits, various peripheral circuits are formed along the RRAM array, and the memory array and peripheral circuits are manufactured using the same process node. However, this is not optimal practice because only the memory array needs to be manufactured using state-of-the-art process technology to achieve high density, while the peripheral circuits can be manufactured using more mature (and less expensive) process nodes.

[0005] Furthermore, even in memory chips employing hybrid bonding, meeting varying memory capacity requirements remains a challenge, as manufacturing chips with different capacities typically necessitates a complete redesign and remanufacturing of the entire chip. Crucially, when chips with different capacities are required, the entire memory wafer manufactured using high-cost advanced node process technologies usually needs to be redesigned and re-fabricated, while control wafers also need to be adjusted simultaneously, leading to a significant increase in manufacturing costs and extended product development cycles. Summary of the Invention

[0006] To address the aforementioned problems, according to an embodiment of the present invention, a dual-chip solution employing heterogeneous integration is provided.

[0007] According to a first aspect of the present invention, a memory device is provided, comprising: a memory chip including a plurality of memory cells manufactured at a first process node; and a control chip including control circuitry manufactured at a second process node, wherein the first process node is more advanced than the second process node, wherein the control chip and the memory chip are bonded together by a hybrid bonding integration technique to form the memory device, and the control circuitry is used to control the operation of the plurality of memory cells within the memory chip.

[0008] In another embodiment of the invention, the control circuit further includes a multiplexer for controlling the source lines or bit lines of the memory cells.

[0009] In another embodiment of the invention, the memory chip does not include a multiplexer for source lines or bit lines used to control memory cells.

[0010] In another embodiment of the invention, the control circuit further includes a decoder for controlling word lines of memory cells.

[0011] In another embodiment of the invention, the memory chip does not include a decoder for controlling word lines of memory cells.

[0012] In another embodiment of the invention, the control circuit further includes an inductive amplifier for amplifying signals from the memory cell.

[0013] In another embodiment of the invention, the control circuit further includes a charge pump for generating the voltage required for the programmable memory cell.

[0014] In another embodiment of the invention, the control chip further includes a processor.

[0015] In another embodiment of the present invention, the control chip further includes analog circuitry.

[0016] In another embodiment of the invention, the control chip further includes a transmitter.

[0017] In another embodiment of the invention, the control chip further includes a sensor.

[0018] In another embodiment of the present invention, the gate length of the transistor in the memory chip is smaller than the gate length of the transistor in the control chip.

[0019] In another embodiment of the invention, the memory chip includes only one type of transistor, while the control chip includes multiple types of transistors.

[0020] In another embodiment of the invention, the memory chip comprises only NMOS transistors.

[0021] In another embodiment of the invention, the memory chip comprises only PMOS transistors.

[0022] In another embodiment of the invention, each memory cell includes a memory element formed on a substrate.

[0023] In another embodiment of the invention, the memory element is selected from the group consisting of: resistive random access memory (RRAM) elements; conductive bridged random access memory (CBRAM) elements; magnetoresistive random access memory (MRAM) elements; ferroelectric random access memory (FeRAM) elements; and phase change random access memory (PCRAM) elements.

[0024] In another embodiment of the invention, each memory cell includes a resistive switching memory element formed on a substrate.

[0025] In another embodiment of the present invention, the memory cell includes: an access transistor formed on the substrate; a contact; a first metal layer; a bottom electrode; the resistive switching memory element; a first via; and a second metal layer, wherein the contact is disposed between the terminal of the access transistor and the first metal layer, the bottom electrode is disposed between the first metal layer and the resistive switching memory element, and the first via is disposed between the resistive switching memory element and the second metal layer.

[0026] In another embodiment of the present invention, the top surface of the memory chip includes a plurality of first conductive pads and a first insulating region, and the top surface of the control chip includes a plurality of second conductive pads and a second insulating region.

[0027] In another embodiment of the present invention, the first conductive pad is bonded to the second conductive pad, and the first insulating region is bonded to the second insulating region.

[0028] In another embodiment of the present invention, the plurality of first conductive pads are connected to a second metal layer within the memory chip through a plurality of memory chip vias, and the plurality of second conductive pads are connected to a second metal layer within the control chip through a plurality of control chip vias, wherein the plurality of memory chip vias have the same length.

[0029] In another embodiment of the invention, the control circuit performs a read operation on the memory cell before performing a write operation on the memory cell.

[0030] In another embodiment of the invention, the control circuit compares the data to be written with the result of a read operation before performing a write operation on the memory cell.

[0031] In another embodiment of the present invention, the control circuit is used to perform the write operation only when the data to be written does not match the result of the read operation.

[0032] According to a second aspect of the present invention, a method for performing a write operation within a memory device is provided, wherein the memory device includes: a memory chip including a plurality of memory cells manufactured at a first process node; and a control chip including control circuitry manufactured at a second process node, wherein the first process node is more advanced than the second process node, wherein the control chip and the memory chip are bonded together to form the memory device, wherein the control circuitry is used to control the operation of the plurality of memory cells within the memory chip, the method comprising: receiving, by the control chip, an address of a memory cell within the memory chip and data to be written to the memory cell; performing a read operation on the memory cell; and performing a write operation on the memory cell after the read operation.

[0033] In another embodiment of the present invention, the method further includes: comparing the data to be written with the result of the read operation before performing the write operation on the memory cell.

[0034] In another embodiment of the present invention, performing a write operation on the memory cell after the read operation includes: performing a write operation on the memory cell only if the data to be written does not match the result of the read operation after the read operation.

[0035] In this invention, the memory chip is manufactured using an advanced process node, while the control chip is manufactured using a mature process node. Subsequently, these two chips are combined using three-dimensional integration techniques such as hybrid bonding to form a fully functional memory chip.

[0036] According to an embodiment of the present invention, only the memory cells are manufactured using advanced process nodes, while the peripheral circuits are manufactured using mature nodes, thereby significantly reducing the cost of memory chips and increasing memory cell density at the same time.

[0037] According to a third aspect of the present invention, a method for manufacturing an integrated memory chip is provided, comprising: forming a plurality of basic memory arrays on a memory wafer using a memory photomask group at a first process node, wherein each of the basic memory arrays is surrounded by a plurality of scribe lines; forming a plurality of control chips on a control wafer using a control photomask group at a second process node, wherein the first process node is more advanced than the second process node, and each of the control chips is configured to control the operation of a corresponding memory chip, the memory chip comprising at least two basic memory arrays; bonding the memory wafer and the control wafer together to form a bonding wafer, wherein each of the control chips is bonded to a corresponding memory chip; and dicing the bonding wafer along a portion (but not all) of the scribe lines to form a plurality of integrated memory chips, wherein each of the integrated memory chips comprises an undicated scribe line.

[0038] In some implementations, each base storage array has the same storage capacity.

[0039] In some embodiments, at least some of the scribe lines include alignment marks or overlap marks, and the method further includes bonding the storage wafer to the control wafer according to the alignment marks or overlap marks.

[0040] In some implementations, a virtual metal layer is not present in the scribed portion containing the alignment mark or overlap mark.

[0041] In some embodiments, at least a portion of the scribing lines include a pattern indicating whether the scribing lines need to be cut, and the method further includes cutting the bonding wafer according to the pattern.

[0042] In some implementations, the control chip is selected from the group consisting of: microcontroller unit (MCU), power management integrated circuit (PMIC), display driver integrated circuit (DDIC), and application-specific integrated circuit (ASIC).

[0043] In some embodiments, the control chip includes control circuitry, wherein the control circuitry includes a multiplexer configured to control the source lines or bit lines of memory cells in the memory chip.

[0044] In some implementations, the memory chip does not include a multiplexer for source lines or bit lines used to control its internal memory cells.

[0045] In some implementations, the memory chip does not include a decoder for controlling the word lines of its internal memory cells.

[0046] In some embodiments, the gate length of the transistor in the memory chip is smaller than the gate length of the transistor in the control chip.

[0047] In some implementations, the memory chip contains only one type of transistor, while the control chip contains multiple types of transistors.

[0048] In some implementations, the memory chip contains only NMOS transistors.

[0049] In some implementations, the memory chip contains only PMOS transistors.

[0050] In some implementations, each memory cell includes a memory element formed on a substrate.

[0051] In some embodiments, the memory element is selected from the group consisting of: resistive random access memory (RRAM), bridge random access memory (BRAM), magnetoresistive random access memory (RAM), ferroelectric random access memory (FRAM), and phase-change random access memory (PCRAM).

[0052] In some embodiments, each memory cell includes a resistive switching memory element formed on a substrate.

[0053] In some embodiments, the memory cell includes: an access transistor formed on a substrate, a contact, a first metal layer, a bottom electrode, the resistive switching memory element, a first via, and a second metal layer, wherein the contact is disposed between a terminal of the access transistor and the first metal layer, the bottom electrode is disposed between the first metal layer and the resistive switching memory element, and the first via is disposed between the resistive switching memory element and the second metal layer.

[0054] In some embodiments, the top surface of the memory chip includes a plurality of first conductive pads and a first insulating region, and the top surface of the control chip includes a plurality of second conductive pads and a second insulating region.

[0055] In some embodiments, a first conductive pad is bonded to a second conductive pad, and the first insulating region is bonded to the second insulating region.

[0056] In some embodiments, a plurality of first conductive pads are connected to a second metal layer in a memory chip through a plurality of memory chip vias, and a plurality of second conductive pads are connected to a second metal layer in a control chip through a plurality of control chip vias, wherein the plurality of memory chip vias have the same length.

[0057] In some embodiments, the method further includes: forming a plurality of basic memory arrays on a second memory wafer using the memory mask group at a first process node, wherein each of the basic memory arrays is surrounded by a plurality of second scribe lines; forming a plurality of second control chips on a second control wafer using a second control mask group different from the control mask group at a second process node, wherein each of the second control chips is configured to control the operation of a corresponding second memory chip, the second memory chip including at least two basic memory arrays; bonding the second memory wafer to the second control wafer to form a second bonded wafer, wherein each of the second control chips is bonded to a corresponding second memory chip; and dicing the second bonded wafer along a subset (but not all) of the second scribe lines to form a plurality of second chips with integrated memory, wherein each second chip with integrated memory includes an undicated second scribe line.

[0058] In some implementations, the memory chip and the second memory chip comprise different numbers of basic memory arrays.

[0059] According to a fourth aspect of the present invention, an integrated memory chip is provided, comprising: a memory chip formed at a first process node, wherein the memory chip includes at least two basic memory arrays and each pair of basic memory arrays is separated by at least one scribe line; and a control chip formed at a second process node, wherein the first process node is more advanced than the second process node, and the control chip is configured to control the operation of the memory chip, wherein the top surface of the memory chip includes a plurality of first conductive pads and a first insulating region, the top surface of the control chip includes a plurality of second conductive pads and a second insulating region, the first conductive pads being bonded to the second conductive pads, and the first insulating region being bonded to the second insulating region.

[0060] In some implementations, each base storage array has the same storage capacity.

[0061] According to embodiments of the present invention, the hybrid bonding technology described above is further optimized for manufacturing chips with different memory capacities. This method only requires redesigning and re-fabrication of control wafers for low-cost, mature process nodes, while memory wafers for high-cost, advanced process nodes can be reused. Therefore, this approach significantly reduces the manufacturing time and cost required to produce chips with different memory capacities. Attached Figure Description

[0062] The embodiments of the present invention will be more readily understood by referring to the following figures.

[0063] Figure 1A is a schematic diagram of a common storage device architecture in the industry.

[0064] Figure 1B is a schematic diagram of a novel storage device architecture employing a hybrid bonding structure according to an embodiment of the present invention.

[0065] Figure 2A is a schematic diagram of the memory chip architecture in a common hybrid bonding structure memory device in the industry.

[0066] Figure 2B is a schematic diagram of a novel multiplexer-free memory chip architecture according to an embodiment of the present invention.

[0067] Figure 3 is a schematic diagram of a novel user-customized storage device architecture employing a hybrid bonding structure according to an embodiment of the present invention.

[0068] Figure 4 is a schematic diagram of a novel storage device architecture employing a hybrid bonding structure according to an embodiment of the present invention.

[0069] Figures 5A and 5B are schematic diagrams showing the thickness and material of each layer in the RRAM stack in the new embedded RRAM process according to an embodiment of the present invention.

[0070] Figure 6 shows a flowchart embodiment of performing a write operation on a storage device according to an embodiment of the present invention.

[0071] Figure 7 shows a commonly used storage device architecture in the industry.

[0072] Figure 8 shows a storage device of an integrated memory according to an embodiment of the present invention.

[0073] Figure 9 is a top view of an integrated memory chip obtained by bonding a memory chip with different control chips according to an embodiment of the present invention.

[0074] Figures 10A and 10B illustrate a storage device for an integrated memory according to an embodiment of the present invention.

[0075] Figure 11 is a top view of storage devices with different storage capacities according to an embodiment of the present invention.

[0076] Figure 12 is a top view of a storage device according to an embodiment of the present invention.

[0077] Figure 13 is a top view of a storage wafer with alignment marks or overlap marks according to an embodiment of the present invention.

[0078] Figure 14 is a top view of a storage wafer with alignment marks according to an embodiment of the present invention.

[0079] Figure 15 is a top view of a storage device according to an embodiment of the present invention. Detailed Implementation

[0080] In typical RRAM memory integrated circuits, in addition to the RRAM array, many peripheral circuits are required to support the RRAM functionality. Figure 1A is a schematic diagram of a common memory device architecture in the industry. As shown in Figure 1A, a typical RRAM memory integrated circuit 100 may include an RRAM array 101, a bit line (BL) / source line (SL) multiplexer (Mux) 102, a word line (WL) decoder 103, a sense amplifier 104, a charge pump 105, analog circuitry 106, and digital circuitry 107. Therefore, a significant amount of valuable wafer area is used to manufacture the peripheral circuitry, thus limiting the area available for manufacturing RRAM memory cells. Furthermore, the manufacturing of memory cells requires state-of-the-art processes to achieve high density, while peripheral circuitry can be manufactured using mature nodes. However, different process nodes cannot be used on the same wafer. This invention proposes a dual-chip solution, in which the RRAM array is manufactured using an advanced node, while other circuitry is manufactured using a mature node. Subsequently, these two chips are combined using hybrid bonding technology. Through this method, the entire area of ​​the advanced process node wafer can be dedicated to manufacturing high-density memory cells, thereby improving the competitiveness of memory devices. Furthermore, since only one type of transistor with a repeating regular pattern needs to be manufactured, the advanced process for manufacturing high-density memory cells can be further simplified, thereby ultimately greatly reducing process defects and improving chip yield.

[0081] Figure 1B is a schematic diagram of a novel memory device architecture employing a hybrid bonding structure according to an embodiment of the present invention. As shown in Figure 1B, the present invention proposes a dual-chip scheme in which the RRAM array is manufactured using an advanced node, while other circuitry is manufactured using a mature node. The memory device 110 may include a memory chip 111 and a control chip 112. The memory chip 111 includes multiple memory cells (labeled "RRAM array 101" in Figure 1B) manufactured using a first process mode. The control chip 112 includes control circuitry manufactured using a second process node, wherein the first process node is more advanced than the second process node. These two chips are bonded together using a "hybrid bonding" technique (labeled "hybrid bonding structure 113" in Figure 1B) to form the memory device 110, and the control circuitry is used to control the operation of the multiple memory cells within the memory chip 111. Hybrid bonding includes metal bonding and insulating bonding, which will be further described in detail below with reference to Figure 4. For clarity of illustration, only metal bonding 113 is shown in Figure 1B, but insulating bonding is not shown, although it is also part of the hybrid bonding structure.

[0082] Since the wafer used to manufacture the memory chip 111 contains only memory cells and not control circuitry, more memory cells can be manufactured on the same wafer, thereby optimizing wafer utilization.

[0083] As shown in Figure 1B, the control chip 112 includes a multiplexer (Mux) 102, a decoder 103, an inductive amplifier 104, a charge pump 105, analog circuitry 106, and digital circuitry 107. The multiplexer 102 in the control chip 112 controls the source lines or bit lines of the memory cells within the RRAM array 101, while the memory chip 111 does not include a multiplexer for controlling the source lines or bit lines of the memory cells within the RRAM array 101. The decoder 103 in the control chip 112 controls the word lines of the memory cells within the RRAM array 101, while the memory chip 111 does not include a decoder for controlling the word lines of the memory cells within the RRAM array 101. The inductive amplifier 104 in the control chip 112 amplifies the signals from the memory cells within the RRAM array 101, while the memory chip 111 does not include an inductive amplifier for amplifying the signals from the memory cells within the RRAM array 101. The charge pump 105 within the control chip 112 is used to generate the programming voltage required for the memory cells within the RRAM array 101, while the memory chip 111 does not include a charge pump for generating the programming voltage required for the memory cells within the RRAM array 101. Furthermore, the memory chip 111 does not include analog circuitry 106 or digital circuitry 107.

[0084] Figure 2A is a schematic diagram of a memory chip architecture in a common hybrid bonding structure memory device in the industry. Figure 2B is a schematic diagram of a novel memory chip architecture without multiplexers according to an embodiment of the present invention. As shown in Figure 2A, the prior art using a hybrid bonding structure includes a bit line (BL) / source line (SL) multiplexer 202 and a word line (WL) decoder 203 on the memory chip 200, and hybrid bonding connections 213a, 213b, and 213c are provided downstream of the BL / SL multiplexer 202 or the WL decoder 203. As shown in Figure 2B, since the memory chip 230 of the present invention only includes one type of transistor (NMOS or PMOS) formed on the RRAM chip, a multiplexer is not required. The hybrid bonding connection 213 is directly connected to the word line 223, the bit line 221, and the source line 222, respectively.

[0085] Figure 3 is a schematic diagram of a novel customer-defined memory device architecture employing a hybrid bonding structure according to an embodiment of the present invention. Figure 3 is a schematic diagram of a customer-defined memory (CDM) 300, which may include a memory chip 321 and a customer-defined functional module chip 322 connected by hybrid bonding (for ease of reading, Figure 3 only shows the metal bonding 323; the insulating bonding is not shown, but the insulating bonding is also part of the hybrid bonding structure). The customer-defined functional module chip 322 may include a multiplexer 302, a decoder 303, a sensing amplifier 304, an MCU 305, analog circuits 306, digital circuits 307, an ECC memory 308, passive devices 309, a sensor 310, a transmitter 311, and other customer-defined modules. Other customer-defined functional modules may include other memories (such as SRAM), power management integrated circuits, mixed-signal interfaces, and radio frequency components. The analog circuits 306 may include analog circuits such as ADCs, DACs, PLLs, V / I reference DC / DC converters, and power supplies. The digital circuits 307 may include digital circuits such as MCUs, NPUs, GPUs, and CPUs. Passive device 309 may include passive devices such as inductors, capacitors, and resistors. Sensor 310 may include sensors such as image sensors, CCD sensors, temperature sensors, pressure sensors, and gas sensors. Mixed-signal interface may include mixed-signal interfaces such as PCIe, SerDes, DDR, CXL, and SPI / QPI. Radio frequency components may include radio frequency components such as LNAs, VCOs, and mixers. Transmitter 311 can transmit communication signals. Memory chip 321 may include high-density, high-bandwidth, low-power memory. In some embodiments, memory chip 321 may include only simple memory cells.

[0086] The user-customized memory 300 provides a combined solution of non-volatile memory (NVM) space and non-volatile static random access memory (NVSRAM) space. This solution offers the best cost-performance ratio, with densities ranging from approximately several megabits (M) to several gigabits (G) of storage, and with finer-grained storage capacity.

[0087] In addition to integrating user-customized functional modules, the user-customized memory 300 can provide greater value within the same cost range. This flexibility enables cost-effective customization solutions that not only meet specific customer requirements but also lower the barrier to entry for emerging memory technologies such as RRAM, as only the control chip needs to be fabricated using low-cost, mature processes, and advanced node memory chips can be reused.

[0088] The user-customized memory 300 improves storage density through multi-layer 3D integration and achieves high bandwidth through 2.5D interposer technology, thereby enabling functional expansion. The user-customized memory 300 is compatible with advanced memory interfaces including SPI / QPI, DDR5, CXL, PCIe 6.0, and 112G SerDes.

[0089] In addition, the user-customized memory 300 achieves SRAM-compatible random access speeds, making it suitable for AI applications in both edge and data center environments, thereby improving performance while reducing power consumption.

[0090] The user-customizable memory 300 of this invention allows customers to select specific functions that match their needs, thereby increasing versatility. This approach enables the memory to integrate multiple control functions, allowing control circuitry to be directly integrated with the memory cells, thus providing a more adaptable and feature-rich solution.

[0091] Figure 4 is a schematic diagram of a novel memory device architecture employing a hybrid bonding structure according to an embodiment of the present invention. As shown in Figure 4, the memory 400 includes a memory chip 431 and a control chip 432. The memory chip 431 uses a more advanced node than the control chip 432. The memory chip 431 includes multiple memory cells. The memory chip 431 includes only one type of transistor 410, which can be either an NMOS transistor or a PMOS transistor. On the other hand, the control chip 432 can contain various types of transistors, such as NMOS, PMOS, and I / O transistors.

[0092] Because the memory chip 431 uses a more advanced node than the control chip 432, the gate length 421 of the access transistor 401 in the memory chip 431 is smaller than the gate length 422 of all transistors in the control chip 432.

[0093] LGate_Memory <LGate_Control。

[0094] This invention uses only one type of transistor within the memory chip 431, thereby greatly simplifying the manufacturing process. By reducing the number of transistor types required, this approach reduces technical complexity, decreases the number of masks needed, and minimizes the number of manufacturing steps. This simplified process not only reduces production difficulty but also improves yield and reliability, ultimately reducing overall manufacturing costs.

[0095] Memory chip 431 includes a P-type silicon substrate, a back-to-offset (BEOL) metal and dielectric layer 433, and a hybrid bonding metal and dielectric layer 434. The P-type silicon substrate includes an access transistor 401. The BEOL metal and dielectric layer 433 includes a contact 402, a first metal layer 403, a bottom electrode 404, a resistive random access memory (RRAM) element 405, a first via 406, a second metal layer 407, and an insulating layer 415. The contact 402 is located between the terminal of the access transistor 401 and the first metal layer 403, the bottom electrode 404 is located between the first metal layer 403 and the RRAM element 405, and the first via 406 is located between the RRAM element 405 and the second metal layer 407. The BEOL metal and dielectric layer and its components, including the RRAM element 405, are formed above the substrate.

[0096] The resistive switching memory element 405 is produced in the back-end process (BEOL) of the memory chip 431.

[0097] The resistive random access memory element 405 can be replaced by a resistive random access memory (RRAM) element, a conductive bridged random access memory (CBRAM) element, a magnetoresistive random access memory (MRAM) element, a ferroelectric random access memory (FeRAM) element, or a phase change random access memory (PCRAM) element.

[0098] Figures 5A and 5B are schematic diagrams showing the thickness and material of each layer in the RRAM stack in the new embedded RRAM process according to an embodiment of the present invention. The resistive switching memory element 405 may have two types of RRAM stacks disposed in the RRAM region 520: (a) as shown in Figure 5A, an RRAM stack with only one bottom electrode (BE) material; and (b) as shown in Figure 5B, an RRAM stack with two bottom electrodes. Referring to Figure 5A, the thickness of the RRAM bottom electrode 522 can be 5 nm to 500 nm, and the material of the RRAM bottom electrode 522 can be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or other suitable conductive materials. The thickness of the dielectric layer 523 can be from 0.1 nm to 50 nm, and the material of the dielectric layer 523 can be a dielectric (SiO2, Ta2O5, TiO2, ZrO2, HfO2, Al2O3, etc.), including mixtures and / or combinations of these materials. The thickness of the capping layer 524 can be from 1 nm to 500 nm, and the material of the capping layer 524 can be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or other suitable conductive materials. The thickness of the top electrode 525 can be from 1 nm to 500 nm. The material of the top electrode 525 can be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or other suitable conductive materials. A hard mask layer 526 is also deposited on top of the RRAM stack. The material of the hard mask layer 526 can be SiN. In this embodiment, a via Vx+1 527 and a metal layer Mx+2 528 are used, wherein the via Vx+1 527 is etched through the hard mask 526 and connected to the RRAM top electrode 525.

[0099] Referring to Figure 5B, a second RRAM bottom electrode 522a is deposited between the dielectric layer 523 and the first RRAM bottom electrode 522. The thickness of the second RRAM bottom electrode 522a can be 1 nm to 500 nm, and the material of the second RRAM bottom electrode 522a can be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or other suitable conductive materials.

[0100] As shown in Figure 4, the memory chip portion of the hybrid bonding metal and dielectric layer 434 includes memory chip vias 411, memory chip pads 412, and an insulating layer 416. The control chip portion of the hybrid bonding metal and dielectric layer 434 includes control chip vias 414, control chip pads 413, and an insulating layer 416. The top surface of the memory chip 431 includes a plurality of first conductive pads serving as memory chip pads 412 and a first insulating region. The top surface of the control chip 432 includes a plurality of second conductive pads serving as control chip pads 413 and a second insulating region. In the hybrid bonding process, the memory chip pads 412 and the control chip pads 413 are bonded, and the first insulating region and the second insulating region are bonded. The plurality of memory chip pads 412 are connected to the metal layer 407 in the memory chip 431 through a plurality of vias serving as memory chip vias 411, and the plurality of second conductive pads 413 are connected to the metal layer in the control chip 432 through a plurality of second vias serving as control chip vias 414. The plurality of memory chip vias 411 are of the same length to avoid forming a stepped shape.

[0101] Figure 6 is an example process flow for performing a write operation in a storage device according to an embodiment of the present invention. Hereinafter, with reference to Figure 6, a method for performing a write operation in a storage device will be described. The method shown in Figure 6 includes the following control flow steps:

[0102] S601: The control chip receives the address of the memory cell of the memory chip and the data to be written to the memory cell;

[0103] S602: Decodes the address and sends signals to the multiplexer and decoder to activate specific BL and WL;

[0104] S603: The control chip performs read operations on memory cells;

[0105] S604: Selective storage device receives read bias and returns current;

[0106] S605: The sensing amplifier distinguishes whether the current of the selective RRAM is logic "0" or logic "1";

[0107] S606: The control chip compares the data to be written with the result of the read operation;

[0108] S607: If the data to be written matches the result of the read operation, end the write operation;

[0109] S608: If the data to be written does not match the result of the read operation, perform a write operation on the memory cell.

[0110] S609: Selective storage device receives write bias, and the resistance of the storage device changes to the desired resistance state.

[0111] The aforementioned memory device includes: a memory chip comprising a plurality of memory cells manufactured at a first process node; and a control chip comprising control circuitry manufactured at a second process node, wherein the first process node is more advanced than the second process node, the control chip and the memory chip are bonded together to form the memory device, and the control circuitry is used to control the operation of the plurality of memory cells within the memory chip.

[0112] In S601, S602, S605, S606 and S607, signals are transmitted within the same chip (control chip or memory chip).

[0113] In S603, S604, S608, and S609, signals are transmitted between the control chip and the memory chip.

[0114] In existing technologies, all bits must be programmed regardless of the value to be stored. This invention proposes a more efficient method that differs from existing technologies. Before a write operation, the control chip performs a read operation on the memory cell to determine whether the bit needs to be programmed. If the stored value matches the required data, no programming operation is performed. Furthermore, this invention eliminates the need for a refresh operation.

[0115] This selective write process of the present invention reduces unnecessary write cycles. This is particularly beneficial for RRAM, given its limited write tolerance. By reducing the number of write operations, the method of the present invention extends the lifespan of both the RRAM and the entire device, thereby improving durability and reliability.

[0116] In some implementations, the hybrid bonding technology described above is further optimized to meet more advanced application requirements. Specifically, a memory wafer and a control wafer are connected via hybrid bonding to form a fully functional memory device. The memory wafer contains thousands of uniformly sized memory array grids. To manufacture integrated memory chips with different memory capacities, only the control wafer needs to be redesigned according to the required number of memory arrays. Crucially, regardless of configuration changes, the memory wafer remains unchanged; only the design and dicing process of the control wafer need to be adjusted to assemble specific memory array units during wafer dicing. This method significantly reduces the manufacturing time and cost of chips with different memory capacities because only the control wafer at low-cost, mature process nodes needs to be redesigned and fabricated, while the memory wafer at high-cost, advanced process nodes can be reused.

[0117] Figure 7 illustrates a commonly used memory device architecture in the industry. As shown in Figure 7, in traditional memory device designs, various peripheral circuits are typically integrated with the memory array on the same wafer. Although peripheral circuits can be manufactured using mature process nodes, to meet the rapidly growing market demands for miniaturization, high performance, and large-capacity data storage, memory cells must employ state-of-the-art processes to achieve high density and high performance. However, since different process nodes cannot be mixed on the same wafer, advanced process nodes must be used to manufacture the memory array and peripheral circuits simultaneously. Typically, only one mask assembly is used when manufacturing fixed-capacity (e.g., 4Mbit) memory devices. To produce memory devices of different capacities (e.g., 8Mbit, 16Mbit, etc.), a completely new mask assembly must be designed. Because new capacity memory chips need to be redeveloped based on high-cost advanced process nodes, this method results in high mask costs when developing memory devices of different capacities.

[0118] In the above embodiments, a memory device structure based on hybrid bonding technology is proposed. By bonding memory chips from advanced process nodes with control chips from mature process nodes, the advantages of hybrid bonding technology are fully utilized. In this invention, the advantages of this hybrid bonding technology are further expanded: when producing memory devices with different storage capacities, only the control chips from mature nodes need to be redesigned and re-fabricated using new photomask assemblies, while the photomask assemblies used for the memory wafers from advanced nodes can be reused in various storage capacity configurations. This design significantly reduces the cost and time required to develop memory devices with different capacities.

[0119] Figure 8 illustrates a memory device for an integrated memory according to an embodiment of the present invention. As shown in Figure 8, the memory device 810 includes a memory chip 811 and a control chip 812. The memory chip 811 is fabricated on a memory wafer at a first (more advanced) process node and uses a set of memory photomasks. The memory chip 811 can conceptually be similar to any of the memory chips 911A to 911E shown in Figure 9. The memory chip 811 includes one or more (preferably at least two) identical basic memory arrays 801. It should be noted that the scribe lines used to separate the basic memory arrays and the grid structure of the memory arrays 801 are not explicitly shown in Figure 8; these will be shown and described in Figure 9 and its related paragraphs.

[0120] In contrast, the control chip 812 is manufactured on a separate control wafer using a second process node, which is more mature than the first process node used for memory chips. Conceptually, the control chip 812 can be similar to any of the control chips 912A to 912E shown in Figure 9. The control chip 812 is manufactured using a set of control photomasks. Each control chip 812 is specifically designed to manage the operation of its corresponding memory chip 811.

[0121] To fabricate a fully functional memory device 810, each control chip 812 is bonded to its corresponding memory chip 811 using a hybrid bonding technique or a similar bonding method. This hybrid bonding process, described in more detail in Figure 4, involves metal-to-metal bonding (labeled 813 in Figure 8) and insulator-to-insulator bonding. Although the insulator bonding portion is not explicitly shown in Figure 8 for simplification, it plays a crucial role in the structural integrity of the bonded device.

[0122] As shown in Figure 8, the control chip 812 integrates several key circuit components, including a multiplexer (Mux) 802, a decoder 803, an inductive amplifier 804, a charge pump 805, analog circuitry 806, and digital circuitry 807. The multiplexer 802 in the control chip 812 selects and controls source lines or bit lines to access individual memory cells in the underlying memory array 801. The memory chip 811 itself does not contain a multiplexer. Similarly, the decoder 803 in the control chip 812 controls the word lines used to access memory cells in the underlying memory array 801, while the memory chip 811 does not have a built-in word line decoder. The inductive amplifier 804 on the control chip 812 amplifies the weak signals read from the underlying memory array 801, while the memory chip 811 does not contain a dedicated inductive amplifier. The charge pump 805, located on the control chip 812, generates the high voltage required to write data to the memory cells. For high-density design considerations, the memory chip 811, manufactured using advanced process nodes, maintains a simplified design and does not integrate a charge pump. Furthermore, the memory chip 811 does not include analog circuitry 806 or digital circuitry 807; all control and peripheral functions are concentrated on the control chip 812. This strategic partitioning enables independent optimization of functional modules, ensuring high-density memory chips while implementing control and peripheral circuitry on mature nodes in a more cost-effective manner, thereby improving the overall system performance and manufacturing efficiency.

[0123] In some embodiments, a method for manufacturing an integrated memory chip is provided. The method includes: forming a plurality of basic memory arrays 801 on a memory wafer, these memory arrays being fabricated using a set of memory photomasks at a first (more advanced) process node. Each basic memory array 801 is surrounded by scribe lines. The method further includes: forming a plurality of control chips 812 on another control wafer, these control chips being fabricated using a set of control photomasks at a second (more mature) process node. Each control chip 812 is designed to control the operation of a corresponding memory chip 811, the memory chip 811 including one or more basic memory arrays 801, preferably including at least two basic memory arrays. Subsequently, the memory wafer and the control wafer are bonded together, forming a bonded wafer by aligning and connecting each control chip 812 to its corresponding memory chip 811. Finally, the bonded wafer is selectively diced along the scribe lines, but not all scribe lines, to form a single chip with integrated memory. Each final chip will contain at least one undone scribe line to indicate the boundary between the original basic memory arrays.

[0124] Figure 9 is a top view of an integrated memory chip obtained by bonding a memory chip to different control chips according to an embodiment of the present invention. As shown in Figure 9, the various memory chips 911A, 911B, 911C, and 911E each contain one or more identical basic memory arrays 901. These basic memory arrays 901 are arranged in a grid pattern and are physically isolated from each other by a series of scribe lines 921. The scribe lines 921 extend along the x-axis and y-axis directions, effectively separating each basic memory array from each other to form a regular grid structure.

[0125] Figure 9 further illustrates that different control chips 912A, 912B, 912C, and 912E (the control wafers on which they reside are not explicitly shown in Figure 9 for simplicity) can be designed to bond and control different combinations of base memory arrays 901 on the memory wafer. Furthermore, these different types of control chips (912A–912E) can be fabricated on the same control wafer or distributed across different control wafers. For example, a single control wafer can be repeatedly patterned using a set of control masks to fabricate multiple sets of the same type of control chip (such as 912A); multiple sets of control masks (or a more complex set) can also be used to pattern two or more different types of control chips on the same wafer (e.g., fabricating 912A and 912B simultaneously). This design approach allows for flexible combinations of various final memory device configurations. For example, control chip 912A can correspond to memory chip 911A controlling a smaller number of base memory arrays 901, while control chip 912E can correspond to memory chip 911E controlling a larger number of base memory arrays 901. This approach highlights the flexibility of the invention: multiple control chips (912A–912E) with different designs can be bonded to different subsets of the base memory array 901 derived from the same memory wafer design to meet the manufacturing of memory devices with different capacity and performance requirements.

[0126] As shown in Figure 9, the final storage capacity of the memory device is determined after the bonding and dicing processes are completed. This capacity variation is achieved through two methods: first, redesigning the control mask assembly for the mature node control wafer; and second, selectively cutting specific scribe lines 921 during the dicing process. This method allows chips with different storage capacities to be manufactured using the same memory wafer. Crucially, the memory wafer manufactured using advanced and expensive process nodes remains unchanged throughout the process, eliminating the need for redesign or re-fabrication for different chip configurations. This strategy significantly reduces the cost of redesigning and remanufacturing (i.e., re-fabrication) advanced node memory wafers for different storage capacities.

[0127] Figures 10A and 10B are schematic diagrams illustrating an integrated memory device structure according to an embodiment of the present invention. As shown in Figure 10A, a plurality of basic memory arrays 1001 are formed on a first memory wafer 1061, which is fabricated using a set of memory photomasks at a first (more advanced) process node. Each basic memory array 1001 is surrounded by scribe lines 1021. A plurality of control chips 1012 are formed on a first control wafer 1062, which is fabricated using a second (more mature) process node different from that of the memory wafer, and a control photomask set. Each control chip 1012 is configured to control a corresponding memory chip 1011, which includes two basic memory arrays 1001. Through a bonding step, the first memory wafer is aligned and bonded to the first control wafer, such that each control chip 1012 is aligned with its corresponding memory chip 1011. Subsequently, a plurality of final chips, as labeled memory devices 1010 in Figure 10A, are formed by dicing along some (but not all) of the scribe lines 1021. Each final chip contains at least one uncut scribe line 1021 to indicate the boundary between the original base arrays. Figure 10B shows the second set of memory devices. As shown, multiple base memory arrays 1001 are fabricated on a second memory wafer 1061' using the same memory mask set as before, employing the same first process node. The difference is that the number of base memory arrays contained in the memory chips 1011' formed on this wafer differs from that in Figure 10A. These base memory arrays are surrounded by the second scribe line 1021'. Multiple second control chips 1012' are formed on a second control wafer 1062', using a different set of control masks than the first control wafer, and are still fabricated at the second process node. Each control chip 1012' is designed to control the memory chip 1011' containing four base memory arrays 1001. The second memory wafer is then bonded to the second control wafer, aligning each control chip 1012' with its corresponding memory chip 1011'. Subsequently, the bonding wafer is diced along a portion of the second scribe line 1021' to form multiple second memory devices 1010' with integrated storage. Each device also retains at least one uncut scribe line 1021'. More generally, embodiments of the present invention allow for the flexible construction of various memory devices of different capacities (e.g., 1, 2, 3, 4, or even N basic memory arrays, where N is a positive integer) by integrating a base memory array using the same memory mask set and manufactured at an advanced process node with a control chip tailored to the number of base arrays and manufactured at a more mature process node. This manufacturing process demonstrates a high degree of flexibility and cost-effectiveness in creating multiple types of memory devices without altering the memory wafer design.

[0128] Figure 11 is a schematic diagram showing a top view of memory devices with different storage capacities according to an embodiment of the present invention. The total storage capacity of all memory devices is an integer multiple of the capacity of a single basic memory array. For example, as shown in Figure 11, assuming that the capacity of each basic memory array 1101 is 2 Mbit, memory devices with different configurations can be constructed by the aforementioned manufacturing method. For example: a 2 Mbit memory device 11A is formed by bonding a memory chip 1111A containing only one basic memory array 1101 to its corresponding control chip 1112A; a 4 Mbit memory device 11B is formed by bonding a memory chip 1111B containing two basic memory arrays 1101 to a control chip 1112B; a 6 Mbit memory device 11C is formed by bonding a memory chip 1111C containing three basic memory arrays 1101 to a control chip 1112C; and an 8 Mbit memory device 11D is formed by bonding a memory chip 1111D containing four basic memory arrays 1101 to a control chip 1112D. Similarly, the same method can be used to manufacture memory devices with further increased capacities (in 2Mbit increments), such as 10Mbit, 12Mbit, etc. This modular design approach offers high flexibility, allowing the manufacture of memory chips with storage capacities (such as 6Mbit or 10Mbit) that were previously uncommon or difficult to obtain on the market, thereby providing more differentiated options for storage products and opening up new market opportunities.

[0129] Each memory chip (1111A, 1111B, 1111C, and 1111D) in Figure 11 is composed of one or more identical basic memory arrays 1101. The basic memory arrays 1101 within each memory chip have exactly the same storage capacity. It should be noted that the capacity of each basic memory array can be adjusted according to actual needs and is not fixed. Therefore, the total capacity of the memory device manufactured using the above method will also vary accordingly. Figure 12 is a top view of a memory device according to an embodiment of the present invention. As shown, an 8Mbit memory chip 1211 is composed of four identical 2Mbit basic memory arrays 1201, which are bonded to a corresponding control chip 1212 to form the final device. This structural uniformity greatly simplifies the design and manufacturing process, and improves production efficiency and consistency.

[0130] In the manufacturing process of the aforementioned memory devices, alignment accuracy is crucial for achieving precise bonding between the control wafer and the memory wafer. Figure 13 is a top view of a memory wafer with alignment marks or overlap marks according to an embodiment of the present invention. As shown in Figure 13, alignment marks or overlap marks 1322 are embedded in at least a portion of the scribing lines 1321. These marks are used to ensure precise alignment when bonding the memory wafer to the control wafer, thereby ensuring that the conductive contact pads (e.g., pads for metal interconnects) between the chips are accurately aligned and form a reliable connection. Furthermore, at least a portion of the scribing lines 1321 may also contain specific patterns or indicators to indicate whether the scribing line will be cut during the subsequent dicing process. In this way, the final chip dicing method can be pre-planned at the wafer level, thereby ensuring bonding accuracy while ensuring a chip structure of the required size and memory capacity.

[0131] Figure 14 is a top view of a memory wafer with alignment marks according to an embodiment of the present invention. As shown, in this embodiment, the scribing region is specifically designed to exclude the virtual metal structure 1431. This contrasts with conventional scribing designs—in conventional processes, the scribing region is typically filled with virtual metal structures 1431, which represent placeholders for different metal layers in different shapes to maintain the flatness and process uniformity of the overall metal layers. However, in this embodiment of the invention, these virtual metal structures are deliberately removed from the scribing region to improve wafer alignment accuracy during the bonding process. Virtual metal structures can interfere with the optical alignment system (e.g., by reflecting or blocking light signals), thereby reducing alignment accuracy. By retaining a clear metal-free area in the scribing, the alignment system can effectively identify the marks, achieving higher precision wafer alignment and controlling the precise bonding of the wafer to the memory wafer.

[0132] Integrated memory chips can be manufactured into devices with multiple applications according to specific needs. Figure 15 is a schematic diagram showing a top view of a memory device according to an embodiment of the present invention. As shown in Figure 15, the control chip 1512 can be not only one or more conventional memory chips 1541, but also other types of functional chips that require integrated storage functions during operation, including but not limited to: microcontroller units (MCUs) 1542, power management integrated circuits (PMICs) 1543, display driver integrated circuits (DDICs) 1544, application-specific integrated circuits (ASICs) 1545, and other chip types that require embedded storage support. Through the above integration method, the present invention provides a highly flexible manufacturing platform that not only improves the system integration level (SoC level integration) of the chip, but also provides differentiated storage configurations for various terminal applications. This architecture supports the separate manufacturing and subsequent integration of high-density storage arrays and functional control chips, which helps to reduce costs, improve yield, and achieve product diversification.

[0133] In some embodiments, a chip with integrated memory functionality is provided. The chip includes a memory chip fabricated at a first (more advanced) process node. The memory chip includes at least two basic memory arrays, each spaced apart from the other by at least one scribe line. The chip also includes a control chip fabricated at a second (more mature) process node, designed to manage the operation of the memory chip. The top surface of the memory chip has a plurality of first conductive pads and a first insulating region. Similarly, the top surface of the control chip has a plurality of second conductive pads and a second insulating region. During bonding, the first conductive pads of the memory chip are bonded to corresponding second conductive pads in the control chip. Simultaneously, the first insulating region of the memory chip is also bonded to the second insulating region of the control chip. This hybrid bonding method forms a strong and reliable connection between the two chips.

[0134] The above description of the illustrated embodiments of the present invention (including the description in the abstract) is not intended to be exhaustive or to precisely limit the invention to the disclosed forms. While specific embodiments and examples of the invention have been described herein for illustrative purposes, as those skilled in the art should understand, various equivalent modifications can be made within the scope of this disclosure. Other embodiments may have layers arranged in a different order than those illustrated in the embodiments, or may increase or decrease the number of layers based on the illustrated embodiments.

[0135] Although the operations have been described above as multiple independent operations in order to best facilitate understanding of the invention, this order of description should not be construed as implying that the operations necessarily depend on a specific order. In particular, the operations need not necessarily be performed in the order described.

[0136] In this specification, the terms "above," "over," "below," "between," and "upper" are used to indicate the relative position of a material layer or component to other layers or components. For example, when a layer is described as being deposited "above," "over," or "below" another layer, it means that the layer may be in direct contact with the other layer, or one or more intermediate layers may be present. Similarly, when a layer is described as being deposited "between" two layers, it means that the layer may be in direct contact with both layers, or one or more intermediate layers may be present. Conversely, when a first layer is described as being "above" a second layer, it means that it is in direct contact with the second layer. Likewise, unless otherwise explicitly stated, when a component is described as being deposited "between" two layers, it means that the component may be in direct contact with each of the adjacent components, or one or more intermediate layers may be present.

[0137] In this specification, the terms “example” and “illustration” are used to indicate that something is an example, instance, or illustration. Any aspect or design described herein as an “example” or “illustration” should not necessarily be construed as preferred or superior to other aspects or designs. Rather, the purpose of using the terms “example” or “illustration” is to state concepts in a specific manner. In this specification, the word “or” is intended to mean “or” in an inclusive sense, not in an exclusionary sense. That is, unless otherwise stated or clearly apparent from the context, “X includes A or B” is intended to mean any of the naturally inclusive permutations and combinations. In other words, “X includes A or B” is satisfied if: “X includes A”; “X includes B”; or X includes both A and B. Furthermore, the terms “a” and “an” in this specification and the appended claims are generally understood to mean “one or more” unless otherwise explicitly stated or clearly apparent from the context. Additionally, the terms “implementation” or “an embodiment” used herein are not intended to refer to the same embodiment unless described embodied therein. In this specification, the terms "first," "second," "third," "fourth," etc., are intended to be used as markers to distinguish different components and do not necessarily have the ordinal meaning represented by their numerical parts.

Claims

1. A method for manufacturing an integrated memory chip, comprising: On a memory wafer, multiple basic memory arrays are formed using a memory photomask assembly at a first process node, wherein each of the basic memory arrays is surrounded by multiple scribing lines; On the control wafer, multiple control chips are formed at a second process node using a control photomask assembly, wherein the first process node is more advanced than the second process node, and each of the control chips is configured to control the operation of a corresponding memory chip, the memory chip including at least two basic memory arrays. The memory wafer is bonded together with the control wafer to form a bonded wafer, wherein each control chip is bonded to a corresponding memory chip; The bonding wafer is diced along a portion (but not all) of the scribe line to form a plurality of integrated memory chips, wherein each of the integrated memory chips includes an uncut scribe line.

2. The method as described in claim 1, characterized in that, Each of the aforementioned basic storage arrays has the same storage capacity.

3. The method of claim 1, wherein at least a portion of the scribe lines comprise alignment marks or overlap marks, and the method further comprises bonding the storage wafer to the control wafer according to the alignment marks or overlap marks.

4. The method as described in claim 3, characterized in that, There is no virtual metal layer in the scribed portion including the alignment mark or overlapping mark.

5. The method as described in claim 3, characterized in that, At least a portion of the scribing lines include a pattern for indicating whether the scribing lines need to be cut, and the method further includes cutting the bonding wafer according to the pattern.

6. The method of claim 1, wherein the control chip is selected from the group consisting of: microcontroller unit (MCU), power management integrated circuit (PMIC), display driver integrated circuit (DDIC), and application-specific integrated circuit (ASIC).

7. The method of claim 1, wherein the control chip includes a control circuit, the control circuit including a multiplexer for controlling the source lines or bit lines of the memory cells in the memory chip.

8. The method of claim 7, wherein the memory chip does not include a multiplexer for controlling the source lines or bit lines of the memory cells in the memory chip.

9. The method of claim 8, wherein the memory chip does not include a decoder for controlling word lines of memory cells in the memory chip.

10. The method as described in claim 1, characterized in that, The gate length of the transistor in the memory chip is smaller than the gate length of the transistor in the control chip.

11. The method as described in claim 1, characterized in that, The memory chip includes only one type of transistor, while the control chip includes multiple types of transistors.

12. The method as described in claim 11, characterized in that, The memory chip consists only of NMOS transistors.

13. The method as described in claim 11, characterized in that, The memory chip consists only of PMOS transistors.

14. The method as described in claim 7, characterized in that, Each memory cell includes a memory element formed on a substrate.

15. The method as described in claim 14, characterized in that, The memory element is selected from the group consisting of the following elements: Resistive variable random access memory element; Conductive bridging random access memory elements; Magnetoresistive random access memory elements; Ferroelectric random access memory elements; as well as Phase-change random access memory (PCM) element.

16. The method as described in claim 7, characterized in that, Each memory cell includes a resistive switching memory element formed on a substrate.

17. The method as described in claim 16, characterized in that, The memory unit includes: Access transistors formed on the substrate; Contact; First metal layer; Bottom electrode; The resistive random access memory element; First via; and Second metal layer, The contact is located between the terminal of the access transistor and the first metal layer, the bottom electrode is located between the first metal layer and the resistive switching memory element, and the first via is located between the resistive switching memory element and the second metal layer.

18. The method as described in claim 16, characterized in that, The top surface of the memory chip includes a plurality of first conductive pads and a first insulating region, and the top surface of the control chip includes a plurality of second conductive pads and a second insulating region.

19. The method as described in claim 18, characterized in that, The first conductive pad is bonded to the second conductive pad, and the first insulating region is bonded to the second insulating region.

20. The method as described in claim 18, characterized in that, The plurality of first conductive pads are connected to the second metal layer within the memory chip through a plurality of memory chip vias, and the plurality of second conductive pads are connected to the second metal layer within the control chip through a plurality of control chip vias, wherein the plurality of memory chip vias have the same length.

21. The method as described in claim 1, characterized in that, On the second memory wafer, a plurality of basic memory arrays are formed at a first process node using the memory photomask group, wherein each of the basic memory arrays is surrounded by a plurality of second scribe lines; On the second control wafer, a plurality of second control chips are formed at a second process node using a second control mask group different from the control mask group, wherein each second control chip is configured to control the operation of a corresponding second memory chip, the second memory chip including at least two basic memory arrays; The second memory wafer is bonded to the second control wafer to form a second bonded wafer, wherein each of the second control chips is bonded to a corresponding second memory chip; as well as The second bonding wafer is diced along a subset (but not all) of the second scribe line to form a plurality of second chips with integrated memory, wherein each second chip with integrated memory includes an undicated second scribe line.

22. The method as described in claim 21, characterized in that, The memory chip and the second memory chip contain different numbers of basic memory arrays.

23. An integrated memory chip, comprising: A memory chip formed at a first process node, wherein the memory chip includes at least two basic memory arrays and each pair of basic memory arrays is separated by at least one scribe line; as well as A control chip fabricated using a second process node, wherein the first process node is more advanced than the second process node, and the control chip is configured to control the operation of the memory chip. The memory chip has a top surface including a plurality of first conductive pads and a first insulating region, and the control chip has a top surface including a plurality of second conductive pads and a second insulating region. The first conductive pads are bonded to the second conductive pads, and the first insulating region is bonded to the second insulating region.

24. The chip of claim 23, wherein each of the basic memory arrays has the same storage capacity.

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