Using throttler for droop mitigation
The clock throttler circuit addresses droop-related performance issues in CPUs and GPUs by dynamically throttling clock signals, providing efficient mitigation and recovery from droop events.
WO2026132769A1PCT designated stage Publication Date: 2026-06-25ARM LTD
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- ARM LTD
- Filing Date
- 2025-12-11
- Publication Date
- 2026-06-25
Smart Images
Figure GB2025052682_25062026_PF_FP_ABST
Abstract
A clock throttler circuit for droop mitigation and disclose circuitry, related methods and state machine, the method performed at a system to select a first clock signal or a second clock signal to be provided to a subsystem, the method including: receiving, from a droop detector, a trigger signal indicative of a droop event at the subsystem; invoking modulation circuitry to throttle the selectable clock signal in accordance with the event; selecting the first clock signal; providing, to the modulation circuitry, the first clock signal to be throttled.
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