Method for forming metal oxide film

Abstract

Provided is a semiconductor device that has favorable electrical properties. The present invention relates to a method for forming a metal oxide film including a first layer and a second layer. The method for forming a metal oxide film includes: a first step for forming the first layer using an atomic layer deposition method; and a second step for forming the second layer on the first layer using the atomic layer deposition method. In the first step, a first sequence is performed one or more times. In the second step, a second sequence is performed one or more times. The first sequence and the second sequence each include a first step for introducing a first precursor into a chamber and a second step of introducing a first reactant into the chamber. The first precursor contains a metal. The first reactant is an oxidizing agent. The duration of the second step in the first sequence is shorter than the duration of the second step in the second sequence.

Description

Method for forming metal oxide films

[0001] One aspect of the present invention relates to a metal oxide and a method for forming a metal oxide film. Another aspect of the present invention relates to a transistor and a semiconductor device using the above-mentioned metal oxide.

[0002] Furthermore, examples of the technical fields of one aspect of the present invention disclosed more specifically in this specification include LSI (Large Scale Integration) chips, CPU (Central Processing Unit), GPU (Graphics Processing Unit), FPGA (Field Programmable Gate Array), Application Specific Integrated Circuit (ASIC), AI (Artificial Intelligence) chips, memory (storage device), input device, input / output device, sensor, imaging device, display device, light-emitting device, energy storage device, electronic equipment, methods for driving them, or methods for manufacturing them.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product or method; or to a method (process), machine, manufacture, or composition of matter.

[0004] The technology of constructing transistors using semiconductor thin films formed on insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are also gaining attention as other materials.

[0005] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that takes advantage of this low leakage current characteristic. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time.

[0006] Also, In ２ O ３ Its use in thin-film transistors has been reported (Non-Patent Document 1).

[0007] Examples of oxide semiconductors applicable to the active layer of a transistor include indium oxide and indium gallium zinc oxide. Non-patent document 2 discloses a thin-film transistor using hydride polycrystalline indium oxide formed by low-temperature solid-phase crystallization as the active layer.

[0008] Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383

[0009] Dhananjay & Chu, C. W. Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process. Appl. Phys. Lett. 91, 1-4 (2007). Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, nature COMMUNICATIONS, 13, 1078 (2022).

[0010] One aspect of the present invention aims to provide a novel metal oxide and a method for forming the same film. Another aspect of the present invention aims to provide a transistor and a semiconductor device using the novel metal oxide. Another aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Another aspect of the present invention aims to provide a semiconductor device capable of carrying a large current. Another aspect of the present invention aims to provide a semiconductor device with low power consumption. Another aspect of the present invention aims to provide a semiconductor device with high reliability. Another aspect of the present invention aims to provide a semiconductor device that can be miniaturized. Another aspect of the present invention aims to provide a semiconductor device with a small footprint. Another aspect of the present invention aims to provide a semiconductor device that can be arranged at high density. Another aspect of the present invention aims to provide a semiconductor device with reduced parasitic capacitance. Another aspect of the present invention aims to provide a semiconductor device with reduced wiring load.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0012] One aspect of the present invention is a method for forming a metal oxide film having a first layer and a second layer. The method for forming a metal oxide film comprises a first step of forming a first layer using atomic layer deposition, and a second step of forming a second layer on the first layer using atomic layer deposition. In the first step, a first sequence is performed one or more times. In the second step, a second sequence is performed one or more times. The first sequence and the second sequence each comprise a first step of introducing a first precursor into a chamber and a second step of introducing a first reactant into a chamber. The first precursor contains a metal. The first reactant is an oxidizing agent. The duration of the second step in the first sequence is shorter than the duration of the second step in the second sequence.

[0013] In the above-described method for forming a metal oxide film, it is preferable that the first step involves forming a first layer on a substrate, and that between the first and second steps, the temperature of the substrate is lowered to a temperature lower than that of the first step.

[0014] In the above-described method for forming a metal oxide film, it is preferable that the first step involves forming a first layer on a substrate, and between the first and second steps, the step of removing the substrate from the chamber under reduced pressure, and then placing the substrate back into the chamber while maintaining reduced pressure.

[0015] In the above-described method for forming a metal oxide film, it is preferable that the first precursor contains indium and the first reactant contains oxygen and ozone.

[0016] In the above-described method for forming a metal oxide film, it is preferable that the first layer and the second layer are films containing indium and oxygen, respectively.

[0017] In the above-described method for forming a metal oxide film, it is preferable that the time of the second step in the first sequence is 0.1 sec to 30 sec, and the time of the second step in the second sequence is 15 sec to 180 sec.

[0018] According to one aspect of the present invention, a novel metal oxide and a method for forming the same film can be provided. Alternatively, according to one aspect of the present invention, a transistor and a semiconductor device using the novel metal oxide can be provided. Or, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of carrying a large current can be provided. Or, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Or, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Or, according to one aspect of the present invention, a semiconductor device that can be miniaturized can be provided. Or, according to one aspect of the present invention, a semiconductor device with a small footprint can be provided. Or, according to one aspect of the present invention, a semiconductor device that can be arranged at high density can be provided. Or, according to one aspect of the present invention, a semiconductor device with reduced parasitic capacitance can be provided. Or, according to one aspect of the present invention, a semiconductor device with reduced wiring load can be provided.

[0019] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not need to address all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

[0020] Figures 1A and 1B illustrate examples of metal oxide configurations. Figure 2 illustrates a film deposition sequence. Figure 3 illustrates an example of film deposition apparatus configuration. Figures 4A and 4B illustrate examples of film deposition apparatus configurations. Figures 5A, 5B, 5C, and 5D illustrate examples of semiconductor device configurations. Figures 6A and 6B illustrate examples of semiconductor device configurations. Figures 7A and 7B illustrate examples of semiconductor device configurations. Figures 8A, 8B, and 8C illustrate examples of semiconductor device configurations. Figures 9A, 9B, and 9C illustrate examples of memory device configurations. Figure 10 illustrates an example of memory device configuration. Figure 11 is a block diagram illustrating an example of semiconductor device configuration. Figures 12A, 12B, 12C, 12D, 12E, 12F, 12G, and 12H illustrate examples of memory cell circuit configurations. Figures 13A, 13B, and 13C are perspective views illustrating examples of semiconductor device configurations. Figures 14A and 14B are perspective views of a semiconductor device. Figure 15 is a perspective view of a semiconductor device. Figures 16A and 16B show an example of an electronic component. Figures 17A, 17B, and 17C show an example of a large-scale computer. Figure 17D shows an example of space equipment. Figure 17E shows an example of a storage system applicable to a data center. Figures 18A, 18B, and 18C show examples of sample configurations related to the embodiment. Figures 18D, 18E, 18F, and 18G are planar TEM images related to the embodiment. Figures 19A and 19B are SIMS profiles related to the embodiment. Figures 20A and 20B are SIMS profiles related to the embodiment. Figures 21A and 21B show the electrical measurement results of the semiconductor device related to the embodiment.

[0021] Embodiments will be described with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the contents of the embodiments shown below.

[0022] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the hatching patterns are the same, and reference numerals may not be assigned.

[0023] In the figures described herein, the size of each component, the thickness of the layers, the positional relationships, or the areas may be exaggerated for clarity. Therefore, the scale is not necessarily limited to those figures.

[0024] In addition, in drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X axis, and unless explicitly stated, the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction".

[0025] In this specification, the ordinal numbers "first" and "second" are used for convenience only and do not limit the number of components or the order of components (for example, process order or layering order). Furthermore, the ordinal numbers used for components in one part of this specification may not be the same as those used for the same components in other parts of this specification or in the claims.

[0026] In this specification, when describing matters common to components distinguished by letters or numbers attached to their reference numerals (e.g., conductive layer 37a_1, conductive layer 37a_2, conductive layer 37b_1, conductive layer 37b_2), the reference numerals (e.g., conductive layer 37) without letters or numbers may be used for the description.

[0027] Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0028] In this specification, "oxidized nitride" refers to a material whose composition contains more oxygen atoms than nitrogen atoms, and "nitride oxide" refers to a material whose composition contains more nitrogen atoms than oxygen atoms. For example, when "silicon oxidized nitride" is written, it refers to a material whose composition contains more oxygen atoms than nitrogen atoms, and when "silicon nitride oxide" is written, it refers to a material whose composition contains more nitrogen atoms than oxygen atoms.

[0029] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing transistors, devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties.

[0030] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0031] In this specification, transistors using a metal oxide in the semiconductor layer, and transistors having a metal oxide in the channel formation region, may be referred to as OS transistors. Furthermore, transistors having silicon in the channel formation region may be referred to as Si transistors.

[0032] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region (also called a channel-forming region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel-forming region. In addition to the three terminals described above, a back gate may be present. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as the first gate, and the other of the gate or back gate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable.

[0033] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0034] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conductive state or interrupted state).

[0035] Furthermore, unless otherwise specified in this specification, on-current refers to the drain current when the transistor is in the on state (also called the "conducting state").

[0036] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0037] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0038] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0039] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0040] In this specification, "plan view" means viewing from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0041] In the following, expressions indicating direction, such as "up" and "down," will generally be used in accordance with the orientation shown in the drawings. However, for the purpose of simplifying explanations, the direction referred to as "up" or "down" in the specification may not always coincide with that of the drawings. For example, when explaining the stacking order (or formation order) of a laminate, even if the side on which the laminate is provided (the surface to be formed, the support surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, the side to be formed may be described as "down," and the direction opposite to the surface to be formed may be described as "up."

[0042] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 70 degrees or more and 110 degrees or less.

[0043] In this specification, "matching heights" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, in the manufacturing process, a planarization process (typically CMP (Chemical Mechanical Polishing) process) may be performed to expose the surfaces of one or more layers. In this case, the surfaces subjected to CMP processing will have a configuration in which the heights from the reference surface are equal. However, the heights of multiple layers may differ due to differences in the processing equipment, processing method, materials of the surfaces subjected to CMP processing, or differences in polishing rate and etching rate. In this specification, this case will also be treated as "matching heights."

[0044] In this specification, "ends coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. This includes, for example, cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern.

[0045] In general, it is difficult to clearly distinguish between "exact match" and "approximate match." Therefore, in this specification, "match" includes both exact matches and approximate matches.

[0046] In this specification, space groups are expressed using international notation (or Hermann-Mauguin notation) in short notation. Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by superscripting numbers, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a superscript. Individual orientations within a crystal are represented by [ ], collective orientations representing all equivalent orientations are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}.

[0047] (Embodiment 1) This embodiment describes a metal oxide and a method for forming the same film according to one aspect of the present invention.

[0048] A metal oxide according to one aspect of the present invention preferably exhibits semiconductor properties. A metal oxide according to one aspect of the present invention can be used, for example, in the semiconductor layer of a transistor. However, depending on the type, combination, and composition of the elements constituting the metal oxide, a metal oxide according to one aspect of the present invention is not limited to a semiconductor material; it can also be an insulating material or a conductive material.

[0049] In one embodiment of the present invention, it is preferable to use indium oxide as the metal oxide. For the indium oxide used in the semiconductor layer, refer to the description in Embodiment 2.

[0050] A metal oxide according to one aspect of the present invention can be formed using methods such as atomic layer deposition (ALD). Examples of ALD methods include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. Because ALD allows for the deposition of atoms layer by layer, it offers several advantages, including the ability to deposit extremely thin films, deposit films on structures with high aspect ratios, deposit films with fewer defects such as pinholes, deposit films with excellent coverage, and deposit films at low temperatures.

[0051] The ALD method allows for control over the composition of the resulting film by adjusting the amount of raw material gas (precursor and reactant) introduced. For example, in the ALD method, films of any desired composition can be formed by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), and the time required for each pulse (also called the pulse duration). Furthermore, in the ALD method, films with continuously changing compositions can be formed by changing the raw material gas during film formation. When forming films while changing the raw material gas, the time required for film formation can be shortened compared to forming films using multiple deposition chambers, because the time required for transport and pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0052] Metal oxides may contain lattice defects. Lattice defects include point defects such as atomic vacancies and dissimilar atoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids. Factors that contribute to the formation of lattice defects include deviations in the ratio of constituent elements (excess or deficiency of constituent atoms) and impurities.

[0053] When metal oxides are used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or trapping. Therefore, using a metal oxide with many lattice defects in the semiconductor layer of a transistor may lead to unstable electrical properties of the transistor. For this reason, it is preferable to use a metal oxide with few lattice defects in the semiconductor layer of a transistor.

[0054] Metal oxides used in the semiconductor layer of a transistor are sometimes called oxide semiconductors. In a transistor using an oxide semiconductor for the semiconductor layer, oxygen vacancies (V) are present in the channel formation region of the oxide semiconductor. Ｏ The presence of impurities can easily lead to fluctuations in electrical properties and reduced reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical properties of OS transistors. Examples of impurities include hydrogen and carbon.

[0055] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons, which act as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to produce normally-ion transistors. For this reason, it is preferable to minimize the amount of hydrogen in the channel-forming region of the oxide semiconductor.

[0056] Furthermore, grain boundaries in metal oxides can scatter carriers, potentially reducing the current flowing through the transistor. Therefore, it is preferable to have fewer grain boundaries in metal oxides. Note that metal oxides with fewer grain boundaries also tend to contain larger grains.

[0057] By using an oxide semiconductor with sufficiently reduced impurities and large crystal grains in the channel formation region of a transistor, stable electrical properties can be imparted.

[0058] Figures 1A and 1B show a metal oxide according to one embodiment of the present invention. As shown in Figure 1A, the metal oxide according to one embodiment of the present invention can have a two-layer structure, comprising a first layer 101 formed on a substrate 100 under first film deposition conditions, and a second layer 102 formed on the first layer 101 under second film deposition conditions. The first layer 101 and the second layer 102 are preferably indium oxide. Note that the boundary between the first layer 101 and the second layer 102 may not be clear. Note that the substrate 100 may be provided with one or more of the following: conductors such as gate electrodes, source electrodes, and drain electrodes; insulators such as gate insulating films, interlayer insulating films, and underlayer insulating films; and semiconductors such as metal oxides or silicon.

[0059] In one embodiment of the present invention, a method for forming a metal oxide film is used in the ALD method, with first and second film formation conditions. The first film formation condition is preferably one in which the introduction time of the reactant (oxidizing agent, nonmetallic precursor, etc.) is shorter than that of the second film formation condition. In other words, the second film formation condition is preferably one in which the introduction time of the reactant (oxidizing agent, nonmetallic precursor, etc.) is longer than that of the first film formation condition.

[0060] The first film formation condition is preferably one that contributes to grain expansion (a condition with a low nucleation frequency) compared to the second film formation condition. The second film formation condition is preferably one that reduces the amount of impurities (e.g., carbon) in the film compared to the first film formation condition.

[0061] The first film formation condition is preferably one in which the crystal grains of the metal oxide film are larger compared to the second film formation condition. Alternatively, the first film formation condition is preferably one in which the crystal nuclei in the metal oxide film are not densely packed (sparsely packed) compared to the second film formation condition.

[0062] According to one embodiment of the present invention, a method for forming a metal oxide film can be used to reduce impurities such as hydrogen and carbon, and to form a metal oxide with good crystallinity and large crystal grains.

[0063] Furthermore, the metal oxide according to one embodiment of the present invention can also be formed by three or more different film formation conditions. As an example, Figure 1B shows the metal oxide when a third layer 103 is added to Figure 1A.

[0064] The metal oxide consists of a first layer 101 formed on the substrate 100 under first film deposition conditions, a second layer 102 formed on the first layer 101 under second film deposition conditions, and a third layer 103 formed on the second layer 102 under third film deposition conditions. The third layer 103 is preferably indium oxide. Note that the boundaries between each layer may not be clearly defined.

[0065] The second film formation condition is preferably one in which the introduction time of the reactant (oxidizing agent, nonmetallic precursor, etc.) is shorter than that of the third film formation condition. In other words, the third film formation condition is preferably one in which the introduction time of the reactant (oxidizing agent, nonmetallic precursor, etc.) is longer than that of the second film formation condition. The second film formation condition is preferably one in which the conditions contribute to grain expansion (conditions with a low frequency of nucleation) compared to that of the third film formation condition. The third film formation condition is preferably one in which the amount of impurities (e.g., carbon) in the film is lower than that of the second film formation condition. The second film formation condition is preferably one in which the grain size of the metal oxide film is larger than that of the third film formation condition. Alternatively, the second film formation condition is preferably one in which the crystal nuclei in the metal oxide film are not densely packed (are sparse) compared to that of the third film formation condition.

[0066] [Method and sequence for forming metal oxide films using the ALD method] A method for forming metal oxide films using the ALD method according to one aspect of the present invention will be described.

[0067] A film deposition apparatus utilizing the ALD method uses, for example, a first precursor (sometimes called a metal precursor) and a first reactant (sometimes called a reactant, oxidizing agent, or nonmetal precursor) as raw material gases. Film deposition is performed by alternately introducing the first precursor and the first reactant into the chamber and repeating this process. The introduction of the raw material gases can be switched, for example, by switching the respective switching valves (sometimes called high-speed valves). Alternatively, a carrier gas may be introduced into the chamber along with the raw material gas. Using a carrier gas makes it possible to introduce the raw material gas into the chamber even when the volatility or vapor pressure of the raw material gas is low, by suppressing adsorption of the raw material gas inside the piping and valves. This also improves the uniformity of the formed film, which is desirable.

[0068] As the carrier gas, an inert gas (for example, nitrogen gas, one or more noble gases) can be used. For example, as the inert gas used as the carrier gas, nitrogen (N ２ ), argon (Ar), or helium (He), or mixtures thereof can be used.

[0069] Figure 2 shows the ALD film deposition sequence for the first layer 101 and the second layer 102 in Figure 1A. Sequence T1 is the sequence for one cycle of the first layer 101. Sequence T2 is the sequence for one cycle of the second layer 102. Figure 2 shows the sequence when the first precursor P01 and the first reactant R01 are used as the raw material gases. The vertical axis shows the introduction of the raw material gas into the chamber as ON, and the period when the raw material gas is not introduced as OFF. The horizontal axis represents time.

[0070] As shown in Figure 2, sequences T1 and T2 each have a first step S01 to a fourth step S04.

[0071] In the first step S01, the first precursor P01 is introduced into the chamber. The first step S01 corresponds to the time during which the first precursor P01 is introduced into the chamber. The first precursor P01 introduced into the chamber is adsorbed onto the surface to be formed (for example, the surface of the substrate 100). The first step S01 is terminated by stopping the introduction of the first precursor P01.

[0072] As the first precursor P01, an indium-containing precursor can be used. Examples of indium-containing precursors include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, and indium(III) chloride.

[0073] The second step S02 is performed after the first step S01. In the second step S02, a purge gas is introduced into the chamber to discharge excess first precursor P01 and reaction products from the chamber. Alternatively, instead of introducing a purge gas into the chamber, excess first precursor P01 and reaction products may be discharged from the chamber by vacuum evacuation. The second step S02 is also called purging. The second step S02 corresponds to the time spent discharging excess first precursor P01 and reaction products from the chamber. The second step S02 is completed by introducing an inert gas or stopping vacuum evacuation.

[0074] An inert gas can be used as the purge gas. For example, nitrogen (N) can be used as the inert gas for the purge gas. ２ ), argon (Ar), or helium (He), or mixtures thereof can be used.

[0075] After the second step S02, a third step S03 is performed. In the third step S03, a first reactant R01 is introduced into the chamber. The third step S03 corresponds to the time during which the first reactant R01 is introduced into the chamber. The first reactant R01 introduced into the chamber reacts with the first precursor P01 adsorbed on the formation surface (e.g., the surface of the substrate 100), and a part of the components contained in the first precursor P01 is desorbed while the constituent molecules of the first precursor P01 remain adsorbed on the formation surface (e.g., the surface of the substrate 100). As a result, a metal oxide layer formed by oxidizing the first precursor P01 adsorbed on the formation surface (e.g., the surface of the substrate 100) is formed on the formation surface (e.g., the surface of the substrate 100). The third step S03 ends by stopping the introduction of the first reactant R01.

[0076] As the first reactant R01, an oxidizing agent, a non-metal precursor, etc. can be used. As the oxidizing agent, for example, an oxidizing agent (ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２ ), and a mixed gas thereof, and also, plasmas, radicals, ions, etc. of these can be used. Further, in order to reduce the hydrogen concentration in the metal oxide, a reactant not containing hydrogen is preferable, and it is preferable to use one or both of ozone or oxygen.

[0077] After the third step S03, a fourth step S04 is performed. In the fourth step S04, the excess first reactant R01, reaction products, etc. are discharged from the chamber in the same manner as in the second step S02. Note that the fourth step S04 is also called a purge. The fourth step S04 corresponds to the time for discharging the excess first reactant R01, reaction products, etc. from the chamber. The fourth step S04 ends by introducing an inert gas or stopping the evacuation.

[0078] In the ALD method, a first layer 101 of a desired thickness can be formed by repeating sequence T1, which includes the introduction of a first precursor P01 (first step S01), purging (second step S02), introduction of a first reactant R01 (third step S03), and purging (fourth step S04), for X cycles. Furthermore, a second layer 102 of a desired thickness can be formed by repeating sequence T2 for Y cycles.

[0079] In the formation of a metal oxide, when transitioning from the deposition of the first layer 101 to the deposition of the second layer 102, it is preferable to maintain the substrate 100 under reduced pressure. Alternatively, the deposition of the first layer 101 may be performed in the same chamber while maintaining reduced pressure inside the chamber. Or, after the deposition of the first layer 101 in the chamber, the substrate 100 may be moved to the loading / unloading chamber of the deposition apparatus, and then the substrate 100 may be placed back into the same chamber to deposit the second layer 102. In this case as well, it is preferable to maintain the substrate 100 under reduced pressure when transitioning from the deposition of the first layer 101 to the deposition of the second layer 102. Furthermore, the deposition of the first layer 101 may be performed in the first chamber, and the deposition of the second layer 102 may be performed in the second chamber. In this case as well, when transitioning from the deposition of the first layer 101 to the deposition of the second layer 102, it is preferable to keep the substrate 100 under reduced pressure.

[0080] By maintaining the substrate under reduced pressure in this way, the substrate 100 can be prevented from being exposed to the atmosphere between the deposition of the first layer 101 and the deposition of the second layer 102, thereby enabling the production of a metal oxide with reduced impurity concentration.

[0081] In the formation of a metal oxide, when transitioning from the deposition of the first layer 101 to the deposition of the second layer 102, it is preferable to lower the temperature of the substrate 100 to the substrate temperature at the time of deposition of the first layer 101. Furthermore, it is preferable to then raise the temperature of the substrate 100 to the substrate temperature at the time of deposition of the second layer 102. For example, the substrate 100 may be held in the first chamber and the process may be transitioned from the deposition of the first layer 101 to the deposition of the second layer 102 in the same chamber. Alternatively, after the substrate 100 with the first layer 101 deposited is moved from the first chamber to the loading / unloading chamber of the deposition apparatus, the substrate 100 may be placed back into the first chamber to deposit the second layer 102. Alternatively, the first layer 101 may be deposited in the first chamber and the second layer 102 may be deposited in the second chamber. In these cases as well, it is preferable to lower the temperature of the substrate 100 between the deposition of the first layer 101 and the deposition of the second layer 102 to a temperature lower than the substrate temperature at the time of deposition of the first layer 101, and then raise the temperature of the substrate 100 to the substrate temperature at the time of deposition of the second layer 102.

[0082] By lowering the temperature of the substrate 100 after the deposition of the first layer 101, the crystallization of the first layer 101 can be promoted.

[0083] The above example shows film formation using one type of precursor, but film formation may also be performed using two or more types of precursors.

[0084] In sequences T1 and T2, the duration of the third step S03 is at least different. Specifically, it is preferable that the duration of the third step S03 in sequence T2 is longer than the duration of the third step S03 in sequence T1. In other words, it is preferable that the duration of the third step S03 in sequence T1 is shorter than the duration of the third step S03 in sequence T2. In one embodiment of the present invention, by combining the film formation conditions of sequence T1, in which the duration of the third step is short, with the film formation conditions of sequence T2, it is possible to suppress the increase in the film formation time of the metal oxide and improve productivity.

[0085] The carbon concentration in the metal oxide can be reduced by increasing the duration of the third step S03. On the other hand, if the duration of the third step S03 is made too long, the time for one cycle will increase, which may lead to a longer film deposition time required to obtain the desired film thickness and a decrease in productivity. Therefore, the duration of the third step S03, which is the introduction time for the reactant R01, needs to be kept to an appropriate length.

[0086] The hydrogen concentration in the metal oxide can be reduced by shortening the time of the third step S03. On the other hand, if the time of the third step S03 is shortened too much, there is a concern that the carbon concentration contained in the metal oxide will not be reduced. Therefore, the third step S03 needs to be set to an appropriate time for introducing the reactant R01.

[0087] Furthermore, the shorter the time in the third step S03, the more crystal nucleation is suppressed, allowing for larger crystal grains of the metal oxide.

[0088] Furthermore, in one embodiment of the present invention, the metal oxide tends to have a lower hydrogen concentration as the crystal grain size increases. Also, the second layer 102 deposited on the first layer 101 can form a metal oxide with larger crystal grains compared to when the second layer 102 is deposited as a single layer. Therefore, the metal oxide obtained by depositing the second layer 102 on the first layer 101 can be a metal oxide with large crystal grains and reduced hydrogen and carbon concentrations.

[0089] The substrate temperature during film formation of the first layer 101 and the second layer 102 is, for example, 100°C to 600°C, preferably 200°C to 600°C, and more preferably 200°C to 400°C.

[0090] The time for the third step (introduction time of the reactant) S03 in sequence T1 is, for example, 0.1 sec to 30 sec, preferably 3 sec to 15 sec, and more preferably 5 sec to 15 sec. Typically, it is 9 sec.

[0091] The time for the third step (introduction time of reactants) S03 in sequence T2 is, for example, 15 sec to 180 sec, preferably 30 sec to 120 sec, and more preferably 30 sec to 90 sec. Typically, it is 60 sec.

[0092] The time of the third step S03 in sequence T1 and sequence T2 is preferably within the above time range, while maintaining the relationship that the time of the third step S03 in sequence T1 is shorter than the time of the third step S03 in sequence T2.

[0093] The thickness of the first layer 101 is preferably greater than or equal to the thickness at which crystal nuclei are generated. For example, it is 0.1 nm to 20 nm, preferably 1 nm to 10 nm, and more preferably 5 nm to 10 nm.

[0094] The film thickness of the second layer 102 is, for example, 1 nm to 100 nm, preferably 10 nm to 50 nm, and more preferably 10 nm to 30 nm.

[0095] Furthermore, the total film thickness of the first layer 101 and the second layer 102 is, for example, 3 nm to 100 nm, preferably 3 nm to 50 nm, and more preferably 3 nm to 20 nm. It is preferable that the film thickness of the second layer 102 is thicker than the film thickness of the first layer 101.

[0096] [Film Deposition Apparatus] As an example of an apparatus capable of depositing a metal oxide film according to one aspect of the present invention, the configuration of the film deposition apparatus 4000 will be described with reference to Figures 3, 4A, and 4B. Figure 3 is a schematic diagram of a multi-chamber type film deposition apparatus 4000, and Figures 4A and 4B are cross-sectional views of an ALD apparatus that can be used in the film deposition apparatus 4000.

[0097] The film deposition apparatus 4000 includes an input / output chamber 4002, an input / output chamber 4004, a transport chamber 4006, a film deposition chamber 4008, a film deposition chamber 4009, a processing chamber 4011, and a transport arm 4014. Here, the input / output chambers 4002, 4004, 4008, 4009, and 4011 are independently connected to the transport chamber 4006 via gate valves. This allows for continuous processing in the film deposition chambers 4008, 4009, and 4011 without exposure to the atmosphere, preventing impurities from entering the film. Furthermore, contamination of the substrate-film interface and the interfaces between each film is reduced, resulting in clean interfaces.

[0098] Furthermore, it is preferable to fill loading / unloading room 4002, loading / unloading room 4004, transport room 4006, film deposition room 4008, film deposition room 4009, and processing room 4011 with an inert gas with a controlled dew point to prevent moisture from adhering to them, and it is desirable to maintain a reduced pressure.

[0099] Furthermore, ALD (Advanced Laser Deposition) equipment can be used in deposition chambers 4008 and 4009. Alternatively, a deposition apparatus other than an ALD apparatus may be used in either deposition chamber 4008 or 4009. Examples of deposition apparatus that can be used in deposition chambers 4008 and 4009 include sputtering equipment, plasma CVD (PECVD) equipment, thermal CVD (TCD) equipment, photo CVD (Photo CVD) equipment, metal CVD (MCCVD) equipment, and metal-organic CVD (MOCVD) equipment.

[0100] Furthermore, the processing chamber 4011 may be equipped with devices that have functions other than film deposition, such as a heating device (typically a vacuum heating device), a plasma generator, or a microwave-excited high-density plasma processing device. For example, the processing chamber 4011 may be configured to use a heating device. By performing the heating treatment, impurities such as hydrogen or carbon contained in the metal oxide can be removed. In addition, at the same time as the removal of impurities, the rearrangement of metal atoms and oxygen atoms can be performed, thereby improving crystallinity. Alternatively, for example, the processing chamber 4011 may be configured to use a microwave-excited high-density plasma processing device. By performing microwave-excited high-density plasma treatment, impurities such as hydrogen or carbon contained in the metal oxide can be removed. Since the processing chamber 4011 is connected to the film deposition chambers 4008 and 4009 via the transport chamber 4006, the process can be carried out continuously without being exposed to the outside air.

[0101] For example, if the deposition chamber 4008 is used as an ALD apparatus, the deposition chamber 4009 as a sputtering apparatus, and the processing chamber 4011 as a heating apparatus, then an underlay insulating film can be deposited in the deposition chamber 4009, a metal oxide according to one embodiment of the present invention can be deposited in the deposition chamber 4008, and the metal oxide can be heat-treated in the processing chamber 4011. In this case, the deposition of the underlay insulating film, the deposition of the oxide semiconductor film, and the heat treatment can be carried out continuously without exposure to the atmosphere.

[0102] Furthermore, the film deposition apparatus 4000 is configured to include a loading / unloading chamber 4002, a loading / unloading chamber 4004, a film deposition chamber 4008, a film deposition chamber 4009, and a processing chamber 4011, but the present invention is not limited thereto. The film deposition apparatus 4000 may be configured to have one or three or more film deposition chambers. The film deposition apparatus 4000 may also be configured without a processing chamber, or with two or more processing chambers. In addition, the film deposition apparatus 4000 may be a single-wafer type or a batch type that deposits film on multiple substrates at once.

[0103] Next, the configuration of the thermal ALD apparatus that can be used in the film deposition apparatus 4000 will be explained with reference to Figure 4A. The thermal ALD apparatus has a film deposition chamber (chamber 4520), a raw material supply unit 4521 (raw material supply units 4521a to 4521c), a raw material supply unit 4531, high-speed valves 4522a to 4522d which are introduction amount controllers, a gas supply unit 4532, a raw material inlet 4523, a raw material outlet 4524, and an exhaust device 4525. The raw material inlet 4523 installed in the chamber 4520 is connected to the raw material supply units 4521a, 4521b, 4521c, 4531, and 4532 via supply pipes and valves, respectively, and the raw material outlet 4524 is connected to the exhaust device 4525.

[0104] A substrate holder 4526 is located inside the chamber 4520, and the substrate 4530 is placed on the substrate holder 4526. The substrate holder 4526 may have a rotation mechanism. A heater 4527 is provided on the outer wall of the chamber 4520, which can control the temperature inside the chamber 4520, the substrate holder 4526, and the surface of the substrate 4530. The heater 4527 is preferably capable of controlling the temperature of the substrate 4530 surface to between 100°C and 600°C, preferably between 200°C and 600°C, more preferably between 200°C and below the decomposition temperature of the precursor, and the temperature of the heater 4527 itself is preferably set to between 100°C and 600°C. By performing film deposition while heating the substrate within this temperature range, impurities such as hydrogen or carbon contained in the precursor or reactant can be suitably reduced from the metal oxide. Furthermore, simultaneously with the removal of the above-mentioned impurities, rearrangement of metal atoms and oxygen atoms occurs, allowing each oxide layer to be arranged with high order. Therefore, a metal oxide with a highly crystalline, layered crystalline structure can be formed. Furthermore, heat treatment after metal oxide film formation may be performed using the heater 4527.

[0105] In the raw material supply units 4521a, 4521b, 4521c, and 4531, a raw material gas is formed from solid or liquid raw materials by a vaporizer or heating means. Alternatively, the raw material supply units 4521a, 4521b, 4521c, and 4531 may be configured to supply a gaseous raw material gas.

[0106] In the film deposition apparatus shown in Figure 4A, metal oxides can be formed by appropriately selecting raw materials to be used in the raw material supply unit 4521 and raw material supply unit 4531 and introducing them into the chamber 4520. For example, a configuration can be used in which a precursor containing indium is supplied from the raw material supply unit 4521a. Reactants are supplied from the raw material supply unit 4531. A carrier gas is supplied from the gas supply unit 4532. The precursor from the raw material supply unit 4521 and the reactants from the raw material supply unit 4531 are mixed with the carrier gas and introduced into the chamber 4520.

[0107] Furthermore, a pipe heater 4534a is provided to cover the piping or valves between the raw material supply units 4521a, 4521b, 4521c, 4531, and 4532 and the chamber 4520. Also, a pipe heater 4534b is provided to cover the piping or valves between the exhaust device 4525 and the chamber 4520. The temperatures of the pipe heaters 4534a and 4534b can be appropriately set within a range of, for example, room temperature or above 300°C. By providing such pipe heaters, it is possible to prevent precursors supplied from the raw material supply unit 4521 from solidifying on the inner walls of the piping of the gas introduction system and gas exhaust system. In particular, precursors with high decomposition temperatures, such as inorganic precursors, tend to solidify easily, so when using such precursors, it is preferable to provide a configuration in which pipe heaters are provided to cover the piping of the gas introduction system and gas exhaust system. Furthermore, the temperature control of the pipe heaters 4534a, 4534b, and 4527 can be configured to be controlled independently. By controlling the pipe heaters 4534a, 4534b, and 4527 independently, the temperature of each heater can be controlled individually. However, this is not limited to this configuration, and the temperature control of the pipe heaters 4534a, 4534b, and 4527 can also be configured to be linked. In this case, the temperature control can be adjusted collectively, which reduces the cost of equipment components.

[0108] The high-speed valves 4522a to 4522d can be precisely controlled over time. This configuration allows for the control of the raw material gas supplied from the raw material supply units 4521a, 4521b, 4521c, and 4531 and their introduction into the chamber 4520.

[0109] For example, when supplying precursors contained in raw material supply units 4521a, 4521b, and 4521c, the corresponding high-speed valves from high-speed valves 4522a to 4522c should be opened. Also, when supplying reactants contained in raw material supply unit 4531, high-speed valve 4522d should be opened. Furthermore, when purging chamber 4520, high-speed valves 4522a to 4522d should be closed, and only the carrier gas contained in gas supply unit 4532 should be introduced into chamber 4520.

[0110] Furthermore, Figure 4A shows an example in which three raw material supply units 4521 and one raw material supply unit 4531 are provided, but this embodiment is not limited to this. One, two, or four or more raw material supply units 4521 may be provided. Also, two or more raw material supply units 4531 may be provided.

[0111] Furthermore, in Figure 4A, the heater 4527, raw material inlet 4523, and raw material outlet 4524 are located at the bottom of the chamber 4520, but this is not limited to this arrangement, and their placement can be set as appropriate. Also, in Figure 4A, the inlets for the raw material supply units 4521a, 4521b, 4521c, 4531, and gas supply unit 4532 are grouped into the raw material inlet 4523, but this is not limited to this arrangement, and each may be configured with a separate inlet.

[0112] Next, the configuration of the plasma ALD apparatus that can be used in the film deposition apparatus 4000 will be explained with reference to Figure 4B. The plasma ALD apparatus has a film deposition chamber (chamber 4020), a raw material supply unit 4021 (raw material supply units 4021a to 4021c), a raw material supply unit 4031, high-speed valves 4022a to 4022d which are introduction amount controllers, a gas supply unit 4032, a raw material inlet 4023, a raw material inlet 4033, a raw material outlet 4024, and an exhaust device 4025. The raw material inlet 4023 and raw material inlet 4033 installed in the chamber 4020 are connected to the raw material supply units 4021a, 4021b, 4021c, 4031, and gas supply unit 4032, respectively, via supply pipes and valves, and the raw material outlet 4024 is connected to the exhaust device 4025. Furthermore, a substrate holder 4026 is located inside the chamber 4020, and the substrate 4030 is placed on the substrate holder 4026. In addition, a heater 4027 is provided on the outer wall of the chamber, and pipe heaters 4034a and 4034b are provided to cover the piping connected to the chamber.

[0113] Here, chamber 4020 corresponds to chamber 4520, raw material supply unit 4021 to raw material supply unit 4521, raw material supply unit 4031 to raw material supply unit 4531, high-speed valves 4022a to 4022d to high-speed valves 4522a to 4522d, gas supply unit 4032 to gas supply unit 4532, raw material inlet 4023 to raw material inlet 4523, raw material outlet 4024 to raw material outlet 4524, exhaust device 4025 to exhaust device 4525, substrate holder 4026 to substrate holder 4526, substrate 4030 to substrate 4530, heater 4027 to heater 4527, piping heater 4034a to piping heater 4534a, and piping heater 4034b to piping heater 4534b. For detailed configurations, please refer to the above description.

[0114] As shown in Figure 4B, the plasma ALD apparatus can perform film deposition using the plasma ALD method in addition to the thermal ALD method by connecting a plasma generator 4028 to the chamber 4020. The plasma generator 4028 is preferably an inductively coupled plasma (ICP) type plasma generator using a coil 4029 connected to a high-frequency power supply. The high-frequency power supply can output power with a frequency of 10 kHz to 100 MHz, preferably 1 MHz to 60 MHz, and more preferably 2 MHz to 60 MHz. For example, it can output power with a frequency of 13.56 MHz. Since the plasma ALD method allows film deposition without reducing the deposition rate even at low temperatures, it is suitable for use with single-wafer deposition apparatuses that have low deposition efficiency.

[0115] The reactant discharged from the raw material supply unit 4031 passes through the plasma generator 4028 and becomes a plasma. The reactant in plasma state is introduced into the chamber 4020 from the raw material inlet 4033. Although not shown in Figure 4B, the reactant discharged from the raw material supply unit 4031 may be mixed with a carrier gas.

[0116] Furthermore, the substrate holder 4526 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, the substrate holder 4526 may be floating or grounded.

[0117] In Figure 4B, the raw material inlet 4033 is located at the top of the chamber 4520, the heater 4027 and raw material inlet 4023 are located on the side of the chamber 4520, and the raw material outlet 4524 is located at the bottom of the chamber 4520. However, the arrangement is not limited to this, and these can be set as appropriate.

[0118] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0119] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0120] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0121] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0122] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0123] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single crystals.

[0124] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２It can be expected to be raised to the level of / (V・s).

[0125] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0126] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0127] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0128] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0129] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0130] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0131] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0132] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0133] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0134] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0135] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0136] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0137] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0138] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0139] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0140] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰−２１ A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0141] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0142] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0143] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0144] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0145] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0146] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0147] (Embodiment 3) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0148] [Example of Semiconductor Device Configuration 1] Figures 5A to 5D show an example of a semiconductor device. Figure 5A is a plan view of a semiconductor device having a transistor 10. Figure 5B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 5A. Figure 5C is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 5A. Figure 5D is a horizontal cross-sectional view between the dashed lines C1 and C2 shown in Figure 5B.

[0149] The transistor 10 has at least a conductive layer 12, a conductive layer 17, a conductive layer 20, a semiconductor layer 18, and an insulating layer 19. Part or all of the conductive layer 12 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 17 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 20 functions as a gate electrode. Part or all of the insulating layer 19 functions as a gate insulating film.

[0150] When transistor 10 is used as a memory cell, the conductive layer 17 has a region that functions as a bit line. The conductive layer 20 also has a region that functions as a word line.

[0151] As shown in Figures 5A to 5C, the transistor 10 has a configuration in which current flows in the vertical direction, with one of the source electrode and drain electrode (here, the conductive layer 12) located below and the other source electrode and drain electrode (here, the conductive layer 17) located above. The source electrode and drain electrode are located at different heights (for example, heights perpendicular to the substrate surface or insulating plane on which the transistor is mounted), and the current flowing through the semiconductor layer flows in the height direction. That is, the channel length direction has a component in the height direction (vertical direction), and can therefore be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, or vertical channel type transistor. In one embodiment of the present invention, the source electrode, semiconductor layer, and drain electrode can be stacked, so the occupied area can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a planar shape. Therefore, semiconductor devices can be highly integrated. Furthermore, when a semiconductor device according to one embodiment of the present invention is used as a memory device, the storage capacity per unit area can be increased.

[0152] The insulating layer 11 is provided on a substrate (not shown). The insulating layer 11 functions as an underlay insulating film, an etching stop film, and the like.

[0153] As the insulating layer 11, for example, an inorganic insulating film such as silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide can be used. Alternatively, an insulating film (also called ZAZ) laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. The insulating layer 11 may be planarized by a method such as CMP so that the upper surface of the insulating layer 11 is flat. Furthermore, by using silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide for the insulating layer 11, the diffusion of impurities from structures below the semiconductor layer 18 can be suppressed.

[0154] The conductive layer 12 (conductive layer 12_1, conductive layer 12_2 on conductive layer 12_1, and conductive layer 12_3 on conductive layer 12_2) is provided on the insulating layer 11. Figures 5A to 5C show an example configuration in which the conductive layer 12 extends in the Y direction. The conductive layer 12 may be in an island shape, or it may extend in the X direction, or in a direction oblique to both the X and Y directions (i.e., a direction intersecting both the X and Y directions). An example of the conductive layer 12 being three layers, conductive layer 12_1, conductive layer 12_2, and conductive layer 12_3, is shown, but it can also be formed as a single layer, two layers, or a laminate of four or more layers. Figure 5B shows an example in which the side surface of the conductive layer 12 is perpendicular to the surface to be formed, but the side surface of the conductive layer 12 may be a tapered shape inclined with respect to the surface to be formed.

[0155] The conductive layer 12 has a region that is in contact with the semiconductor layer 18. When an oxide semiconductor is used as the semiconductor layer, if an easily oxidizable metal such as aluminum is used in the region of the conductive layer that is in contact with the semiconductor layer, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer and the semiconductor layer, which may hinder conductivity. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide in at least the region of the conductive layer that is in contact with the semiconductor layer.

[0156] Examples of conductive oxides that can be used include indium oxide, indium tin oxide (In-Sn oxide, also called ITO), silicon-containing indium tin oxide (In-Sn-Si oxide, also called ITSO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, and In-Ti-Sn oxide. Conductive oxides containing indium are particularly preferred due to their high conductivity. Alternatively, oxide semiconductors applicable to the semiconductor layer 18 can also be used as conductive layers by increasing the carrier concentration.

[0157] Titanium nitride can be used as the conductive layer 12_1. Tungsten can be used as the conductive layer 12_2. A conductive oxide can be used as the conductive layer 12_3. Examples of conductive oxides include ITO and ITSO. The conductive layer 12 can be formed using deposition methods such as metal CVD, sputtering, and ALD. By using a material with lower resistance for conductive layer 12_2 than the conductive oxide used for conductive layer 12_3, such as tungsten, the wiring resistance of the conductive layer 12 can be reduced. Furthermore, by using titanium nitride for conductive layer 12_1, oxidation of the conductive material used for conductive layer 12_2 can be suppressed.

[0158] The insulating layer 13 is provided so as to cover the conductive layer 12. The insulating layer 14 is provided on top of the insulating layer 13, and its upper surface may be flattened by a planarization treatment such as the CMP method. Alternatively, the insulating layer 14 may be provided without the insulating layer 13.

[0159] The insulating layer 13 and the insulating layer 14 can be, for example, silicon nitride, silicon oxide nitride, etc. Furthermore, by using silicon nitride, silicon oxide nitride, etc. for one or both of the insulating layer 13 or insulating layer 14, the diffusion of impurities from the structure below the semiconductor layer 18 can be suppressed.

[0160] The insulating layer 15 is provided on top of the insulating layer 14. Note that if the insulating layer 13 is provided, the insulating layer 15 may be provided instead of the insulating layer 14. The upper surface of the insulating layer 15 may be planarized using a method such as CMP to ensure a flat surface.

[0161] The insulating layer 15 can be made of, for example, silicon oxide or silicon oxynitride. The insulating layer 15 can be formed using film deposition methods such as sputtering, CVD, or ALD. It is preferable to use a film deposited by sputtering, in which the deposition gas does not contain hydrogen, for the insulating layer 15.

[0162] Furthermore, it is preferable to perform a heat treatment after the insulating layer 15 is formed. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an inert gas atmosphere (e.g., nitrogen gas, noble gas, or both), or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to use an oxygen gas of about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after performing the heat treatment in an inert gas atmosphere (e.g., nitrogen gas, noble gas, or both), it may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. By performing the heat treatment as described above, impurities such as water and hydrogen contained in the insulating layer 15 can be reduced before the formation of the oxide semiconductor film that will become the semiconductor layer.

[0163] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb (1 × 10⁻¹⁶). −３ ppm) or less, preferably 0.1 ppb (1 × 10⁻¹⁰ −４ ppm) or less, more preferably 0.05 ppb (5 × 10⁻¹⁰ −５ It is preferable to keep the concentration below ppm. By performing heat treatment using highly purified gas, it is possible to prevent moisture and other substances from being incorporated into the insulating layer 15 as much as possible.

[0164] There are no special limitations on the equipment used for heat treatment; it may be an equipment that heats the workpiece by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) equipment such as an LRTA (Lamp Rapid Thermal Anneal) or GRTA (Gas Rapid Thermal Anneal) equipment can be used. An LRTA equipment is an equipment that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA equipment is an equipment that performs heat treatment using high-temperature gas.

[0165] It is preferable to use an insulating layer 15 that easily forms regions containing excess oxygen. It is also preferable that it has a function to release oxygen. Furthermore, it is possible to perform a process to supply oxygen to the insulating layer 15. Oxygen is supplied to the insulating layer 15, and then, due to heat applied after the formation of the semiconductor layer 18, oxygen can be supplied from the insulating layer 15 to the semiconductor layer 18.

[0166] Examples of oxygen supply processes include heating in an oxygen-containing atmosphere or microwave-excited high-density plasma treatment in an oxygen-containing atmosphere. Another example is a method of forming the insulating layer 15 in an oxygen-containing atmosphere.

[0167] Alternatively, as a means of supplying oxygen, an oxide film (preferably a metal oxide film) may be deposited on the insulating layer 15 by sputtering in an oxygen-containing atmosphere, thereby supplying oxygen to the insulating layer 15. It is preferable to remove the deposited oxide film afterward. For example, an oxide film such as aluminum oxide or an oxide semiconductor may be deposited by sputtering and removed by a combination of one or more methods such as CMP, wet etching, or dry etching. If the thickness of the insulating layer 15 decreases when removing the oxide film by CMP, the insulating layer may be deposited again. The oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N２ The atmosphere includes a gas containing oxygen-containing compounds such as O). The substrate temperature during plasma treatment shall be between room temperature (25°C) and 450°C. Furthermore, the oxygen supply process described above may be performed multiple times as the same process, or multiple times in combination of different processes.

[0168] The insulating layer 16 is provided on top of the insulating layer 15.

[0169] The insulating layer 16 can be made of insulating materials such as silicon nitride or silicon nitride oxide. By using these insulating materials, oxidation of the conductive layer 17 can be suppressed. Furthermore, the diffusion of impurities from the layer above the insulating layer 16 to the insulating layer 15 or the semiconductor layer 18 in contact with the insulating layer 15 can be suppressed.

[0170] The conductive layer 17 (conductive layer 17_1, conductive layer 17_2 on conductive layer 17_1) is provided on the insulating layer 16. Figures 5A to 5C show an example configuration in which the conductive layer 17 extends in the X direction. The conductive layer 17 may also extend in the Y direction or in a direction oblique to both the X and Y directions (i.e., a direction intersecting both the X and Y directions). An example is shown in which the conductive layer 17 consists of two layers, conductive layer 17_1 and conductive layer 17_2, but it can also be formed as a single layer or as a stack of three or more layers.

[0171] The conductive layer 17 can refer to the contents of the conductive layer 12. For example, conductive layer 17_1 can refer to the contents of conductive layer 12_2, and conductive layer 17_2 can refer to the contents of conductive layer 12_3.

[0172] For example, tungsten can be used as the conductive layer 17_1. For example, a conductive oxide can be used as the conductive layer 17_2. Examples of conductive oxides that can be used include ITO and ITSO.

[0173] The opening 90 is provided in the insulating layer 13, insulating layer 14, insulating layer 15, insulating layer 16, and conductive layer 17, and reaches the conductive layer 12.

[0174] As shown in Figure 5B, the region of the conductive layer 12 that overlaps with the opening 90 has a recess. Also, in a plan view, the opening 90 is located inside the conductive layer 12. In a plan view, the side surface of the insulating layer 13 at the opening 90 overlaps with the conductive layer 12.

[0175] Although the illustration shows the opening 90 as circular in plan view, it may also be rectangular, elliptical, or polygonal. Furthermore, the shape and size in plan view may differ for each of the insulating layers 13, 14, 15, and 16. For example, the opening diameter D of the opening 90 in insulating layer 13 may be smaller than the opening diameter D of the opening 90 in insulating layer 16. Also, at least a portion of the side surfaces of insulating layers 13, 14, 15, and 16 in the opening 90 may be tapered.

[0176] The semiconductor layer 18 is provided on the conductive layer 17 and has a region in contact with the conductive layer 17 and a region in contact with the conductive layer 12. More specifically, the semiconductor layer 18 has a region in contact with the upper surface of the conductive layer 17 outside the opening 90 and a region in contact with the side surface of the conductive layer 17 at the opening 90. The semiconductor layer 18 also has a region in contact with the upper surface of the conductive layer 12 at the bottom of the opening 90. Furthermore, the semiconductor layer 18 has a region in contact with the side surface of the insulating layer 16, a region in contact with the side surface of the insulating layer 15, a region in contact with the side surface of the insulating layer 14, and a region in contact with the side surface of the insulating layer 13 at the opening 90.

[0177] The metal oxide that can be used in the semiconductor layer 18 is indium oxide as shown in Embodiments 1 and 2.

[0178] The semiconductor layer 18 can also be a laminated structure of indium oxide and other metal oxides. Other metal oxides include zinc oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as "GZO"), aluminum zinc oxide (Al-Zn oxide, also written as "AZO"), and indium aluminum zinc oxide. Lead oxide (In-Al-Zn oxide, also written as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as "IGAZO" or "IAGZO"), etc. can be used. Alternatively, indium tungsten oxide (In-W oxide, also written as IWO), etc. can be used. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0179] It is preferable to perform an impurity removal treatment on the metal oxide used in the semiconductor layer 18. The impurity removal treatment is preferably performed intermittently during the deposition of the metal oxide film. Alternatively, it is preferable to perform the impurity removal treatment after the deposition of the metal oxide film. By performing the impurity removal treatment during and / or after the deposition of the metal oxide film, impurities in the film can be removed. This suppresses the retention of impurities (hydrogen, carbon, nitrogen, etc.) contained in raw materials such as precursors in the metal oxide. It also suppresses the retention of impurities (hydrogen, carbon, nitrogen, etc.) that are incorporated during film deposition in the metal oxide. Therefore, the impurity concentration in the metal oxide can be reduced. Furthermore, the treatment to remove impurities contained in the metal oxide film can also serve to improve the crystallinity of the metal oxide film. By improving the crystallinity of the metal oxide film, a transistor with good reliability can be realized.

[0180] Examples of impurity removal treatments include microwave-excited high-density plasma treatment and heat treatment.

[0181] When performing microwave-excited high-density plasma treatment, it is preferable to set the substrate temperature to room temperature (e.g., 25°C) or higher and 500°C or lower, 100°C or higher and 500°C or lower, 200°C or higher and 500°C or lower, 300°C or higher and 500°C or lower, 400°C or higher and 500°C or lower, or 400°C or higher and 450°C or lower. The heat treatment temperature is preferably, for example, 100°C or higher and 950°C or lower, more preferably 250°C or higher and 650°C or lower, and even more preferably 350°C or higher and 450°C or lower.

[0182] The temperature during the impurity removal process should be set to a temperature below the maximum temperature in the transistor or semiconductor device manufacturing process, which is preferable as it reduces the impurity content in the metal oxide without decreasing productivity. For example, by setting the maximum temperature in the manufacturing of a semiconductor device according to one embodiment of the present invention to 500°C or less, preferably 450°C or less, the productivity of the semiconductor device can be increased.

[0183] Here, microwave-excited high-density plasma processing refers to processing using, for example, a device that has a power supply that generates high-density plasma using microwaves.

[0184] In microwave-excited high-density plasma processing, it is preferable to use a plasma processing apparatus that has a power supply for generating high-density plasma using microwaves. Here, the microwave frequency is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves to the microwave-excited high-density plasma processing apparatus is preferably 1000 W to 10000 W, and more preferably 2000 W to 5000 W. The microwave-excited high-density plasma processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the film.

[0185] Microwave-excited high-density plasma treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and even more preferably 350°C to 450°C.

[0186] Microwave-excited high-density plasma processing can be performed, for example, using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / ( O ２ The oxygen flow rate ratio (O) is greater than 0% and less than or equal to 100%. Preferably, the oxygen flow rate ratio (O) ２ / ( O ２ The oxygen flow rate ratio (O) is greater than 0% and 50% or less. ２ / ( O ２ The oxygen flow rate ratio (O) is set to 10% or more and 40% or less. More preferably, the oxygen flow rate ratio (O) ２ / ( O ２ The amount of +Ar)) should be between 10% and 30%.

[0187] Alternatively, after microwave-excited high-density plasma treatment, continuous heating treatment may be performed without exposure to the outside air.

[0188] Furthermore, the heat treatment is carried out in an inert gas atmosphere (e.g., nitrogen gas, a noble gas, or both) or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an inert gas atmosphere (e.g., nitrogen gas, a noble gas, or both), the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. The heat treatment may also be carried out in an atmosphere of ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, and more preferably 10 ppb or less).

[0189] By performing this heat treatment, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be removed by CO2. ２ And release as CO, and hydrogen in metal oxides H ２ It can be released as oxygen. Furthermore, simultaneously with the removal of the above-mentioned impurities, the rearrangement of metal atoms and oxygen atoms can occur, thereby improving crystallinity.

[0190] The insulating layer 19 is provided so as to cover the semiconductor layer 18. The insulating layer 19 has a region in contact with the semiconductor layer 18 at the opening 90. In addition, the insulating layer 19 has a region in contact with the insulating layer 16 outside the opening 90 and in a region that does not overlap with the conductive layer 17.

[0191] Although the example shown illustrates a single layer of the insulating layer 19, it can also be formed by laminating two or more layers.

[0192] The insulating layer 19 can be a four-layer structure, for example, using aluminum oxide, silicon oxide, hafnium oxide, and silicon nitride, arranged from the semiconductor layer 18 side to the conductive layer 20 side. It is preferable to use the ALD method for forming the insulating layer 19, as it provides better step coverage than other film formation methods.

[0193] The conductive layer 20 (conductive layer 20_1, conductive layer 20_2 on conductive layer 20_1) is provided on the insulating layer 19. The conductive layer 20 has a region between it and the semiconductor layer 18, with the insulating layer 19 sandwiched in between. Figures 5A to 5C show an example configuration in which the conductive layer 20 extends in the Y direction. The conductive layer 20 may also extend in the X direction, or in a direction oblique to the X and Y directions (i.e., a direction intersecting both the X and Y directions). An example is shown in which the conductive layer 20 consists of two layers, conductive layer 20_1 and conductive layer 20_2, but it can also be formed as a single layer or as a stack of three or more layers.

[0194] The conductive layer 20 has a region at the opening 90 in which an insulating layer 19 is sandwiched between it and the semiconductor layer 18.

[0195] Titanium nitride can be used as the conductive layer 20_1. Tungsten can be used as the conductive layer 20_2.

[0196] The conductive layer 20 can be formed using deposition methods such as metal CVD, sputtering, and ALD. By using a material with lower resistance for the conductive layer 20_2 than the conductive material used for conductive layer 20_1, such as tungsten, the wiring resistance of the conductive layer 20 can be reduced. Furthermore, by using titanium nitride for conductive layer 20_1, oxidation of the conductive material used for conductive layer 20_2 can be suppressed.

[0197] The insulating layer 21 is provided on the conductive layer 20 and is provided so as to cover the conductive layer 20.

[0198] For example, silicon nitride or silicon oxide nitride can be used as the insulating layer 21. Furthermore, by using silicon nitride or silicon oxide nitride for the insulating layer 21, the diffusion of impurities from structures above the insulating layer 21 can be suppressed.

[0199] The insulating layer 22 is provided on the insulating layer 21. Preferably, the upper surface of the insulating layer 22 is flat.

[0200] The insulating layer 22 can be made of, for example, silicon oxide or silicon oxynitride deposited by sputtering. The insulating layer 22 can be formed by a film deposition method such as sputtering, CVD, or ALD.

[0201] Furthermore, by having a recess in the region overlapping with the opening 90 of the conductive layer 12, the contact area between the conductive layer 12 and the semiconductor layer 18 can be increased compared to the case where there is no recess. As a result, the contact resistance between the conductive layer 12 and the semiconductor layer 18 can be reduced.

[0202] It is preferable that the depth of the recess in the conductive layer 12 be the same as or greater than the total film thickness of the semiconductor layer 18 and the insulating layer 19. It is also preferable that the height of the bottom surface of the conductive layer 20 within the opening 90 be the same as or lower than the height of the top surface of the conductive layer 12 other than the recess. With this configuration, compared to the case without a recess, the controllability of the electron density of the semiconductor layer 18 near one of the source electrode and drain electrode (in this case, the conductive layer 12) can be improved by the gate electric field from the gate electrode (conductive layer 20).

[0203] The recess in the conductive layer 12 may have a curved portion, as shown in Figures 5B and 5C. Because the recess has a curved portion, the regions of the semiconductor layer 18, insulating layer 19, and conductive layer 20 provided on the recess near the recess may also have a curved portion. In other words, these regions may have a curved or concave surface in cross-sectional view. Furthermore, these regions may not have corners (right angles or acute angles) in cross-sectional view. This reduces electric field concentration on the insulating layer 19 near the recess, improves the dielectric breakdown voltage of the transistor 10, and suppresses electrostatic discharge breakdown of the transistor 10. Therefore, the reliability of the semiconductor device can be improved.

[0204] Furthermore, as shown in Figures 5B and 5C, the semiconductor layer 18 is in contact with the conductive layer 17 and the conductive layer 12, and is provided along the sides of the insulating layer 16, insulating layer 15, insulating layer 14, and insulating layer 13 at the opening 90. Therefore, the channel length of the transistor 10 can be determined by the total film thickness of the insulating layers 13, 14, 15, and 16 on the conductive layer 12, and this channel length does not affect the area occupied by the transistor 10, for example, the area of ​​the transistor 10 in a plan view. In addition, the channel length of the transistor 10 can be controlled regardless of the performance of the exposure machine. For this reason, it is possible to set an extremely fine channel length below the exposure limit of photolithography.

[0205] Furthermore, by reducing the total thickness of insulating layers 13, 14, 15, and 16, transistors with extremely short channel lengths can also be fabricated. Transistors with channel lengths of, for example, 5 nm to 500 nm, preferably 7 nm to 300 nm, preferably 10 nm to 200 nm, preferably 10 nm to 200 nm, preferably 10 nm to 100 nm, preferably 10 nm to 50 nm, and preferably 10 nm to 30 nm can be fabricated. Therefore, transistors with channel lengths of less than 10 nm can be realized without using extremely expensive exposure equipment used in state-of-the-art LSI technology.

[0206] [Example of Semiconductor Device Configuration 2] Figures 6A to 7B show an example of a semiconductor device. Figure 6A is a plan view of a semiconductor device having a transistor 30. Figure 6B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 6A. Figure 7A is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 6A. Figure 7B is a horizontal cross-sectional view between the dashed lines C1 and C2 shown in Figure 6B.

[0207] The transistor 30 has at least a conductive layer 32, a conductive layer 37, a conductive layer 40, a semiconductor layer 38, and an insulating layer 39. Part or all of the conductive layer 32 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 37 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 40 functions as a gate electrode. Part or all of the insulating layer 39 functions as a gate insulating film.

[0208] When transistor 30 is used as a memory cell, part or all of the conductive layer 37 functions as part of the bit line. Also, part or all of the conductive layer 40 functions as a word line.

[0209] The insulating layer 31 is provided on a substrate (not shown). The insulating layer 31 functions as an underlay insulating film, an etching stop film, and the like.

[0210] The insulating layer 31 can refer to the contents described in the insulating layer 11.

[0211] The conductive layer 32 (conductive layer 32_1, conductive layer 32_2 on conductive layer 32_1, conductive layer 32_3 on conductive layer 32_2) is provided on the insulating layer 31. Figures 6A to 7A show an example of the conductive layer 32 being configured in an island shape. The conductive layer 32 may extend in the X direction, the Y direction, or in a direction oblique to both the X and Y directions (i.e., a direction intersecting both the X and Y directions). An example of the conductive layer 32 being composed of three layers, conductive layer 32_1, conductive layer 32_2, and conductive layer 12_3, is shown, but it can also be formed as a single layer, two layers, or a laminate of four or more layers. Figure 6B shows an example where the side surface of the conductive layer 32 is perpendicular to the surface to be formed, but the side surface of the conductive layer 32 may be tapered with respect to the surface to be formed.

[0212] The conductive layer 32 can refer to the contents of the conductive layer 12. For example, conductive layer 32_1 can refer to the contents of conductive layer 12_1, conductive layer 32_2 can refer to the contents of conductive layer 12_2, and conductive layer 32_3 can refer to the contents of conductive layer 12_3.

[0213] The insulating layer 33 is provided on the conductive layer 32, covering the conductive layer 32. The insulating layer 34 is provided on the insulating layer 33, and its upper surface may be flattened by a planarization treatment such as the CMP method. Alternatively, the insulating layer 34 may be provided without the insulating layer 33.

[0214] The insulating layer 33 can refer to the contents described in the insulating layer 13, and the insulating layer 34 can refer to the contents described in the insulating layer 14.

[0215] The insulating layer 35 is provided on top of the insulating layer 34. Note that if the insulating layer 33 is provided, the insulating layer 35 may be provided instead of the insulating layer 34. The upper surface of the insulating layer 35 may be planarized using a method such as CMP so that the upper surface is flat.

[0216] The insulating layer 35 can refer to the contents described in the insulating layer 15.

[0217] Furthermore, it is preferable to perform a heat treatment after the formation of the insulating layer 35 to reduce the amount of hydrogen in the insulating layer 35. The heat treatment can be described in relation to the heat treatment applicable to the insulating layer 15.

[0218] It is preferable to use an insulating layer 35 that easily forms regions containing excess oxygen. It is also preferable that it has a function to release oxygen. Furthermore, it is possible to perform a process to supply oxygen to the insulating layer 35. Oxygen is supplied to the insulating layer 35, and by heat applied after the formation of the semiconductor layer 38, oxygen can be supplied from the insulating layer 35 to the semiconductor layer 38. For means of supplying oxygen to the insulating layer 35, refer to the description of means of supplying oxygen to the insulating layer 15.

[0219] The insulating layer 36 is provided on top of the insulating layer 35.

[0220] The insulating layer 36 can refer to the contents described in the insulating layer 16.

[0221] The conductive layer 37a (conductive layer 37a_1, conductive layer 37a_2 on conductive layer 37a_1) and conductive layer 37b (conductive layer 37b_1, conductive layer 37b_2 on conductive layer 37b_1) are provided on the insulating layer 36. The conductive layers 37a and 37b can be in an island shape in plan view, as shown in Figure 6A. Although the conductive layer 37 is shown as two layers, conductive layer 37_1 and conductive layer 37_2, it can also be formed as a single layer or as a stack of three or more layers.

[0222] The conductive layer 37 can refer to the contents of the conductive layer 12. For example, conductive layer 37_1 can refer to the contents of conductive layer 12_2, and conductive layer 17_2 can refer to the contents of conductive layer 12_3.

[0223] The groove 91 is provided in the insulating layer 33, insulating layer 34, insulating layer 35, and insulating layer 36, and reaches the conductive layer 32. The groove 91 also extends in the Y direction.

[0224] Furthermore, in a plan view, the conductive layer 37a and the conductive layer 37b are positioned opposite each other with the groove 91 in between. Also, in a plan view, the lower end of the side surface of the conductive layer 37a on the groove 91 side has a region that overlaps with the upper end of one of the opposing sides of the insulating layer 36 of the groove 91, and the lower end of the side surface of the conductive layer 37b on the groove 91 side has a region that overlaps with the upper end of the other opposing side of the insulating layer 36 of the groove 91.

[0225] The sides of the grooves 91 provided in insulating layers 33, 34, 35, and 36 are preferably approximately perpendicular to the reference surface (e.g., the substrate surface). On the other hand, the widths W of the grooves 91 in insulating layers 33, 34, 35, and 36 may be different. For example, the width W of the grooves 91 in insulating layer 36 may be greater than the width W of the grooves 91 in insulating layer 33. Also, at least a portion of the sides of the insulating layers in the grooves 91 may be tapered.

[0226] The semiconductor layer 38 is provided on the conductive layer 37 and has a region in contact with conductive layer 37a, a region in contact with conductive layer 37b, and a region in contact with conductive layer 32. More specifically, the semiconductor layer 38 has a region in contact with the upper surface of conductive layer 37a outside the groove 91. The semiconductor layer 38 also has a region in contact with the upper surface of conductive layer 37b outside the groove 91. The semiconductor layer 38 also has a region in contact with the upper surface of conductive layer 32 in the groove 91. The semiconductor layer 38 has a region in contact with the side surface of conductive layer 37a and a region in contact with the side surface of conductive layer 37b. The semiconductor layer 38 also has a region in contact with the side surface of insulating layer 36, an insulating layer 35, an insulating layer 34, and an insulating layer 33 in the groove 91.

[0227] The metal oxides that can be used in the semiconductor layer 38 are those shown in Embodiment 1 and Embodiment 2.

[0228] The composition and materials of the semiconductor layer 38 can be found by referring to the description of the semiconductor layer 18.

[0229] The insulating layer 39 is provided so as to cover the semiconductor layer 38. The insulating layer 39 has a region in contact with the semiconductor layer, a region in contact with the side surface of the insulating layer 36, a region in contact with the side surface of the insulating layer 35, a region in contact with the side surface of the insulating layer 34, and a region in contact with the side surface of the insulating layer 33 in the groove 91.

[0230] Figures 6B and 7A show an example where the insulating layer 39 is a single layer, but it can also be formed by laminating two or more layers.

[0231] The insulating layer 39 can refer to the contents described in the insulating layer 19.

[0232] As shown in Figure 7B, the insulating layer 39 has a first region and a second region. In the first region, one of a pair of opposing surfaces of the insulating layer 39 is in contact with the insulating layer 35, and the other is in contact with the conductive layer 40. In the second region, one of a pair of opposing surfaces of the insulating layer 39 is in contact with the semiconductor layer 38, and the other is in contact with the conductive layer 40. If the insulating layer 35 has an oxygen-releasing function, oxygen can be supplied from the insulating layer 35 to the semiconductor layer 38. On the other hand, oxygen contained in the insulating layer 35 may be absorbed by the conductive layer 40 through the first region of the insulating layer 39. This can cause oxidation of the conductive layer 40, which can increase the wiring resistance of the conductive layer 40. Also, oxygen in the insulating layer 35 that is originally supplied to the semiconductor layer 38 may be supplied to the conductive layer 40. For this reason, it is preferable to use an insulating layer having oxygen barrier properties in at least a part or all of the insulating layer 39. More preferably, a barrier insulating layer is used in the insulating layer 39 that is in contact with the semiconductor layer 38. For example, aluminum oxide is preferably used as the insulating layer having barrier properties against oxygen. The thickness of the insulating layer having barrier properties against oxygen is, for example, 1 nm to 30 nm, preferably 2 nm to 10 nm, and more preferably 3 nm to 5 nm. This suppresses the absorption of oxygen contained in the insulating layer 35 by the conductive layer 40, and allows for a more efficient supply of oxygen from the insulating layer 35 to the semiconductor layer 38. In particular, since the region of the semiconductor layer 38 in contact with the insulating layer 35 functions as a channel-forming region, this configuration allows for an efficient supply of oxygen to the channel-forming region.

[0233] As a specific example of a laminated structure for the insulating layer 39, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are laminated in that order from the semiconductor layer 38 side, with thicknesses of 3 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 38 side. Another specific example is a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are laminated in that order from the semiconductor layer 38 side, with thicknesses of 3 nm, 2 nm, and 2 nm from the semiconductor layer 38 side, or 2 nm, 2 nm, and 2 nm from the semiconductor layer 38 side. It is preferable that the aluminum oxide film, silicon oxide film, hafnium oxide film, and silicon nitride film used in the insulating layer 39 are formed by the ALD method.

[0234] As shown in Figure 6B, the surface to which the insulating layer 39 is formed is composed of multiple materials, and there are regions in which at least the conductive layer 37_2, conductive layer 37_1, insulating layer 36, insulating layer 35, insulating layer 34, insulating layer 33, and conductive layer 32 exist. In the case of the ALD method, the thickness of the film formed on the surface to be formed may vary depending on the difference in the material of the surface to be formed, so it is preferable that the material of the surface to be formed is one. When forming the insulating layer 39 by the ALD method, forming aluminum oxide as the first layer makes it possible to make the thickness of silicon oxide and other materials formed from the second layer onwards uniform. Among the materials that can be used for the insulating layer 39, silicon oxide has a high dielectric strength and suppresses leakage current, so it is preferable to form a more uniform thickness.

[0235] The conductive layer 40 (conductive layer 40_1, conductive layer 40_2 on conductive layer 40_1) is provided on the insulating layer 39. The conductive layer 40 has a region between it and the semiconductor layer 38, with the insulating layer 39 sandwiched in between. The conductive layer 40 extends along the groove 91. Although an example is shown where the conductive layer 40 consists of two layers, conductive layer 40_1 and conductive layer 40_2, it can also be formed as a single layer or as a laminate of three or more layers.

[0236] The conductive layer 40 has a region in the groove 91 where an insulating layer 39 is sandwiched between it and the semiconductor layer 38. The conductive layer 40 can refer to the contents of the conductive layer 20. For example, conductive layer 40_1 can refer to the contents of conductive layer 20_1, and conductive layer 40_2 can refer to the contents of conductive layer 20_2.

[0237] The insulating layer 41 is provided on the conductive layer 40 and is provided so as to cover the conductive layer 40.

[0238] The insulating layer 41 can refer to the contents described in the insulating layer 21.

[0239] The insulating layer 42 is provided on the insulating layer 41. Preferably, the upper surface of the insulating layer 42 is flat.

[0240] The insulating layer 42 can refer to the contents described in the insulating layer 22.

[0241] The conductive layer 44 is provided on the insulating layer 42 and extends in the X direction. When the transistor 30 is used as a memory cell, part or all of the conductive layer 44 functions as a bit line.

[0242] For example, titanium, titanium nitride, aluminum, tungsten, etc., can be used as the conductive layer 44. When the conductive layer 44 has a laminated structure, these films can be laminated, and for example, a five-layer structure of titanium, titanium nitride, aluminum, titanium nitride, and titanium can be used from the bottom layer to the top layer. By using a low-resistance material such as aluminum, the wiring resistance of the conductive layer 44 can be reduced. In addition, by using titanium nitride, oxidation of low-resistance conductive materials such as aluminum can be suppressed.

[0243] The conductive layer 43 is provided embedded in the insulating layer 42, insulating layer 41, insulating layer 39, and semiconductor layer 38, and is provided to connect the conductive layer 37 and the conductive layer 44. Alternatively, for example, if a conductive oxide is used for the conductive layer 37_2 and a material with lower resistance is used for the conductive layer 37_1, an opening may be provided in the conductive layer 37_2 so that the conductive layer 43 is in contact with the conductive layer 37_1. With such a configuration, the conductive layer 43 can form good contact with the conductive layer 37_1. Alternatively, for example, the semiconductor layer 38 may be configured to connect the semiconductor layer 38 and the conductive layer 44 without providing an opening in the semiconductor layer 38.

[0244] The transistor 30 can be called a VFET, vertical transistor, vertical channel transistor, or vertical channel type transistor, similar to the transistor 10 shown in [Semiconductor Device Configuration Example 1]. In one aspect of the present invention, the transistor 30 can have the source electrode, semiconductor layer, and drain electrode stacked on top of each other, so the occupied area can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a planar manner. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device in one aspect of the present invention is used as a memory device, the storage capacity per unit area can be increased.

[0245] The region of the conductive layer 32 that overlaps with the groove 91 has a recess, which increases the contact area between the conductive layer 32 and the semiconductor layer 38 compared to the case where there is no recess. Therefore, the contact resistance between the conductive layer 32 and the semiconductor layer 38 can be reduced.

[0246] It is preferable that the depth of the recess in the conductive layer 32 be the same as or greater than the total film thickness of the semiconductor layer 38 and the insulating layer 39. It is also preferable that the height of the bottom surface of the conductive layer 40 within the groove 91 be the same as or lower than the height of the upper surface of the conductive layer 32 other than the recess. With this configuration, compared to the case without a recess, the controllability of the electron density of the semiconductor layer 38 near one of the source electrode and drain electrode (in this case, the conductive layer 32) can be improved by the gate electric field from the gate electrode (conductive layer 40).

[0247] The recess in the conductive layer 32 may have a curved portion, as shown in Figure 6B. Because the recess has a curved portion, the regions of the semiconductor layer 38, insulating layer 39, and conductive layer 40 provided on the recess near the recess may also have a curved portion. In other words, these regions may have a curved or concave surface in cross-sectional view. Furthermore, these regions may not have corners (right angles or acute angles) in cross-sectional view. This reduces electric field concentration on the insulating layer 39 near the recess, improves the dielectric breakdown voltage of the transistor 30, and suppresses electrostatic discharge breakdown of the transistor 30. Therefore, the reliability of the semiconductor device can be improved.

[0248] Furthermore, as shown in Figure 6B, the semiconductor layer 38 is in contact with the conductive layer 37 and the conductive layer 32, and is provided along the sides of the insulating layer 36, insulating layer 35, insulating layer 34, and insulating layer 33 in the groove 91. Therefore, since the channel length of the transistor 30 can be determined by the total film thickness of the insulating layers 33, 34, 35, and 36 on the conductive layer 32, the channel length of the transistor 30 does not affect the area occupied by the transistor 30, for example, the area of ​​the transistor 30 in a plan view. In addition, the channel length of the transistor 30 can be controlled regardless of the performance of the exposure machine. For this reason, it is possible to set the channel length to an extremely fine length below the exposure limit of photolithography.

[0249] Furthermore, by reducing the total thickness of insulating layers 33, 34, 35, and 36, transistors with extremely short channel lengths can also be fabricated. Transistors with channel lengths of, for example, 5 nm to 500 nm, preferably 7 nm to 300 nm, preferably 10 nm to 200 nm, preferably 10 nm to 200 nm, preferably 10 nm to 100 nm, preferably 10 nm to 50 nm, and preferably 10 nm to 30 nm can be fabricated. Therefore, transistors with channel lengths of less than 10 nm can be realized without using the extremely expensive exposure equipment used in state-of-the-art LSI technology.

[0250] [Example of Semiconductor Device Configuration 3] Figures 8A to 8C show an example of a semiconductor device including a transistor 50. Figure 8A is a plan view of the semiconductor device having the transistor 50. Figure 8B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 8A. Figure 8C is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 8A.

[0251] The transistor 50 has at least a conductive layer 55, a conductive layer 60, a conductive layer 65, a semiconductor layer 59, an insulating layer 56, an insulating layer 57, an insulating layer 58, and an insulating layer 64. Part or all of the conductive layer 65 functions as a first gate electrode. Part or all of the conductive layer 55 functions as a second gate electrode. Part or all of the conductive layer 60a functions as either a source electrode or a drain electrode. Part or all of the conductive layer 60b functions as either a source electrode or a drain electrode. Part or all of the insulating layer 64 functions as a first gate insulating film. In addition, part or all of the insulating layers 56, 57, and 58 function as a second gate insulating film.

[0252] The semiconductor device including the transistor 50 shown in Figures 8A to 8C has an insulating layer 51 on a substrate (not shown). The insulating layer 52 is located on the insulating layer 51. The insulating layer 53 is located on the insulating layer 52. The insulating layer 54 is located on the insulating layer 53.

[0253] For insulating layers 51, 52, 53, and 54, inorganic insulating films such as silicon oxide, silicon nitride, silicon oxide nitride, aluminum oxide, and hafnium oxide can be used. For insulating layer 51, for example, silicon oxide is preferable. For insulating layer 52, for example, silicon nitride is preferable. For insulating layer 53, for example, aluminum oxide is preferable. For insulating layer 54, for example, silicon oxide is preferable. By using insulating films such as aluminum oxide, silicon nitride, and hafnium oxide in one or both of insulating layer 52 or insulating layer 53, the diffusion of impurities from the structure below insulating layer 53 can be suppressed.

[0254] The conductive layer 55 (conductive layer 55_1, conductive layer 55_2 on conductive layer 55_1) is positioned so as to be embedded in the insulating layer 54. Preferably, the upper surface of the conductive layer 55 and the upper surface of the insulating layer 54 are at the same height.

[0255] It is preferable to use titanium nitride as the conductive layer 55_1. It is preferable to use tungsten as the conductive layer 55_2.

[0256] The conductive layer 55 can refer to the contents of the conductive layer 20. For example, conductive layer 55_1 can refer to the contents of conductive layer 12_1, and conductive layer 55_2 can refer to the contents of conductive layer 12_2.

[0257] The insulating layer 56 is located on the insulating layer 54 and the conductive layer 55, and has a region in contact with the upper surface of the insulating layer 54 and a region in contact with the conductive layer 55. The insulating layer 57 is located on the insulating layer 56. The insulating layer 58 is located on the insulating layer 57.

[0258] In a plan view, the insulating layer 58 has a shape in which its edges coincide with those of the semiconductor layer 59.

[0259] For insulating layers 56, 57, and 58, inorganic insulating films such as silicon nitride, silicon oxide nitride, aluminum oxide, hafnium oxide, and silicon oxide can be used in appropriate combinations, either as single layers or in laminated layers. Alternatively, an insulating film (also called ZAZ) consisting of zirconium oxide, aluminum oxide, and zirconium oxide laminated in that order can be used for any of insulating layers 56, 57, and 58. Furthermore, a material capable of ferroelectricity can be used for any of insulating layers 56, 57, and 58.

[0260] The insulating layer 56 or insulating layer 57, or both, can be made of an insulating layer material having the function of suppressing the permeation of impurities and oxygen, an insulating layer material having the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, an insulating layer material having the function of capturing or fixing hydrogen, an insulating layer material having barrier properties against hydrogen, or an insulating layer material having barrier properties against oxygen. For the insulating layer 58, it is preferable to use an insulating material with high dielectric strength or that suppresses leakage current. For the insulating layer 56, for example, silicon nitride is preferable. For the insulating layer 57, for example, hafnium oxide is preferable. For the insulating layer 58, for example, silicon oxide is preferable. When insulating layers 56 and 57 are formed using such materials, insulating layers 56 and 57 function as layers that suppress the release of oxygen from one or both of the semiconductor layer 59 or insulating layer 63 to the substrate side, or the diffusion of impurities such as hydrogen from the layer below insulating layers 56 and 57 to the semiconductor layer 59. By providing insulating layers 56 and 57, the formation of oxygen vacancies in the semiconductor layer 59 can be suppressed.

[0261] The semiconductor layer 59 is located on the insulating layer 58. The semiconductor layer 59 also has a region that overlaps with the conductive layer 55 via the insulating layers 56, 57, and 58. In Figures 8B and 8C, an example of a two-layer structure of semiconductor layer 59_1 and semiconductor layer 59_2 on semiconductor layer 59_1 is shown, but the semiconductor layer 59 may be a single layer or a stacked structure of three or more layers.

[0262] The metal oxide that can be used in the semiconductor layer 59 is indium oxide as shown in Embodiments 1 and 2.

[0263] The composition and materials of the semiconductor layer 59 can be found by referring to the description of the semiconductor layer 18.

[0264] For example, IGZO can be used for semiconductor layer 59_1, and indium oxide as shown in Embodiments 1 and 2 can be used for semiconductor layer 59_2.

[0265] The conductive layer 60a (conductive layer 60a_1, conductive layer 60a_2 on conductive layer 60a_1) and the conductive layer 60b (conductive layer 60b_1, conductive layer 60b_2 on conductive layer 60b_1) are located on the semiconductor layer 59, spaced apart from each other. Although the example shown illustrates the conductive layer 60 as two layers, conductive layer 60_1 and conductive layer 60_2, it can also be formed as a single layer or as a stack of three or more layers.

[0266] The conductive layer 60 can refer to the contents of the conductive layer 12. For example, conductive layer 60_1 can refer to the contents of conductive layer 12_3, and conductive layer 60_2 can refer to the contents of conductive layer 12_2.

[0267] The insulating layer 61 is located on the conductive layer 60. Although the insulating layer 61 is shown as a single layer, it may also be a laminated structure of two or more layers. The insulating layer 61 can be used as part or all of the mask for dry etching when forming the conductive layer 60, the semiconductor layer 59, and the insulating layer 58. By providing the insulating layer 61, it is possible to suppress the occurrence of pattern formation abnormalities such as pattern reduction when forming the conductive layer 60, the semiconductor layer 59, and the insulating layer 58.

[0268] The insulating layer 61 can be, for example, a two-layer structure consisting of silicon nitride and silicon oxide on the silicon nitride.

[0269] The insulating layer 62 is positioned to cover the conductive layer 60 and the semiconductor layer 59. The insulating layer 62 also has a region that is in contact with the insulating layer 57.

[0270] As the insulating layer 62, for example, an insulating layer material having the function of suppressing the permeation of impurities and oxygen, an insulating layer material having the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating layer material having the function of capturing or fixing hydrogen, an insulating layer material having barrier properties against hydrogen, or an insulating layer material having barrier properties against oxygen can be used. For example, silicon nitride is preferably used for the insulating layer 62. The insulating layer 62 functions as a layer that suppresses the diffusion of impurities such as hydrogen from the layer above it to the semiconductor layer 59. Furthermore, the insulating layer 62 is in contact with the insulating layer 57 located below the semiconductor layer 59 and surrounds the semiconductor layer 59, thereby suppressing the diffusion of impurities such as hydrogen from the outside to the semiconductor layer. It can also suppress the formation of oxygen vacancies in the semiconductor layer 59.

[0271] The insulating layer 63 is provided so as to cover the insulating layer 62. Furthermore, the upper surface of the insulating layer 63 is preferably flat. As the insulating layer 63, a material that easily forms regions containing excess oxygen can be used. Furthermore, for example, silicon oxide is preferably used for the insulating layer 63.

[0272] Furthermore, it is preferable to perform a heat treatment after the formation of the insulating layer 63 to reduce the amount of hydrogen in the insulating layer 63. The heat treatment can be described in relation to the heat treatment applicable to the insulating layer 15.

[0273] It is preferable to use an insulating layer 63 that is prone to forming regions containing excess oxygen. It is also preferable that it has a function to release oxygen. Furthermore, it is possible to perform a process to supply oxygen to the insulating layer 63. Oxygen can be supplied from the insulating layer 63 to the semiconductor layer 59 by heat applied during the manufacturing process of the semiconductor device. For means of supplying oxygen to the insulating layer 63, refer to the description of means of supplying oxygen to the insulating layer 15.

[0274] The conductive layer 65, which functions as the first gate electrode, and the insulating layer 64, which functions as the first gate insulating layer, are positioned to be embedded in the grooves of the insulating layer 63 and insulating layer 62, as shown in Figures 8B and 8C. The insulating layer 64 also has regions in contact with the side surface of the insulating layer 63, the side surface of the insulating layer 62, the side surface of the insulating layer 61, and the side surface of the conductive layer 60 in the grooves. The insulating layer 64 also has regions in contact with the top surface and side surface of the semiconductor layer 59. It is preferable that the top surface of the conductive layer 65 and the top surface of the insulating layer 63 are at the same height. For the conductive layer 65, it is preferable to use titanium nitride for conductive layer 65_1, and tungsten for conductive layer 65_2. The insulating layer 64 can be used as a single layer or in a laminated form by appropriately combining, for example, aluminum oxide, silicon oxide, hafnium oxide, and silicon nitride.

[0275] The conductive layer 65 can refer to the contents of the conductive layer 20. For example, conductive layer 65_1 can refer to the contents of conductive layer 20_1, and conductive layer 65_2 can refer to the contents of conductive layer 20_2.

[0276] The insulating layer 66 is located on the conductive layer 65 and the insulating layer 63. The insulating layer 67 is located on the insulating layer 66.

[0277] The insulating layer 66 or insulating layer 67, or both, can be made of an insulating layer material having the function of suppressing the permeation of impurities and oxygen, an insulating layer material having the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating layer material having the function of capturing or fixing hydrogen, an insulating layer material having barrier properties against hydrogen, or an insulating layer material having barrier properties against oxygen. For the insulating layer 66, it is preferable to use aluminum oxide produced by the sputtering method, for example. For the insulating layer 67, it is preferable to use silicon nitride, for example. The insulating layer 66 or insulating layer 67, or both, function as layers that suppress the release of oxygen to the layers above the insulating layers 66 and 67, or the diffusion of impurities such as hydrogen from the layers above the insulating layers 66 and 67 to the semiconductor layer 59.

[0278] Alternatively, the insulating layer 66 may be formed by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using a sputtering method, thereby supplying oxygen to the insulating layer 63. It is preferable to subsequently remove the deposited oxide film. For example, an oxide film such as aluminum oxide or an oxide semiconductor may be deposited by sputtering and then removed by a CMP method. If the thickness of the insulating layer 63 decreases when removing the oxide film by the CMP method, the insulating layer may be deposited again. The oxygen-containing atmosphere may be oxygen gas (O₂O₃). ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing oxygen-containing compounds such as O). The substrate temperature during plasma treatment shall be between room temperature (25°C) and 450°C. Furthermore, the oxygen supply process described above may be performed multiple times as the same process, or multiple times in combination of different processes.

[0279] The insulating layer 68 is located on the insulating layer 67. It is preferable to use an insulating material with high dielectric strength or that suppresses leakage current for the insulating layer 68; for example, silicon oxide is preferred. Furthermore, the insulating layer 68 functions as an etching stop film when forming the conductive layer 71.

[0280] The insulating layer 69 and the conductive layer 70 are positioned to be embedded in the openings of the insulating layers 61, 62, 63, 66, 67, and 68. The insulating layer 69 has regions in contact with the side surfaces of the insulating layer 61, 62, 63, 66, 67, and 68 within these openings. The conductive layer 70 is in contact with the upper surface of the conductive layer 60.

[0281] The insulating layer 69 can be made of an insulating layer material having the function of suppressing the permeation of impurities and oxygen, an insulating layer material having the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, an insulating layer material having the function of capturing or fixing hydrogen, an insulating layer material having barrier properties against hydrogen, or an insulating layer material having barrier properties against oxygen. For example, silicon nitride is preferably used for the insulating layer 69. Furthermore, for example, titanium nitride is preferably used for conductive layer 70_1, and tungsten is preferably used for conductive layer 70_2. By providing the insulating layer 69, it is possible to suppress the absorption of oxygen contained in the insulating layer 63 into the conductive layer 70. Also, for example, it is possible to suppress the diffusion of hydrogen from the conductive layer 70 to the insulating layer 63 and the semiconductor layer 59.

[0282] The conductive layer 71 is located on the insulating layer 68. The conductive layer 71 can be made of, for example, tungsten.

[0283] [Materials for the semiconductor device] The following describes the materials that can be used in the semiconductor device of this embodiment. Note that each layer constituting the semiconductor device of this embodiment may be a single-layer structure or a multilayer structure.

[0284] [Substrate] For the substrate used to form the transistor, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can also be used. Furthermore, there are substrates in which a conductive layer or semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or insulating layer is provided on a conductive substrate. Alternatively, substrates on which elements are provided may be used. Elements provided on the substrate include capacitive elements, resistive elements, switching elements (including transistors), light-emitting elements, and memory elements.

[0285] [Conductive Layers] It is preferable to use a highly conductive material for the conductive layers such as conductive layer 12, conductive layer 17, conductive layer 20, conductive layer 32, conductive layer 37, conductive layer 40, conductive layer 43, conductive layer 44, conductive layer 55, conductive layer 60, conductive layer 65, conductive layer 70, and conductive layer 71. It is preferable to use a conductive material for conductive layers such as conductive layer 12, conductive layer 17, conductive layer 20, conductive layer 32, conductive layer 37, conductive layer 40, conductive layer 43, conductive layer 44, conductive layer 55, conductive layer 60, conductive layer 65, conductive layer 70, and conductive layer 71, which is a metallic element selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing such a metallic element, as the conductive material. Alternatively, nitrides of the above metallic elements or alloys containing such metallic elements, or oxides of the above metallic elements or alloys containing such metallic elements may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. These are preferred because they are conductive materials that are resistant to oxidation, or materials that maintain conductivity even after oxidation. In addition, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used. Furthermore, tantalum, tantalum nitride, etc., are preferable to use as conductive layers because they have barrier properties against hydrogen.

[0286] Furthermore, the conductive layer may be a single-layer structure or a multi-layer structure of the conductive material described above. For example, a laminated structure combining the aforementioned metal element material with a conductive oxide may be used. For example, a single-layer structure of the conductive oxide film, a two-layer structure in which a ruthenium film or ruthenium oxide film is laminated on a tungsten film, a two-layer structure in which the conductive oxide film is laminated on a ruthenium film or ruthenium oxide film, a two-layer structure in which a conductive oxide film is laminated on a tungsten film, and so on can be used. Alternatively, a three-layer structure in which tungsten is laminated on titanium nitride and a conductive oxide is laminated on the tungsten can be used. Or, a four-layer structure can be used in which tantalum nitride is laminated from the bottom, titanium nitride is laminated on the tantalum nitride, tungsten is laminated on the titanium nitride, and a conductive oxide is laminated on the tungsten in that order.

[0287] [Insulating Layers] It is preferable to use inorganic insulating films for the insulating layers of semiconductor devices (insulating layers 11, 13, 14, 15, 16, 19, 21, 22, 31, 33, 34, 35, 36, 39, 41, 42, 51, 52, 53, 54, 56, 57, 58, 61, 62, 63, 64, 66, 67, 68, and 69, etc.). As transistors become smaller and more integrated, thinning of the gate insulating layer can lead to problems such as leakage current. By using a material with a high dielectric constant (high-k) for the gate insulating layer, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. Furthermore, it becomes possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, by using a material with a low dielectric constant for the insulating layer that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is preferable to select the material according to the function of the insulating layer. It should be noted that materials with a low dielectric constant are also materials with high dielectric strength.

[0288] Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxidative nitride insulating films, and nitride oxide insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, zinc gallium oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxidative nitride insulating films include silicon oxide nitride films, aluminum oxide nitride films, gallium oxide nitride films, yttrium oxide nitride films, and hafnium oxide nitride films. Examples of nitride oxide insulating films include silicon oxide nitride films and aluminum oxide nitride films. In addition, organic insulating films may be used for the insulating layer of semiconductor devices.

[0289] Examples of materials with a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium-zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium. In addition, an insulating film (also called ZAZ) laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. Alternatively, for example, an insulating film (also called ZAZA) laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used.

[0290] Examples of insulating materials with a lower dielectric constant compared to high-k materials include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0291] Examples of insulating materials with high dielectric strength include silicon oxide, silicon oxide nitride, silicon nitride oxide, and silicon nitride.

[0292] Furthermore, examples of insulating materials that suppress leakage current include silicon oxide and silicon oxide nitride.

[0293] Furthermore, the electrical properties of a transistor using a metal oxide can be stabilized by surrounding it with an insulating layer that has the function of suppressing the permeation of impurities, hydrogen, and oxygen. As an insulating layer that has the function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a multilayer structure.

[0294] Specifically, as materials for the insulating layer that have the function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, nitrides such as aluminum nitride or silicon nitride, and nitride oxides such as silicon nitride can be used.

[0295] Specifically, examples of insulating layer materials that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also, examples of nitrides include aluminum nitride and silicon nitride. Furthermore, examples of nitride oxides include silicon nitride.

[0296] Furthermore, insulating layers that are in contact with the oxide semiconductor layer, such as gate insulating layers, or insulating layers provided near the oxide semiconductor layer, are preferably insulating layers that have regions containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen). For example, an insulating layer having regions containing excess oxygen can reduce oxygen vacancies in the oxide semiconductor layer by releasing oxygen and being in contact with or near the oxide semiconductor layer. Examples of insulating layer materials that easily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide with vacancies.

[0297] It is preferable to use a hydrogen barrier insulating layer for the insulating layer in contact with the oxide semiconductor layer, or an insulating layer provided near the oxide semiconductor layer. The hydrogen barrier properties of this insulating layer suppress the diffusion of hydrogen into the oxide semiconductor layer.

[0298] Examples of insulating layer materials having the function of capturing or fixing hydrogen include metal oxides such as hafnium-containing oxides, magnesium-containing oxides, aluminum-containing oxides, aluminum and hafnium-containing oxides (hafnium aluminate), and hafnium and silicon-containing oxides (hafnium silicate). Furthermore, these metal oxides may also contain zirconium, for example, an oxide containing hafnium and zirconium.

[0299] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, thus having a high ability to capture or fix hydrogen. Therefore, by having an amorphous structure in the insulating layer, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the above metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0300] By making the insulating layer amorphous, the formation of grain boundaries can be suppressed. Suppressing the formation of grain boundaries improves the flatness of the insulating layer. This makes the thickness distribution of the insulating layer more uniform, reducing areas with extremely thin thickness, and thus improving the dielectric strength of the insulating layer. Furthermore, the thickness distribution of the film provided on the insulating layer can be made more uniform. In addition, by suppressing the formation of grain boundaries in the insulating layer, leakage current caused by defect levels at the grain boundaries can be reduced. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0301] Furthermore, the above insulating layer may have, in part, a crystalline region and / or a grain boundary.

[0302] Furthermore, the function of capturing or fixing the corresponding substance can also be described as having the property of making the corresponding substance difficult to diffuse. Therefore, the function of capturing or fixing the corresponding substance can be rephrased as barrier property. In this specification, a barrier insulating layer refers to an insulating layer that has barrier properties. Barrier property is defined as the property of making the corresponding substance difficult to diffuse (also called the property of making the corresponding substance difficult to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). When hydrogen is described as the corresponding substance, for example, it refers to hydrogen atoms, hydrogen molecules, and water molecules and OH − This refers to at least one substance that is bonded with hydrogen, such as [substance name]. Furthermore, when an impurity is described as a corresponding substance, unless otherwise specified, it refers to an impurity in the channel-forming region or semiconductor layer, such as a hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule (N ２ O, NO, and NO ２ This refers to at least one of the following: (etc.), and copper atoms, etc. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of the following: for example, an oxygen atom and an oxygen molecule, etc.

[0303] Examples of insulating layer materials that have barrier properties against hydrogen include silicon nitride, hafnium oxide, aluminum oxide, magnesium oxide, gallium oxide, or silicon nitride oxide.

[0304] Examples of insulating layer materials that have barrier properties against oxygen include oxides containing one or both aluminum and hafnium, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0305] Furthermore, a ferroelectric material may be used for the insulating layer of the semiconductor device. Examples of ferroelectric materials include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Another example of a ferroelectric material is a material obtained by adding element J1 (where element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to it. Another example of a ferroelectric material is a material obtained by adding element J2 (where element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium, etc.) to zirconium oxide. Furthermore, the ratio of the number of zirconium atoms to the number of element J2 atoms can be set as appropriate; for example, the ratio of zirconium atoms to element J2 atoms can be set to 1:1 or close to it. Also, as a material that can have ferroelectric properties, lead titanate (PbTiO) Ｘ ), or piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used.

[0306] Furthermore, metal nitrides containing element Q1, element Q2, and nitrogen are examples of materials that may possess ferroelectric properties. Here, element Q1 is one or more selected from aluminum, gallium, and indium, etc. Element Q2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium, etc. The ratio of the number of atoms of element Q1 to the number of atoms of element Q2 can be set as appropriate. In addition, metal oxides containing element Q1 and nitrogen may possess ferroelectric properties even without containing element Q2. Furthermore, materials in which element Q3 is added to the above metal nitride are examples of materials that may possess ferroelectric properties. Element Q3 is one or more selected from magnesium, calcium, strontium, zinc, and cadmium, etc. Here, the ratio of the number of atoms of element Q1, the number of atoms of element Q2, and the number of atoms of element Q3 can be set as appropriate.

[0307] Furthermore, SrTaO is an example of a material that may possess ferroelectric properties. ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, and GaFeO with a κ-alumina structure. ３ These are some examples.

[0308] While the above explanation uses metal oxides and metal nitrides as examples, it is not limited to these. For example, metal oxynitrides obtained by adding nitrogen to the aforementioned metal oxides, or metal nitrogen oxides obtained by adding oxygen to the aforementioned metal nitrides, may be used.

[0309] Furthermore, as materials that may possess ferroelectricity, for example, a mixture or compound consisting of multiple materials selected from the materials listed above can be used. Incidentally, since the crystal structure (properties) of the materials listed above may change not only depending on the film deposition conditions but also on various processes, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0310] The insulating layer of a capacitive element having a pair of opposing conductive layers and an insulating layer located between them can be a single-layer structure made of a material selected from the materials listed above, or a laminated structure made of multiple materials selected from the materials listed above.

[0311] Furthermore, at least a portion of the gate insulating layer of the transistor may be a single-layer structure made of a material selected from the materials listed above, or a multilayer structure made of multiple materials selected from the materials listed above. A transistor having such gate insulating can be made to function as an FeFET (Ferroelectric Field Effect Transistor).

[0312] It is preferable to use insulating materials for insulating layers such as insulating layer 11, insulating layer 13, insulating layer 14, insulating layer 16, insulating layer 21, insulating layer 31, insulating layer 33, insulating layer 34, insulating layer 36, insulating layer 41, insulating layer 52, insulating layer 53, insulating layer 56, insulating layer 57, insulating layer 61, insulating layer 62, insulating layer 66, insulating layer 67, and insulating layer 69 that have insulating layer materials having the function of suppressing the permeation of impurities and oxygen, insulating layer materials having the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, insulating layer materials having the function of capturing or fixing hydrogen, insulating layer materials having barrier properties against hydrogen, and insulating layer materials having barrier properties against oxygen. By using these insulating layers, the diffusion of hydrogen into the semiconductor layer can be suppressed. In addition, oxidation of conductive layers such as conductive layer 12, conductive layer 17, conductive layer 20, conductive layer 32, conductive layer 37, conductive layer 40, conductive layer 55, conductive layer 60, conductive layer 65, and conductive layer 70 can be suppressed.

[0313] For example, insulating layers such as insulating layer 11, insulating layer 13, insulating layer 14, insulating layer 16, insulating layer 21, insulating layer 31, insulating layer 33, insulating layer 34, insulating layer 36, insulating layer 41, insulating layer 52, insulating layer 53, insulating layer 56, insulating layer 57, insulating layer 61, insulating layer 62, insulating layer 66, insulating layer 67, and insulating layer 69 may be configured to use one or both of silicon nitride and silicon oxide nitride. This can suppress the diffusion of hydrogen into the transistor and semiconductor layers, and a transistor with high reliability can be obtained.

[0314] The insulating material used in insulating layers such as insulating layer 15, insulating layer 22, insulating layer 35, insulating layer 42, insulating layer 54, and insulating layer 63 preferably has a low relative permittivity because it functions as an interlayer insulating layer. Furthermore, it is preferable that the insulating material has a high dielectric strength or suppresses leakage current. By using an insulating material with a lower relative permittivity compared to a high-k material as the interlayer insulating film, parasitic capacitance between wirings can be reduced. By using an insulating material with a high dielectric strength or suppresses leakage current as the interlayer insulating film, leakage current between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as insulating layer 15, insulating layer 22, insulating layer 35, insulating layer 42, insulating layer 54, and insulating layer 63.

[0315] Furthermore, it is preferable that the insulating layers, such as insulating layer 15, insulating layer 22, insulating layer 35, insulating layer 42, insulating layer 54, and insulating layer 63, have reduced concentrations of impurities such as hydrogen or water. For example, the hydrogen concentration in the insulating layer can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the film-forming gas. This suppresses the incorporation of impurities such as hydrogen or water into the channel formation region of the semiconductor layer. In addition, it is preferable that insulating layers 15, insulating layer 35, and insulating layer 63 use insulating layers that have regions containing excess oxygen, and that they have a function to release oxygen. For example, an insulating layer having regions containing excess oxygen can be formed by film-forming using a sputtering method in an oxygen-containing atmosphere. In this way, by forming at least a portion of the layers constituting insulating layer 15, insulating layer 35, and insulating layer 63 using a sputtering method, oxygen is supplied from insulating layer 15, insulating layer 35, and insulating layer 63 to the channel formation region of the semiconductor layer, thereby suppressing oxygen deficiencies and V Ｏ This can help reduce H.

[0316] [Gate Insulation Layer] Insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 function as gate insulation layers of the transistor. Oxide insulating film, nitride insulating film, oxidized nitride insulating film, and nitrided oxide insulating film can be used for insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64. In addition, insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 may have a laminated structure, for example, a laminated structure having one or more oxide insulating films and one or more nitride insulating films.

[0317] Furthermore, insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 can be made by laminating insulating materials made of high-k material. In addition, insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 can be made by laminating one or both of insulating materials with high dielectric strength or insulating materials that suppress leakage current. Furthermore, materials that may have ferroelectric properties can be used as insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64. In addition, insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 can be made by laminating these materials.

[0318] It is preferable to use one or more insulating layer materials for insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, insulating layer materials that have the function of capturing or fixing hydrogen, or insulating layer materials that have barrier properties against hydrogen. This can suppress the diffusion of hydrogen contained in conductive layer 20, conductive layer 40, and conductive layer 65 into the semiconductor layer. For example, silicon nitride films can be used for insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64.

[0319] Furthermore, since insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 are in contact with the semiconductor layer, it is preferable to use insulating layers that have the function of capturing or fixing hydrogen. This makes it possible to capture or fix hydrogen contained in the semiconductor layer more effectively. Therefore, the hydrogen concentration in the semiconductor layer (especially the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V in the channel formation region Ｏ By reducing H, the channel formation region can be made i-type or substantially i-type.

[0320] Furthermore, it is preferable to use insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 that have regions containing excess oxygen. This allows oxygen to be supplied from the insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 to the semiconductor layer, thereby reducing oxygen deficiencies in the semiconductor layer. Silicon oxide films or silicon oxynitride films are suitable as insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 because they have a thermally stable structure.

[0321] Furthermore, it is preferable to use insulating layer materials that have barrier properties against oxygen for insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64. By having oxygen barrier properties for insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 that are in contact with the semiconductor layer, the detachment of oxygen from the semiconductor layer can be suppressed. Aluminum oxide films can be used as insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64.

[0322] The insulating layers, such as insulating layer 19, insulating layer 39, and insulating layer 64, can be a single-layer structure or a laminated structure of two or more layers. When the insulating layers, such as insulating layer 19, insulating layer 39, and insulating layer 64, are formed in a laminated structure of two or more layers, it is preferable to form them with two or more types of films. By forming the insulating layers, such as insulating layer 19, insulating layer 39, and insulating layer 64, with two or more types of films, multiple functions can be imparted to the insulating layers, such as insulating layer 19, insulating layer 39, and insulating layer 64. Examples of functions that the insulating layers, such as insulating layer 19, insulating layer 39, and insulating layer 64, may have include the function of extracting hydrogen from the semiconductor layer and the function of suppressing the diffusion of hydrogen into the semiconductor layer. Furthermore, insulating layers, such as insulating layer 19, insulating layer 39, and insulating layer 64, can have a region containing excess oxygen in a part of it. Oxygen can be supplied from the insulating layers, such as insulating layer 19, insulating layer 39, and insulating layer 64, to the semiconductor layer, thereby reducing oxygen deficiency in the semiconductor layer.

[0323] For example, insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 can have a two-layer structure having a first insulating layer and a second insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer. For example, the first insulating layer can be made of an insulating layer material that has the function of capturing or fixing hydrogen, and the second insulating layer can be made of an insulating layer material that has barrier properties against hydrogen, an insulating layer material that has the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, or an insulating layer material that has barrier properties against oxygen. By using such a configuration, the hydrogen concentration in the semiconductor layer can be reduced, and the diffusion of hydrogen into the semiconductor layer can be suppressed. This makes it possible to realize a highly reliable transistor. When insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 have a two-layer structure having a first insulating layer and a second insulating layer, for example, a hafnium oxide film or a hafnium silicate film can be used as the first insulating layer, and a silicon nitride film can be used as the second insulating layer.

[0324] Alternatively, for example, an insulating layer having a region containing excess oxygen can be used as the first insulating layer, and an insulating layer material having barrier properties against hydrogen or an insulating layer material having the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, can be used as the second insulating layer. Alternatively, for example, an insulating layer having a region containing excess oxygen can be used as the first insulating layer, and an insulating layer material having the function of capturing or fixing hydrogen can be used as the second insulating layer. By adopting such a configuration, the amount of oxygen vacancy and hydrogen concentration in the semiconductor layer can be reduced, and the diffusion of hydrogen into the semiconductor layer can be suppressed. Therefore, a highly reliable transistor can be realized. When insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 are made into a two-layer structure having a first insulating layer and a second insulating layer, for example, a silicon oxide film can be used as the first insulating layer and a silicon nitride film can be used as the second insulating layer.

[0325] For example, insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 can be configured as a three-layer structure having a first insulating layer, a second insulating layer, and a third insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer, and the first insulating layer, the second insulating layer, and the third insulating layer are located from the semiconductor layer side. For example, the first insulating layer can be made of an insulating material with high dielectric strength, an insulating material that suppresses leakage current, or an insulating layer having a region containing excess oxygen; the second insulating layer can be made of an insulating layer material that has the function of capturing or fixing hydrogen; and the third insulating layer can be made of an insulating layer material that has barrier properties against hydrogen, an insulating layer material that has the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, or an insulating layer material that has barrier properties against oxygen. With such a configuration, the amount of oxygen deficiency and hydrogen concentration in the semiconductor layer can be reduced, and the diffusion of hydrogen into the semiconductor layer can be suppressed. Furthermore, the diffusion of oxygen to the conductive layers 20, 40, and 65 can be prevented, and oxidation of the conductive layers such as conductive layers 20, 40, and 65 can be suppressed. Therefore, a highly reliable transistor can be realized. When insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 are made into a three-layer structure having a first insulating layer, a second insulating layer, and a third insulating layer, for example, a silicon oxide film can be used as the first insulating layer, a hafnium oxide film or a hafnium silicate film can be used as the second insulating layer, and a silicon nitride film can be used as the third insulating layer.

[0326] For example, insulating layers such as insulating layer 19, insulating layer 39, and insulating layer 64 can be configured as a four-layer structure having a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer, and the first insulating layer, second insulating layer, third insulating layer, and fourth insulating layer are located from the semiconductor layer side. For example, the first insulating layer can be made of an insulating layer material having barrier properties against oxygen or an insulating layer material having the function of suppressing the permeation of impurities and oxygen; the second insulating layer can be made of an insulating layer material with high dielectric strength, an insulating layer material that suppresses leakage current, or an insulating layer having a region containing excess oxygen; the third insulating layer can be made of an insulating layer material having the function of capturing or fixing hydrogen; and the fourth insulating layer can be made of an insulating layer material having barrier properties against hydrogen, an insulating layer material having the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, or an insulating layer material having barrier properties against oxygen. With such a configuration, the detachment of oxygen from the semiconductor layer can be suppressed. The amount of oxygen vacancies and hydrogen concentration in the semiconductor layer can be reduced, and the diffusion of hydrogen into the semiconductor layer can be suppressed. Furthermore, the diffusion of oxygen to the conductive layer 20, conductive layer 40, and conductive layer 65 can be prevented, and oxidation of conductive layers such as conductive layer 20, conductive layer 40, and conductive layer 65 can be suppressed. Therefore, a highly reliable transistor can be realized. When insulating layer 19, insulating layer 39, and insulating layer 64 are made into a four-layer structure having a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, for example, an aluminum oxide film can be used as the first insulating layer, a silicon oxide film as the second insulating layer, a hafnium oxide film or hafnium silicate film as the third insulating layer, and a silicon nitride film as the fourth insulating layer.

[0327] The insulating layers, such as insulating layer 19, insulating layer 39, and insulating layer 64, are preferably thin films. For example, by setting the film thickness of insulating layer 19, insulating layer 39, and insulating layer 64 to 1 nm to 50 nm, 1 nm to 20 nm, and preferably 3 nm to 10 nm, the subthreshold swing value (also called the S value), which is one of the transistor characteristics, can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0328] Furthermore, the film thickness of each layer constituting the insulating layers, such as insulating layer 19, insulating layer 39, and insulating layer 64, is preferably 0.1 nm to 40 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that each layer constituting insulating layer 19, insulating layer 39, and insulating layer 64 only needs to have a region with the above-mentioned film thickness in at least a portion of it.

[0329] As a specific example of the insulating layer 19, insulating layer 39, and insulating layer 64, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer side, with thicknesses of 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer side. Alternatively, it is preferable to have thicknesses of 1 nm, 30 nm, 1.5 nm, and 1 nm from the semiconductor layer side. Alternatively, it is preferable to have thicknesses of 1 nm, 30 nm, 1.5 nm, and 5 nm from the semiconductor layer side.

[0330] Another specific example is the use of a four-layer structure in which hafnium oxide film, silicon oxide film, hafnium oxide film, and silicon nitride film are stacked in that order from the semiconductor layer side, and it is preferable that the thicknesses of these layers be 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer side.

[0331] Another specific example is the use of a two-layer structure in which a silicon oxide film and a hafnium oxide film are stacked in that order from the semiconductor layer side, and it is preferable that the thicknesses of these layers be 1 nm and 1.5 nm from the semiconductor layer side.

[0332] Furthermore, as a specific example, it is preferable to use a three-layer structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer side, with the thicknesses of these layers being 30 nm, 1.5 nm, and 5 nm from the semiconductor layer side.

[0333] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0334] (Embodiment 4) A memory device according to one aspect of the present invention will be described with reference to Figures 9A to 10. The memory device according to one aspect of the present invention has a memory cell. The memory cell has a transistor and a capacitive element. The transistor can be the same as the transistor described in Embodiment 3. A detailed description of the transistor will be omitted as it can be referenced from the description of Embodiment 3. In Figures 9A to 10, an example is shown using the transistor 10 shown in [Semiconductor Device Configuration Example 1] of Embodiment 3, but the transistor 30 shown in [Semiconductor Device Configuration Example 2] of Embodiment 3 and the transistor 50 shown in [Semiconductor Device Configuration Example 3] of Embodiment 3 can also be used.

[0335] The configuration of a semiconductor device having a memory cell 99 will be explained using Figures 9A and 9B. Figure 9A is a plan view of a memory device having a memory cell 99. Figure 9B is a cross-sectional view between the dashed-dotted lines A1 and A2 shown in Figure 9A. Figure 9C is a horizontal cross-sectional view between the dashed-dotted lines C1 and C2 shown in Figure 9B.

[0336] The memory device shown in Figures 9A to 9C has a memory cell 99 on a substrate (not shown). The memory cell 99 has at least a capacitive element 80 and a transistor 10.

[0337] The memory device shown in Figures 9A to 9C has an insulating layer 81, an insulating layer 82, a conductive layer 83_1, and a conductive layer 83_2 on a substrate (not shown), and a capacitive element 80 on the conductive layer 83.

[0338] The capacitive element 80 has at least a conductive layer 88, an insulating layer 89, and a conductive layer 12. The insulating layer 89 is provided between the conductive layer 88 and the conductive layer 12. At least a portion of the conductive layer 88 functions as one of a pair of electrodes of the capacitive element. At least a portion of the conductive layer 12 functions as the other of a pair of electrodes of the capacitive element. At least a portion of the conductive layer 12 functions as either the source electrode or the drain electrode of the transistor 10. At least a portion of the insulating layer 89 functions as the dielectric of the capacitive element.

[0339] Insulating layers 84, 85, and 86 are provided on insulating layer 82. The opening 92 is formed in insulating layers 84, 85, and 86 and is provided to reach the conductive layer 83. Insulating layer 87 is provided along the inside of the opening 92. The conductive layer 88 has a region provided along the inside of the opening 92 and a region that contacts the conductive layer 83 at the bottom of the opening. The conductive layer 88, insulating layer 89, and a part of the conductive layer 12 are provided so as to be located inside the opening 92. Preferably, the conductive layer 12 is provided so as to embed the opening 92. In this embodiment, an example is shown in which the opening 92 is circular in plan view, but the present invention is not limited to this. The shapes applicable to the opening 92 are the same as the shapes applicable to the opening 90.

[0340] Since at least a portion of the capacitive element 80 can be placed inside the opening 92, the capacitance per unit area in a plan view can be increased.

[0341] As shown in Figure 9B, the transistor 10 is provided so as to overlap with the capacitive element 80. Furthermore, the opening 90, through which part of the structure of the transistor 10 is provided, has a region that overlaps with the opening 92, through which part of the structure of the capacitive element 80 is provided. In particular, since the conductive layer 12 functions as one of the pair of electrodes of the capacitive element 80 and as one of the source electrode and drain electrode of the transistor 10, the capacitive element 80 and the transistor 10 share part of their structure. This configuration reduces the number of processes, thereby improving productivity. In addition, the capacitive element 80 and the transistor 10 can be provided without significantly increasing the occupied area in a plan view. As a result, the occupied area of ​​the memory cell 99 can be reduced, allowing for a high-density arrangement of the memory cell 99 and increasing the storage capacity of the storage device. In other words, the storage device can be highly integrated.

[0342] For insulating layers such as insulating layer 81, insulating layer 82, insulating layer 84, insulating layer 85, insulating layer 86, insulating layer 87, and insulating layer 89, the materials and configurations described in the [insulating layer] section of Embodiment 3 can be used. In particular, for insulating layer 81, insulating layer 84, insulating layer 86, and insulating layer 87, it is preferable to use insulating layer materials that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, insulating layer materials that have the function of capturing or fixing hydrogen, and insulating layer materials that have barrier properties against hydrogen. By using these insulating layers, the diffusion of hydrogen into the semiconductor layer 18 of the transistor 10 arranged on the capacitive element 80 can be suppressed. In addition, the transistor 10 arranged on the capacitive element 80 can be made highly reliable.

[0343] The conductive layers, such as conductive layer 83 and conductive layer 88, can be formed as a single layer or a laminate using the materials and configuration described in [Conductive Layer] of Embodiment 3. For example, conductive layer 83 can have a two-layer structure using titanium nitride for conductive layer 83_1 and tungsten for conductive layer 83_2. Since a highly conductive material such as tungsten can be used, the wiring resistance of conductive layer 83 can be reduced. Conductive layer 83 can also have a three-layer structure of tantalum nitride, titanium nitride, and tungsten from the bottom layer. It is also preferable to use a conductive material that is resistant to oxidation for conductive layer 83. Conductive layer 83 can also have a four-layer structure of tantalum nitride, tantalum, titanium nitride, and tungsten from the bottom layer. Alternatively, conductive layer 83 can have a four-layer structure of tantalum, tantalum nitride, titanium nitride, and tungsten from the bottom layer. For conductive layer 88, it is preferable to use a conductive oxide such as titanium nitride or In-Sn oxide.

[0344] The insulating layer, such as the insulating layer 89, can be formed as a single layer or in a laminated form using the material and configuration described in the [insulating layer] of Embodiment 3. It is preferable to use a material with a high dielectric constant (high-k), an insulating material with high dielectric strength, and an insulating material that suppresses leakage current for the insulating layer 89. For example, an insulating film (also called ZAZ) laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. Alternatively, for example, an insulating film (also called ZAZA) laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. By using a high-k material as the insulating layer 89, the film thickness of the insulating layer 89 can be increased to a degree that suppresses leakage current, while also ensuring sufficient capacitance of the capacitive element 80.

[0345] Furthermore, the insulating layer, such as the insulating layer 89, may be made of a material capable of ferroelectricity. For example, a metal oxide containing one or both of hafnium and zirconium can be used as the material capable of ferroelectricity. By using a ferroelectric material for the dielectric of the capacitive element 80, the memory device shown in this embodiment can function as a ferroelectric memory.

[0346] The transistors in the memory cell 99 are not limited to transistor 10, and one or more of the transistors exemplified in Embodiment 3 can be used.

[0347] Figure 10 shows an example of a cross-sectional configuration of a memory device in which layers having memory cells 99, as shown in Figures 9A and 9B, are stacked on a layer on which a drive circuit including a sense amplifier is provided.

[0348] In Figure 10, a memory cell 99 (capacitor element 80 and transistor 10) is provided above the Si transistor 900. The Si transistor 900 is one of the transistors in the drive circuit, which includes a sense amplifier.

[0349] The Si transistor 900 will now be described. The Si transistor 900 is a Fin-type transistor. Figure 10 shows a schematic cross-sectional view in the channel length direction.

[0350] The Si transistor 900 is provided on a substrate 901 and has a conductive layer 908a that functions as a gate electrode, an insulating layer 907 that functions as a gate insulating film, a semiconductor region 903 that functions as a channel forming region, and a low-resistance region 904 that functions as a source region or drain region.

[0351] For example, a silicon substrate or an SOI substrate can be used as the substrate 901.

[0352] A device isolation layer 902, an insulating layer 905, and dummy gate electrodes 908b and 908c are provided on the substrate 901. The insulating layer 905 functions as a sidewall. In addition, insulating layers 906, 909, 910, 911, 913, 915, and 916 are provided, and these insulating layers function as interlayer insulating films. In addition, insulating layers 909, 911, and 915 function as barrier films. Conductive layers 912 and 914 function as plugs, electrodes, or wiring.

[0353] One of the sources or drains of the Si transistor 900 (in this case, the low-resistance region 904) is connected to the memory cell 99 via a conductive layer.

[0354] A portion of the conductive layer 83a is provided so as to be embedded in the insulating layer 916. The conductive layer 83a is connected to the Si transistor 900 via the conductive layer 914.

[0355] The insulating layers 803 and 804 are provided on the memory cell 99. The insulating layers such as insulating layer 803 and insulating layer 804 can use the materials and configurations described in the [insulating layer] section of Embodiment 3. In particular, for insulating layers such as insulating layer 803, it is preferable to use insulating layer materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, insulating layer materials that have the function of capturing or fixing hydrogen, and insulating layer materials that have barrier properties against hydrogen. Furthermore, for insulating layers such as insulating layer 804, it is preferable to use insulating materials with a lower dielectric constant compared to high-k materials. By using these insulating films, the diffusion of hydrogen into the semiconductor layer 18 of the transistor 10 can be suppressed. In addition, the transistor 10 can be made highly reliable.

[0356] The conductive layers 805a, 805b, 805c, and 805d are provided so as to be embedded in the insulating layers 803 and 804. The conductive layers such as conductive layers 805a, 805b, 805c, and 805d can be formed as single layers or laminates using the materials and configuration described in the [Conductive Layer] section of Embodiment 3. For example, the conductive layer 805 can be a two-layer structure using tungsten on titanium nitride. Because a highly conductive material such as tungsten can be used, the wiring resistance of the conductive layer 805 can be reduced. The conductive layer 805 can also be a three-layer structure of tantalum nitride, titanium nitride, and tungsten from the bottom layer. Alternatively, the conductive layer 805 can be a four-layer structure of tantalum nitride, tantalum, titanium nitride, and tungsten from the bottom layer.

[0357] The conductive layer 802a is provided to connect the conductive layer 805a and the conductive layer 83a via the conductive layer 801. The conductive layer 83a can be manufactured using the same process as the conductive layer 83.

[0358] The conductive layer 802b is provided to connect the conductive layer 805b and the conductive layer 12a. Alternatively, if, for example, a conductive oxide is used for conductive layer 12a_3 and a lower-resistance material is used for conductive layers 12a_2 and 12a_1, an opening may be provided in conductive layer 12a_3 so that conductive layer 802b is in contact with conductive layer 12a_2. This configuration allows conductive layer 802b to form good contact with conductive layer 12a_2. The conductive layer 12a can be manufactured using the same process as conductive layer 12.

[0359] The conductive layer 802c is provided to connect the conductive layer 805c and the conductive layer 20a.

[0360] The conductive layer 802d is provided to connect the conductive layer 805d and the conductive layer 17. Alternatively, for example, if a conductive oxide is used for the conductive layer 17_2 and a material with lower resistance is used for the conductive layer 17_1, an opening may be provided in the conductive layer 17_2 so that the conductive layer 802d is in contact with the conductive layer 17_1. With such a configuration, the conductive layer 802d can form good contact with the conductive layer 17_1.

[0361] Furthermore, conductive layers such as conductive layer 802a, conductive layer 802b, conductive layer 802c, and conductive layer 802d can be formed as single layers or laminates using the materials and configuration described in [Conductive Layer] of Embodiment 3. For example, conductive layer 802 can be a two-layer structure using tungsten on titanium nitride.

[0362] The conductive layers 805a, 805b, 805c, 805d, 802a, 802b, 802c, 802d, and 801 function as a plug or wiring.

[0363] The conductive layers 805a, 805b, 805c, and 805d may be connected to each other. Furthermore, the conductive layers 12a and 12 may be connected to each other. Also, the conductive layers 83a and 83 may be connected to each other.

[0364] Furthermore, by using a material with a low dielectric constant for the insulating layer 85 (insulating layer 15), parasitic capacitance occurring between the wirings arranged above and below the insulating layer 85 (insulating layer 15) can be reduced. For example, parasitic capacitance occurring between the wiring between the conductive layer 83a located below the insulating layer 85 and the conductive layer 12a located above the insulating layer 85 can be reduced. Also, for example, parasitic capacitance occurring between the wiring between the conductive layer 12a located below the insulating layer 15 and one or both of the conductive layer 20a or conductive layer 17 located above the insulating layer 15 can be reduced.

[0365] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0366] (Embodiment 5) In this embodiment, a semiconductor device 8000 according to one aspect of the present invention will be described. The semiconductor device 8000 can function as a storage device.

[0367] Figure 11 shows a block diagram illustrating an example configuration of the semiconductor device 8000. The semiconductor device 8000 shown in Figure 11 includes a drive circuit 8110 and a memory array 8120. The memory array 8120 has one or more memory cells 8130. Figure 11 shows an example in which the memory array 8120 has multiple memory cells 8130 arranged in a matrix.

[0368] The memory cell 8130 can be a storage device as described in Embodiment 4.

[0369] The drive circuit 8110 includes a PSW 8001 (power switch), a PSW 8002, and a peripheral circuit 8003. The peripheral circuit 8003 includes a peripheral circuit 8004, a control circuit 8005, and a voltage generation circuit 8006.

[0370] In a semiconductor device, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0371] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 8005.

[0372] The control circuit 8005 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 8000. For example, the control circuit 8005 performs a logic operation on signals CE, GW, and BW to determine the operating mode of the semiconductor device 8000 (e.g., write operation, read operation). Alternatively, the control circuit 8005 generates control signals for the peripheral circuit 8004 so that this operating mode is executed.

[0373] The voltage generation circuit 8006 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 8006. For example, when a high-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 8006, and the voltage generation circuit 8006 generates a negative voltage.

[0374] The peripheral circuit 8004 is a circuit for writing and reading data to and from the memory cell 8130. The peripheral circuit 8004 includes a row decoder 8007, a column decoder 8008, a row driver 8009, a column driver 8010, a sense amplifier 8011, an input circuit 8012, and an output circuit 8013.

[0375] The row decoder 8007 and column decoder 8008 have the function of decoding the ADDR signal. The row decoder 8007 is a circuit for specifying the row to access, and the column decoder 8008 is a circuit for specifying the column to access. The row driver 8009 has the function of selecting the row specified by the row decoder 8007. The column driver 8010 has the function of writing data to the memory cell 8130, reading data from the memory cell 8130, and holding the read data.

[0376] The input circuit 8012 has the function of holding the signal WDA. The data held by the input circuit 8012 is output to the column driver 8010. The output data of the input circuit 8012 is the data (Din) to be written to the memory cell 8130. The data (Dout) read by the column driver 8010 from the memory cell 8130 is output to the output circuit 8013. The output circuit 8013 has the function of holding Dout. The output circuit 8013 also has the function of outputting Dout to the outside of the semiconductor device 8000. The data output from the output circuit 8013 is the signal RDA.

[0377] PSW8001 provides V to peripheral circuit 8003 ＤＤ It has the function of controlling the supply. PSW8002 connects to the line driver 8009. ＨＭ It has a function to control the supply. Here, the high power supply potential of semiconductor device 8000 is V ＤＤ Therefore, the low power supply potential is GND (ground potential). Also, V ＨＭ This is a high power supply potential used to raise the word line to a high level, V ＤＤ It is higher than. The on / off state of PSW8001 is controlled by signal PON1, and the on / off state of PSW8002 is controlled by signal PON2. In Figure 11, in peripheral circuit 8003, V ＤＤ The number of power domains supplied is set to one, but it can be multiple. In this case, a power switch should be provided for each power domain.

[0378] Using Figures 12A to 12H, other examples of memory cell configurations applicable to the memory cell 8130 will be described.

[0379] [DOSRAM] Figure 12A shows an example of the circuit configuration of a memory cell of a DRAM (Dynamic Random Access Memory). In this specification and elsewhere, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 8131 has a transistor M1 and a capacitive element CA.

[0380] Transistor M1 may have a front gate (sometimes simply called a gate) and a back gate. In this case, the back gate may be connected to a wire to which a constant potential or signal is supplied, or the front gate and back gate may be connected.

[0381] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitive element CA is connected to wiring CAL.

[0382] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0383] For example, the conductive layer 17 shown in Figures 9A and 9B corresponds to the wiring BIL. For example, the conductive layer 20 shown in Figures 9A and 9B corresponds to the wiring WOL. Also, for example, the conductive layer 83 shown in Figures 9A and 9B corresponds to the wiring CAL.

[0384] Data writing and reading are performed by applying a high-level potential to the wiring WOL, turning on transistor M1, and creating a conductive state (a state in which current can flow) between the wiring BIL and the first terminal of the capacitive element CA.

[0385] Furthermore, the memory cell that can be used in memory cell 8130 is not limited to memory cell 8131, and the circuit configuration can be changed. For example, the memory cell 8132 can be configured as shown in Figure 12B. Memory cell 8132 is an example in which there is no capacitive element CA and wiring CAL. The first terminal of transistor M1 is electrically floating.

[0386] In the memory cell 8132, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, indicated by the dashed line. This configuration significantly simplifies the structure of the memory cell.

[0387] Furthermore, it is preferable to use an OS transistor as transistor M1. OS transistors have the characteristic of having an extremely low off-current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. In other words, the written data can be held by transistor M1 for a long time, so the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very low, multi-level data or analog data can be held in memory cells 8131 and 8132.

[0388] [NOSRAM] Figure 12C shows an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 8133 has a transistor M2, a transistor M3, and a capacitance element CB. In this specification and elsewhere, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 is called NOSRAM (Nonvolatil Oxide Semiconductor RAM).

[0389] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0390] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0391] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M2, and creating a conductive state between the wiring WBL and the first terminal of the capacitive element CB. Specifically, when transistor M2 is ON, a potential corresponding to the information to be recorded in the wiring WBL is applied, and this potential is written to the first terminal of the capacitive element CB and the gate of transistor M3. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M2, thereby maintaining the potential of the first terminal of the capacitive element CB and the potential of the gate of transistor M3.

[0392] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3, and the potential of the first terminal of transistor M3, are determined by the potential of the gate and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3).

[0393] Further, for example, a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL may be adopted. An example of the circuit configuration of the memory cell is shown in FIG. 12D. In the memory cell 8134, the wiring WBL and the wiring RBL of the memory cell 8133 are made into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. That is, the memory cell 8134 is configured to operate with a single wiring BIL for the write bit line and the read bit line.

[0394] The memory cell 8135 shown in FIG. 12E is an example in the case where the capacitor element CB and the wiring CAL in the memory cell 8133 are omitted. The memory cell 8136 shown in FIG. 12F is an example in the case where the capacitor element CB and the wiring CAL in the memory cell 8134 are omitted. By adopting such a configuration, the integration degree of the memory cell can be increased.

[0395] It is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use an OS transistor for the transistor M2 and the transistor M3.

[0396] Since the OS transistor has the characteristic that the off-current is extremely small, the written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cell can be reduced. Or, the refresh operation of the memory cell can be made unnecessary. Further, since the leakage current is very low, multi-valued data or analog data can be held for the memory cells 8133, 8134, 8135, and 8136.

[0397] The memory cells 8133, 8134, 8135, and 8136 to which an OS transistor is applied as the transistor M2 are one aspect of NOSRAM.

[0398] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field-effect mobility, and can also be a p-channel type transistor, so the degree of freedom in circuit design can be increased.

[0399] Also, when an OS transistor is used as the transistor M3, the memory cell can be composed of only n-type transistors.

[0400] Further, FIG. 12G shows a gain cell type memory cell 8137 of a 3-transistor 1-capacitor element. The memory cell 8137 includes transistors M4 to M6 and a capacitor element CC.

[0401] The first terminal of the transistor M4 is connected to the first terminal of the capacitor element CC, the second terminal of the transistor M4 is connected to the wiring BIL, and the gate of the transistor M4 is connected to the wiring WOL. The second terminal of the capacitor element CC is connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor element CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RWL.

[0402] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that provides a low-level potential.

[0403] Writing of data is performed by applying a high-level potential to the wiring WOL, turning on the transistor M4, and making the wiring BIL and the first terminal of the capacitor element CC conductive. Specifically, when the transistor M4 is in the on state, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the first terminal of the capacitor element CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL to turn off the transistor M4, thereby holding the potential of the first terminal of the capacitor element CC and the potential of the gate of the transistor M5.

[0404] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M6 turns ON, and the wiring BIL and the second terminal of transistor M5 become conductive. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL change depending on the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5). By reading the potential of the wiring BIL, the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5).

[0405] Furthermore, it is preferable to use an OS transistor for at least transistor M4.

[0406] Note that Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.

[0407] Furthermore, if OS transistors are used as transistors M5 and M6, the memory cell can be constructed using only n-type transistors.

[0408] [OS-SRAM] Figure 12H shows an example of SRAM (Static Random Access Memory) using an OS transistor. In this specification and elsewhere, SRAM using an OS transistor is called OS-SRAM (Oxide Semiconductor-SRAM). The memory cell 8138 shown in Figure 12H is a memory cell of a backup-capable SRAM.

[0409] The memory cell 8138 includes transistors M7 to M10, transistors MS1 to MS4, and capacitive elements CD1 and CD2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0410] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0411] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0412] The second terminal of transistor M9 is connected to the first terminal of capacitive element CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitive element CD2, and the gate of transistor M10 is connected to wiring BRL.

[0413] The second terminal of capacitive element CD1 is connected to wiring GNDL, and the second terminal of capacitive element CD2 is connected to wiring GNDL.

[0414] Wires BIL and BILB function as bit lines, wire WOL functions as a word line, and wire BRL controls the on and off states of transistors M9 and M10.

[0415] Wiring VDL is a wiring that provides a high-level potential, and wiring GNDL is a wiring that provides a low-level potential.

[0416] Data is written by applying a high-level potential to the wiring WOL and also to the wiring BRL. Specifically, when transistor M10 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the second terminal side of transistor M10.

[0417] Incidentally, since the memory cell 8138 is configured as an inverter loop by transistors MS1 to MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal side of transistor M8. Because transistor M8 is ON, the potential applied to wiring BIL, i.e., the inverted signal of the signal input to wiring BIL, is output to wiring BILB. Also, because transistors M9 and M10 are ON, the potential of the second terminal of transistor M7 and the potential of the second terminal of transistor M8 are held at the first terminal of capacitive element CD2 and the first terminal of capacitive element CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and wiring BRL, and turning off transistors M7 to M10, the potentials of the first terminal of capacitive element CD1 and the first terminal of capacitive element CD2 are maintained.

[0418] The data reading process is described below. First, wiring BIL and wiring BILB are precharged to a predetermined potential. Then, a high-level potential is applied to wiring WOL and wiring BRL. As a result, the potential of the first terminal of capacitive element CD1 is refreshed by the inverter loop of memory cell 8138 and output to wiring BILB. Also, the potential of the first terminal of capacitive element CD2 is refreshed by the inverter loop of memory cell 8138 and output to wiring BIL. In wiring BIL and wiring BILB, the potential changes from the precharged potential to the potential of the first terminal of capacitive element CD2 and the potential of the first terminal of capacitive element CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0419] Furthermore, it is preferable to use OS transistors as transistors M7 to M10. This allows the written data to be retained for a long time by transistors M7 to M10, thereby reducing the frequency of memory cell refreshes. Alternatively, it may be possible to eliminate the need for memory cell refresh operations altogether.

[0420] Furthermore, Si transistors may be used as transistors MS1 to MS4.

[0421] Figures 13A and 13C show perspective views of the semiconductor device 8200A. The semiconductor device 8200A has a layer 8220 on which memory arrays are provided on the arithmetic unit 8210. Memory arrays 8120L1, 8120L2, and 8120L3 are provided on layer 8220. The arithmetic unit 8210 and each memory array have overlapping regions. To make the configuration of the semiconductor device 8200A easier to understand, Figure 13B shows the arithmetic unit 8210 and layer 8220 separately. The arithmetic unit 8210 can be, for example, a CPU, GPU, etc.

[0422] By stacking the layer 8220 containing the memory array and the arithmetic unit 8210, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, power consumption can be reduced due to the short connection distance.

[0423] As a method for stacking the layer 8220 having a memory array and the arithmetic unit 8210, one may use a method in which the layer 8220 having a memory array is directly stacked on the arithmetic unit 8210 (also called monolithic stacking), or one may use a method in which the arithmetic unit 8210 and the layer 8220 are formed on different substrates, the two substrates are bonded together, and they are connected using through-via or conductive film bonding technology (such as Cu-Cu bonding). The former does not require consideration of positional misalignment during bonding, so not only can the chip size be reduced, but manufacturing costs can also be reduced.

[0424] Here, the arithmetic unit 8210 does not have a cache, and the memory arrays 8120L1, 8120L2, and 8120L3 provided in layer 8220 can each be used as caches. In this case, for example, memory array 8120L1 can be used as an L1 cache (also called a level 1 cache), memory array 8120L2 can be used as an L2 cache (also called a level 2 cache), and memory array 8120L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 8120L3 has the largest capacity and the lowest access frequency. Also, memory array 8120L1 has the smallest capacity and the highest access frequency.

[0425] Furthermore, when the cache provided in the arithmetic unit 8210 is used as the L1 cache, each memory array provided in layer 8220 can be used as a lower-level cache or main memory, respectively. Main memory has a larger capacity than cache and is accessed less frequently.

[0426] Furthermore, as shown in Figure 13B, drive circuits 8110L1, 8110L2, and 8110L3 are provided. Drive circuit 8110L1 is connected to memory array 8120L1 via connecting electrode 8230L1. Similarly, drive circuit 8110L2 is connected to memory array 8120L2 via connecting electrode 8230L2, and drive circuit 8110L3 is connected to memory array 8120L3 via connecting electrode 8230L3.

[0427] Note that while this example shows three memory arrays functioning as a cache, it can also be one, two, or four or more.

[0428] When the memory array 8120L1 is used as a cache, the drive circuit 8110L1 may function as part of the cache interface, or the drive circuit 8110L1 may be configured to be connected to the cache interface. Similarly, the drive circuits 8110L2 and 8110L3 may also function as part of the cache interface, or be configured to be connected to it.

[0429] In Figures 13A and 13B, an example is shown in which one layer 8220 on which a memory array is provided is placed on the arithmetic unit 8210. However, as shown in Figure 13C, two or more layers 8220 on which memory arrays are provided may be placed.

[0430] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0431] (Embodiment 6) A semiconductor device according to one aspect of the present invention will be described. Figure 14A is a schematic perspective view of a semiconductor device 8310 according to one aspect of the present invention. Figure 14B is a schematic perspective view of a part of the semiconductor device 8310. Figure 15 is a schematic perspective view illustrating the configuration of the semiconductor device 8310.

[0432] In FIGS. 14A, 14B, and 15, a semiconductor device 8310 has an element layer 8370 under an element layer 8320 including a substrate 8322 which is a semiconductor substrate, and has a support substrate 8340 via an insulating layer 8341 on the element layer 8320. The element layer 8320 has a plurality of transistors 8321 constituting a functional circuit 8311. The element layer 8370 has a plurality of transistors 8371 constituting a switch circuit 8315. The transistor 8371 functions as a switch for controlling conduction / non-conduction between a conductive layer 8372 that functions as a power supply line from the outside and a power supply line.

[0433] The transistor exemplified in Embodiment 3 can be applied to the transistor 8371.

[0434] The transistor 8321 included in the element layer 8320 is formed on the surface (also referred to as the "first surface") side of the substrate 8322. Further, the element layer 8370 is formed on the back surface (the surface opposite to the surface, also referred to as the "second surface") side of the substrate 8322. Therefore, the transistor 8371 included in the element layer 8370 is formed on the second surface side of the substrate 8322.

[0435] In FIG. 15, a CPU 8312, a GPU 8313, and a memory 8314 are exemplified as the functional circuit 8311.

[0436] Note that the functional circuit 8311 is not limited to the CPU 8312, the GPU 8313, and the memory 8314, and one or more of these can be used. Further, it is also possible to include a circuit having other functions.

[0437] In order to improve the operating speed, mounting density, and power saving of the semiconductor device 8310, the functional circuit 8311 is required to be miniaturized and thinned, such as transistors and wirings, and the power supply potential is required to be reduced. The switch circuit 8315 can control supplying a voltage supplied from the outside to each circuit included in the functional circuit 8311 and stopping the supply. Thereby, it is possible to stop supplying the power supply potential to the circuit in the standby state, and the power consumption can be reduced.

[0438] Furthermore, the transistors constituting the switch circuit 8315 require high dielectric strength. One effective way to increase the dielectric strength of the transistors is to thicken the gate insulating film. Thus, transistors 8321 and 8371 require different performance characteristics. Therefore, different measures are needed to improve the characteristics of transistors 8321 and 8371.

[0439] Furthermore, miniaturization and thinning are required for the functional circuit 8311. Therefore, if the switch circuit 8315 is constructed using the same process node as the functional circuit 8311, not only the routing wiring but also the wiring for supplying power (power lines) will become thinner, and sufficient power cannot be supplied to the functional circuit 8311. In addition, if the wiring resistance increases due to miniaturization, uneven power potential is likely to occur within the functional circuit 8311 due to voltage drop. In order to stably supply power to the functional circuit 8311, it is preferable that the wiring constituting the switch circuit 8315 has a lower wiring resistance than the wiring constituting the functional circuit 8311. In particular, it is preferable that the wiring that functions as a power line has a lower wiring resistance than the wiring constituting the functional circuit 8311. One means of reducing wiring resistance is to increase the cross-sectional area of ​​the conductive layer that functions as wiring. However, in order to increase the cross-sectional area of ​​the conductive layer, it is necessary to increase one or both of the width and height of the conductive layer. Thus, it is preferable to use different process nodes for the functional circuit 8311 and the switch circuit 8315.

[0440] In a semiconductor device 8310 according to one aspect of the present invention, by providing the functional circuit 8311 and the switch circuit 8315 on different element layers, different improvement measures can be implemented in the functional circuit 8311 and the switch circuit 8315. Furthermore, the functional circuit 8311 and the switch circuit 8315 can be formed at different process nodes.

[0441] In one aspect of the present invention, a plurality of conductive layers 8372 that function as power lines and a switch circuit 8315 can be arranged below the functional circuit 8311, thereby reducing the occupied area of ​​the semiconductor device 8310. Furthermore, it is preferable that the element layer 8370, which is superimposed on the element layer 8320, be formed using thin-film formation techniques such as CVD or sputtering. Therefore, the transistor 8371 included in the element layer 8370 is preferably a thin-film transistor.

[0442] At least a portion of the multiple conductive layers 8372 of the element layer 8370 can function as power lines. Furthermore, if the element layer 8370 has a clock signal generation circuit, at least a portion of the multiple conductive layers 8372 can function as clock signal lines. It is also possible to supply either or both of the power supply and / or clock signal supplied from an external source to the functional circuit 8311 of the element layer 8320 via at least a portion of the multiple conductive layers 8372.

[0443] For example, it is possible to manufacture a die (semiconductor chip) containing the functional circuit 8311 and a die containing the switch circuit 8315 separately, and then mechanically bond them together using 3D integration technology. However, with 3D integration technology, improving alignment accuracy is difficult because the two are bonded mechanically, and miniaturizing the bumps used to connect them is also difficult, making it difficult to narrow the pitch of the connection points. As a result, there was a challenge in shortening the wiring distance required to supply power to the necessary parts of the functional circuit 8311.

[0444] According to one aspect of the present invention, an element layer 8370 including a switch circuit 8315 is formed on the back side of the substrate 8322 using thin-film formation technology, photolithography technology, or the like. Therefore, the semiconductor device 8310 according to one aspect of the present invention is a monolithically stacked semiconductor device.

[0445] By forming the element layer 8370 using thin-film formation technology, high-precision alignment at the photolithography level can be achieved. Furthermore, conductive layers that function as power lines can be connected to the necessary locations of the functional circuit 8311 over extremely short distances. Therefore, the necessary voltage of power can be supplied to the necessary locations of the functional circuit 8311. In addition, in the semiconductor device 8310 according to one aspect of the present invention, since the connection distance between the switch circuit 8315 and the functional circuit 8311 is short, power loss related to power transmission is reduced, and power consumption can be reduced.

[0446] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0447] (Embodiment 7) This embodiment describes an application example of a semiconductor device according to one aspect of the present invention. Because a semiconductor device according to one aspect of the present invention can provide a transistor with high on-current and small footprint, it is suitable for, for example, electronic components, electronic equipment, large computers, space equipment, and data centers.

[0448] [Electronic Components] Figure 16A shows a perspective view of a substrate (mounted substrate 9109) on which electronic components 9100 are mounted. The electronic component 9100 shown in Figure 16A has a semiconductor device 9101 inside a mold 9104. Some details are omitted in Figure 16A to show the inside of the electronic component 9100. The electronic component 9100 has a land 9105 on the outside of the mold 9104. The land 9105 is electrically connected to an electrode pad 9106, and the electrode pad 9106 is electrically connected to the semiconductor device 9101 via a wire 9107. The electronic component 9100 is mounted on a printed circuit board 9108, for example. Multiple such electronic components are combined and electrically connected on the printed circuit board 9108 to complete the mounted substrate 9109.

[0449] Furthermore, the semiconductor device 9101 includes a drive circuit layer 9102 and a storage layer 9103. The storage layer 9103 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 9102 and the storage layer 9103 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 9102 and the storage layer 9103, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0450] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0451] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 9103 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or the memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 9103, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0452] The semiconductor device 9101 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0453] Next, a perspective view of the electronic component 9110 is shown in Figure 16B. The electronic component 9110 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 9110 has an interposer 9111 on a package substrate 9112 (printed circuit board), and a semiconductor device 9114 and a plurality of semiconductor devices 9101 are provided on the interposer 9111.

[0454] Electronic component 9110 shows an example of using semiconductor device 9101 as a high-bandwidth memory (HBM). Furthermore, semiconductor device 9114 can be used in integrated circuits such as CPUs, GPUs, or FPGAs (Field Programmable Gate Arrays).

[0455] The package substrate 9112 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 9111 can be, for example, a silicon interposer, a resin interposer, or a glass substrate interposer.

[0456] The interposer 9111 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 9111 also has the function of connecting integrated circuits provided on the interposer 9111 to electrodes provided on the package substrate 9112. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 9111, and these through electrodes may be used to connect the integrated circuits and the package substrate 9112. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0457] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0458] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0459] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 9110, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0460] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 9110. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 9111. For example, in the electronic component 9110 shown in this embodiment, it is preferable to align the heights of the semiconductor device 9101 and the semiconductor device 9114.

[0461] To mount the electronic component 9110 onto another substrate, electrodes 9113 may be provided at the bottom of the package substrate 9112. Figure 16B shows an example in which the electrodes 9113 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 9112, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 9113 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 9112, PGA (Pin Grid Array) mounting can be achieved.

[0462] The electronic component 9110 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0463] [Large-scale computer] Next, Figure 17A shows a perspective view of the large-scale computer 9200. The large-scale computer 9200 shown in Figure 17A has multiple rack-mount type computers 9220 housed in rack 9210. The large-scale computer 9200 may also be called a supercomputer.

[0464] The computer 9220 can have the configuration shown in the perspective view in Figure 17B, for example. In Figure 17B, the computer 9220 has a motherboard 9230, which has multiple slots 9231 and multiple connection terminals. A PC card 9221 is inserted into a slot 9231. In addition, the PC card 9221 has connection terminals 9223, 9224, and 9225, which are each connected to the motherboard 9230.

[0465] The PC card 9221 shown in Figure 17C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 9221 has a board 9222. The board 9222 also has connection terminals 9223, 9224, 9225, semiconductor device 9226, semiconductor device 9227, semiconductor device 9228, and connection terminal 9229. Although Figure 17C shows semiconductor devices other than semiconductor devices 9226, 9227, and 9228, you can refer to the descriptions of semiconductor devices 9226, 9227, and 9228 below for details on these semiconductor devices.

[0466] The connector 9229 has a shape that allows it to be inserted into slot 9231 of the motherboard 9230, and the connector 9229 functions as an interface for connecting the PC card 9221 and the motherboard 9230.

[0467] The semiconductor device 9226 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 9226 and the board 9222 can be connected by inserting these terminals into sockets (not shown) provided on the board 9222.

[0468] Examples of semiconductor device 9227 include FPGAs, GPUs, and CPUs. For example, an electronic component 9110 can be used as the semiconductor device 9227.

[0469] Examples of semiconductor devices 9228 include memory devices. For example, an electronic component 9110 can be used as the semiconductor device 9228.

[0470] The 9200 mainframe computer can also function as a parallel computer. By using the 9200 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0471] [Space Equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment.

[0472] One embodiment of the present invention includes an OS transistor. Compared to Si transistors, OS transistors exhibit less variation in electrical properties due to radiation exposure. In other words, they have high resistance to radiation, making them highly reliable and suitable for use in environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used as transistors constituting semiconductor devices installed in space shuttles, artificial satellites, or space probes. Outer space refers to, for example, an altitude of 100 km or higher, but the outer space described herein may include one or more of the thermosphere, mesosphere, and stratosphere.

[0473] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0474] Figure 17D shows an example of space equipment, specifically a satellite 9300. The satellite 9300 comprises a body 9301, solar panels 9302, an antenna 9303, a secondary battery 9305, and a control device 9306. In Figure 17D, a planet 9304 is shown as an example in outer space.

[0475] Furthermore, although not shown in Figure 17D, a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 9305. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0476] Furthermore, the control device 9306 has the function of controlling the artificial satellite 9300. The control device 9306 is configured using, for example, one or more selected from a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 9306.

[0477] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, and space probes.

[0478] As explained above, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0479] [Data Center] One embodiment of the present invention is suitably used in storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as by ensuring the immutability of the data. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, or securing cooling equipment required for data storage, which necessitates the construction of larger buildings.

[0480] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that holds the data. Therefore, it is possible to miniaturize the storage system, the power supply for data retention, and the cooling equipment. This, in turn, contributes to space savings in the data center.

[0481] Furthermore, because the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0482] Figure 17E shows a storage system applicable to a data center. The storage system 9400 shown in Figure 17E has multiple servers 9401sb as hosts 9401 (shown as Host Computer) and multiple storage devices 9403md as storage 9403 (shown as Storage). The host 9401 and the storage 9403 are connected via a storage area network 9404 (SAN: Storage Area Network) and a storage control circuit 9402 (shown as Storage Controller).

[0483] Host 9401 corresponds to a computer that accesses data stored in storage 9403. The hosts 9401 may be connected to each other via a network.

[0484] Although the storage 9403 uses flash memory to shorten data access speed, that is, the time required for data storage and output, this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage. In storage systems, cache memory is usually provided within the storage to shorten the time required for data storage and output in order to solve the problem of the long access speed of the storage 9403.

[0485] The aforementioned cache memory is used within the storage control circuit 9402 and storage 9403. Data exchanged between the host 9401 and storage 9403 is stored in the cache memory within the storage control circuit 9402 and storage 9403, and then output to the host 9401 or storage 9403.

[0486] By using OS transistors as the transistors for storing the aforementioned cache memory data, and configuring them to maintain a potential corresponding to the data, the frequency of refresh can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking the memory cell arrays.

[0487] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0488] In this example, we will describe the results of forming and analyzing indium oxide according to one embodiment of the present invention.

[0489] Samples 1 through 4 were prepared and analyzed. First, the preparation methods for Samples 1 through 4 will be explained.

[0490] Sample 1, as shown in Figure 18A, had a silicon thermal oxide film with a target thickness of 100 nm formed on a Si substrate as structure 200, and then indium oxide with a target thickness of 20 nm deposited on structure 200 as layer 202 by thermal ALD. Sample 2, as shown in Figure 18B, had a silicon thermal oxide film with a target thickness of 100 nm formed on a Si substrate as structure 200, and then indium oxide with a target thickness of 1 nm deposited on structure 200 as layer 201 by thermal ALD, and then indium oxide with a target thickness of 19 nm deposited on layer 202 by thermal ALD. Sample 3, as shown in Figure 18B, had a silicon thermal oxide film with a target thickness of 100 nm formed on a Si substrate as structure 200, and then indium oxide with a target thickness of 5 nm deposited on structure 201 by thermal ALD, and then indium oxide with a target thickness of 15 nm deposited on layer 202 by thermal ALD. As shown in Figure 18C, sample 4 had a silicon thermal oxide film with a target thickness of 100 nm formed on a Si substrate as structure 200, and an indium oxide film with a target thickness of 20 nm formed on the structure 200 by thermal ALD method as layer 201.

[0491] The layer 201 shown in Figures 18B and 18C was formed using the sequence T1 shown in Figure 2.

[0492] The layer 202 shown in Figures 18A and 18B was formed using the sequence T2 shown in Figure 2.

[0493] In the deposition of indium oxide films in layers 201 and 202, triethylindium was used as the precursor P01. A mixed gas of oxygen and ozone was used as the reactant R01, with an ozone concentration of 19 wt%. Nitrogen was used as the carrier gas for both precursor P01 and reactant R01. Nitrogen was also used for purging the chamber.

[0494] For the deposition of layer 201, the substrate was placed in the chamber, heated for 7 minutes to stabilize the substrate temperature at 200°C, and then the sequence T1 shown in Figure 2 was performed as one cycle, with the desired number of cycles (X cycles) being used to achieve the desired film thickness. In the deposition of layer 201, in the sequence T1 shown in Figure 2, the time for introducing the precursor P01 into the chamber (first step S01) was 0.1 seconds. The purging time (second step S02) was 3 seconds. The time for introducing the reactant R01 into the chamber (third step S03) was 9 seconds. The purging time (fourth step S04) was 3 seconds.

[0495] For the deposition of layer 202, the substrate was placed in the chamber, heated for 7 minutes to stabilize the substrate temperature at 200°C, and then the sequence T2 shown in Figure 2 was performed as one cycle, with the number of cycles (Y cycles) required to achieve the desired film thickness. In the deposition of layer 202, in the sequence T2 shown in Figure 2, the time for introducing the precursor P01 into the chamber (first step S01) was 0.1 sec. The purging time (second step S02) was 3 sec. The time for introducing the reactant R01 into the chamber (third step S03) was 60 sec. The purging time (fourth step S04) was 3 sec.

[0496] As shown in Figure 18B, when forming layer 201 on structure 200 and then depositing layer 202 on layer 201, after depositing layer 201, the substrate was kept under reduced pressure, moved to the loading / unloading chamber of the apparatus, and then moved back to the chamber to deposit layer 202. Therefore, although the substrate was not exposed to the atmosphere between the deposition of layer 201 and layer 202, the substrate temperature was lower than the substrate temperature at the time of deposition.

[0497] As described above, the prepared samples were subjected to planar transmission electron microscopy (TEM) imaging. Spherical aberration correction was used for observing the TEM images.

[0498] TEM images were acquired using a JEM-ARM200F atomic-resolution analytical electron microscope manufactured by JEOL Ltd., with an acceleration voltage of 200 kV.

[0499] The planar TEM image of sample 1 is shown in Figure 18D. The planar TEM image of sample 2 is shown in Figure 18E. The planar TEM image of sample 3 is shown in Figure 18F. The planar TEM image of sample 4 is shown in Figure 18G.

[0500] Based on the observation results of the acquired planar TEM images, the extended length of the grain boundaries (sometimes called the grain boundary length) was calculated. Specifically, in the planar TEM image, areas where the connection of the grid lines is interrupted were considered grain boundary regions, and lines were drawn at these locations. Next, the centerlines of the grain boundary regions to which lines were drawn were approximated with polyline graphs, and the sum of the lengths of the polyline graphs was taken as the extended length of the grain boundaries. In other words, the longer the extended length of the grain boundaries, the greater the grain boundary component. Note that the extended length of the grain boundaries may be calculated for each field of view, and the average value may be used.

[0501] The grain boundary length calculated from the planar TEM image shown in Figure 18D was 1380 nm, the grain boundary length calculated from the planar TEM image shown in Figure 18E was 1290 nm, the grain boundary length calculated from the planar TEM image shown in Figure 18F was 690 nm, and the grain boundary length calculated from the planar TEM image shown in Figure 18G was 518 nm. The grain boundary lengths shown here are the average values ​​obtained by extracting two 90 nm square fields from a planar TEM image with a total magnification of 2 million times, and calculating the values ​​for each of the two fields.

[0502] Figures 18D to 18G show that polycrystalline indium oxide films were observed in samples 1 to 4. Furthermore, the crystal grains observed in the planar TEM images were confirmed to increase in size in the order of sample 1, sample 2, sample 3, and sample 4.

[0503] It was confirmed that sample 4, shown in Figure 18G, had larger crystal grains compared to sample 1, shown in Figure 18D. A tendency was observed for the average crystal grain size to increase with shorter treatment time (oxidation time) for the reactant R01.

[0504] Furthermore, it was confirmed that sample 3, shown in Figure 18F, had larger crystal grains compared to sample 2, shown in Figure 18E. When layer 202 was laminated on layer 201, a tendency was observed for the average crystal grain size to be larger in samples where layer 201 was deposited with a target thickness of 5 nm compared to samples where layer 201 was deposited with a target thickness of 1 nm.

[0505] Next, secondary ion mass spectrometry (SIMS) was performed on samples 1 through 4.

[0506] SIMS analysis was performed using an ULVAC-PHI quadrupole secondary ion mass spectrometer (PHI-ADEPT1010), with cesium primary ions (Cs) being the primary ion species. ＋ The following was used: The primary acceleration voltage was 2.0 kV, and the detection area was 140 μm × 140 μm.

[0507] Figures 19A to 20B show the hydrogen (H) and carbon (C) profiles in Samples 1 to 4. Figures 19A to 20B show the results of quantitative analysis of the hydrogen concentration and carbon concentration in the indium oxide layer. In Figures 19A to 20B, the horizontal axis represents the depth [nm] from the sample surface, and the depth of 0 nm at the left end corresponds to the sample surface (the surface of the indium oxide film). Also, the left vertical axis represents the H (hydrogen) concentration [atoms / cm ３ and the C (carbon) concentration [atoms / cm ３ . The right vertical axis represents the In+O secondary ion intensity [counts / sec] and the Si secondary ion intensity [counts / sec]. In the figures, the H profile is shown by a thick dashed line, the C profile is shown by a thick solid line, the In+O profile is shown by a thin dashed line, and the Si profile is shown by a thin solid line. Note that the SIMS analysis was performed in the direction from the sample surface toward the substrate direction.

[0508] Note that the background level (B.G.) of carbon in the indium oxide layer in Figures 19A and 20B in the SIMS is about 2×10 １８ atoms / cm ３ , and the background level (B.G.) of carbon in Figures 19B and 20A is about 8×10 １７ atoms / cm ３ .

[0509] Since the secondary ion intensity of hydrogen in the silicon thermal oxide film located below the indium oxide layer of Samples 1 to 4 has decreased, it was found that the hydrogen concentration in the indium oxide layer can be evaluated.

[0510] The hydrogen concentration in the indium oxide in Sample 1 was 8.46×10 ２０ atoms / cm ３ . The carbon concentration was 2.27×10 １８ atoms / cm ３ .

[0511] The hydrogen concentration in the indium oxide in Sample 2 was 8.69×10 ２０ atoms / cm ３ . The carbon concentration was 3.23×10 １８ atoms / cm３ It was.

[0512] In the indium oxide in Sample 3, the hydrogen concentration was 4.19×10 ２０ atoms / cm ３ It was. Also, the carbon concentration was 1.89×10 １８ atoms / cm ３ It was.

[0513] In the indium oxide in Sample 4, the hydrogen concentration was 5.07×10 ２０ atoms / cm ３ It was. Also, the carbon concentration was 8.59×10 １８ atoms / cm ３ It was.

[0514] The hydrogen concentration and carbon concentration in the indium oxide in Samples 1 to 4 are average values in the range of 8 nm to 12 nm in depth.

[0515] Referring to FIGS. 19A to 20B, it was confirmed that the hydrogen concentration of Samples 3 and 4 tended to be lower than that of Samples 1 and 2. Also, it was confirmed that the carbon concentration of Samples 1 to 3 tended to be lower than that of Sample 4. For Sample 3, it was confirmed that both the hydrogen concentration and the carbon concentration were lower than those of the other samples.

[0516] Referring to the results of the plan-view TEM image and the SIMS analysis, it was found that Sample 3 had a larger average grain size of crystal grains and lower hydrogen and carbon concentrations than Sample 1.

[0517] The configurations, structures, methods, etc. shown in this example can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments or examples.

[0518] In this example, a semiconductor device according to one aspect of the present invention was fabricated, and the results of evaluating its electrical characteristics will be described.

[0519] In this example, Transistor A was fabricated and its electrical characteristics were evaluated. Transistor A was fabricated with the configuration of Transistor 10 shown in FIGS. 5A to 5C of [Configuration Example 1 of Semiconductor Device] in Embodiment 3.

[0520] The insulating layer 11 used an insulating layer (also called ZAZ) which was laminated in the following order: zirconium oxide formed by ALD with a target thickness of 4 nm, aluminum oxide formed by ALD with a target thickness of 0.5 nm, and zirconium oxide formed by ALD with a target thickness of 4 nm. The conductive layer 12_1 used titanium nitride formed by metal CVD with a target thickness of 5 nm. The conductive layer 12_2 was formed by depositing tungsten by metal CVD with a target thickness of 40 nm. The conductive layer 12_3 used ITO formed by sputtering with a target thickness of 20 nm. The insulating layer 13 used silicon nitride formed by ALD with a target thickness of 5 nm. The insulating layer 14 used silicon nitride formed by sputtering and was formed on the conductive layer 12 with a target thickness of 10 nm. The insulating layer 15 used silicon oxide formed by sputtering with a target thickness of 80 nm. The insulating layer 16 uses silicon nitride formed by sputtering with a target thickness of 10 nm. The conductive layer 17_1 uses tungsten formed by sputtering with a target thickness of 30 nm. The conductive layer 17_2 uses ITO formed by sputtering with a target thickness of 10 nm.

[0521] The semiconductor layer 18 was formed from a first layer, a second layer on the first layer, and a third layer on the second layer. The first layer of the semiconductor layer 18 used indium oxide formed by the ALD method with a target film thickness of 2 nm. The second layer of the semiconductor layer 18 used indium oxide formed by the ALD method with a target film thickness of 3 nm. The first layer of the semiconductor layer 18 was deposited by setting the first step S01 of the sequence T1 shown in Figure 2 to 0.1 seconds, the second step S02 to 3 seconds, the third step S03 to 3 seconds, and the fourth step S04 to 3 seconds. The second layer of the semiconductor layer 18 was formed by setting the first step S01 of sequence T2 shown in Figure 2 of Embodiment 1 to 0.1 seconds, the second step S02 to 3 seconds, the third step S03 to 9 seconds, and the fourth step S04 to 3 seconds. In sequences T1 and T2, triethylindium was used as the precursor P01. A mixed gas of oxygen and ozone (ozone concentration 19 wt%) was used as the reactant R01. The third layer of the semiconductor layer 18 was formed using IGZO, which was formed by sputtering with an oxide target of In:Ga:Zn = 1:1:1.2 [atomic ratio] and aimed for a film thickness of 5 nm.

[0522] The insulating layer 19 uses a four-layer structure in which aluminum oxide formed by ALD with a target thickness of 1 nm, silicon oxide formed by ALD with a target thickness of 2 nm, hafnium oxide formed by ALD with a target thickness of 2 nm, and silicon nitride formed by ALD with a target thickness of 1 nm are stacked in that order from the semiconductor layer 18 side. The conductive layer 20_1 uses titanium nitride formed by metal CVD with a target thickness of 5 nm. The conductive layer 20_2 uses tungsten formed by metal CVD with a target thickness of 20 nm. The insulating layer 21 uses silicon nitride formed by ALD with a target thickness of 5 nm.

[0523] Figure 21A shows the Id-Vg characteristics of transistor A. The Id-Vg characteristics of transistor A shown in Figure 21A were measured using a device fabricated with an aperture diameter of 90 nm, which is the mask design value. The vertical axis represents the drain current (Id) on a logarithmic scale, and the horizontal axis represents the gate-source voltage (Vgs). The Id-Vg characteristics were measured under the following conditions: the substrate temperature was room temperature, and the gate-source voltage (Vgs) was applied in 0.1V increments from -4V to +4V. The drain-source voltage (Vds) was set to +0.1V or +1.2V, and the source voltage (Vs) was set to 0V. In Figure 21A, the measurement result for drain-source voltage (Vds) = +0.1V is shown by a solid line, and the measurement result for drain-source voltage (Vds) = +1.2V is shown by a dashed line.

[0524] As shown in Figure 21A, according to this embodiment, it was confirmed that the transistor according to one aspect of the present invention exhibits good electrical characteristics.

[0525] The configurations, structures, or methods shown in this embodiment can be used in appropriate combination with the configurations, structures, or methods shown in other embodiments or examples.

[0526] In this embodiment, a semiconductor device according to one aspect of the present invention is fabricated, and the results of evaluating its electrical characteristics are described.

[0527] In this example, transistor B was fabricated and its electrical characteristics were evaluated. Transistor B was fabricated with the same configuration as transistor 30 shown in Figures 6A to 7B of [Semiconductor Device Configuration Example 2] of Embodiment 3.

[0528] The insulating layer 31 used an insulating layer (also called ZAZ) which was laminated in the following order: zirconium oxide formed by ALD with a target thickness of 4 nm, aluminum oxide formed by ALD with a target thickness of 0.5 nm, and zirconium oxide formed by ALD with a target thickness of 4 nm. The conductive layer 32_1 used titanium nitride formed by metal CVD with a target thickness of 5 nm. The conductive layer 32_2 was formed by depositing tungsten by metal CVD with a target thickness of 40 nm. The conductive layer 32_3 used ITO formed by sputtering with a target thickness of 20 nm. The insulating layer 33 used silicon nitride formed by ALD with a target thickness of 5 nm. The insulating layer 34 used silicon nitride formed by sputtering and was formed on the conductive layer 32 with a target thickness of 10 nm. The insulating layer 35 also used silicon oxide formed by sputtering with a target thickness of 80 nm. After forming the insulating layer 35, heat treatment was performed at 400°C for 1 hour under a nitrogen atmosphere. Subsequently, aluminum oxide was formed by sputtering to a thickness of 10 nm, and the aluminum oxide was removed by CMP treatment. For the insulating layer 36, silicon nitride formed by sputtering to a thickness of 10 nm was used. For the conductive layer 37_1, tungsten formed by sputtering to a thickness of 15 nm was used. For the conductive layer 37_2, ITO formed by sputtering to a thickness of 15 nm was used.

[0529] The semiconductor layer 38 was formed from a first layer, a second layer on the first layer, and a third layer on the second layer. The first layer of the semiconductor layer 38 was made of indium oxide formed by the ALD method with a target film thickness of 1 nm. The second layer of the semiconductor layer 38 was made of indium oxide formed by the ALD method with a target film thickness of 4 nm. The first layer of the semiconductor layer 38 was formed by setting the first step S01 of sequence T1 shown in Figure 2 of Embodiment 1 to 0.1 seconds, the second step S02 to 3 seconds, the third step S03 to 9 seconds, and the fourth step S04 to 3 seconds. The second layer of the semiconductor layer 38 was formed by setting the first step S01 of sequence T2 shown in Figure 2 of Embodiment 1 to 0.1 seconds, the second step S02 to 3 seconds, the third step S03 to 60 seconds, and the fourth step S04 to 3 seconds. In sequences T1 and T2, triethylindium was used as the precursor P01. A mixed gas of oxygen and ozone (ozone concentration 19 wt%) was used as the reactant R01. The third layer of the semiconductor layer 38 was formed using IGZO, which was formed by sputtering with an oxide target of In:Ga:Zn = 1:1:1.2 [atomic ratio] and aimed for a film thickness of 5 nm.

[0530] The insulating layer 39 uses a four-layer structure in which aluminum oxide formed by ALD with a target thickness of 1 nm, silicon oxide formed by ALD with a target thickness of 2 nm, hafnium oxide formed by ALD with a target thickness of 2 nm, and silicon nitride formed by ALD with a target thickness of 1 nm are stacked in that order from the semiconductor layer 38 side. The conductive layer 40_1 uses titanium nitride formed by metal CVD with a target thickness of 5 nm. The conductive layer 40_2 uses tungsten formed by metal CVD with a target thickness of 20 nm. The insulating layer 41 uses silicon nitride formed by ALD with a target thickness of 5 nm.

[0531] Figure 21B shows the Id-Vg characteristics of transistor B. The Id-Vg characteristics of transistor B shown in Figure 21B were measured using a device fabricated with a groove width W of 60 nm (mask design value) and a semiconductor layer width of 600 nm (mask design value). The vertical axis shows the drain current (Id) on a logarithmic scale, and the horizontal axis shows the gate-source voltage (Vgs). The measurement conditions for the Id-Vg characteristics were: substrate temperature at room temperature, gate-source voltage (Vgs) = -4V to +4V, 0.1V step, drain-source voltage (Vds) = +0.1V or +1.2V, and source voltage (Vs) = 0V. In Figure 21B, the measurement result for drain-source voltage (Vds) = +0.1V is shown by a solid line, and the measurement result for drain-source voltage (Vds) = +1.2V is shown by a dashed line.

[0532] As shown in Figure 21B, according to this embodiment, it was confirmed that the transistor according to one aspect of the present invention exhibits good electrical characteristics.

[0533] The configurations, structures, or methods shown in this embodiment can be used in appropriate combination with the configurations, structures, or methods shown in other embodiments or examples.

[0534] ADDR: signal, BIL: wiring, BILB: wiring, BRL: wiring, BW: signal, CA: capacitive element, CAL: wiring, CB: capacitive element, CC: capacitive element, CE: signal, CLK: signal, GNDL: wiring, GW: signal, RBL: wiring, RDA: signal, RWL: wiring, SL: wiring, VDL: wiring, WAKE: signal, WBL: wiring, WDA: signal, WOL: wiring, 10: transistor, 11: insulating layer, 12: conductive layer, 12_1: conductive layer, 12_2: conductive layer, 12_3: conductive layer, 12a: conductive layer, 12a_1: conductive layer, 12a_2: conductive layer, 12a_3: conductive layer, 13: Insulating layer, 14: Insulating layer, 15: Insulating layer, 16: Insulating layer, 17: Conductive layer, 17_1: Conductive layer, 17_2: Conductive layer, 18: Semiconductor layer, 19: Insulating layer, 20: Conductive layer, 20_1: Conductive layer, 20_2: Conductive layer, 20a: Conductive layer, 21: Insulating layer, 22: Insulating layer, 30: Transistor, 31: Insulating layer, 32: Conductive layer, 32_1: Conductive layer, 32_2: Conductive layer, 32_3: Conductive layer, 33: Insulating layer, 34: Insulating layer, 35: Insulating layer, 36: Insulating layer, 37: Conductive layer, 37_1: Conductive layer, 37_2: Conductive layer, 37a: Conductive layer, 37a_1: Conductive layer, 37a_2: Conductive layer, 37b: Conductive layer Layer, 37b_1: conductive layer, 37b_2: conductive layer, 38: semiconductor layer, 39: insulating layer, 40: conductive layer, 40_1: conductive layer, 40_2: conductive layer, 41: insulating layer, 42: insulating layer, 43: conductive layer, 44: conductive layer, 50: transistor, 51: insulating layer, 52: insulating layer, 53: insulating layer, 54: insulating layer, 55: conductive layer, 55_1: conductive layer, 55_2: conductive layer, 56: insulating layer, 57: insulating layer, 58: insulating layer, 59: semiconductor layer, 59_1: semiconductor layer, 59_2: semiconductor layer, 60: conductive layer, 60_1: conductive layer, 60_2: conductive layer, 60a: conductive layer, 60a_1: conductive layer, 60a_2 : conductive layer, 60b: conductive layer, 60b_1: conductive layer, 60b_2: conductive layer, 61: insulating layer, 62: insulating layer, 63: insulating layer, 64: insulating layer, 65: conductive layer, 65_1: conductive layer, 65_2: conductive layer, 66: insulating layer, 67: insulating layer, 68: insulating layer, 69: insulating layer, 70: conductive layer, 70_1: conductive layer, 70_2: conductive layer, 71: conductive layer, 80: capacitive element, 81: insulating layer, 82: insulating layer, 83: conductive layer, 83_1: conductive layer, 83_2: conductive layer, 83a: conductive layer, 84: insulating layer, 85: insulating layer, 86: insulating layer, 87: insulating layer, 88: conductive layer, 89: insulating layer, 90: opening,91: Groove, 92: Opening, 99: Memory cell, 100: Substrate, 101: First layer, 102: Second layer, 103: Third layer, 200: Structure, 201: Layer, 202: Layer, 801: Conductive layer, 802: Conductive layer, 802a: Conductive layer, 802b: Conductive layer, 802c: Conductive layer, 802d: Conductive layer, 803: Insulating layer, 804: Insulating layer, 805: Conductive layer, 805a: Conductive layer, 805b: Conductive layer, 805c: Conductive layer, 805d: Conductive layer, 900: Si transistor, 901: Substrate, 902: Element isolation layer, 903: Semiconductor region, 904: Low resistance region, 905: Insulating layer, 90 6: Insulating layer, 907: Insulating layer, 908a: Conductive layer, 908b: Dummy gate electrode, 908c: Dummy gate electrode, 909: Insulating layer, 910: Insulating layer, 911: Insulating layer, 912: Conductive layer, 913: Insulating layer, 914: Conductive layer, 915: Insulating layer, 916: Insulating layer, 4000: Film deposition apparatus, 4002: Loading / unloading room, 4004: Loading / unloading room, 4006: Conveying room, 4008: Film deposition room, 4009: Film deposition room, 4011: Processing room, 4014: Conveying arm, 4020: Chamber, 4021: Raw material supply unit, 4021a: Raw material supply unit, 4021b: Raw material supply unit, 4021c: Raw material supply unit Feeding section, 4022a: High-speed valve, 4022d: High-speed valve, 4023: Raw material inlet, 4024: Raw material outlet, 4025: Exhaust device, 4026: Substrate holder, 4027: Heater, 4028: Plasma generator, 4029: Coil, 4030: Substrate, 4031: Raw material supply section, 4032: Gas supply section, 4033: Raw material inlet, 4034a: Piping heater, 4034b: Piping heater, 4520: Chamber, 4521: Raw material supply section, 4521a: Raw material supply section, 4521b: Raw material supply section, 4521c: Raw material supply section, 4522a: High-speed valve, 4522c: High-speed valve, 4522d: High-speed valve, 4523: Raw material inlet, 4524: Raw material outlet, 4525: Exhaust device, 4526: Substrate holder, 4527: Heater, 4530: Substrate, 4531: Raw material supply unit, 4532: Gas supply unit, 4534a: Piping heater, 4534b: Piping heater, 8000: Semiconductor device, 8001: PSW, 8002: PSW, 8003: Peripheral circuit, 8004: Peripheral circuit, 8005: Control circuit, 8006: Voltage generation circuit, 8007: Row decoder, 8008: Column decoder, 8009: Row driver, 8010: Column driver, 8011: Sense amplifier,8012: Input circuit, 8013: Output circuit, 8110: Drive circuit, 8120: Memory array, 8130: Memory cell, 8131: Memory cell, 8132: Memory cell, 8133: Memory cell, 8134: Memory cell, 8135: Memory cell, 8136: Memory cell, 8137: Memory cell, 8138: Memory cell, 8200A: Semiconductor device, 8210: Arithmetic unit, 8220: Layer, 8310: Semiconductor device, 8311: Machine Function circuit, 8312: CPU, 8313: GPU, 8314: Memory, 8315: Switch circuit, 8320: Element layer, 8321: Transistor, 8322: Substrate, 8340: Support substrate, 8341: Insulating layer, 8370: Element layer, 8371: Transistor, 8372: Conductive layer, 9100: Electronic component, 9101: Semiconductor device, 9102: Drive circuit layer, 9103: Memory layer, 9104: Mold, 9105: Land, 9106: Electrode Pad, 9107: Wire, 9108: Printed circuit board, 9109: Mounted circuit board, 9110: Electronic component, 9111: Interposer, 9112: Package substrate, 9113: Electrode, 9114: Semiconductor device, 9200: Large computer, 9210: Rack, 9220: Computer, 9221: PC card, 9222: Board, 9223: Connector, 9224: Connector, 9225: Connector, 9226: Semiconductor device, 9227: Semiconductor Device, 9228: Semiconductor device, 9229: Connection terminal, 9230: Motherboard, 9231: Slot, 9300: Artificial satellite, 9301: Aircraft body, 9302: Solar panel, 9303: Antenna, 9304: Planet, 9305: Secondary battery, 9306: Control device, 9400: Storage system, 9401: Host, 9401sb: Server, 9402: Storage control circuit, 9403: Storage, 9403md: Memory device,

Claims

A method for forming a metal oxide film having a first layer and a second layer, A first step of forming the first layer using atomic layer deposition, The process includes a second step of forming a second layer on the first layer using the atomic layer deposition method described above, In the first step, the first sequence is performed one or more times. In the second step, the second sequence is performed one or more times. The first sequence and the second sequence each comprise a first step of introducing a first precursor into a chamber and a second step of introducing a first reactant into the chamber. The first precursor contains a metal, The first reactant is an oxidizing agent, The time of the second step in the first sequence is shorter than the time of the second step in the second sequence. A method for forming metal oxide films. 　 In claim 1, The first step is to form the first layer on the substrate, Between the first step and the second step, A method for forming a metal oxide film, comprising the step of lowering the temperature of the substrate to a temperature lower than that of the first step. 　 In claim 1, The first step is to form the first layer on the substrate. Between the first step and the second step, A step of removing the substrate from the chamber under reduced pressure, A method for forming a metal oxide film, comprising the steps of: then placing the substrate in the chamber while maintaining it under reduced pressure. 　 In any one of claims 1 to 3, The first precursor comprises indium, The first reactant is a method for forming a metal oxide film, wherein the reactant contains oxygen and ozone. 　 In any one of claims 1 to 3, A method for forming a metal oxide film, wherein the first layer and the second layer are films containing indium and oxygen, respectively. 　 In any one of claims 1 to 3, The time of the second step in the first sequence is 0.1 seconds or more and 30 seconds or less. A method for forming a metal oxide film, wherein the time of the second step in the second sequence is 15 seconds or more and 180 seconds or less.

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