Twirling operations for parametric two-qubit quantum logic gates

Abstract

In a general aspect, twirling operations are applied to parametric two-qubit quantum logic gates. In some cases, a quantum logic circuit includes a parametric two-qubit quantum logic gate, which has gate parameters and is a native quantum logic operation of a quantum processing unit. Multiple sets of twirling operations for the parametric two-qubit quantum logic gate are identified. At least one of the sets includes twirling operations that were determined based on specified values of the gate parameters. A first set of the twirling operations is selected, and a modified quantum logic circuit is generated. The modified quantum logic circuit includes the first set of twirling operations applied to the parametric two-qubit quantum logic gate.

Description

Attorney Docket No.: RIGET-139WO1Twirling Operations for Parametric Two-Qubit Quantum Logic GatesCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U. S. Provisional Application No. 63 / 736,097, filed December 19, 2024 and entitled " Twirls of Fermionic Simulation Gates.” The abovereferenced priority application is hereby incorporated by reference.TECHINCAL FIELD

[0002] The following description relates to twirling operations for parametric two-qubit quantum logic gates.BACKGROUND

[0003] Quantum computers can perform computational tasks by storing and processing information within quantum states of quantum systems. For example, qubits (i.e., quantum bits) can be stored in and represented by an effective two-level sub-manifold of a quantum coherent physical system. A variety of physical systems have been proposed for quantum computing applications. Examples include superconducting circuits, trapped ions, spin systems and others.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a block diagram of an example computing system.

[0005] FIG. 2 is a flow chart showing aspects of an example computing process.

[0006] FIG. 3 is a block diagram showing an example of twirling operations applied to an FSIM gate.

[0007] FIG. 4 shows an example of weights applied to a Pauli-transfer matrix M of a two-qubit noise channel simulated under combined twirling operations of an FSIM gate.Attorney Docket No.: RIGET-139WO1DETAILED DESCRIPTION

[0008] In some aspects of what is described here, twirling operations are applied to parametric two-qubit quantum logic gates, each of which is defined by a set of continuous parameters. In some examples, the parametric two-qubit quantum logic gate is a "fermionic simulation" (FSIM) gate; in some examples, twirling operations are applied to other types of two-qubit quantum logic gates. FSIM gates can be used in a variety of quantum computing systems and applications. In some contexts, FSIM gates are used in simulating fermionic systems like electrons in molecules. In some environments, FSIM gates are native gates that can be directly executed by a quantum processing unit. In some environments, FSIM gates may be implemented by combining other quantum logic gates, for example, by combining an iSWAP gate with a controlled-phase (CPHASE) gate, allowing for controlled phase shifts depending on the qubit states. FSIM gates can be a valuable tool for near-term quantum algorithms like the Quantum Approximate Optimization Algorithm due to their ability to efficiently represent electron conservation properties within a quantum logic circuit. In some instances, compared to other general two-qubit gates, the FSIM gate can require fewer control parameters, simplifying implementation. Furthermore, algorithms using FSIM gates can benefit from error mitigation techniques due to its inherent structure.

[0009] In some implementations, twirling operations applicable to a specified two-qubit quantum logic gate (e.g., an FSIM gate or another type of gate) are determined and constructed. Twirling operations can be selected and applied to a quantum logic circuit that includes one or more of the specified two-qubit quantum logic gates; when the twirling operations are applied, the original quantum logic circuit is modified to include the selected twirling operations (e.g., quantum logic gates corresponding to the selected twirling operations may be added to the quantum logic circuit). Typically, the internal structure of the quantum logic circuit is modified without necessarily changing the composite action of the quantum logic circuit, meaning that the modified quantum logic circuit can be logically equivalent to the original quantum logic circuit. For example, twirling operations can be applied before and after the specified two-qubit quantum logic gate, so that the action of the first twirling operations (applied before the two-qubit quantum logic gate) is effectively reversed or "undone” by the second twirling operations (applied after the two-qubitAttorney Docket No.: RIGET-139WO1quantum logic gate). In some examples, twirling operations can be transformed within the quantum logic circuit; for example, twirling gates may be combined with other gates or broken into multiple gates with logical equivalence. In some instances, twirling operations may be identified, parameters of the twirling operations may be selected, and the quantum logic circuit may be updated iteratively using different twirling operations or twirling operations with different parameter values. The updated quantum logic circuits can be iteratively executed by a quantum processing unit.

[0010] In some implementations, the systems and techniques described here can provide technical advantages and improvements. For example, the systems and techniques described here may allow an identification of twirling operations based on gate characteristics and hardware configurations. Aspects of the present disclosure provide parameterized twirling operations for FSIM gates, which allow a larger (e.g., practically infinite) number of twirling operation sets to be defined for FSIM gates. For instance, an array of distinct twirling operation sets can be defined from an array of distinct parameter values applied to the parameterized twirling operations. Furthermore, certain parameter values provide twirling operations that include Pauli gates or other standard gates, which may provide additional efficiency or applicability in some environments. Twirling of parametric two-qubit quantum logic gates, performed using the parameterized twirling operations and twirling operation sets described here, can be used to effectively modify noise channels in a quantum computing system. For instance, twirling can make complex noise channels behave more stochastically, which can improve the effectiveness of noise / error mitigation techniques. In some cases, the systems and techniques described here may systematically determine suitable twirling transformations; enhance the accuracy of gate fidelity measurements; improve error benchmarking consistency across different hardware platforms; facilitate calibration of two-qubit gates for high-fidelity quantum computation; or provide a combination of these and other advantages and improvements.

[0011] FIG. 1 is a block diagram of an example computing environment 100. The example computing environment 100 shown in FIG. 1 includes a computing system 101 and user devices 110A, 110B, 110C. A computing environment may include additional orAttorney Docket No.: RIGET-139WO1different features, and the components of a computing environment may operate as described with respect to FIG. 1 or in another manner.

[0012] The example computing system 101 includes classical and quantum computing resources and exposes their functionality to the user devices 110A, 110B, 110C (referred to collectively as "user devices 110”). The computing system 101 shown in FIG. 1 includes one or more servers 108, quantum computing systems 103A, 103B, a local network 109 and other resources 107. The computing system 101 may also include one or more user devices (e.g., the user device 110A) as well as other features and components. A computing system may include additional or different features, and the components of a computing system may operate as described with respect to FIG. 1 or in another manner.

[0013] The example computing system 101 can provide services to the user devices 110, for example, as a cloud-based or remote-accessed computer system, as a distributed computing resource, as a supercomputer or another type of high-performance computing resource, or in another manner. The computing system 101 or the user devices 110 may also have access to one or more other quantum computing systems (e.g., quantum computing resources that are accessible through the wide area network 115, the local network 109 or otherwise).

[0014] The user devices 110 shown in FIG. 1 may include one or more classical processor, memory, user interfaces, communication interfaces, and other components. For instance, the user devices 110 may be implemented as laptop computers, desktop computers, smartphones, tablets or other types of computer devices. In the example shown in FIG. 1, to access computing resources of the computing system 101, the user devices 110 send information (e.g., programs, instructions, commands, requests, input data, etc.) to the servers 108; and in response, the user devices 110 receive information (e.g., application data, output data, prompts, alerts, notifications, results, etc.) from the servers 108. The user devices 110 may access services of the computing system 101 in another manner, and the computing system 101 may expose computing resources in another manner.

[0015] In the example shown in FIG. 1, the local user device 110A operates in a local environment with the servers 108 and other elements of the computing system 101. ForAttorney Docket No.: RIGET-139WO1instance, the user device 110A may be co-located with (e.g., located within 0.5 to 1 km of) the servers 108 and possibly other elements of the computing system 101. As shown in FIG.1, the user device 110A communicates with the servers 108 through a local data connection.

[0016] The local data connection in FIG. 1 is provided by the local network 109. For example, some or all of the servers 108, the user device 110A, the quantum computing systems 103A, 103B and the other resources 107 may communicate with each other through the local network 109. In some implementations, the local network 109 operates as a communication channel that provides one or more low-latency communication pathways from the server 108 to the quantum computer systems 103A, 103B (or to one or more of the elements of the quantum computer systems 103A, 103B). The local network 109 can be implemented, for instance, as a wired or wireless Local Area Network, an Ethernet connection, or another type of wired or wireless connection. The local network 109 may include one or more wired or wireless routers, wireless access points (WAPs), wireless mesh nodes, switches, high-speed cables, or a combination of these and other types of local network hardware elements. In some cases, the local network 109 includes a software-defined network that provides communication among virtual resources, for example, among an array of virtual machines operating on the server 108 and possibly elsewhere.

[0017] In the example shown in FIG. 1, the remote user devices 110B, 110C operate remote from the servers 108 and other elements of the computing system 101. For instance, the user devices 110B, 110C may be located at a remote distance (e.g., more than 1 km, 10 km, 100 km, 1,000 km, 10,000 km, or farther) from the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, each of the user devices 110B, 110C communicates with the servers 108 through a remote data connection.

[0018] The remote data connection in FIG. 1 is provided by a wide area network 115, which may include, for example, the Internet or another type of wide area communication network. In some cases, remote user devices use another type of remote data connection (e.g., satellite-based connections, a cellular network, a virtual private network, etc.) to access the servers 108. The wide area network 115 may include one or more internetAttorney Docket No.: RIGET-139WO1servers, firewalls, service hubs, base stations, or a combination of these and other types of remote networking elements. Generally, the computing environment 100 can be accessible to any number of remote user devices.

[0019] The example servers 108 shown in FIG. 1 can manage interaction with the user devices 110 and utilization of the quantum and classical computing resources in the computing system 101. For example, based on information from the user devices 110, the servers 108 may delegate computational tasks to the quantum computing systems 103 A, 103B and the other resources 107; the servers 108 can then send information to the user devices 110 based on output data from the computational tasks performed by the quantum computing systems 103A, 103B and the other resources 107.

[0020] As shown in FIG. 1, the servers 108 are classical computing resources that include classical processors 111 and memory 112. The servers 108 may also include one or more communication interfaces that allow the servers to communicate via the local network 109, the wide area network 115 and possibly other channels. In some implementations, the servers 108 may include a host server, an application server, a virtual server or a combination of these and other types of servers. The servers 108 may include additional or different features and may operate as described with respect to FIG. 1 or in another manner.

[0021] The classical processors 111 can include various kinds of apparatus, devices, and machines for processing data, including, by way of example, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or combinations of these. The memory 112 can include, for example, a random-access memory (RAM), a storage device (e.g., a writable read-only memory (ROM) or others), a hard disk, or another type of storage medium. The memory 112 can include various forms of volatile or non-volatile memory, media and memory devices, etc.

[0022] Each of the example quantum computing systems 103A, 103B operates as a quantum computing resource in the computing system 101. The other resources 107 may include additional quantum computing resources (e.g., quantum computing systems,Attorney Docket No.: RIGET-139WO1quantum simulators, or both) as well as classical (non-quantum) computing resources such as, for example, digital microprocessors, specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), etc., or combinations of these and other types of computing modules.

[0023] In some implementations, the servers 108 generate programs, identify appropriate computing resources (e.g., a QPU or QVM) in the computing system 101 to execute the programs, and send the programs to the identified resources for execution. For example, the servers 108 may send programs to the quantum computing system 103 A, the quantum computing system 103B or any of the other resources 107. The programs may include classical programs, quantum programs, hybrid classical / quantum programs, and may include any type of function, code, data, instruction set, etc.

[0024] In some instances, programs can be formatted as source code that can be rendered in human-readable form (e.g., as text) and can be compiled, for example, by a compiler running on the servers 108, on the quantum computing systems 103, or elsewhere. In some instances, programs can be formatted as compiled code, such as, for example, binary code (e.g., machine-level instructions) that can be executed directly by a computing resource. Each program may include instructions corresponding to computational tasks that, when performed by an appropriate computing resource, generate output data based on input data. For example, a program can include instructions formatted for a quantum computer system, a simulator, a digital microprocessor, coprocessor or other classical data processing apparatus, or another type of computing resource.

[0025] In some cases, a program may be expressed in a hardware-independent format. For example, quantum machine instructions may be provided in a quantum instruction language such as Quil, described in the publication " A Practical Quantum Instruction Set Architecture,” arXiv:1608.03355v2, dated Feb. 17, 2017, or another quantum instruction language. For instance, the quantum machine instructions may be written in a format that can be executed by a broad range of quantum processing units or simulators. In someAttorney Docket No.: RIGET-139WO1cases, a program may be expressed in high-level terms of quantum logic gates or quantum algorithms, in lower-level terms of fundamental qubit rotations and controlled rotations, or in another form. In some cases, a program formatted for a target QPU includes a native quantum logic circuit that utilizes only native quantum logic gates of the target QPU, which are quantum logic gates that can be executed by the target QPU without further logical decomposition or transformation. For example, a program may be originally expressed in terms of native quantum logic gates of the target QPU, or a program originally expressed in a hardware-independent can be converted (e.g., compiled or transformed) to a native format. In some cases, a program may be expressed in terms of control signals (e.g., pulse sequences, delays, etc.) and parameters for the control signals (e.g., frequencies, phases, durations, channels, etc.). In some cases, a program may utilize Quil-T. In some cases, a program may be expressed in another form or format.

[0026] In some implementations, the servers 108 include one or more compilers that convert programs between formats. For example, the servers 108 may include a compiler that converts hardware-independent instructions to binary programs for execution by the quantum computing systems 103A, 103B. In some cases, a compiler can compile a program to a format that targets a specific quantum resource in the computer system 101. For example, a compiler may generate a different binary program (e.g., from the same source code) depending on whether the program is to be executed by the quantum computing system 103A or the quantum computing system 103B.

[0027] In some cases, a compiler generates a partial binary program that can be updated, for example, based on specific parameters. For instance, if a quantum program is to be executed iteratively on a quantum computing system with varying parameters on each iteration, the compiler may generate the binary program in a format that can be updated with specific parameter values at runtime (e.g., based on feedback from a prior iteration, or otherwise); the parametric update can be performed without further compilation. In some cases, a compiler generates a full binary program that does not need to be updated or otherwise modified for execution.

[0028] In some implementations, the servers 108 generate a schedule for executing programs, allocate computing resources in the computing system 101 according to theAttorney Docket No.: RIGET-139WO1schedule, and delegate the programs to the allocated computing resources. The servers 108 can receive, from each computing resource, output data from the execution of each program. Based on the output data, the servers 108 may generate additional programs that are then added to the schedule, output data that is provided back to a user device 110, or perform another type of action.

[0029] In some implementations, all or part of the computing environment operates as a cloud-based quantum computing (QC) environment, and the servers 108 operate as a host system for the cloud-based QC environment. The cloud-based QC environment may include software elements that operate on both the user devices 110 and the computer system 101 and interact with each other over the wide area network 115. For example, the cloud-based QC environment may provide a remote user interface, for example, through a browser or another type of application on the user devices 110. The remote user interface may include, for example, a graphical user interface or another type of user interface that obtains input provided by a user of the cloud-based QC environment. In some cases, the remote user interface includes, or has access to, one or more application programming interfaces (APIs), command line interfaces, graphical user interfaces, or other elements that expose the services of the computer system 101 to the user devices 110.

[0030] In some cases, the cloud-based QC environment may be deployed in a "serverless” computing architecture. For instance, the cloud-based QC environment may provide on-demand access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, services, quantum computing resources, classical computing resources, etc.) that can be provisioned for requests from user devices 110. Moreover, the cloud-based computing systems 101 may include or utilize other types of computing resources, such as, for example, edge computing, fog computing, etc.

[0031] In an example implementation of a cloud-based QC environment, the servers 108 may operate as a cloud provider that dynamically manages the allocation and provisioning of physical computing resources (e.g., GPUs, CPUs, QPUs, etc.). Accordingly, the servers 108 may provide services by defining virtualized resources for each user account. For instance, the virtualized resources may be formatted as virtual machine images, virtual machines, containers, or virtualized resources that can be provisioned for a user account andAttorney Docket No.: RIGET-139WO1configured by a user. In some cases, the servers 108 include a container management and execution system that is implemented, for example, using KUBERNETES ® or another software platform for container management. In some cases, the cloud-based QC environment is implemented, for example, using OPENSTACK ® or another software platform for cloud-based computing that provides virtual servers or other virtual computing resources for users.

[0032] In some cases, the server 108 stores quantum machine images (QMI) for each user account. A quantum machine image may operate as a virtual computing resource for users of the cloud-based QC environment. For example, a QMI can provide a virtualized development and execution environment to develop and run programs (e.g., quantum programs or hybrid classical / quantum programs). When a QMI operates on the server 108, the QMI may engage either of the quantum processor units 102A, 102B, and interact with a remote user device (110B or 110C) to provide a user programming environment. The QMI may operate in close physical proximity to and have a low-latency communication link with the quantum computing systems 103 A, 103 B. In some implementations, remote user devices connect with QMIs operating on the servers 108 through secure shell (SSH) or other protocols over the wide area network 115.

[0033] In some implementations, all or part of the computing system 101 operates as a hybrid computing environment. For example, quantum programs can be formatted as hybrid classical / quantum programs that include instructions for execution by one or more quantum computing resources and instructions for execution by one or more classical resources. The servers 108 can allocate quantum and classical computing resources in the hybrid computing environment, and delegate programs to the allocated computing resources for execution. The quantum computing resources in the hybrid environment may include, for example, one or more quantum processing units (QPUs), one or more quantum simulators, or possibly other types of quantum resources. The classical computing resources in the hybrid environment may include, for example, one or more digital microprocessors, one or more specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., fieldAttorney Docket No.: RIGET-139WO1programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), or other types of computing modules.

[0034] In some cases, the servers 108 can select the type of computing resource (e.g., quantum or classical) to execute an individual program, or part of a program, in the computing system 101. For example, the servers 108 may select a particular quantum processing unit (QPU) or other computing resource based on availability of the resource, speed of the resource, information or state capacity of the resource, a performance metric (e.g., process fidelity) of the resource, or based on a combination of these and other factors. In some cases, the servers 108 can perform load balancing, resource testing and calibration, and other types of operations to improve or optimize computing performance.

[0035] Each of the example quantum computing systems 103A, 103B shown in FIG. 1 can perform quantum computational tasks by executing quantum machine instructions (e.g., a binary program compiled for the quantum computing system). In some implementations, a quantum computing system can perform quantum computation by storing and manipulating information within quantum states of a composite quantum system. For example, qubits (i.e., quantum bits) can be stored in and represented by an effective two-level sub-manifold of a quantum coherent physical system. In some instances, quantum logic can be executed in a manner that allows large-scale entanglement within the quantum system. Control signals can manipulate the quantum states of individual qubits and the joint states of multiple qubits. In some instances, information can be read out from the composite quantum system by measuring the quantum states of the qubits. In some implementations, the quantum states of the qubits are read out by measuring the transmitted or reflected signal from auxiliary quantum devices that are coupled to individual qubits.

[0036] In some implementations, a quantum computing system can operate using gatebased models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g.,Attorney Docket No.: RIGET-139WO1entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation.

[0037] In some models, fault-tolerance can be achieved by applying a set of high-fidelity control and measurement operations to the qubits. For example, quantum error correcting schemes can be deployed to achieve fault-tolerant quantum computation. Other computational regimes may be used; for example, quantum computing systems may operate in non-fault-tolerant regimes. In some implementations, a quantum computing system is constructed and operated according to a scalable quantum computing architecture. For example, in some cases, the architecture can be scaled to a large number of qubits to achieve large-scale general purpose coherent quantum computing. Other architectures may be used; for example, quantum computing systems may operate in small-scale or non-scalable architectures.

[0038] The example quantum computing system 103A shown in FIG. 1 includes a quantum processing unit 102A and a control system 105A, which controls the operation of the quantum processing unit 102A. Similarly, the example quantum computing system 103B includes a quantum processing unit 102B and a control system 105B, which controls the operation of a quantum processing unit 102B. A quantum computing system may include additional or different features, and the components of a quantum computing system may operate as described with respect to FIG. 1 or in another manner.

[0039] In some instances, all or part of the quantum processing unit 102A functions as a quantum processor, a quantum memory, or another type of subsystem. In some examples, the quantum processing unit 102A includes a quantum circuit system. The quantum circuit system may include qubit devices, readout devices and possibly other devices that are used to store and process quantum information. In some cases, the quantum processing unit 102A includes a superconducting circuit, and the qubit devices are implemented as circuit devices that include Josephson junctions, for example, in superconducting quantumAttorney Docket No.: RIGET-139WO1interference device (SQUID) loops or other arrangements, and are controlled by radiofrequency signals, microwave signals, and bias signals delivered to the quantum processing unit 102A. In some cases, the quantum processing unit 102A includes an ion trap system, and the qubit devices are implemented as trapped ions controlled by optical signals delivered to the quantum processing unit 102A. In some cases, the quantum processing unit 102A includes a spin system, and the qubit devices are implemented as nuclear or electron spins controlled by microwave or radio-frequency signals delivered to the quantum processing unit 102A. The quantum processing unit 102A may be implemented based on another physical modality of quantum computing.

[0040] The quantum processing unit 102A may include, or may be deployed within, a controlled environment. The controlled environment can be provided, for example, by shielding equipment, cryogenic equipment, and other types of environmental control systems. In some examples, the components in the quantum processing unit 102A operate in a cryogenic temperature regime and are subject to very low electromagnetic and thermal noise. For example, magnetic shielding can be used to shield the system components from stray magnetic fields, optical shielding can be used to shield the system components from optical noise, thermal shielding and cryogenic equipment can be used to maintain the system components at controlled temperature, etc.

[0041] In some implementations, the example quantum processing unit 102A can process quantum information by applying control signals to the qubits in the quantum processing unit 102A. The control signals can be configured to encode information in the qubits, to process the information by performing quantum logic gates or other types of operations, or to extract information from the qubits. In some examples, the operations can be expressed as single-qubit quantum logic gates, two-qubit quantum logic gates, or other types of quantum logic gates that operate on one or more qubits. A quantum logic circuit, which includes a sequence of quantum logic operations, can be applied to the qubits to perform a quantum algorithm. The quantum algorithm may correspond to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.Attorney Docket No.: RIGET-139WO1

[0042] The example control system 105A includes controllers 106A and signal hardware 104A. Similarly, control system 105B includes controllers 106B and signal hardware 104B. All or part of the control systems 105A, 105B can operate in a roomtemperature environment or another type of environment, which may be located near the respective quantum processing units 102A, 102B. In some cases, the control systems 105A, 105B include classical computers, signaling equipment (microwave, radio, optical, bias, etc.), electronic systems, vacuum control systems, refrigerant control systems or other types of control systems that support operation of the quantum processing units 102A, 102B.

[0043] The control systems 105A, 105B maybe implemented as distinct systems that operate independent of each other. In some cases, the control systems 105A, 105B may include one or more shared elements; for example, the control systems 105A, 105B may operate as a single control system that operates both quantum processing units 102A, 102B. Moreover, a single quantum computer system may include multiple quantum processing units, which may operate in the same controlled (e.g., cryogenic) environment or in separate environments.

[0044] The example signal hardware 104A includes components that communicate with the quantum processing unit 102A. The signal hardware 104A may include, for example, waveform generators, amplifiers, digitizers, high-frequency sources, DC sources, AC sources, etc. The signal hardware may include additional or different features and components. In the example shown, components of the signal hardware 104A are adapted to interact with the quantum processing unit 102A. For example, the signal hardware 104A can be configured to operate in a particular frequency range, configured to generate and process signals in a particular format, or the hardware may be adapted in another manner.

[0045] In some instances, one or more components of the signal hardware 104A generate control signals, for example, based on control information from the controllers 106A. The control signals can be delivered to the quantum processing unit 102A during operation of the quantum computing system 103A. For instance, the signal hardware 104A may generate signals to implement quantum logic operations, readout operations or other types of operations. As an example, the signal hardware 104A may include arbitraryAttorney Docket No.: RIGET-139WO1waveform generators (AWGs) that generate electromagnetic waveforms (e.g., microwave or radio-frequency) or laser systems that generate optical waveforms. The waveforms or other types of signals generated by the signal hardware 104A can be delivered to devices in the quantum processing unit 102A to operate qubit devices, readout devices, bias devices, coupler devices or other types of components in the quantum processing unit 102A.

[0046] In some instances, the signal hardware 104A receives and processes signals from the quantum processing unit 102A. The received signals can be generated by the execution of a quantum program on the quantum computing system 103A. For instance, the signal hardware 104A may receive signals from the devices in the quantum processing unit 102A in response to readout or other operations performed by the quantum processing unit 102A. Signals received from the quantum processing unit 102A can be mixed, digitized, filtered, or otherwise processed by the signal hardware 104A to extract information, and the information extracted can be provided to the controllers 106A or handled in another manner. In some examples, the signal hardware 104A may include a digitizer that digitizes electromagnetic waveforms (e.g., microwave or radio-frequency) or optical signals, and a digitized waveform can be delivered to the controllers 106A or to other signal hardware components. In some instances, the controllers 106A process the information from the signal hardware 104A and provide feedback to the signal hardware 104A; based on the feedback, the signal hardware 104A can in turn generate new control signals that are delivered to the quantum processing unit 102A.

[0047] In some implementations, the signal hardware 104A includes signal delivery hardware that interfaces with the quantum processing unit 102 A. For example, the signal hardware 104A may include filters, attenuators, directional couplers, multiplexers, diplexers, bias components, signal channels, isolators, amplifiers, power dividers and other types of components. In some instances, the signal delivery hardware performs preprocessing, signal conditioning, or other operations to the control signals to be delivered to the quantum processing unit 102A. In some instances, signal delivery hardware performs preprocessing, signal conditioning or other operations on readout signals received from the quantum processing unit 102A.Attorney Docket No.: RIGET-139WO1

[0048] The example controllers 106A communicate with the signal hardware 104A to control operation of the quantum computing system 103A. The controllers 106A may include classical computing hardware that directly interfaces with components of the signal hardware 104A. The example controllers 106A may include classical processors, memory, clocks, digital circuitry, analog circuitry, and other types of systems or subsystems. The classical processors may include one or more single- or multi-core microprocessors, digital electronic controllers, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), or other types of data processing apparatus. The memory may include any type of volatile or non-volatile memory or another type of computer storage medium. The controllers 106A may also include one or more communication interfaces that allow the controllers 106A to communicate via the local network 109 and possibly other channels. The controllers 106A may include additional or different features and components.

[0049] In some implementations, the controllers 106A include memory or other components that store quantum state information, for example, based on qubit readout operations performed by the quantum computing system 103A. For instance, the states of one or more qubits in the quantum processing unit 102A can be measured by qubit readout operations, and the measured state information can be stored in a cache or other type of memory system in or more of the controllers 106A. In some cases, the measured state information is subsequently used in the execution of a quantum program, a quantum error correction procedure, a quantum processing unit (QPU) calibration or testing procedure, or another type of quantum process.

[0050] In some implementations, the controllers 106A include memory or other components that store a quantum program containing quantum machine instructions for execution by the quantum computing system 103A. In some instances, the controllers 106A can interpret the quantum machine instructions and perform hardware-specific control operations according to the quantum machine instructions. For example, the controllers 106A may cause the signal hardware 104A to generate control signals that are delivered to the quantum processing unit 102A to execute the quantum machine instructions.Attorney Docket No.: RIGET-139WO1

[0051] In some instances, the controllers 106A extract qubit state information from qubit readout signals, for example, to identify the quantum states of qubits in the quantum processing unit 102A or for other purposes. For example, the controllers may receive the qubit readout signals (e.g., in the form of analog waveforms) from the signal hardware 104A, digitize the qubit readout signals, and extract qubit state information from the digitized signals. In some cases, the controllers 106A compute measurement statistics based on qubit state information from multiple shots of a quantum program. For example, each shot may produce a bitstring representing qubit state measurements for a single execution of the quantum program, and a collection of bitstrings from multiple shots may be analyzed to compute quantum state probabilities.

[0052] In some implementations, the controllers 106A include one or more clocks that control the timing of operations. For example, operations performed by the controllers 106A may be scheduled for execution over a series of clock cycles, and clock signals from one or more clocks can be used to control the relative timing of each operation or groups of operations. In some implementations, the controllers 106A may include classical computer resources that perform some or all of the operations of the servers 108 described above. For example, the controllers 106A may operate a compiler to generate binary programs (e.g., full or partial binary programs) from source code; the controllers 106A may include an optimizer that performs classical computational tasks of a hybrid classical / quantum program; the controllers 106A may update binary programs (e.g., at runtime) to include new parameters based on an output of the optimizer, etc.

[0053] The other quantum computer system 103 B and its components (e.g., the quantum processing unit 102B, the signal hardware 104B and controllers 106B) can be implemented as described above with respect to the quantum computer system 103A; in some cases, the quantum computer system 103B and its components maybe implemented or may operate in another manner.

[0054] In some implementations, the quantum computer systems 103A, 103B are disparate systems that provide distinct modalities of quantum computation. For example, the computer system 101 may include both an adiabatic quantum computer system and a gate-based quantum computer system. As another example, the computer system 101 mayAttorney Docket No.: RIGET-139WO1include a superconducting circuit-based quantum computer system and an ion trap-based quantum computer system. In such cases, the computer system 101 may utilize each quantum computing system according to the type of quantum program that is being executed, according to availability or capacity, or based on other considerations.

[0055] FIG. 2 is a flow chart showing aspects of an example computing process 200. The example process 200 can be used to generate an updated quantum logic circuit based on a quantum logic circuit including an FSIM gate. In some instances, the computing process 200 may be performed by a classical computer system (e.g., by the servers 108 or the user devices 110 in FIG. 1), by a control system of a quantum computing system (e.g., the control system 105 in FIG. 1), or by a combination of these and other computer systems. The quantum logic circuit may be executed by operation of a quantum processing unit (e.g., the quantum processing units 102 in FIG. 1), by a quantum simulator, or another quantum resource. The example process 200 may include additional or different operations, and the operations may be performed in the order shown or in another order. In some cases, operations in the example process 200 can be combined, iterated, or otherwise repeated or performed in another manner.

[0056] In some implementations, one or more operations in the example process 200 can be performed by a computer system, for instance, by a digital computer system having one or more digital processors (e.g., a microprocessor or other data processing apparatus) that execute instructions (e.g., instructions stored in a digital memory or other computer-readable medium), or by another type of digital, quantum or hybrid computer system. As an example, in some cases the quantum processing unit can be deployed as the quantum processing unit 102 shown in FIG. 1, and operations in the example process 200 shown in FIG. 2 can be initiated, executed, or controlled by one or more components of the control system 105 shown in FIG. 1.

[0057] At 202, a quantum logic circuit is identified. The quantum logic circuit may be expressed in any form or format specified, for example, by a user device, by a control system, by a target QPU or otherwise. In some embodiments, when a quantum logic circuit is identified for execution on a quantum processing unit (QPU), the quantum logic circuit may be specified directly using a native gate set supported by the QPU. For example, a userAttorney Docket No.: RIGET-139WO1or design tool may construct the quantum logic circuit as an ordered sequence of native quantum operations (e.g., single-qubit rotations and two-qubit entangling gates defined according to the hardware), each operation being associated with one or more qubit identifiers corresponding to physical qubits on the QPU. The native quantum logic circuit may further specify measurement operations, classical control operations conditioned on prior measurement results, and explicit barriers or synchronization markers, such that the entire computation is expressed in terms of operations that are directly executable on the target QPU without further logical-to-native decomposition.

[0058] In some instances, the quantum logic circuit can be obtained by compiling a quantum program expressed at a higher level of abstraction into a native quantum logic circuit for the target QPU. For example, a user or design tool may construct the quantum program in a hardware-agnostic format that does not necessarily utilize native quantum operations of the target QPU. The quantum program represented in a hardware-agnostic intermediate form can be translated, for example, into a logical circuit over a standard gate set and then transformed into a native quantum logic circuit that conforms to the QPU’s native gate set, qubit connectivity, and timing constraints. The resulting native quantum logic circuit may include, for each operation, a gate type selected from the native gate set, a mapping of logical qubits to physical qubits, and associated scheduling information (e.g., relative ordering or timing slots), as well as measurement primitives and optional errormitigation or calibration directives. In this manner, both directly specified hardware-native descriptions and compiled high-level quantum programs yield a native quantum logic circuit suitable for subsequent execution on the quantum processing unit.

[0059] In some implementations, the quantum program is obtained by performing a compilation operation on a received quantum program from a user (e.g., a user program from a user device 110 in FIG. 1). A sequence of quantum logic gates in the quantum program before compilation can be converted to a sequence of native quantum logic gates in the quantum program after compilation. In some instances, the sequence of native quantum logic gates can be applied on qubits defined by qubit devices in the quantum processing unit. In some implementations, a quantum program can be represented, for example, as a quantum Hamiltonian, a sequence of quantum logic gates, a set of quantumAttorney Docket No.: RIGET-139WO1machine instructions, or otherwise. The quantum program may correspond to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations. In some instances, a quantum program includes a sequence of quantum logic gates, e.g., single-qubit quantum logic gates, two-qubit quantum logic gates, multi-qubit quantum logic gates, identity gates, and other quantum logic gates. In some instances, the quantum program can be an Quil program generated by a user device (e.g., the user device 110 as shown in FIG. 1), another computer resource outside the local environment of the quantum computer system 103, or in another manner; and received by a quantum computing system (e.g., the control system 105 of the quantum computing system 103 in FIG. 1).

[0060] In some implementations, the native quantum logic circuit includes at least one two-qubit quantum logic gate defined by a set of N continuous parameters 6, where i=1, 2,..., N. Each of the at least one two-qubit quantum logic gates is a native quantum logic gate that is applied on a respective pair of qubits defined by a pair of physical qubit devices in a quantum processing unit and can be natively performed. In some instances, when there are multiple two-qubit quantum logic gates, the two-qubit quantum logic gates may be the same two-qubit quantum logic gate applied on the same or different pair of qubits, or they may be distinct two-qubit quantum logic gates applied on the same or different pair of qubits. Each distinct two-qubit quantum logic gate in the quantum logic circuit may be defined by a respective set of continuous parameters. In some examples, the at least one two-qubit quantum logic gate includes one or more FSIM (fermionic simulation) gates. In some instances, the at least one two-qubit quantum logic gate may include other types of arbitrary two-qubit quantum logic gates.

[0061] In some instances, the quantum logic circuit includes an FSIM gate which can be viewed as a two-qubit unitary operation parameterized by multiple continuous gate parameters. In some implementations, the gate parameters of the FSIM gate refer to one or more real-valued parameters that define the entangling strength and conditional-phase behavior of the two-qubit interaction up to local single-qubit rotations. In some implementations, an FSIM gate corresponds to the unitary operator:Attorney Docket No.: RIGET-139WO1FSIM(θ,φ) = exp(i θ / 4(XX + YY) + i φ / 4(1-Z)(1-Z)) \ 4 4 1 0 0 0 \ 0 cos0 / 2 isin0 / 2 0 Cl) 0 isin0 / 2 cos0 / 2 0 0 0 0,FSIM gates according to Equation (1) above are characterized by two gate parameters, e.g., a swap-like mixing angle 0 and a conditional phase angle. The mixing angle 0 determines the amplitude and phase of population exchange between the 101) and 110 ) basis states (i.e., a partial iSWAP-type interaction), while the conditional phase angle 0 determines the relative conditional phase accumulated on one or more computational basis states (for example, a phase applied to 111)). In some cases, FSIM gates maybe expressed in another form or another structure. For example, FSIM gates may be represented with logical equivalence as a combination of multiple quantum logic gates, parameterized by additional or different gate parameters, etc.

[0062] In some instances, the values of the gate parameters of the two-qubit quantum logic gate may be determined by a calibration procedure performed on a given pair of physical qubits of the quantum processing unit. In some embodiments, the control system applies a family of trial control pulses (e.g., with different pulse durations, amplitudes, and / or detunings) implementing candidate two-qubit interactions and measures resulting output states for a set of known input states. The measurement data may be processed to reconstruct, at least approximately, the effective two-qubit unitary implemented by each candidate pulse configuration, for example by fitting the measured transition probabilities and phases to a parametric model of the FSIM gate. From this reconstruction, the control system identifies calibrated values of the gate parameters (e.g., a calibrated mixing angle 0* and a calibrated conditional phase 0*) that achieve a desired target operation (for instance, a particular entangling strength or an approximation to a controlled-Z or iSWAP gate up to single-qubit rotations). These calibrated gate parameter values, and optionally associated low-level control parameters such as pulse amplitudes, frequencies, phases, and durations, may be stored in a calibration data structure indexed by gate type and qubit pair.Attorney Docket No.: RIGET-139WO1Thereafter, when a native quantum logic circuit specifies a two-qubit quantum logic gate (e.g., an FSIM gate or another two-qubit quantum logic gate) on the calibrated qubit pair, the control system can directly identify and apply the stored gate parameters and corresponding control parameters, enabling repeatable realization of the desired entangling operation without re-deriving the gate parameters for each gate instance.

[0063] At 204, multiple sets of twirling operations for a two-qubit quantum logic gate in the quantum logic circuit are identified. Each set of twirling operations may include a set of random local unitaries (often single-qubit quantum logic gates) applied before and after the two -qubit quantum logic gate for arbitrary but known values of the gate parameters. In some implementations, each set of twirling operations includes two pairs of single-qubit quantum logic gates. In some instances, a set of twirling operations includes a first pair of single-qubit quantum logic gates that when applied before the two-qubit quantum logic gate can be "undone” afterwards by a second pair of single-qubit quantum logic gates, e.g., the overall logical operation applied to the pair of qubits is not affected by the inclusion of the set of twirling operations. In other words, each set of possible twirling operations do not change the intended computation defined by the respective two-qubit quantum logic gate. In some implementations, the first and second pairs of single-qubit quantum logic gates in a set of twirling operations can be functions of the gate parameter(s), which requires a pre-characterization of the gate parameter(s) of the two-qubit quantum logic gate. When the quantum logic circuit includes multiple distinct two-qubit quantum logic gates, multiple sets of twirling operations can be identified.

[0064] In some implementations, when a set of twirling operations are applied before and after an FSIM gate, the set of twirling operations can transform its noise channel into for example a stochastic Pauli noise channel. Each set of twirling operations includes a first pair of single-qubit quantum logic gates applied on a pair of qubits, and a second pair of single-qubit quantum logic gates applied on the same pair of qubits. These operations themselves can be separable into a pair of single-qubit quantum logic gates, one to be applied to each qubit. The single-qubit quantum logic gates in the set of twirling operations for the FSIM gate are local twirling gates. The first pair of twirling operations are performed before the FSIM gate, and the second pair of twirling operations are performedAttorney Docket No.: RIGET-139WO1after the FSIM gate. The second pair of twirling operations applied after the FSIM gate is configured to undo the effect introduced by the first pair of twirling operations, thereby making the net effect of the entire process simply the original FSIM gate. In some instances, the single-qubit quantum logic gates thus the twirling operations may be non-parametric or parametric. Each single-qubit parametric quantum logic gate of a twirling operation can be parameterized by one or more of the gate parameters of the FSIM gate. In other words, a single-qubit parametric quantum logic gate of a twirling operation can be determined based on specific values of the gate parameters of the FSIM gate, e.g., the mixing angle θ and the conditional phase angle φ.

[0065] As shown in FIG. 3, twirling operations (e.g., local twirling gates) for the FSIM gate applied on a pair of qubits (Q1 and Q2) are solutions to the equationFSIM(θ,φ) = (u1 ⊗ u2) · FSIM(θ,φ) · (u3 ⊗ u4) (2) wherein u1 represents a first single-qubit quantum logic operation applied to a first qubit (Q1), u2 represents a second single-qubit quantum logic operation applied to a second qubit (Q2), u3 represents a third single-qubit quantum logic operation applied to the first qubit (Q1), and u4 represents a fourth single-qubit quantum logic operation applied to the second qubit (Q2), u1 and u2 are applied to the pair of qubits (Q1 and Q2) before the FSIM gate, and u3 and u4 are applied to the pair of qubits after the FSIM gate. In some instances, the sets of twirling operations include solutions that commute with the FSIM gate, e.g., ul (g) u2 = (u3 (g) u4).

[0066] In some instances, an FSIM gate can be considered to be formed from four commuting parts. Explicitly,FSIM(θ,φ) = exp(iφ / 4·II) · exp(iφ / 4·ZZ) · exp(−iφ / 4(IZ + ZI)) · exp(iθ / 4(XX4 4 4 4 (0]+ YY))

[0067] There is a basis therefore in which the four components (II, IZ + ZI, ZZ, XX + YY) are simultaneously diagonalized. The first three components (II, IZ + ZI, ZZ) are diagonal in the computational basis, and also degenerate in the subspace spanned by |01⟩ and |10⟩. The last component (XX + YY) is degenerate in the subspace spanned by |00⟩ andAttorney Docket No.: RIGET-139WO1|11⟩ (with eigenvalue 0, in fact) and has eigenvectors |01⟩ + |10⟩ and |01⟩ − |10⟩ up to a normalization factor. The basis in which these operators are simulatenously diagonalized is therefore uniquely specified as |00⟩, |11⟩, |01⟩ + |10⟩ and |01⟩ − |10⟩. A local operation that can also be diagonalized in this basis can trivially solve the twirling equation as its inverse will also be a local operation.

[0068] Without loss of any generality, a local twirling operation on one qubit has two orthogonal eigenvectors |ψ₊⟩, |ψ₋⟩ with eigenvalues ψ₊, ψ₋. It follows that an operator formed of the kronecker product of two local operations has the formu1 ⊗ u2 = ψ₊φ₊|ψ₊⟩ ⊗ |φ₊⟩⟨φ₊| ⊗ ⟨φ₊| + ψ₋φ₊|ψ₋⟩ ⊗ |φ₊⟩⟨φ₋| ⊗ ⟨φ₊|+ ··· + ψ₊φ₋|ψ₊⟩ ⊗ |φ₋⟩⟨φ₊| ⊗ ⟨φ₋| + ψ₋φ₋|ψ₋⟩ ⊗ |φ₋⟩⟨φ₋| ⊗ ⟨φ₋|where the label ψ has been exchanged for φ on the eigenvectors and values of the second qubit operator.

[0069] It is clear that for such a form to share the basis of and therefore commute with the FSIM gate, it is required that |ψ₊⟩ ⊗ |φ₊⟩ is equal |00⟩. It is noted that 111) is also possible but yields an equivalent solution. This operator can then also be degenerate in the 101), 110) subspace to allow for the eigenvectors of XX+YY to be accommodated, requiring additionally that ψ₊φ₋ = ψ₋φ₊ or rather that ψ₊ / ψ₋ = φ₋ / φ₊.

[0070] As the operator is unitary, and ignoring any global phase, it is therefore clear that the only operator formed of two local single-qubit operators that commutes with the FSIM gate is the simultaneous rotation around Z of both qubits by the same angle.Explicitly, this gives a family of solutions to the original equation ofFSIM(0, 0) = (ul (g) u2) • FSIM(0, 0) • (u3 (g) u4)(X C t= exp(-i-Z) (g) exp(-i-Z) • FSIM(0, 0) • exp(+i-Z)a⊗ exp(+i α / 2 Z)for any value of a.Attorney Docket No.: RIGET-139WO1

[0071] In some implementations, the multiple sets of twirling operations may include sets of twirling operations that do not commute with the FSIM gate. To investigate other potential solutions, operators that commute with the non-local ZZ and XX + YY parts of the Hamiltonian can be considered. To first give a justification as to why this is useful, consider the result of pre-multiplying the equation (2) by FSIM(θ,φ)† (which is trivially equiavalent to FSIM(−θ,−φ) via inspection of the original definition). This yieldsI ⊗ I = (u1 ⊗ u2) · FSIM(θ,φ) · (u3 ⊗ u4) · FSIM(−θ,−φ). (6)

[0072] Inserting the commuting product form of the FSIM gate, one can getI ⊗ I = (u1 ⊗ u2) · exp(iφ / 4·II) · exp(iφ / 4·ZZ) · exp(−iφ / 4·(IZ + ZI))4 4 4 · exp(iθ / 4(XX + YY)) · (u3 ⊗ u4) · exp(−iφ / 4·II) · exp(−iφ / 4·ZZ) · exp(iφ / 4(IZ + ZI)) · exp(−iθ / 4(XX + YY))4 4

[0073] It is then clear that for any choice of u3, u4 that satisfies the constraint of commutation with XX + YY and ZZ, one can getI ⊗ I = (u1 ⊗ u2) · exp(iφ / 4·II) · exp(−iφ / 4·II) · exp(iφ / 4·ZZ) · exp(−iφ / 4·ZZ)4 4 4 4 • exp(— i — 0 9(IZ + ZI)) •• exp(i — (XX + FF)) • exp(— i — 0 (XX (8) 4 4 4 + FF)) • (u3 (g) u4) • exp(iy 0 (IZ + ZI))4 which then heavily simplifies toI ⊗ I = (u1 ⊗ u2) · exp(−i φ / 4(IZ + ZI)) · (u3 ⊗ u4) · exp(i φ / 4(IZ + ZI))9)4 4

[0074] This can be solved to find that(u1 ⊗ u2) = exp(−iφ / 4(IZ + ZI)) · (u3 ⊗ u4)† · exp(iφ / 4(IZ + ZI)). (10)4 4

[0075] It is left as self evident that if u3 and u4 are local then their inverse is local, and their combination with the other local operations here is also local too. Note that theAttorney Docket No.: RIGET-139WO1relationship between ul, u2 and u3, u4 here is dependent on <>; such solutions can only twirl the FSIM(θ,φ) gate for a specific known φ.

[0076] The question now becomes which values can u3 (g) u4 take which commute with the non-local operators XX + YY and ZZ. It can be shown that only linear combinations of the following two-qubit Pauli operations can commute with XX + YY, includingII, ZI + IZ, XY + YX, XX, YY, ZZ. (11)

[0077] Similarly, only linear combinations of the following can commute with ZZ;II, ZI, IZ, XX, XY, YX, YY, ZZ (12)

[0078] It is trivial to show then that for (u3 (g) u4) to commute with both operators XX + YY and ZZ, u3 (g) u4 may have a formu3 (g) u4 = a₀II + a₁(ZI + IZ) + a2(XY + YX) + a3XX + a4YY + a₅ZZ (13) for some complex values aᵢ.

[0079] For u3, u4 to be separable single-qubit operators (single-qubit quantum logic gates applied to two distinct qubits), they have the formu3 ⊗ u4 = exp(iα₁ / 2 · n⃗₁ · σ⃗) ⊗ exp(iα₂ / 2 · n⃗₂ · σ⃗)= cos(α₁ / 2)cos(α₂ / 2) · I ⊗ I + isin(α₁ / 2)cos(α₂ / 2) · (n⃗₁· σ⃗) ⊗ I + ··· + isin(α₂ / 2)cos(α₁ / 2) · I ⊗ (n⃗₂ · σ⃗)—sin(α₁ / 2)sin(α₂ / 2) · (n⃗₁ · σ⃗) ⊗ (n⃗₂ · σ⃗)

[0080] Inspection of this makes clear that for arbitrary rotation angles αᵢ the only solution that can only introduce a ZI + IZ term without introducing any IX, IY, XI, YI as required by the above is the choice n⃗₁ = n⃗₂ = (0,0,1). Moreover in this case one can choose that α₁ = α₂, and so the original solution can be recovered when considering terms that fully commute with the FSIM gate.

[0081] The only other solutions require that sin(α₁ / 2)cos(α₂ / 2) = sin(α₂ / 2)cos(α₁ / 2) = 0. This means that either sin(αᵢ / 2) are both zero or cos(αᵢ / 2) are both 0. The former yields that both α₁ and α₂ are integer multiples of 2π which is uninteresting. The latter yields only one distinct interesting solution that α₁ = α₂ = π.Attorney Docket No.: RIGET-139WO1

[0082] With this knowledge of a, it can be simplified thatu3 ⊗ u4 = −(n⃗₁ · σ⃗) ⊗ (n⃗₂ · σ⃗). (15)

[0083] It is straightforward to see by comparison with the above form that the only solutions for ntwhich do not have both z-components equal to 0 is the trivial solution u3 ® u4 = ZZ, which is a part of the continuous solution found earlier.

[0084] Otherwise, the simultaneous equations to be solved includen²₁ₓ + n²₁ᵧ = 1n²₂ₓ + n²₂ᵧ = 1 (16)nlXn2Y= nlYn2X

[0085] Substituting n⃗ᵢ = (cosγᵢ, sinγᵢ, 0), it can be found that γ₁ = γ₂ + mπ for some integer m. It can be found that the new interesting solutions to u3, u4 that satisfy the commutation requirement have the formu3 ⊗ u4 = −(cosγ · X + sinγ · Y) ⊗ (cos(γ + mπ) · X + sin(γ + mπ) · Y) (17)

[0086] Noting that the value of m is unimportant as it changes the operator only up to a global phase, m can be set to 0, e.g., m = 0, to findu3 ⊗ u4 = (cosγ · X + sinγ · Y) ⊗ (cosγ · X + sinγ · Y) (18)

[0087] This is simply a flip of both qubits around the same axis in their respective XY planes. Substituting this back into the original equation, one can find(u1 ⊗ u2) = exp(−iφ / 4(IZ + ZI)) · (u3 ⊗ u4)† · exp(iφ / 4(IZ + ZI))4 \ 4 ) = exp(−iφ / 4(IZ + ZI)) · (cosγ · X + sinγ · Y) \ 4 / ⊗ (cosγ · X + sinγ · Y) · exp(iφ / 4(IZ + ZI))\ 4 )= (cos(y + 0 / 2) • X + sin(y + 0 / 2) • Y) ® (cos(y + 0 / 2)• X + sin(y + 0 / 2) • Y)Attorney Docket No.: RIGET-139WO1

[0088] This completes a new solution family to the sets of twirling operations of the FSIM(θ,φ) gate. It is worth noting that this solution can be stated more simply with y = 0 if it is then combined with the other general continuous solution via multiplication. As shown in Equation 18-19, u1 and u2 represent operations determined by the conditional phase angle of the FSIM gate, while u3 and u4 are operations that are independent of the gate parameters of the FSIM gate. All the four operations u1, u2, u3 and u4 are parametric single-qubit quantum logic gates, where u1 and u2 are parameterized by (γ,φ) and u3 and u4 are parameterized by γ.

[0089] In some implementations, the sets of twirling operations for the FSIM gate (the pair of twirling operations applied after the FSIM gate) include a subset of Pauli operations including II, XX, YY, ZZ. Twirling over such a group is equivalent to twirling over the group (II, ZZ) followed by (II, XX); this is because all elements in the original can be generated from the latter two. In some instances, the selection of only Pauli operations as the sets of twirling operations can provide advantages, not least in the simplicity of the derivation. If the full set of Pauli operations can be twirled with, then the noise channel is reduced to a stochastic Pauli error channel. In some instances, by limiting the twirling operations of the FSIM(θ,φ) gate to those that commuted with the XX, YY and ZZ coherent rotations in the unitary, coherent errors in these subspaces may not be expected to be mapped to stochastic Pauli errors, but others still can be.

[0090] In some examples, an FSIM gate can be defined byFSIM(θ,φ) = v · FSIM(θ,φ) · w (20)

[0091] In some implementations, the sets of twirling operations for (v, w) to the FSIM gate include a first set including two pairs of identity gates, (I® I, I® I) with a pair of identity gates applied before the FSIM gate and a pair of identity gates applied after the FSIM gate; a second set including two pairs of Pauli Z gates (Z® Z, Z® Z) with a pair of Pauli Z gates applied before the FSIM gate and a pair of Pauli Z gates applied after the FSIM gate; a third set including a pair of Pauli X gates (X⊗X) applied before the FSIM gate and a pair of gates of the form ((cos(φ / 2) · X − sin(φ / 2) · Y) ⊗ (cos(φ / 2) · X − sin(φ / 2) · Y)) applied after the FSIM gate; and a fourth set including a pair of Pauli Y gates (Y⊗Y) applied beforeAttorney Docket No.: RIGET-139WO1the FSIM gate and a pair of gates of the form ((cos(φ / 2) · Y + sin(φ / 2) · X) ⊗ (cos(φ / 2) · Y + sin(φ / 2) · X)) applied after the FSIM gate. In summary, the sets of twirling operations include(I ⊗ I, I ⊗ I),(Z ⊗ Z, Z ⊗ Z),(X ⊗ X, (cos(φ / 2) · X − sin(φ / 2) · Y) ⊗ (cos(φ / 2) · X − sin(φ / 2) · Y)), (Y ⊗ Y, (cos(φ / 2) · Y + sin(φ / 2) · X) ⊗ (cos(φ / 2) · Y + sin(φ / 2) · X)) As shown in Equation (21), the v operation includes a Pauli operation, while the w operation may or may not include a Pauli operation. The w operation is also dependent on the conditional phase angle <> which is one of the gate parameters of the FSIM gate, and v is independent of the gate parameters of the FSIM gate. The specific angles used in the twirling circuits being performed will work for an FSIM gate with arbitrary value of the mixing angle 9 but will change depending on the value of the conditional phase angle <>. As shown in Equation 21, the operations ul, u2, u3, u4 in the first set are all non-parametric single-qubit quantum logic gates; the operations ul, u2, u3, u4 in the second set are all nonparametric single-qubit quantum logic gates; the operations ul, u2 in the third set are nonparametric single-qubit quantum logic gates and the operations u3, u4 in the third set are parametric single-qubit quantum logic gates; and the operations ul, u2 in the fourth set are non-parametric single-qubit quantum logic gates and the operations u3, u4 in the fourth set are parametric single-qubit quantum logic gates. The twirling operations ul and u2 in the third and fourth sets are Pauli operations. The twirling operations u3 and u4 in the third and fourth sets are parameterized by the conditional phase angle <> of the FSIM gate. In some instances, the twirling operations ul, u2 in a set of twirling operations may be parametric single-qubit quantum logic gates; and the twirling operations u3 and u4 in the same set may be non-parametric single-qubit quantum logic gates.

[0092] Starting with a state p and applying the w(φ) operation to it, one can find the mappi-> w(φ)pw(φ)† (22)Attorney Docket No.: RIGET-139WO1

[0093] An FSIM gate is then applied, which is denoted as a unitary U(θ,φ) for simplicity.P↦ U(θ,φ)w(φ)pw(φ)†U(θ,φ)† (23)

[0094] At this point, if no errors are considered, the corresponding v operation can be applied and one can havep ↦ vU(θ,φ)w(φ)pw(φ)†U(θ,φ)†v† = U(θ,φ)pU(θ,φ)† (24) which is the targeted operation. However, defining a generic error channel instead as ε(p) = MpM† ΣM†M = 1 (25)M M and applying it directly after the FSIM gate to model its noise, one can getp ↦ MU(θ,φ)w(φ)pw(φ)†U(θ, (26)M

[0095] Following this with the final operation v to make the entire operation an FSIM gate in the absence of noise, one can getp_out = vMU(θ,φ)w(φ)pw(φ)†U(θ,φ)†M†v† (27M

[0096] Now the relation v†U(θ,φ) = U(θ,φ)w(φ) can be inserted to show that this map is equivalent top_out = vMv† U(θ,φ) pU(θ,φ)† vM† (28)M

[0097] This is then entirely equivalent to if the error channelẼ(p) = vMv† pv†M†v = M'pM'† (2SM Mr is applied to the original state after operating on it with the FSIM gate.

[0098] When a v operation (and its corresponding w operation) is selected from the group (I ⊗ I, Z ⊗ Z) at random and with equal probability, one can find an effective error channel ofAttorney Docket No.: RIGET-139WO1KP) = | Z 1 vMv' pvM^v't (30)VE(II, ZZ) M

[0099] For a component of the error channel M with its action on a state p described asW) = mtj^pP^Pj / d (-31jij one can obtain the resultant error channel component M' withW'(p) = | mij’Yr^pvPi)vPjV^ / d (32)ve( / / , ZZ) ij

[0100] Due to the cyclic property of the trace this reduces toM'(p) = | mijlrfipvPiV^vPjV^ / d (33jve( / / , ZZ) ij

[0101] Now v and Pj, both being Pauli operations, may either commute or anticommute. When they commute, the term vPjV^ = Pj. When they anti-commute vPj = —PjV, and so vPjV^ = —Pj. A structure of the form can be obtainedM'(p) = |mijrljvrliv^r(pPi)Pj / d (-34^ve( / / , ZZ) ij where ijjV= 1 if Pj and Pvcommute and ijjV= — 1 if Pj and Pvanti-commute.

[0102] The new M' may be written in the formM '(p) = m'ij’Yr^pP^Pj / d, (35)ij where, _ ™ij Vmij — 2 / , ^jv'Hiv (36)VEII. ZZ

[0103] The sum reduces to 1 + f]jtzzrli,zz which takes the value 2 if Ptand Pj both commute or both anti-commute with ZZ and 0 otherwise. This means thatm'i7is equal toAttorney Docket No.: RIGET-139WO1rrtij when Pt and Pj are both in the same group below.is equal to 0 when Ptand Pj are in separate groups below.

[0104] In some implementations, Pauli operations that commute with ZZ (ZZ= Z®Z, which are used interchangebly in the present applicaiton) include:II, IZ, XX, XY, YX, YY, ZI, ZZ. (37)

[0105] In some implementations, Pauli operations that anti-commute with ZZ include:IX, IY, XI, XZ, YI, YZ, ZX, ZY (38)

[0106] For v G II, XX, Pauli operations that commute with XX include:II, IX, XI, XX, YY, YZ, ZY, ZZ. (39)

[0107] In some implementations, Pauli operations that anti-commute with XX include:IY, IZ, XY, XZ, YI, YX, ZI, ZX. (40)

[0108] Therefore any off diagonal term in the original Mij can be zeroed out if Ptand Pj are in separate groups for either of these two pairs.

[0109] FIG. 4 shows a pattern 400 of weights applied to the Pauli-transfer matrix Mof the two-qubit noise channel under the combined twirling operations. Rows and columns in FIG. 4 are labeled by the two-qubit Pauli basis {II, IX, IY, IZ, XI,..., ZZ}, and a "1” at position (P, Q) indicates that the corresponding matrix element MP Qsurvives the averaging, while a "0” indicates that it is averaged to zero. Out of the original 256 entries, only 64 remain nonzero after twirling, e.g., the operation projects M onto a much sparser structure. Sixteen of these surviving entries lie on the diagonal (the Pauli-to-same-Pauli components), while 48 are off-diagonal elements that are left untouched by this particular twirl.

[0110] Looking at the structure for the table in the II row / column it is clear that for a component of the noise channel M describing a coherent error around an interaction axis that can be written as a linear combination of XX, YY and ZZ, the error will not be made to behave like a stochastic Pauli error. Other such errors will be made to behave like stochastic Pauli errors, however. The entangling interaction part of the FSIM gate commutes with the twirling operators, and so coherent error in these remains untwirled.Attorney Docket No.: RIGET-139WO1

[0111] If the v operation is not required to be Pauli operations but just Clifford operations, there are then a total of 8 rather than 4 twirling operations one can perform. These turn out to be equivalent to the existing 4 multiplied by a gate Co.C0= exp(^(Z7 + 7Z))C41)

[0112] We can therefore find the error channel that results from twirling the previous Pauli-only result over the group II, Co) to find the result of twirling over this larger group. Note that if v = Cothen w = exp(— i - (ZI + IZ~)~).

[0113] Picking up the derivation from before just before the point where the v operation is a Pauli operation as shown in Equation 33 above,y, mij’Yr(pvPiV^')vPjV^ / d (42)ve( / / , C0) ij The action of vPjV^ = +Pkwhere the map k ■-> i is injective. This map for Cocan be denoted as k = / (i), such that vP^ = s(i)P^( and s(i) = +1.

[0114] This results in a simplification toM '(p)=2^1 ^i7sG)s(i)Tr(pP / (O)P / (7)j (43)\ b b / which results in each term in the final map becoming half the sum or half of the difference of two terms in the original map.

[0115] The m’XX:YY term is equal to1m'xx, YY=2 (mxx, YY +mrr,xx) ( 4)

[0116] These are all terms unaffected by the previous twirling. Consider if one had some coherent error noise component M of the form of an under or over rotation in the iSWAP-like interaction.Attorney Docket No.: RIGET-139WO16 6 6M = exp(i-(XX + KF)) = exp(i-XX)exp(i — YY)= (cos(c / 2) / / + isin(6 / 2)XX)(cos(c / 2) / / + isin(e / 2)'YY)~= cos2(c / 2) / / + sin2(c / 2)ZZ + icos(c / 2)sin(e / 2)(XX + rr)

[0117] Its action on a state p is then p» MpM^ (46)

[0118] This makes its action on a state p have non-zero off diagonal terms inmn, YY>mn,zz>mxx, YY’mxx,zz>mYY,zz (and their transposition).

[0119] Then accordance with above, for example,mxx, YY =mYY,xx = cos2(6 / 2)sin2(c / 2)(47) and1m'xX, YY=2 (.mXX, YY +mYY, Xx)= mXX, YY ( 8) this error term is still left unchanged. This makes sense as this Clifford operation commutes with the FSIM gate which is also an interaction in this axis.

[0120] Carefully looking at the action of this Clifford operation can summise that terms which have already been set to zero by the previous Pauli twirling operations will be only mixed with other terms that have already been set to zero by the previous twirling operations, and vice versa. There is not any clear benefit in general to therefore including it, although for a specific noise model or approach to characterising the noise model perhaps there could be.

[0121] For 0 < y < 2n, a set of twirling operations of the FSIM(0, <>) gate may include ul ® u2 = exp(iy • ( / Z + Z / ))= cos2(y) / / — sin2(y)ZZ + isin (y) cos (y)(IZ + Z / ),(49) u3 ® u4 = exp(— iy • ( / Z + Z / ))= cos2(y) / / — sin2(y)ZZ — isin(y)cos(y)( / Z + Z / ) Simplifying just slightly as ZI and IZ commute we can expand the exponential,Attorney Docket No.: RIGET-139WO1ul ® u2 = exp(iy • Z) ® exp(iy • Z)(50) u3 ® u4 = exp(— iy • Z) ® exp(— iy • Z)where ul and u3 act on the first qubit QI, u2 and u4 act on the second qubit Q2, ul and u2 are applied on the first and second qubit QI and Q2 before the FSIM gate, u3 and u4 are applied on the first and second qubit QI and Q2 after the FSIM gate. As shown in Equation 50, ul and u2 are rotations of the first and second qubit around the Z axis by an arbitrary angle y / 2, and u3 and u4 are just the equivalent rotation in the opposite direction (rotating around Z in the opposite direction by y / 2), 0 < y < 2n.

[0122] In some implementations, for 0 < y < 2n, a set of twirling operations of the FSIM(0, <>) gate includeul ® u2 = cos2(y + < / > / 2)XX + sin2(y + < / > / 2)FF + cos(y + < / > / 2)sin(y + 0 / 2)(xr + rx)(51)u3 ® u4 = cos2(y)XX + sin2(y)FF + cos(y)sin(y)(XF + YX~)

[0123] Starting with a state p and applying the w(y) = u3 ® u4 operation on the state, one can obtainw(y)pw(y)+(52)

[0124] Then applying the FSIM gate givesFSIM(0, < / >)w(y)pw(y)+FSIM(0, < / >)+(53)

[0125] Finally, the u(y, <>) = ul ® u2 operation can be applied to give a total action of simply the FSIM gate. However, imagine that now an error channel(54) = £M^M=M M is applied at the moment of the FSIM gate. This will yield1 MFSIM(0, < / >)w(y)pw(y)+FSIM(0, (55)M which would then be followed by the u(y, <>) operation to giveAttorney Docket No.: RIGET-139WO1Pout= / v(y, < / >)MFSIM(0, < / >)w(y)pw(y)tFSIM(0, 0)tAftv(y, < / >)\ (55)M

[0126] Now it is known thatv(y, )FSIM(0, )w(y) = FSIM(0, ) (57) and so also thatFSIM(0, 0)w(y) = v(y, < / >)+FSIM(0, 0) (58) This can be rewritten asPout=v(y, <p~)Mv(y, < / >)tFSIM(0, < / >)pFSIM(0, 0)tv(y, < / >)Mtv(y, cp^M where it is noted that this is equivalent to the output if the FSIM gate is applied followed by the noise channelm = y, v(y, <p)Mv(y, tp^pv^y, <p)M^v(y, cpy^ (60)M

[0127] If rather than picking a particular v(y, <>) operation, it is found the average over all choices of the v operation in the two subsets, the twirled error channel can be obtained asKP) = — v(y, < / >)Mv(y, (p~)^pv(y, cp^M^vty, (p^dy 2 • 2n Z y-i (61)v&(v1,v2)

[0128] For a component of the error channel M with its action on a state p described asW) = mij’Yr(j)Pi)Pj / d, (62)ij twirling over one of the two groups defined in the pauli basis asv = ^ pk(y,(p)Pk(63)fc will have the resultant error channel component M' ofAttorney Docket No.: RIGET-139WO1M'(P) = YmU if

[0064] / d^njPk*(~Y’pfY’ ^pf>pf> P™(Y’ ^Pn(y> <t>)PmPjPndY71k I mn M’fjP) = ^i7 / fcinmTr(pP;PiPk)PmP7Pn / d, (-65Jijklnm where1 [nfklnm =^- l Pk^’^Pl^’^Pm^.^Wniy.^dY. (66)271)-^

[0129] These integrals are all independent of the conditional phase angle <> in the final result. One can apply the same procedure on these using computational power to find the new M' in terms of the original.

[0130] At 206, a first set of twirling operations are selected. In some implementations, the first set of twirling operations can be drawn at random from multiple candidate sets of twirling operations that have been identified during operation 204 with equal probability, thereby introducing an additional layer of averaging. In the case of FSIM gate, the twirling operations can be defined by Equations 18, 19, 21 and 50. Conceptually, this means that the effective noise channel experienced by the gate is a convex combination of the channels associated with each individual set of twirling operations, which further suppresses structure in the coherent error and reduces any bias that might arise from relying on a single, fixed pattern of local randomizers. This averaging over multiple twirling sets can be particularly useful when different sets are tailored to mitigate different dominant error mechanisms, or when hardware drifts cause the noise to move within a family of channels over time. In some implementations, selecting a first set of twirling operations also includes selecting the parameters values for the twirling operations to further enrich the averaging effect of the twirling procedure while preserving the desired logical action.

[0131] At 208, an updated quantum logic circuit is generated. In response to the first set of twirling operations being selected, the quantum logic circuit can be modified by adding two pairs of twirling operations to the two qubits where the two-qubit quantum logic gateAttorney Docket No.: RIGET-139WO1is applied. A first pair of twirling operations before the two-qubit quantum logic gate; and a second pair of twirling operations after the two-qubit quantum logic gate. When the quantum logic circuit includes multiple two-qubit quantum logic gates, the twirling set for each two-qubit quantum logic gate can be independently and separately selected to further enrich the effective averaging of the noise across the entire quantum logic circuit. Over many executions (or compilation instances), different combinations of twirling sets are sampled at each FSIM gate application, and so coherent errors in the FSIM gates which are affected by the twirls tend to not coherently reinforce one another over the ensemble. This process may yield an effective noise model that is closer to a stochastic Pauli channel.

[0132] In some instances, the operations 202-208 are performed iteratively to prepare multiple updated quantum logic circuits executions on the quantum processing unit. Each iteration of the iterative process may include selecting a set of twirling operations (which may include selecting specific parameter values for the same twirling operations) for the iteration; and generating an updated quantum logic circuit for the iteration. The selected twirling operations are used to modify the quantum logic circuit to determine the updated quantum logic circuit for execution on the quantum processing unit. In some instances, before the execution of the updated quantum logic circuit on the quantum processing unit, the updated quantum logic circuit may be optimized, e.g., combining different single-qubit quantum logic gates into one single-qubit quantum logic gates. Once the updated quantum logic circuit is determined, the updated quantum logic circuit can be executed on the quantum processing unit. For instance, the updated quantum logic circuit can be executed using selected gate parameters and predetermined control parameters, by communicating control signals to qubit devices and other quantum circuit devices in the quantum processing unit. Measurements of output states generated by the quantum logic circuit, or other types of outputs, can be combined (e.g., averaged) over the iterations to generate an overall output. The twirling operations may cause noise processes to behave more stochastically with respect to the overall output.

[0133] In some implementations, an error mitigation process is applied with the quantum logic circuit under different noise conditions or with additional calibration runs. The resulting measurement data can be post-processed using classical algorithms to moreAttorney Docket No.: RIGET-139WO1accurately estimate what the ideal, noise-free outcome would have been. In some instances, an error mitigation process may include executing approaches such as zero-noise extrapolation, probabilistic error cancellation, symmetry verification, and subspace or subspace-expansion methods. In some implementations, during an error mitigation process, errors are reduced through a sequence of characterization, calibration and postprocess steps. In some instances, when an error mitigation process is performed with the execution of the quantum logic circuit, the twirling operations may improve efficacy of the quantum error mitigation process, thereby improving the accuracy of the overall output.

[0134] Some of the subject matter and operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Some of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage medium for execution by, or to control the operation of, data-processing apparatus. A computer storage medium can be, or can be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them. Moreover, while a computer storage medium is not a propagated signal, a computer storage medium can be a source or destination of computer program instructions encoded in an artificially generated propagated signal. The computer storage medium can also be, or be included in, one or more separate physical components or media.

[0135] Some of the operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0136] The term "data-processing apparatus” encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, a system on a chip, or multiple ones, or combinations, of the foregoing. The apparatus can include special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). TheAttorney Docket No.: RIGET-139WO1apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a crossplatform runtime environment, a virtual machine, or a combination of one or more of them.

[0137] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

[0138] Some of the processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0139] In a general aspect, twirling operations form FSIM gates are presented.

[0140] In a first example, a quantum computing method includes identifying a quantum logic circuit includes a two-qubit quantum logic gate, the two-qubit quantum logic gate having gate parameters and being a native quantum logic operation of a quantum processing unit; identifying a plurality of sets of twirling operations for the two-qubit quantum logic gate, at least one of the sets of twirling operations being determined based on specified values of at least one of the gate parameters of the two-qubit quantum logicAttorney Docket No.: RIGET-139WO1gate; selecting a first set of twirling operations from the plurality of sets of twirling operations; and generating an updated quantum logic circuit. Generating the updated quantum logic circuit includes modifying the quantum logic circuit to include the first set of twirling operations applied to the two-qubit quantum logic gate.

[0141] Implementations of the first example may include one or more of the following features. The two-qubit quantum logic gate is a FSIM gate. The method includes performing an iterative process to prepare the quantum logic circuit for a plurality of executions on the quantum processing unit. Each iteration of the iterative process includes selecting from the plurality of sets of twirling operations, a set of twirling operations for the iteration; and generating an updated quantum logic circuit for the iteration, wherein the updated quantum logic circuit for the iteration includes the selected set of twirling operations applied to the FSIM gate. Selecting, from the plurality of sets of twirling operations, the set of twirling operations for the iteration includes selecting, from the plurality of sets of twirling operations at random with equal probability, the set of twirling operations for the iteration.

[0142] Implementations of the first example may include one or more of the following features. The FSIM gate has a unitary defined as0 0 0cos0 / 2 isin0 / 2 0FSIM(0,0) = isin0 / 2 cos0 / 2 00 0where the gate parameters include a mixing angle 0 and a conditional phase angle <>, at least one of the sets of twirling operations is determined based on specified values of the conditional phase angle <>.

[0143] Implementations of the first example may include one or more of the following features. The method includes determining the specified values of the gate parameters of the FSIM gate; and determining the at least one of the sets of twirling operations based on the specified values. Generating an updated quantum logic circuit includes compiling a program for execution on the quantum processing unit, and the method further includes providing the compiled program for execution on the quantum processing unit. GeneratingAttorney Docket No.: RIGET-139WO1the updated quantum logic circuit includes adding, to the quantum logic circuit, pairs of single-qubit quantum logic gates before and after the FSIM gate.

[0144] Implementations of the first example may include one or more of the following features. The plurality of sets of twirling operations include a first plurality of single-qubit non-parametric quantum logic gates and a second plurality of single-qubit parametric quantum logic gates, and each single-qubit parametric quantum logic gate is parameterized by one of the gate parameters of the FSIM gate. Each set of twirling operations include a first pair of single-qubit quantum logic gates applied to a pair of qubits, a second pair of single-qubit quantum logic gates applied to the pair of qubits, and the first pair of singlequbit quantum logic gates includes a pair of Pauli operations or a pair of Clifford operations. The plurality of sets of twirling operations include the first set of twirling operations, and the first set of twirling operations includes a first pair of Pauli operations applied before the FSIM gate, and a second pair of non-Pauli operations applied after the FSIM gate.

[0145] Implementations of the first example may include one or more of the following features. The gate parameters of the FSIM gate include a pair of angles (0, <p), and the plurality of sets of twirling operations include a set including two pairs of identity gates, (7 ® I, I ® / ), a set including two pairs of Pauli Z gates (Z ® Z, Z ® Z), a set including a pair of Pauli X gates X ® X) and a pair of gates of the form ((cos(0 / 2) ■ X — sin(0 / 2) ■ T) ® (cos(0 / 2) ■ X — sin(0 / 2) ■ Y)); and a set including a pair of Pauli Y gates (Y ® Y) and a pair of gates of the form ((cos(0 / 2) ■ Y + sin(0 / 2) ■ X) ® (cos(0 / 2) ■ Y + sin(0 / 2) ■ X)). The plurality of sets of twirling operations include a set including a pair of gates of the form ((cos(y + 0 / 2) ■ X + sin(y + 0 / 2) ■ Y) ® (cos(y + 0 / 2) ■ X + sin(y + 0 / 2) ■ Y)) and a pair of gates of the form ((cosy ■ X + siny ■ Y) ® (cosy ■ X + siny ■ Y)), where y is a parameter value in the range of 0 to 2TI. The method further includes executing the updated quantum logic circuit on the quantum processing unit with an error mitigation process.

[0146] In a second example, a quantum computing system includes a quantum processing unit; and a control system communicably connected to the quantum processing unit. The control system is configured to perform one or more operations of the first example.Attorney Docket No.: RIGET-139WO1

[0147] While this specification contains many details, these should not be understood as limitations on the scope of what may be claimed, but rather as descriptions of features specific to particular examples. Certain features that are described in this specification or shown in the drawings in the context of separate implementations can also be combined. Conversely, various features that are described or shown in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination.

[0148] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single product or packaged into multiple products.

[0149] A number of embodiments have been described. Nevertheless, it will be understood that various modifications can be made. Accordingly, other embodiments are within the scope of the following claims.

Claims

Attorney Docket No.: RIGET-139WO1CLAIMSWhat is claimed is:

1. A quantum computing method comprising:identifying a quantum logic circuit comprising a parametric two-qubit quantum logic gate, the parametric two-qubit quantum logic gate having gate parameters and being a native quantum logic operation of a quantum processing unit;identifying a plurality of sets of twirling operations for the parametric two-qubit quantum logic gate, at least one of the sets of twirling operations being determined based on specified values of at least one of the gate parameters of the parametric two-qubit quantum logic gate;selecting a first set of twirling operations from the plurality of sets of twirling operations; andgenerating an updated quantum logic circuit, wherein generating the updated quantum logic circuit comprises modifying the quantum logic circuit to include the first set of twirling operations applied to the parametric two-qubit quantum logic gate.

2. The method of claim 1, where the parametric two-qubit quantum logic gate is an FSIM gate.

3. The method of claim 2, comprising performing an iterative process to prepare the quantum logic circuit for a plurality of executions on the quantum processing unit, wherein each iteration of the iterative process comprises:selecting, from the plurality of sets of twirling operations, a set of twirling operations for the iteration; andgenerating an updated quantum logic circuit for the iteration, wherein the updated quantum logic circuit for the iteration comprises the selected set of twirling operations applied to the FSIM gate.

4. The method of claim 3, wherein selecting from the plurality of sets of twirling operations, the set of twirling operations for the iteration comprises:selecting from the plurality of sets of twirling operations at random with equal probability, the set of twirling operations for the iteration.Attorney Docket No.: RIGET-139WO15. The method of any one of claims 2 - 4, wherein the FSIM gate corresponds to the unitary operator0 0 0cos0 / 2 isin0 / 2 0FSIM(0,0) = isin0 / 2 cos0 / 2 00 0where the gate parameters comprise a mixing angle 0 and a conditional phase angle <>.

6. The method of claim 5, wherein at least one of the sets of twirling operations is determined based on specified values of the conditional phase angle <>.

7. The method of any one of claims 2 - 4, comprising:determining the specified values of the gate parameters of the FSIM gate; and determining the at least one of the sets of twirling operations based on the specified values.

8. The method of any one of claims 2 - 4, wherein generating an updated quantum logic circuit comprises compiling a program for execution on the quantum processing unit, and the method comprises:providing the compiled program for execution on the quantum processing unit.

9. The method of any one of claims 2 - 4, wherein generating the updated quantum logic circuit comprises:adding, to the quantum logic circuit, pairs of single-qubit quantum logic gates before and after the FSIM gate.

10. The method of any one of claims 2 - 4, wherein the first set of twirling operations comprises:a first pair of single-qubit non-parametric quantum logic gates, anda second pair of single-qubit parametric quantum logic gates, each single-qubit parametric quantum logic gate being parameterized by one of the gate parameters of the FSIM gate.

11. The method of claim 10, wherein the pair of single qubit non-parametric quantum logic gates comprises a pair of Pauli operations or a pair of Clifford operations.Attorney Docket No.: RIGET-139WO112. The method of any one of claims 2 - 4, wherein the first set of twirling operations comprises a first pair of Pauli operations applied before the FSIM gate, and a second pair of non-Pauli operations applied after the FSIM gate.

13. The method of any one of claims 2 - 4, wherein the gate parameters of the FSIM gate comprise a pair of angles (0, <p), and the plurality of sets of twirling operations comprise:a set comprising two pairs of identity gates, (I ⊗ I, I ⊗ I),a set comprising two pairs of Pauli Z gates [Z ® Z, Z ® Z),a set comprising a pair of Pauli X gates X ® X) and a pair of gates of the form ((cos(0 / 2) ■ X — sin(0 / 2) ■ Y) ® (cos(0 / 2) ■ X — sin(0 / 2) ■ Y)); anda set comprising a pair of Pauli Y gates (Y ® Y) and a pair of gates of the form ((cos(0 / 2) ■ Y + sin(0 / 2) ■ X) ® (cos(0 / 2) ■ Y + sin(0 / 2) ■ X)).

14. The method of any one of claims 2 - 4, wherein the gate parameters of the FSIM gate include a pair of angles (0, <p), and the plurality of sets of twirling operations include:a set comprising a pair of gates of the form ((cos(y + 0 / 2) ■ X + sin(y + 0 / 2) ■ Y) ® (cos(y + 0 / 2) ■ X + sin(y + 0 / 2) ■ Y)) and a pair of gates of the form((cosy ■ X + siny ■ Y) ® (cosy ■ X + siny ■ Y)), wherein y is a parameter value in the range of 0 to 2TI.

15. The method of any one of claims 2 - 4, comprising:executing the modified quantum logic circuit on the quantum processing unit with an error mitigation process.

16. A quantum computing system comprising:a quantum processing unit; anda control system communicably connected to the quantum processing unit, the control system being configured to perform operations comprising:identifying a quantum logic circuit comprising a parametric two-qubit quantum logic gate, the two-qubit quantum logic gate having gate parameters and being a native quantum logic operation of the quantum processing unit;identifying a plurality of sets of twirling operations for the parametric two-qubit quantum logic gate, at least one of the sets of twirling operations being determinedAttorney Docket No.: RIGET-139WO1based on specified values of at least one of the gate parameters of the parametric two-qubit quantum logic gate;selecting a first set of twirling operations from the plurality of sets of twirling operations; andgenerating an updated quantum logic circuit, wherein generating the updated quantum logic circuit comprises modifying the quantum logic circuit to include the first set of twirling operations applied to the parametric two-qubit quantum logic gate.

17. The system of claim 16, wherein the parametric two-qubit quantum logic gate is an FSIM gate.

18. The system of claim 17, wherein the operations comprise performing an iterative process to prepare the quantum logic circuit for a plurality of executions on the quantum processing unit, wherein each iteration of the iterative process comprises:selecting, from the plurality of sets of twirling operations, a set of twirling operations for the iteration; andgenerating an updated quantum logic circuit for the iteration, wherein the updated quantum logic circuit for the iteration comprises the selected set of twirling operations applied to the FSIM gate.

19. The system of claim 17, wherein selecting from the plurality of sets of twirling operations, the set of twirling operations for the iteration comprises:selecting from the plurality of sets of twirling operations at random with equal probability, the set of twirling operations for the iteration.

20. The system of any one of claims 17 -19, wherein the FSIM gate corresponds to the unitary operatorZ10 0 0 \0 cos0 / 2 isin0 / 2 0FSIM(0,0) = 0 isin0 / 2 cos0 / 2 0,0 0 0where the gate parameters comprise a mixing angle 9 and a conditional phase angle <>.Attorney Docket No.: RIGET-139WO121. The system of claim 20, wherein at least one of the sets of twirling operations is determined based on specified values of the conditional phase angle <>.

22. The system of any one of claims 17 -19, wherein the operations comprise:determining the specified values of the gate parameters of the FSIM gate; and determining the at least one of the sets of twirling operations based on the specified values.

23. The system of any one of claims 17 -19, wherein generating an updated quantum logic circuit comprises compiling a program for execution on the quantum processing unit, and the method comprises:providing the compiled program for execution on the quantum processing unit.

24. The system of claim 16, wherein generating the updated quantum logic circuit comprises:adding, to the quantum logic circuit, pairs of single-qubit quantum logic gates before and after the FSIM gate.

25. The system of any one of claims 17 -19, wherein the first set of twirling operations comprises:a first pair of single-qubit non-parametric quantum logic gates, anda second pair of single-qubit parametric quantum logic gates, each single-qubit parametric quantum logic gate being parameterized by one of the gate parameters of the FSIM gate.

26. The system of claim 25, wherein the pair of single qubit non-parametric quantum logic gates comprises a pair of Pauli operations or a pair of Clifford operations.

27. The system of any one of claims 17 -19, wherein the first set of twirling operations comprises a first pair of Pauli operations applied before the FSIM gate, and a second pair of non-Pauli operations applied after the FSIM gate.

28. The system of any one of claims 17 -19, wherein the gate parameters of the FSIM gate comprise a pair of angles (0, <p), and the plurality of sets of twirling operations comprise:a set comprising two pairs of identity gates, (7 ® I, I ® / ),Attorney Docket No.: RIGET-139WO1a set comprising two pairs of Pauli Z gates (Z ® Z, Z ® Z),a set comprising a pair of Pauli X gates X ® X) and a pair of gates of the form ((cos(0 / 2) ■ X — sin(0 / 2) ■ F) ® (cos(0 / 2) ■ X — sin(0 / 2) ■ Y)); anda set comprising a pair of Pauli Y gates (Y ® Y) and a pair of gates of the form ((cos(0 / 2) ■ Y + sin(0 / 2) ■ X) ® (cos(0 / 2) ■ Y + sin(0 / 2) ■ X)).

29. The system of any one of claims 17 -19, wherein the gate parameters of the FSIM gate include a pair of angles (0, <p), and the plurality of sets of twirling operations include:a set comprising a pair of gates of the form ((cos(y + 0 / 2) ■ X + sin(y + 0 / 2) ■ Y) ® (cos(y + 0 / 2) ■ X + sin(y + 0 / 2) ■ Y)) and a pair of gates of the form((cosy ■ X + siny ■ Y) ® (cosy ■ X + siny ■ Y)), wherein y is a parameter value in the range of 0 to 2TI.

30. The system of any one of claims 17 -19, wherein the operations comprise:executing the modified quantum logic circuit on the quantum processing unit with an error mitigation process.

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