Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device comprises a silicon carbide substrate comprising a first main surface and a second main surface opposite to the first main surface, a gate insulating film, and a gate electrode. The silicon carbide substrate comprises: a source region comprising a first conductivity type and comprising the first main surface; a body region that comprises a second conductivity type different from the first conductivity type, is disposed between the source region and the second main surface, and is in contact with the source region; a first drift region that comprises the first conductivity type, is disposed between the body region and the second main surface, and is in contact with the body region; a first electric field relaxation region that comprises the second conductivity type, is disposed between the body region and the second main surface, and is in contact with the body region and the first drift region; an intermediate region that comprises the first conductivity type, is disposed between the first electric field relaxation region and the second main surface, and is in contact with the first electric field relaxation region; a second electric field relaxation region that comprises the second conductivity type, is disposed between the intermediate region and the second main surface, and is in contact with the intermediate region; and a second drift region that comprises the first conductivity type, is disposed between the first drift region and second electric field relaxation region and the second main surface, and is in contact with the first drift region. The first main surface has a gate trench comprising a side surface penetrating the source region and the body region and reaching the first drift region, and a bottom surface continuous with the side surface. The gate insulating film is in contact with the side surface and the bottom surface, and the gate insulating film is interposed between the gate electrode and the body region

Description

Silicon carbide semiconductor equipment

[0001] This disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority under Japanese application No. 2024-221148, filed on 17 December 2024, and incorporates all the provisions contained in the said Japanese application.

[0003] One example of a silicon carbide semiconductor device is a trench-type MOSFET (metal oxide semiconductor field effect transformer) equipped with an electric field relaxation region.

[0004] International Publication No. 2020 / 110514, Japanese Patent Publication No. 2018-190994

[0005] The silicon carbide semiconductor device of the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, a gate insulating film, and a gate electrode, wherein the silicon carbide substrate has a source region having a first conductivity type and the first main surface, a body region having a second conductivity type different from the first conductivity type, located between the source region and the second main surface and in contact with the source region, a first drift region having the first conductivity type, located between the body region and the second main surface and in contact with the body region, a first field relaxation region having the second conductivity type, located between the body region and the second main surface and in contact with the body region and the first drift region, and a first field relaxation region having the first conductivity type and the first field The device has an intermediate region between the field relaxation region and the second main surface that contacts the first field relaxation region, a second field relaxation region having the second conductivity type and located between the intermediate region and the second main surface that contacts the intermediate region, and a second drift region having the first conductivity type and located between the first drift region and the second field relaxation region and the second main surface that contacts the first drift region, the first main surface has a gate trench having a side surface that penetrates the source region and the body region and reaches the first drift region, and a bottom surface connected to the side surface, the gate insulating film is in contact with the side surface and the bottom surface, and the gate electrode sandwiches the gate insulating film between itself and the body region.

[0006] Figure 1 is a diagram showing the configuration of the interlayer insulating film and the first main surface in a silicon carbide semiconductor device according to an embodiment. Figure 2 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to an embodiment. Figure 3 is a diagram showing an example of the distribution of impurity concentration in the silicon carbide epitaxial layer. Figure 4 is a diagram showing an example of the distribution of effective impurity concentration in the silicon carbide epitaxial layer. Figure 5 is a schematic diagram showing the ranges of the first semiconductor region and the second semiconductor region. Figure 6 is a cross-sectional view (1) showing the manufacturing method of a silicon carbide semiconductor device according to an embodiment. Figure 7 is a cross-sectional view (2) showing the manufacturing method of a silicon carbide semiconductor device according to an embodiment. Figure 8 is a cross-sectional view (3) showing the manufacturing method of a silicon carbide semiconductor device according to an embodiment. Figure 9 is a cross-sectional view (4) showing the manufacturing method of a silicon carbide semiconductor device according to an embodiment. Figure 10 is a cross-sectional view (5) showing the manufacturing method of a silicon carbide semiconductor device according to an embodiment. Figure 11 is a cross-sectional view (6) showing the manufacturing method of a silicon carbide semiconductor device according to an embodiment. Figure 12 is a cross-sectional view (7) showing the manufacturing method of a silicon carbide semiconductor device according to an embodiment. Figure 13 shows an example of the distribution of impurity concentration in an n-type semiconductor layer. Figure 14 shows an example of the distribution of impurity concentration in an n-type semiconductor layer after ion implantation of p-type impurities.

[0007] [Problems this disclosure aims to solve] In conventional silicon carbide semiconductor devices, it is difficult to achieve both improved breakdown voltage and reduced on-resistance.

[0008] The purpose of this disclosure is to provide a silicon carbide semiconductor device that can achieve both improved voltage resistance and reduced on-resistance.

[0009] [Effects of this disclosure] According to this disclosure, it is possible to achieve both improved voltage resistance and reduced on-resistance.

[0010] The implementation methods are described below.

[0011] [Description of Embodiments of the Disclosure] Embodiments of the Disclosure are first listed and described. In the following description, the same or corresponding elements are denoted by the same reference numeral, and the same description is not repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. Also, while negative crystallographic exponents are usually indicated by placing a "-" (bar) above the number, in this disclosure a negative sign is placed before the number. Also, in the following description, the XYZ Cartesian coordinate system is used, but this coordinate system is defined for illustrative purposes and is not limited to the orientation of the silicon carbide semiconductor device. Also, from any point, the +Z direction may be referred to as upward, upper side, or up, and the -Z direction may be referred to as downward, lower side, or down.

[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, a gate insulating film, and a gate electrode, wherein the silicon carbide substrate has a first conductivity type and a source region having the first main surface, a body region having a second conductivity type different from the first conductivity type, located between the source region and the second main surface and in contact with the source region, a first drift region having the first conductivity type, located between the body region and the second main surface and in contact with the body region, a first field relaxation region having the second conductivity type, located between the body region and the second main surface and in contact with the body region and the first drift region, and the first conductivity type, The device has an intermediate region between the first electric field relaxation region and the second main surface, which is in contact with the first electric field relaxation region; a second electric field relaxation region having the second conductivity type, which is between the intermediate region and the second main surface, which is in contact with the intermediate region; and a second drift region having the first conductivity type, which is between the first drift region and the second electric field relaxation region and the second main surface, which is in contact with the first drift region. The first main surface has a gate trench having a side surface that penetrates the source region and the body region and reaches the first drift region, and a bottom surface connected to the side surface. The gate insulating film is in contact with the side surface and the bottom surface, and the gate electrode sandwiches the gate insulating film between itself and the body region.

[0013] The first and second field relaxation regions improve the breakdown voltage, while the intermediate region reduces the formation of a wide depletion layer near the first and second field relaxation regions, thereby reducing on-resistance. In other words, it is possible to achieve both improved breakdown voltage and reduced on-resistance.

[0014] [2] In [1], the first drift region may contain the first conductivity type impurity at a higher concentration than the second drift region. In this case, the on-resistance is easier to reduce.

[0015] [3] In [1] or [2], the first electric field relaxation region comprises a first semiconductor region in contact with the body region and a second semiconductor region located between the first semiconductor region and the second main surface and in contact with the first semiconductor region and the first drift region, wherein the first semiconductor region is away from the gate trench and the second semiconductor region is further away from the gate trench than the first semiconductor region. In this case, the voltage across the gate insulating film is reduced by the first semiconductor region, while current can be made to flow more easily within the first drift region.

[0016] [4] In [3], the interface between the first semiconductor region and the second semiconductor region may be closer to the second main surface than to the bottom surface. In this case, the voltage applied to the gate insulating film can be reduced, making it easier to improve the breakdown voltage.

[0017] [5] In [3] or [4], the first semiconductor region may contain the second conductivity type impurity at a higher concentration than the second semiconductor region. The method for forming the first and second semiconductor regions is not limited, but when the first and second semiconductor regions are formed by channeling injection, the first semiconductor region tends to contain the second conductivity type impurity at a higher concentration than the second semiconductor region.

[0018] [6] In any of [3] to [5], the body region has a third semiconductor region that overlaps with the first semiconductor region in a plan view perpendicular to the first main surface, and a fourth semiconductor region between the third semiconductor region and the gate trench, wherein the third semiconductor region may contain the second conductivity type impurity at a higher concentration than the fourth semiconductor region. In this case, the fourth semiconductor region makes it possible to reduce the resistance between the body region and the first field relaxation region while making it less likely for leakage to occur in the third semiconductor region.

[0019] [7] In any of [3] to [6], the first drift region has a fifth semiconductor region in contact with the body region and a sixth semiconductor region in contact with the second semiconductor region along a first axis parallel to the first main surface, and the fifth semiconductor region may contain the first conductivity type impurity at a higher concentration than the sixth semiconductor region. In this case, current flows more easily within the fifth semiconductor region, so that current flows more easily over a wide area of ​​the first drift region in plan view, making it easier to reduce on-resistance.

[0020] [Embodiments of the Disclosure] The embodiments relate to a so-called vertical MOS (metal oxide semiconductor) type field-effect transistor (FET) using silicon carbide. This MOS type FET is an example of a silicon carbide semiconductor device. Figure 1 is a diagram showing the configuration of the interlayer insulating film and the first main surface in the silicon carbide semiconductor device according to the embodiment. Figure 2 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the embodiment. Figure 2 corresponds to a cross-sectional view along the line II-II in Figure 1.

[0021] As shown in Figures 1 and 2, the silicon carbide semiconductor device 100 according to the embodiment includes a silicon carbide substrate 20, a gate insulating film 31, a gate electrode 32, a source electrode 40, a drain electrode 45, an interlayer insulating film 35, and a barrier metal film 36.

[0022] The silicon carbide substrate 20 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is on the +Z side when viewed from the second main surface 2. The silicon carbide substrate 20 includes a silicon carbide single crystal substrate 21 and a silicon carbide epitaxial layer 10. The silicon carbide epitaxial layer 10 is on the silicon carbide single crystal substrate 21. The first main surface 1 is on the silicon carbide epitaxial layer 10, and the second main surface 2 is on the silicon carbide single crystal substrate 21. The silicon carbide single crystal substrate 21 and the silicon carbide epitaxial layer 10 are formed of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 21 contains n-type impurities such as nitrogen (N) and has an n-type conductivity type (first conductivity type). Hereafter, a plan view perpendicular to the first principal plane 1 will simply be referred to as a plan view.

[0023] The first main surface 1 is the {0001} surface or a surface inclined by an off-angle of 8° or less in the off-direction. Preferably, the first main surface 1 is the (000-1) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The off-direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more or 2° or more. The off-angle may be 6° or less or 4° or less. The first main surface 1 may be the (0001) surface or a surface inclined by an off-angle of 8° or less in the off-direction.

[0024] The silicon carbide epitaxial layer 10 has a first drift region 11A, a second drift region 11B, an intermediate region 11C, a body region 12, a source region 13, a contact region 14, a first field relaxation region 15A, and a second field relaxation region 15B. The source region 13 and the contact region 14 have a first main surface 1.

[0025] The source region 13 has a first main surface 1. The source region 13 contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity.

[0026] The body region 12 is located between the source region 13 and the second main surface 2. The body region 12 is in contact with the source region 13. The lower end surface of the source region 13 and the upper end surface of the body region 12 are in contact with each other. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity (second conductivity).

[0027] The first drift region 11A is located between the body region 12 and the second main surface 2. The first drift region 11A is in contact with the body region 12. The lower end surface of the body region 12 and the upper end surface of the first drift region 11A are in contact with each other. The first drift region 11A extends along the Y-axis. Multiple first drift regions 11A are provided along the X-axis at regular intervals (first pitch P1). The first drift region 11A contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity. The source region 13 and the first drift region 11A are separated from each other by the body region 12.

[0028] The first field relaxation region 15A is located between the body region 12 and the second main surface 2. The first field relaxation region 15A is in contact with the body region 12 and the first drift region 11A. The lower end surface of the body region 12 and the upper end surface of the first field relaxation region 15A are in contact with each other. The first field relaxation region 15A extends along the Y-axis. Multiple first field relaxation regions 15A are provided along the X-axis at regular intervals (first pitch P1). The first drift region 11A and the first field relaxation region 15A are arranged alternately along the X-axis. The first field relaxation region 15A contains p-type impurities such as aluminum (Al) and has a p-type conductivity.

[0029] The intermediate region 11C is located between the first field relaxation region 15A and the second main surface 2. The intermediate region 11C is in contact with the first field relaxation region 15A. The lower end surface of the first field relaxation region 15A and the upper end surface of the intermediate region 11C are in contact with each other. The intermediate region 11C extends along the Y-axis. Multiple intermediate regions 11C are provided along the X-axis at regular intervals (first pitch P1). The intermediate region 11C is also in contact with the first drift region 11A. The first drift region 11A and the intermediate region 11C are arranged alternately along the X-axis. The intermediate region 11C contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity. The intermediate region 11C may further contain p-type impurities as long as it has an n-type conductivity.

[0030] The second field relaxation region 15B is located between the intermediate region 11C and the second main surface 2. The second field relaxation region 15B is in contact with the intermediate region 11C. The lower end surface of the intermediate region 11C and the upper end surface of the second field relaxation region 15B are in contact with each other. The second field relaxation region 15B extends along the Y-axis. Multiple second field relaxation regions 15B are provided along the X-axis at regular intervals (first pitch P1). The second field relaxation region 15B contains p-type impurities such as aluminum (Al) and has a p-type conductivity.

[0031] The second drift region 11B is located between the first drift region 11A, the second field relaxation region 15B, and the second main surface 2. The second drift region 11B is in contact with the first drift region 11A. The lower end surface of the first drift region 11A and the upper end surface of the second drift region 11B are in contact with each other. The second drift region 11B is also in contact with the second field relaxation region 15B. The lower end surface of the second field relaxation region 15B and the upper end surface of the second drift region 11B are in contact with each other. The portion of the upper end surface of the second drift region 11B that is in contact with the first drift region 11A and the upper end surface of the second field relaxation region 15B may be flush. The second drift region 11B contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity. The second drift region 11B may be in contact with the silicon carbide single crystal substrate 21. A buffer layer containing n-type impurities such as nitrogen (N) and having an n-type conductivity may be present between the second drift region 11B and the silicon carbide single crystal substrate 21.

[0032] A gate trench 5 is located on the first main surface 1. The gate trench 5 comprises a side surface 3 that penetrates the source region 13 and the body region 12 and reaches the first drift region 11A, and a bottom surface 4 connected to the side surface 3. The gate trench 5 is defined by the side surface 3 and the bottom surface 4. The bottom surface 4 is located in the first drift region 11A. In plan view, the gate trench 5 overlaps with the first drift region 11A. The gate trench 5 extends along the Y-axis. Multiple gate trenches 5 are provided along the X-axis at regular intervals (first pitch P1). The first electric field relaxation region 15A is separated from the gate trench 5. For example, the bottom surface 4 is parallel to the first main surface 1 and the second main surface 2. In a cross-sectional view perpendicular to the Y-axis, the angle θ1 of the side surface 3 with respect to the virtual plane 9 including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. Side surface 3 has, for example, a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent electron mobility.

[0033] Along the Z-axis, there is a silicon carbide single crystal substrate 21, a second drift region 11B, and a first drift region 11A between the bottom surface 4 and the second main surface 2, and the conductivity type of the silicon carbide substrate 20 between the bottom surface 4 and the second main surface 2 is n-type.

[0034] The contact region 14 has a first main surface 1. The contact region 14 is in contact with the source region 13. The contact region 14 is also in contact with the body region 12. The contact region 14 contains p-type impurities such as aluminum (Al) and has a p-type conductivity. The contact region 14 may be in contact with the first field relaxation region 15A. The contact region 14, the body region 12, and the first field relaxation region 15A are electrically connected to each other. The contact region 14 is located, for example, between adjacent gate trenches 5 along the X-axis in a plan view. Between two adjacent gate trenches 5 along the X-axis, the contact region 14 and the source region 13 may be alternately provided along the Y-axis. Between two adjacent gate trenches 5 along the X-axis, the contact region 14 may be provided intermittently along the Y-axis.

[0035] A plurality of gate trenches 5 may be arranged at regular intervals along the Y-axis. When a plurality of gate trenches 5 are arranged at regular intervals along the Y-axis, a part of the contact region 14 may be between adjacent gate trenches 5 along the Y-axis. The plurality of gate trenches 5 may be provided in an array in a plan view.

[0036] The gate insulating film 31 contacts the side surface 3 and the bottom surface 4. The gate insulating film 31 is, for example, an oxide film. The gate insulating film 31 contains, for example, silicon dioxide (SiO ２ ). The gate insulating film 31 contacts the first drift region 11A at the bottom surface 4. The gate insulating film 31 contacts the source region 13, the body region 12, and the first drift region 11A at the side surface 3. The gate insulating film 31 may contact the source region 13 at the first main surface 1.

[0037] The gate electrode 32 sandwiches the gate insulating film 31 with the body region 12. The gate electrode 32 is on the gate insulating film 31 and sandwiches the gate insulating film 31 with the silicon carbide substrate 20. The gate electrode 32 contains, for example, polycrystalline silicon containing a conductive impurity. The gate electrode 32 faces the side surface 3 and the bottom surface 4. The gate electrode 32 extends along the Y-axis. In a plan view, the gate electrode 32 may overlap with a plurality of gate trenches 5 arranged along the Y-axis.

[0038] The interlayer insulating film 35 covers the gate electrode 32. The interlayer insulating film 35 has insulating films 33 and 34. The insulating film 33 contacts the upper surface of the gate electrode 32 and the upper surface of the gate insulating film 31. The insulating film 34 is on the insulating film 33. The insulating films 33 and 34 are, for example, oxide films. The insulating film 33 is, for example, a non-doped silicate glass (NSG) film. The insulating film 34 is, for example, a borophosphosilicate glass (BPSG) film or a phosphosilicate glass (PSG) film. The insulating film 34 has a curved surface that curves convexly when viewed from the gate electrode 32.

[0039] Contact holes 39 are formed in the interlayer insulating film 35 and the gate insulating film 31 at regular intervals (first pitch P1) along the X-axis. The contact holes 39 are arranged such that the gate electrode 32 is positioned between adjacent contact holes 39 along the X-axis. The contact holes 39 extend along the Y-axis. The contact holes 39 reach the source region 13 and the contact region 14.

[0040] The source electrode 40 contacts the first main surface 1. The source electrode 40 includes a contact electrode 41 that contacts the source region 13 and the contact region 14, and a source pad 42 that contacts the contact electrode 41. The contact electrode 41 includes, for example, nickel silicide (NiSi). The contact electrode 41 may include titanium (Ti), aluminum (Al), and silicon (Si). The contact electrode 41 is ohmically connected to the source region 13 and the contact region 14.

[0041] The barrier metal film 36 covers the surface of the interlayer insulating film 35. The barrier metal film 36 is in contact with the interlayer insulating film 35 and the contact electrode 41. The barrier metal film 36 includes, for example, titanium nitride (TiN).

[0042] The source pad 42 covers the surface of the barrier metal film 36 and the upper surface of the contact electrode 41. The source pad 42 is in contact with the barrier metal film 36 and the contact electrode 41. The barrier metal film 36 is between the source pad 42 and the interlayer insulating film 35. The source pad 42 includes, for example, aluminum (Al). The interlayer insulating film 35 electrically insulates the gate electrode 32 and the source electrode 40 from each other.

[0043] There may be a passivation film covering a part of the source electrode 40.

[0044] The drain electrode 45 is in contact with the second main surface 2. The drain electrode 45 is in contact with the silicon carbide single crystal substrate 21 on the second main surface 2. The drain electrode 45 is electrically connected to the second drift region 11B. The drain electrode 45 includes, for example, nickel silicide (NiSi). The drain electrode 45 may also include titanium (Ti), aluminum (Al), and silicon (Si). The drain electrode 45 is ohmic bonded to the silicon carbide single crystal substrate 21.

[0045] Here, the concentration of impurities in the silicon carbide epitaxial layer 10 will be explained. Figure 3 is a diagram showing an example of the distribution of impurity concentrations in the silicon carbide epitaxial layer 10. Figure 4 is a diagram showing an example of the distribution of effective impurity concentrations in the silicon carbide epitaxial layer 10. In this disclosure, the effective concentration of n-type (first conductivity type) impurities is the concentration obtained by subtracting the concentration of p-type (second conductivity type) impurities from the concentration of n-type impurities, and the effective concentration of p-type impurities is the concentration obtained by subtracting the concentration of n-type impurities from the concentration of p-type impurities. The effective concentration can be measured, for example, using a scanning capacitance microscope (SCM). Furthermore, the effective concentration of impurities contained in each region is the average value of the effective concentrations of impurities contained in that region. Figures 3 and 4 show an example of the distribution along arrow 19 in Figure 2.

[0046] As shown in Figure 3, the concentration of n-type impurities has a maximum value in the source region 13, decreases from there toward the first field relaxation region 15A, and becomes constant in the first field relaxation region 15A and the intermediate region 11C. Also, the concentration of n-type impurities is constant in the second field relaxation region 15B and the second drift region 11B, and is lower than in the first field relaxation region 15A and the intermediate region 11C. The concentration of p-type impurities has a maximum value in the body region 12, decreases from there toward the second drift region 11B. The concentration of p-type impurities at the boundary between the intermediate region 11C and the second field relaxation region 15B is lower than the concentration of n-type impurities in the intermediate region 11C, and higher than the concentration of n-type impurities in the second field relaxation region 15B.

[0047] For example, the concentration of n-type impurities in the first drift region 11A is equal to the concentration of n-type impurities in the first field relaxation region 15A and the concentration of n-type impurities in the intermediate region 11C, and the first drift region 11A contains n-type impurities at a higher concentration than the second drift region 11B.

[0048] As shown in Figure 4, for example, the effective concentration of n-type impurities in the source region 13 is higher than the effective concentration of p-type impurities in the body region 12, the effective concentration of p-type impurities in the body region 12 is higher than the effective concentration of p-type impurities in the first field relaxation region 15A, and the effective concentration of p-type impurities in the first field relaxation region 15A is higher than the effective concentration of p-type impurities in the second field relaxation region 15B. Furthermore, there are minimum effective concentrations at the boundary between the source region 13 and the body region 12, the boundary between the first field relaxation region 15A and the intermediate region 11C, and the boundary between the second field relaxation region 15B and the second drift region 11B. That is, the concentration of n-type impurities and the concentration of p-type impurities are equal at the boundary between the source region 13 and the body region 12, the boundary between the first field relaxation region 15A and the intermediate region 11C, and the boundary between the second field relaxation region 15B and the second drift region 11B. In Figure 4, there is no minimum value at the boundary between the intermediate region 11C and the second field relaxation region 15B. This is because the concentration of n-type impurities changes in a step-like manner and cannot be determined to a single value.

[0049] The concentrations of n-type impurities may be equal between the first drift region 11A and the intermediate region 11C, and the effective concentration of n-type impurities in the first drift region 11A may be higher than the effective concentration of n-type impurities in the intermediate region 11C.

[0050] The first field relaxation region 15A has a first semiconductor region 51 and a second semiconductor region 52. The first semiconductor region 51 is in contact with the body region 12. The second semiconductor region 52 is located between the first semiconductor region 51 and the second main surface 2. The second semiconductor region 52 is in contact with the first semiconductor region 51 and the first drift region 11A. The first semiconductor region 51 is away from the gate trench 5, and the second semiconductor region 52 is further away from the gate trench than the first semiconductor region 51.

[0051] Here, the scopes of the first semiconductor region 51 and the second semiconductor region 52 in this disclosure will be described. Figure 5 is a schematic diagram showing the scopes of the first semiconductor region 51 and the second semiconductor region 52.

[0052] The first drift region 11A has an n-type conductivity, while the body region 12, the first semiconductor region 51, and the second semiconductor region 52 have a p-type conductivity. Therefore, the boundaries between the first drift region 11A and the body region 12, the boundary between the first drift region 11A and the first semiconductor region 51, and the boundary between the first drift region 11A and the second semiconductor region 52 are clearly defined.

[0053] The upper end surface 61 of the first drift region 11A is in contact with the lower end surface 62 of the body region 12. In this disclosure, the upper end surface 63 of the first semiconductor region 51 is assumed to be on the same plane as the upper end surface 61 of the first drift region 11A. Furthermore, in the region closer to the second main surface 2 than the upper end surface 63, if the center of the contact circle 68 that contacts the curve indicating the boundary between the p-type region (first semiconductor region 51 or second semiconductor region 52) and the n-type region (first drift region 11A) in a cross-sectional view perpendicular to the Y-axis is moved toward the second main surface 2, the center of the contact circle 68 moves from the p-type region to the n-type region on a plane a certain distance from the first main surface 1. In this disclosure, the lower end surface 64 of the first semiconductor region 51 and the upper end surface 65 of the second semiconductor region 52, i.e., the interface 69 between the first semiconductor region 51 and the second semiconductor region 52, are assumed to be on this plane. The interface 69 is closer to the second main surface 2 than to the bottom surface 4. Furthermore, the first semiconductor region 51 contains p-type impurities at a higher concentration than the second semiconductor region 52.

[0054] The body region 12 has a third semiconductor region 53 and a fourth semiconductor region 54. The third semiconductor region 53 overlaps with the first semiconductor region 51 in a plan view. The fourth semiconductor region 54 is located between the third semiconductor region 53 and the gate trench 5. For example, the third semiconductor region 53 contains p-type impurities at a higher concentration than the fourth semiconductor region 54.

[0055] The first drift region 11A has a fifth semiconductor region 55 and a sixth semiconductor region 56. The fifth semiconductor region 55 contacts the fourth semiconductor region 54 of the body region 12. The sixth semiconductor region 56 contacts the second semiconductor region 52 along the X-axis. For example, the fifth semiconductor region 55 contains n-type impurities at a higher concentration than the sixth semiconductor region 56. The fifth semiconductor region 55 may be called a current diffusion region. The X-axis is an example of the first axis.

[0056] The effective concentration of p-type impurities in the contact region 14 may be higher than the effective concentration of p-type impurities in the body region 12. For example, the effective concentration of p-type impurities in the contact region 14 is, for example, 1×10 １８ cm －３ or more and 1×10 ２０ cm －３ or less, and the effective concentration of p-type impurities in the body region 12 is 5×10 １７ cm －３ or more and 5×10 １８ cm －３ or less. Also, the effective concentration of n-type impurities in the source region 13 is, for example, 1×10 １９ cm －３ or more and 1×10 ２０ cm －３ or less.

[0057] In the silicon carbide semiconductor device 100, there is an intermediate region 11C between the first electric field relaxation region 15A and the second electric field relaxation region 15B. Therefore, while improving the breakdown voltage by the first electric field relaxation region 15A and the second electric field relaxation region 15B, the intermediate region 11C makes it difficult to form a wide depletion layer in the vicinity of the first electric field relaxation region 15A and the second electric field relaxation region 15B, and the on-resistance can be reduced. That is, according to the silicon carbide semiconductor device 100, both improvement of the breakdown voltage and reduction of the on-resistance can be achieved.

[0058] When the first drift region 11A contains n-type impurities at a higher concentration than the second drift region 11B, the on-resistance in the first drift region 11A can be reduced.

[0059] In the first electric field relaxation region 15A, if the second semiconductor region 52 is further from the gate trench than the first semiconductor region 51, the voltage across the gate insulating film 31 can be reduced by the first semiconductor region 51, while current can be made to flow more easily within the first drift region 11A. If the interface 69 is closer to the second main surface 2 than to the bottom surface 4, the voltage across the gate insulating film 31 can be reduced, making it easier to improve the breakdown voltage.

[0060] In the body region 12, if the third semiconductor region 53 contains p-type impurities at a higher concentration than the fourth semiconductor region 54, the fourth semiconductor region 54 can reduce the resistance between the body region 12 and the first field relaxation region 15A while making it less likely for leakage to occur within the third semiconductor region 53.

[0061] In the first drift region 11A, if the fifth semiconductor region 55 contains n-type impurities at a higher concentration than the sixth semiconductor region 56, current flows more easily within the fifth semiconductor region 55. As a result, current flows more easily over a wider area of ​​the first drift region 11A in a plan view, making it easier to reduce on-resistance.

[0062] Next, a method for manufacturing the silicon carbide semiconductor device 100 will be described. Figures 6 to 12 are cross-sectional views showing a method for manufacturing the silicon carbide semiconductor device 100 according to an embodiment.

[0063] First, as shown in Figure 6, a silicon carbide single crystal substrate 21 is prepared, and n-type semiconductor layers 71 and 72 are formed on the silicon carbide single crystal substrate 21. The n-type semiconductor layer 71 contains n-type impurities at the same concentration as the second drift region 11B, and the n-type semiconductor layer 72 contains n-type impurities at the same concentration as the portion of the first drift region 11A near the second drift region 11B where the concentration of n-type impurities is constant. Figure 13 shows an example of the distribution of impurity concentrations in the n-type semiconductor layers 71 and 72.

[0064] Next, ion implantation of p-type impurities is performed. In the ion implantation of p-type impurities, channeling implantation and random implantation are performed. Channeling implantation is mainly performed to form the second semiconductor region 52 and the second field relaxation region 15B of the first field relaxation region 15A, and random implantation is mainly performed to form the first semiconductor region 51 of the first field relaxation region 15A. In channeling implantation, at the boundary between the n-type semiconductor layer 71 and the n-type semiconductor layer 72, the concentration of p-type impurities is made higher than the concentration of n-type impurities in the n-type semiconductor layer 71 and lower than the concentration of n-type impurities in the n-type semiconductor layer 72. As a result, as shown in Figure 7, the second field relaxation region 15B is formed in the n-type semiconductor layer 71, and the first field relaxation region 15A and the intermediate region 11C are formed in the n-type semiconductor layer 72. The remaining part of the n-type semiconductor layer 71 becomes the second drift region 11B. Figure 14 shows an example of the distribution of impurity concentrations in n-type semiconductor layers 71 and 72 after ion implantation of p-type impurities.

[0065] When channeling injection of p-type impurities is performed, the first semiconductor region 51 is more likely to contain p-type impurities at a higher concentration than the second semiconductor region 52.

[0066] Next, ion implantation of p-type and n-type impurities is performed to form a body region 12, a source region 13, and a contact region 14 in the n-type semiconductor layer 72, as shown in Figure 8. The remaining portion of the n-type semiconductor layer 72 becomes the first drift region 11A.

[0067] Next, as shown in Figure 9, a gate trench 5 is formed on the first main surface 1, and a gate insulating film 31 and a gate electrode 32 are formed.

[0068] Next, as shown in Figure 10, an interlayer insulating film 35 having insulating films 33 and 34 is formed, and contact holes 39 are formed in the interlayer insulating film 35 and the gate insulating film 31. For example, the insulating film 33 is an NSG film, and the insulating film 34 is a BPSG film or a PSG film.

[0069] Next, as shown in Figure 11, annealing is performed at a temperature at which the gate insulating film 31 and insulating film 33 do not soften, but the insulating film 34 softens, for example, a temperature of 800°C to 1000°C. As a result, the insulating film 34 flows, and a curved surface is formed on the insulating film 34 that is convex when viewed from the gate electrode 32.

[0070] Next, as shown in Figure 12, the contact electrode 41, barrier metal film 36, and source pad 42 are formed.

[0071] Next, the drain electrode 45 is formed (see Figure 2). In this way, the silicon carbide semiconductor device 100 according to the embodiment can be manufactured.

[0072] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims.

[0073] 1. First main surface 2. Second main surface 3. Side surface 4. Bottom surface 5. Gate trench 9. Virtual plane 10. Silicon carbide epitaxial layer 11A. First drift region 11B. Second drift region 11C. Intermediate region 12. Body region 13. Source region 14. Contact region 15A. First field relaxation region 15B. Second field relaxation region 19. Arrow 20. Silicon carbide substrate 21. Silicon carbide single crystal substrate 31. Gate insulating film 32. Gate electrode 33, 34. Insulating films 35. Interlayer insulating film 36. Barrier metal film 39. Contact hole 40. Source electrode 41. Contact electrode 42. Source pad 45. Drain electrode 51. First semiconductor region 52. Second semiconductor region 53. Third semiconductor region 54. Fourth semiconductor region 55. Fifth semiconductor region 56. Sixth semiconductor region 61, 63, 65 Upper end surface 62, 64 Lower end surface 68 Contact circle 69 Interface 71, 72 n-type semiconductor layer 100 Silicon carbide semiconductor device P1 First pitch θ1 Angle X X-axis (first axis) Y Y-axis Z Z-axis

Claims

1. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, a gate insulating film, and a gate electrode, wherein the silicon carbide substrate has a source region having a first conductivity type and having the first main surface, a body region having a second conductivity type different from the first conductivity type, located between the source region and the second main surface and in contact with the source region, a first drift region having the first conductivity type, located between the body region and the second main surface and in contact with the body region, a first field relaxation region having the second conductivity type, located between the body region and the second main surface and in contact with the body region and the first drift region, an intermediate region having the first conductivity type, located between the first field relaxation region and the second main surface and in contact with the first field relaxation region, and a second field relaxation region having the second conductivity type, located between the intermediate region and the second main surface and in contact with the intermediate region. A silicon carbide semiconductor device having the first conductivity type, a second drift region located between the first drift region and the second electric field relaxation region and the second main surface and in contact with the first drift region, the first main surface having a gate trench with a side surface that penetrates the source region and the body region and reaches the first drift region, and a bottom surface connected to the side surface, the gate insulating film in contact with the side surface and the bottom surface, and the gate electrode sandwiching the gate insulating film between itself and the body region.

2. The silicon carbide semiconductor device according to claim 1, wherein the first drift region contains impurities of the first conductivity type at a higher concentration than the second drift region.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein the first electric field relaxation region comprises a first semiconductor region in contact with the body region and a second semiconductor region located between the first semiconductor region and the second main surface and in contact with the first semiconductor region and the first drift region, the first semiconductor region being away from the gate trench and the second semiconductor region being further away from the gate trench than the first semiconductor region.

4. The silicon carbide semiconductor device according to claim 3, wherein the interface between the first semiconductor region and the second semiconductor region is closer to the second main surface than to the bottom surface.

5. The silicon carbide semiconductor device according to claim 3 or 4, wherein the first semiconductor region contains impurities of the second conductivity type at a higher concentration than the second semiconductor region.

6. The silicon carbide semiconductor device according to any one of claims 3 to 5, wherein the body region comprises a third semiconductor region that overlaps with the first semiconductor region in a plan view perpendicular to the first main surface, and a fourth semiconductor region located between the third semiconductor region and the gate trench, and the third semiconductor region contains impurities of the second conductivity type at a higher concentration than the fourth semiconductor region.

7. The silicon carbide semiconductor device according to any one of claims 3 to 6, wherein the first drift region comprises a fifth semiconductor region in contact with the body region and a sixth semiconductor region in contact with the second semiconductor region along a first axis parallel to the first main surface, and the fifth semiconductor region contains impurities of the first conductivity type at a higher concentration than the sixth semiconductor region.

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