Resistors for capacitor correlation systems and methods

Abstract

Resistors for capacitor correlation systems and methods are provided. In one example, an integrated circuit includes a resistor. The resistor includes a resistive structure disposed on a plurality of integrated circuit metal layers and having a pattern. The resistive structure includes a first conductive layer with the pattern and a second conductive layer with the pattern. The patterns on the first and second conductive layers are aligned and overlap each other. The integrated circuit also includes a via connecting the first and second conductive layers serially. Related systems and methods are also provided.

Description

6165864WO01 PER-557-PCTRESISTORS FOR CAPACITOR CORRELATION SYSTEMS AND METHODSArpita Moghe Chadha and Tero RantaCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and prionty to U.S. Provisional Patent Application No. 63 / 737,601 filed December 20, 2024 and entitled “RESISTORS FOR CAPACITOR CORRELATION SYSTEMS AND METHODS,” which is incorporated herein by reference in their entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to resistors and capacitors, and more particularly for example to resistors for capacitor correlation systems and methods.BACKGROUND

[0003] Modem electronic devices may incorporate electronic components designed to operate within certain parameters. Passive components such as resistors, inductors, and capacitors may be used in circuitry for applications including filtering, impedance matching, biasing, and so forth. Such applications may include circuitry with passive components designed and formed to have appropriate resistances, inductances, and / or capacitances while mitigating effects associated with any exhibited parasitics (e.g., parasitic resistances, capacitances, inductances).SUMMARY

[0004] In one or more embodiments, an integrated circuit includes a resistor. The resistor includes a resistive structure disposed on a plurality of integrated circuit metal layers and having a pattern. The resistive structure includes a first conductive layer with the pattern and a second conductive layer with the pattern. The patterns on the first and second conductive layers are aligned and overlap each other. The integrated circuit also includes a via connecting the first and second conductive layers serially.

[0005] In one or more embodiments, a method includes measuring a first current through a resistor on an integrated circuit. The resistor includes a resistive structure disposed on a plurality7of integrated circuit metal layers and having a pattern. The resistive structure6165864WO01 PER-557-PCT includes a first conductive layer with the pattern and a second conductive layer with the pattern. The resistor further includes a via connecting the first and second conductive layers serially. The patterns on the first and second conductive layers are aligned and overlap each other. The method further includes measuring a second current through a test path. The method further includes determining a resistance associated with the resistor based at least on the first current and the second current.

[0006] The scope of the disclosure is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present disclosure will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 illustrates an integrated circuit for facilitating correlation between resistance and capacitance in accordance with one or more embodiments of the present disclosure.

[0008] FIG. 2 illustrates an example resistive structure of a resistor in accordance with one or more embodiments of the present disclosure.

[0009] FIG. 3 illustrates an example equivalent resistance circuit of the resistive structure of FIG. 2 in accordance with one or more embodiments of the present disclosure.

[0010] FIG. 4 illustrates an example capacitive structure of a capacitor in accordance with one or more embodiments of the present disclosure.

[0011] FIG. 5 illustrates a cross-sectional view of two layers of a capacitive structure in accordance with one or more embodiments of the present disclosure.

[0012] FIG. 6 illustrates a top view of a layout of a resistive structure of a resistor in accordance with one or more embodiments.

[0013] FIG. 7 illustrates a top view of a layout of a capacitive structure of a capacitor that correlates with the resistive structure associated with the top view of FIG. 6 in accordance with one or more embodiments of the present disclosure.

[0014] FIG. 8 illustrates an example system for determining a resistance value of a resistor in accordance with one or more embodiments of the present disclosure.6165864WO01 PER-557-PCT

[0015] FIG. 9 illustrates a flow diagram of an example process for measuring a resistance of a resistor and correlating the resistance to a capacitance of a capacitor in accordance with one or more embodiments of the present disclosure.

[0016] FIG. 10 illustrates an example system for determining a capacitance of a capacitive structure of a capacitor in accordance with one or more embodiments of the present disclosure.

[0017] FIG. 11 illustrates a graph showing a relationship between a resistance of a resistor and a capacitance of a correlated capacitor in accordance with one or more embodiments of the present disclosure.

[0018] Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It is noted that sizes of various components and distances between these components are not draw n to scale in the figures. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.DETAILED DESCRIPTION

[0019] The detailed description set forth below is intended as a description of various configurations of the subject technology and is not intended to represent the only configurations in which the subject technology can be practiced. The appended drawings are incorporated herein and constitute a part of the detailed description. The detailed description includes specific details for the purpose of providing a thorough understanding of the subject technology. However, it will be clear and apparent to those skilled in the art that the subject technology is not limited to the specific details set forth herein and may be practiced using one or more embodiments. In one or more instances, structures and components are show n in block diagram form in order to avoid obscuring the concepts of the subject technology. One or more embodiments of the subject disclosure are illustrated by and / or described in connection with one or more figures and are set forth in the claims.

[0020] In one or more embodiments, resistors for capacitor correlation systems and methods are provided. In one embodiment, a resistor may include a resistive structure having a pattern. The resistive structure may include conductive layers with the pattern and interlayer vias (e g., also referred to as intermetal layer vias or vias) disposed between the conductive layers. The patterns on the conductive layers may be aligned and overlap each other. The conductive layers and the interlayer vias may be formed of conductive material,6165864WO01 PER-557-PCT such as copper, aluminum, tungsten, or a combination thereof. In some cases, the resistor may have dielectric material between the conductive layers. As non-limiting examples, the dielectric material may include oxides (e.g., silicon dioxide, aluminum oxide), air, and / or other appropriate dielectric material. Such dielectric material may be referred to as an interlayer dielectric or an intermetal layer dielectric. In some aspects, the pattern may be a serpentine pattern (e.g., also referred to as a square-wave pattern). The serpentine pattern may define features (e.g., also referred to as fingers) within each conductive layer. In some cases, the resistor may have dielectric material (e.g., air, oxides, etc.) between sidewalls of the features. In some aspects, to serially connect the conductive layers, a single interlayer via may be disposed between adjacent conductive layers. In some cases, the resistive structure may have other patterns, such as a saw tooth pattern or a sinusoidal pattern, dependent on desired appli cati on / characteristi cs .

[0021] In some embodiments, the resistor may be correlated with a capacitor such that a resistance of the resistor correlates with (e.g., maps to) a capacitance of the capacitor. To provide such correlation, the capacitor, which may be referred to as a corresponding / correlated capacitor of the resistor and / or a capacitor correlated with the resistor, may have a capacitive structure that correlates with / corresponds to the resistive structure. The capacitive structure has conductive layers of interdigitated conductive features (e.g., fingers) and interlayer vias disposed between the conductive layers. The conductive layers may be aligned and overlap each other. Each conductive layer may include a first layer of conductive features and a second layer of conductive features to form a layer of interdigitated conductive features. The first layer of conductive features and the second layer of conductive features may extend from a first conductive line and a second conductive line, respectively. In some cases, the capacitor may have dielectric material (e.g., air, oxides, etc.) between the conductive layers and / or between sidewalls of the conductive features. Between any two adjacent conductive layers, a first interlayer via extends between the first conductive lines of the adjacent conductive layers and a second interlayer via extends between the second conductive lines of the adjacent conductive layers. In some aspects, such connections between adjacent conductive layers using the interlayer vias of the capacitor correlate with the serial connection between adjacent conductive layers using a single interlayer via of the capacitor. In some aspects, the capacitance of the capacitor may include a capacitive coupling effect betw een the conductive layers. The capacitive coupling effect may include an intralayer capacitive coupling effect (e.g., within a conductive layer such as between6165864WO01 PER-557-PCT sidewalls of the fingers) and an interlayer capacitive coupling effect (e.g., between the conductive layers separated by an intermetal layer distance).

[0022] In some embodiments, a resistor having a resistive structure according to embodiments herein may be referred to as a metal-oxide-metal (MOM) resistor or an RMOM, and a capacitor having a corresponding / correlated capacitive structure may be referred to as a MOM capacitor, a MOM cap, or a CMOM. MOM may generally refer to structures having conductive layers (e.g., metal layers or metallic layers) and insulator(s) (e.g., oxides and / or other insulative material) between the conductive layers. In this regard, in some embodiments, metal material / layer may refer to conductive material / layer and oxide material may refer to insulative / dielectric material / layer.

[0023] For the resistors and capacitors to correlate well, the number of conductive layers and material system utilized (e.g., conductive material(s), insulative material(s) to implement the resistors and capacitors may generally be designed to be the same between the resistors and the capacitors. In addition, dimensions and spacings associated with various aspects of the capacitive structure may be designed to be similar to or the same as dimensions and spacings associated with corresponding aspects of the resistive structure. In some cases, the capacitor and the resistor may be defined with the same conductive feature width (e.g., metal finger width) and the same spacing between conductive features as each other. In some cases, the resistor and the corresponding capacitor may be designed to have the same metal thickness for their conductive layers and the same spacing(s) between their conductive layers. For example, the resistor and the correlated / corresponding capacitor may each have a first conductive layer and a second conductive layer separated by the same distance i and the second conductive layer and a third conductive layer separated by the same distance di, where d\ and di may be the same or different from each other. In this regard, the resistance of the resistor may correlate well with the capacitance of the capacitor due to metal thickness and intermetal layer thickness being well correlated due to fabrication processes like deposition and chemical mechanical polishing (CMP).

[0024] In some cases, a computer-aided design (CAD) tool may have a capacitor (e.g., MOM capacitor) defined with certain parameters such as metal thickness(es), intermetal layer dielectric (IMD) thickness(es), finger width(s), finger spacing(s), and so forth. A corresponding / correlated resistor (e.g., MOM resistor) may be defined with these parameters. For example, the capacitor and the resistor may be designed to correlate well by defining / implementing the capacitor and the resistor to have the same finger width, the same6165864WO01 PER-557-PCT finger spacing, the same intermetal layer thickness(es), and the same metal thickness(es) as each other.

[0025] In some embodiments, a resistor may be implemented on an integrated circuit (IC). In such embodiments, a resistive structure of the resistor may be disposed on IC metal layers of the IC. Vias may each be an electrical connection between metal layers of an IC and may extend through one or more such IC metal layers. In some cases, the conductive layers may be disposed on adjacent IC metal layers with the via disposed between and connecting these adjacent IC metal layers. A capacitor correlated with such a resistor may have the same number of conductive layers. In some aspects, conductive layers of the capacitive structure may have features of the same width and the same spacing as the resistive structure, the same distances between the conductive layers, and on the same IC metal layers. In some cases, the resistor and the capacitor may be formed using similar processes (e.g., IC processes).

[0026] In some embodiments, the resistor may be correlated with a capacitor such that a resistance of the resistor correlates with (e.g., maps to) a capacitance of the capacitor. Using various embodiments, a determination (e.g., by performing associated measurements and / or computations) of the resistance of the resistor may be associated with less costs (e.g., less chip space, less time) than a determination of the capacitance of the capacitor corresponding to the resistor, as further described herein. In this regard, the capacitance may be determined by determining the resistance value of the corresponding resistor and then correlating / mapping the resistance value to a capacitance value (e.g., without using equipment to perform measurements on the capacitor).

[0027] In some aspects, a correlation / relationship between the resistance of the resistor and the capacitance of the correlated / corresponding capacitor may be provided via an equation(s), a lookup table(s), and / or others. In some cases, the correlation / relationship may be based on measurements / calibration data, such as data obtained through measurements of resistances of resistors as well as measurements of capacitances of corresponding capacitors, as further described herein. Such calibration data may provide a regression line that associates resistance values with capacitance values and / or a correlation coefficient (or correlation- squared coefficient) associated with the resistors and the capacitors. In some embodiments, an amount of correlation between resistances of resistors (e g., MOM resistors) and capacitances of capacitors (e.g., MOM capacitors) is generally application dependent. Higher correlation may be associated with applications that need better accuracy / estimates between the resistance values and their corresponding / correlated capacitance values and thus would6165864WO01 PER-557-PCT need beter control (e.g., tighter manufacturing tolerances) over physical characteristics (e.g., finger width, finger spacing, IMD thicknesses, etc.) of the resistors and the corresponding capacitors.

[0028] FIG. 1 illustrates an IC 100 for facilitating correlation between resistance and capacitance in accordance with one or more embodiments of the present disclosure. Not all of the depicted components may be required, however, and one or more embodiments may include additional components not shown in the figure. Variations in the arrangement and type of the components may be made without departing from the spirit or scope of the claims as set forth herein. Additional, fewer, and / or different components may be provided.

[0029] The IC 100 includes a resistor 105 (e.g., MOM resistor), a measurement circuit 110, and a capacitor 115 (e.g., MOM capacitor). The resistor 105 may correlate with (e.g., correspond to) the capacitor 115. In some embodiments, to allow a strong correlation, the resistor 105 and the capacitor 115 may be designed with a similar or the same feature width, the same feature spacing, the same metal thickness(es), and the same intermetal layer thickness(es), as further described herein. A resistive structure of the resistor 105 may be disposed on IC metal layers of the IC 100. Vias may each be an electrical connection between metal layers of IC 100 and may extend through one or more such IC metal lay ers. In some cases, conductive layers of the resistor 105 may be disposed on adjacent IC metal layers with the via disposed between and connecting these adjacent IC metal layers. The capacitor 115 may have the same number of conductive layers disposed on the same IC metal layers and vias disposed between the conductive layers. In some cases, the resistor 105 and the capacitor 115 may be formed using similar processes (e.g., IC processes).

[0030] The measurement circuit 110 may determine a resistance of the resistor 105 through current-voltage (IV) measurements. The measurement circuit 110 may then determine (e.g., correlate) a capacitance of the capacitor 115 based on the resistance of the resistor 105. In some aspects, a correlation / relationship between the resistance of the resistor 105 and the capacitance of the capacitor 115 may be provided via an equation(s), a lookup table(s), and / or others.

[0031] In some aspects, a determination (e.g., by performing associated measurements and / or computations) of the resistance of the resistor 105 may be associated with less costs (e.g., less chip space, less time) than a determination of the capacitance of the capacitor 115 corresponding to the resistor 105. In this regard, the capacitance may be determined by6165864WO01 PER-557-PCT determining the resistance value of the resistor 105 and then correlating / mapping the resistance value to a capacitance value of the capacitor 115 (e.g., without using equipment to perform measurements on the capacitor 115).

[0032] It is noted that structures and / or portions thereof in the present disclosure may be described and / or depicted as equidistant, parallel, perpendicular, and so forth. Due to tolerances associated with dimensional aspects and / or fabrication processes / flows, such terms generally describe the structures and / or portions thereof in a nominal / substantial sense.

[0033] FIG. 2 illustrates an example resistive structure 200 of a resistor (e.g., MOM resistor) in accordance with one or more embodiments of the present disclosure. The resistive structure 200 extends along three directions (e.g., three orthogonal directions) x, y, and z, as shown by the coordinate system in FIG. 2. Not all of the depicted components may be required, however, and one or more embodiments may include additional components not shown in the figure. Variations in the arrangement and type of the components may be made without departing from the spirit or scope of the claims as set forth herein. Additional, fewer, and / or different components may be provided.

[0034] The resistive structure 200 includes conductive layers 205, 210. and 215, intermetal layer vias 220 and 225 (e.g., also referred to as interlayer vias or vias), and pins 230 and 235. An example length LR (e.g., along the y-direction) of the resistive structure 200 may be between approximately 30 pm and approximately 35 pm, although the length LR may be of other sizes as appropriate to support a desired resistance value. In general, a larger resistor (e.g., larger length (e.g., along y-direction) and / or larger width (e.g., along x direction)) is associated with larger resistance. The conductive layers 205, 210, and 215 are formed of conductive material. The conductive material may be selected from materials associated with a given manufacturing process (e.g., a given IC manufacturing process). As a non-limiting example, the conductive layers 205, 210, and 215 may be formed of metal, such as copper. The conductive layers 205, 210, and / or 215 may be formed of the same conductive material or different conductive material. An example thickness (e.g., along the z-direction) of the conductive layers 205, 210, and 215 may be between approximately 0.25 pm and approximately 0.4 pm.

[0035] The conductive layers 205. 210, and 215 are aligned and overlap each other. In this regard, the conductive layers 205, 210, and 215 are stacked (e.g., separated / displaced from each other) along the z-direction and parallel to the xy -plane. Along the z-direction, the6165864WO01 PER-557-PCT conductive layer 205 may be considered as being adjacent to the conductive layer 210, and the conductive layer 210 may be considered as being adjacent to the conductive layers 205 and 215. The conductive layers 205 and 210 may be separated from each other along the z- direction by a distance di and the conductive layers 210 and 215 may be separated from each other along the z-direction by a distance 2. In an aspect, the distances d\ and di may be referred as intermetal layer distances or intermetal layer spacing. The distance di may be the same or different from the distance di. An example distance di and di may be between approximately 0.30 pm and approximately 0.70 pm. In some IC technologies, the intermetal layer spacing di and di may be approximately 0.5 pm.

[0036] The resistive structure 200 has a serpentine pattern. The conductive layers 205, 210, and 215 have substantially the same serpentine pattern. As shown in FIG. 2, the serpentine pattern of each of the conductive layers 205, 210, and 215 are aligned and overlap each other such that the serpentine patterns are parallel (e.g., extending nominally / substantially along the same x- and y-coordinates) to each other and separated / displaced from each other along the z-direction.

[0037] As shown in FIG. 2, the conductive layer 215 is formed of features having (e.g., substantially / nominally having) a width wf and a distance / spacing sr. The spacing sr is a spacing between sidewalls of adjacent features and may be referred to as a sidewall spacing. Although not labeled in FIG. 2, the conductive layers 205 and 210 below (e.g., along the z- direction) the conductive layer 215 also have (e.g., substantially / nominally have) the same width wr and the same distance / spacing sr as the conductive layer 215. An example width wf may be between approximately 0. 15 pm and approximately 0.25 pm. An example spacing Sf may be between approximately 0. 15 pm and approximately 0.25 pm.

[0038] Each of the conductive layers 205, 210, and 215 has a first end and a second end. Each of the conductive layers 205, 210, and 215 may extend along the serpentine pattern between its first end and its second end. The first end of the conductive layer 205 may be coupled to the pin 230, and the second end of the conductive layer 205 may be coupled to the via 220. The second end of the conductive layer 210 may be coupled to the via 220, and the first end of the conductive layer 210 may be coupled to the via 225. The first end of the conductive layer 215 may be coupled to the via 225, and the second end of the conductive layer 215 may be coupled to the pin 235. In some aspects, the pin 230 (e.g., labeled PIN1) and the pin 235 (e.g., labeled PIN2) may be considered as and / or may be considered as being coupled to a first end and a second end, respectively, of the resistive structure 200 of the6165864WO01 PER-557-PCT resistor. Dependent on a voltage difference across the pins 230 and 235, a current may flow from the first end to the second end or from the second end to the first end of the resistive structure 200. It is noted that an index / identifier associated with a structure (e.g., a first end, a second end, etc.), such as an end of a resistive structure or a conductive layer identified as a first end or a second end, may be arbitrary and utilized for convenience in referring to ends of the structure.

[0039] The via 220 may be disposed between and contact the second end of the conductive layers 205 and 210. The via 225 may be disposed between and contact the first end of the conductive layers 210 and 215. The via 220 may provide a connection (e.g., an electrical connection) between the conductive layer 205 and the conductive layer 210. The via 225 provides a connection (e.g., an electrical connection) between the conductive layer 210 and the conductive layer 215. In this regard, the conductive layers 205 and 210 may be serially connected using the via 220 and the conductive layers 210 and 215 may be serially connected using the via 225 such that the conductive layers 205, 210, and 215 are serially connected. The vias 220 and 225 may be formed of conductive material, such as tungsten and / or copper. The vias 220 and / or 225 may be formed of the same conductive material or different conductive material.

[0040] In this regard, a length (e.g., along the z-direction) of the via 220 extends the distance d\ between the conductive layer 210 (e.g., a bottom surface of the conductive layer 210) and the conductive layer 205 (e.g., a top surface of the conductive layer 210 facing the bottom surface of the conductive layer 210). Similarly, a length of the via 225 extends the distance di between the conductive layer 215 (e.g., a bottom surface thereof) and the conductive layer 210 (e.g.. a top surface thereof facing the bottom surface of the conductive layer 215).

[0041] In some embodiments, the resistive structure 200 may be used to facilitate correlation with a corresponding capacitive structure. To facilitate the correlation, the resistive structure 200 may also include one or more dielectric materials between the conductive layer 205 and the conductive layer 210, between the conductive layer 210 and the conductive layer 215, and between sidewalls (e.g., dielectric material of thickness Sf) within each of the conductive layers 205, 210, and 215. In an aspect, the distances di and di may be referred as IMD thickness. In an aspect, the resistor having the resistive structure 200 may be referred to as a MOM resistor due to its correlation with a MOM capacitor, as further6165864WO01 PER-557-PCT described herein, and / or having a structure with conductive layers and dielectric material(s) between the conductive lavers.

[0042] As further described herein, the corresponding capacitive structure has conductive layers corresponding to the conductive layers 205, 210, and 215 and interdigitated features that correspond to the features of the conductive layers 205, 210, and 215. The interdigitated features of the capacitive structure have the same width wf and the same spacing sr as the resistive structure 200. Dielectric material may be disposed between sidewalls of the interdigitated features and / or between conductive layers of the capacitive structure. In an aspect, such features of the conductive layers 205, 210, and 215 may be referred to as fingers, since these features of the resistive structure 200 are associated with fingers of a capacitive structure corresponding to the resistive structure 200, as further described herein. As such, the width wf may be referred to as a finger width and / or a finger thickness and the distance / spacing sr may be referred to as a finger spacing. In some aspects, a capacitance of the capacitive structure may correlate well with the resistance of the resistive structure 200 when the capacitive structure and the resistive structure 200 have the same number of conductive layers, utilize the same or similar material system (e.g., for its conductive layers and dielectrics), have the same or similar width wf, have the same or similar spacing Sf as each other, have the same or similar metal thickness, and have the same or similar corresponding IMD thickness (e.g., t / i of the capacitive structure and the resistive structure 200 are the same or similar, di of the capacitive structure and the resistive structure 200 are the same or similar).

[0043] In some embodiments, the resistor 200 may be implemented on an IC, such as the IC 100 of FIG. 1. In such embodiments, the resistive structure of the resistor 200 may be disposed on IC metal layers of the IC. The vias 220 and 225 may each be an electrical connection between metal layers of an IC and may extend through one or more such IC metal layers. In some cases, the conductive layers 205 and 210 may be disposed on adjacent IC metal layers with the via 220 disposed between and connecting these adjacent IC metal layers, and / or the conductive layers 210 and 215 may be disposed on adjacent IC metal layers with the via 225 disposed between and connecting these adjacent IC metal layers.

[0044] FIG. 3 illustrates an example equivalent resistance circuit 300 (e g., also referred to as an equivalent resistance representation) of the resistive structure 200 in accordance with one or more embodiments of the present disclosure. Not all of the depicted components may be required, however, and one or more embodiments may include additional components not6165864WO01 PER-557-PCT shown in the figure. Variations in the arrangement and type of the components may be made without departing from the spirit or scope of the claims as set forth herein. Additional, fewer, and / or different components may be provided.

[0045] The equivalent resistance circuit 300 includes representations (e.g., equivalent circuit models / representations) of the conductive layers 205, 210, and 215, the vias 220 and 225, and the pins 230 and 235. The conductive layers 205, 210, and 215 are represented by resistors RCLI, RCL2, and RCLS, respectively. The resistors RCLI and RCL2 are serially connected by a line 320 that represents the via 220. The resistors RCL2 and RCLI are serially connected by a line 325 that represents the via 225. The resistors RCLI, RCL2, and RCL3 and the lines 320 and 325 extend between and couple to pins 330 and 335 that represent the pins 230 and 235, respectively. A resistance of the equivalent resistance circuit 300 may be, or may be indicative of. a resistance of the resistive structure 200. In some aspects, the resistance of the equivalent resistance circuit 300 may be determined as a sum of resistances of the resistors RCLI, RCL2, and RCL3. Dependent on a voltage difference across the pins 330 and 335, a current may flow in a direction from the pin 330 to the pin 335 or a direction from the pin 335 to the pin 330.

[0046] In some embodiments, a resistance of a resistor’s resistive structure, such as the resistance of the resistive structure 200 and the equivalent resistance circuit 300 illustrated in FIGS. 2 and 3, respectively, may be correlated with (e.g., mapped to) a capacitance of a capacitive structure of a capacitor, as further described herein. In this regard, the resistive structure may have a corresponding capacitive structure whose capacitance can be determined by determining the resistance of the resistive structure. In some aspects, the capacitance of the capacitive structure may be difficult to determine / measure and, as such, the capacitance of the capacitive structure may be determined by determining the resistance of the resistive structure. In some aspects, a correlation / relationship between the resistance of the resistive structure and the capacitance of the capacitive structure may be provided via an equation(s), a lookup table(s), and / or others.

[0047] FIG. 4 illustrates an example capacitive structure 400 of a capacitor (e.g., MOM capacitor) in accordance with one or more embodiments of the present disclosure. The capacitive structure 400 extends along three directions (e.g., three orthogonal directions) x, y, and z, as shown by the coordinate system in FIG. 4. Not all of the depicted components may be required, however, and one or more embodiments may include additional components not shown in the figure. Variations in the arrangement and type of the components may be made6165864WO01 PER-557-PCT without departing from the spirit or scope of the claims as set forth herein. Additional, fewer, and / or different components may be provided.

[0048] The capacitive structure 400 includes conductive layers 405, 410, and 415, interlayer vias 485 A and 485B between the conductive layers 405 and 410. and interlayer vias 490A and 490B between the conductive layers 410 and 415. In an aspect, each of the conductive layers 405, 410, and 415 may be referred to as a layer or a plate. An example length Lc (e.g., along the y-direction) of the capacitive structure 400 may be between 20 pm and 25 pm. although the length Lc may be of other sizes as appropriate to support a desired capacitance value. In general, a larger capacitor (e.g., larger length (e.g., along y-direction) and / or larger width (e.g., along x direction)) is associated with larger capacitance.

[0049] The conductive layers 405, 410, and 415 are formed of conductive material. The conductive material may be selected from materials associated with a given manufacturing process (e.g., a given IC manufacturing process). As a non-limiting example, the conductive layers 405, 410, and 415 may be formed of metal, such as copper. The conductive layers 405, 410, and / or 415 may be formed of the same conductive material or different conductive material.

[0050] The conductive layer 405 includes conductive lines 430 and 435 and conductive fingers extending from the conductive lines 430 and 435. The conductive fingers extending from the conductive line 430 are interdigitated with the conductive fingers extending from the conductive lines 435 to collectively provide interdigitated fingers of the conductive layer 405. As examples of the conductive fingers, conductive fingers 440A and 440B are two of the fingers that extend from the conductive line 430, conductive fingers 445A and 445B are two of the fingers that extend from the conductive line 435, and so forth for other fingers of the conductive layer 405.

[0051] The conductive layer 410 includes conductive lines 450 and 455 and conductive fingers extending from the conductive lines 450 and 455. The conductive fingers extending from the conductive line 450 are interdigitated with the conductive fingers extending from the conductive lines 455 to collectively provide interdigitated fingers of the conductive layer 410. As examples of the conductive fingers, conductive fingers 460A and 460B are two of the fingers that extend from the conductive line 450, conductive fingers 465A and 465B are two of the fingers that extend from the conductive line 455, and so forth for other fingers of the conductive layer 410.6165864WO01 PER-557-PCT

[0052] The conductive layer 415 includes conductive lines 470 and 475 and conductive fingers extending from the conductive lines 470 and 475. The conductive fingers extending from the conductive line 470 are interdigitated with the conductive fingers extending from the conductive lines 475 to collectively provide interdigitated fingers of the conductive layer 415. As examples of the conductive fingers, conductive fingers 475A and 475B are two of the fingers that extend from the conductive line 470, conductive fingers 480A and 480B are two of the fingers that extend from the conductive line 475, and so forth for other fingers of the conductive layer 415.

[0053] The interlayer via 485A may be disposed between and contact the conductive line 450 of the conductive layer 410 and the conductive line 430 of the conductive line 405. The interlayer via 485B may be disposed between and contact the conductive line 455 of the conductive layer 410 and the conductive line 435 of the conductive line 405. The interlayer vias 485 A and 485B may provide a connection between the conductive layers 405 and 410. The interlayer via 490A may be disposed between and contact the conductive line 470 of the conductive layer 415 and the conductive line 450 of the conductive line 410. The interlayer via 495A may be disposed between and contact the conductive line 475 of the conductive layer 415 and the conductive line 455 of the conductive line 410. A height of the interlayer vias 485A and 485B may be approximately the same as the distance d\ between the conductive layers 405 and 410. A height of the interlayer vias 490A and 490B may be approximately the same as the distance di between the conductive layers 410 and 415. In some cases, a length (e.g., along the x-direction) of the interlayer vias 485A, 490A, 485B, and 490B may span a substantial length (e.g., half or more of the length) of the conductive lines 430, 435, 450, 455, 470, and 475. The interlayer vias 490A and 490B may provide a connection between the conductive layers 410 and 415. The interlayer vias 485A, 485B, 490A, and 490B may be formed of conductive material, such as tungsten and / or copper. The interlayer vias 485 A. 485B, 490A. and / or 490B may be formed of the same conductive material or different conductive material.

[0054] As shown in FIG. 4, the conductive layer 415 have interdigitated fingers having a width wf and a distance / spacing Sf. As examples, each of the fingers 475A, 475B, 480A, and 480B may have (e.g., nominally / substantially have) the same width wf, the finger 475A and the finger 480A are adjacent fingers spaced / separated apart by the spacing sf, and the finger 475B and the finger 480B are adjacent fingers spaced / separated apart by the spacing sr Similarly, the conductive layers 405 and 410 below (e.g., along the z-direction) the6165864WO01 PER-557-PCT conductive layer 415 may also have interdigitated fingers having (e.g., substantially / nominally having) the width wf and the distance / spacing sf.

[0055] Dielectrics may be disposed between the conductive layers 405 and 410 (e.g. , within the intermetal layer spacing d\), between the conductive layers 410 and 415 (e.g., within the intermetal layer spacing di), and / or within the conductive layers 405, 410, and 415 (e.g., between sidew alls of interdigitated fingers, such as between sidewalls of the fingers 475 A and 480A and betw een sidew alls of the fingers 440B and 445B). The capacitance of the capacitive structure 400 is produced by a capacitive coupling effect between the conductive layers 405, 410, and 415. In some cases, the capacitive coupling effect may include intralayer coupling (e.g., predominantly in some cases) and interlayer coupling.

[0056] In some aspects, the conductive line 430, the interlayer via 485 A, the conductive line 450, the interlayer via 490A, and the conductive line 470 may together form a terminal (e.g., a cathode or an anode) of the capacitive structure 400. The conductive line 435, the interlayer via 485B, the conductive line 455, the interlayer via 490B, and the conductive line 475 may together form another terminal (e.g., an anode or a cathode) of the capacitive structure 400.

[0057] As shown by the resistive structure 200 and the capacitive structure 400, while the resistive structure 200 has a single interlayer via between adjacent conductive layers, the capacitive structure 400 has a pair of interlayer vias between adjacent conductive layers. The serially connected conductive layers of the resistive structure 200 correlates with the capacitive structure 400 in which adjacent conductive layers are connected using a pair of interlayer vias.

[0058] In some embodiments, a resistive structure and its corresponding capacitive structure in accordance with one or more embodiments herein have a resistance and a capacitance, respectively, that correlate with (e.g., correspond to) each other. In this regard, if a resistance of the resistive structure is determined, this resistance may correlate with (e.g., correspond to, map to) a capacitance of the capacitive structure. Similarly, if a capacitance of the capacitive structure is determined, this capacitance may correlate with (e.g., correspond to, map to) a resistance of the capacitive structure. In some cases, determining a capacitance of a capacitive structure may be more complex (e.g., measurement circuit may involve more measurements and / or more time and / or occupy more chip area). As such, determination (e.g., measurement) of a resistance of a resistive structure that correlates wdth (e.g., corresponds to)6165864WO01 PER-557-PCT the desired capacitive structure may facilitate determination of the capacitance of the capacitive structure.

[0059] In some cases, when a resistive structure (e.g., the resistive structure 200) is designed to correlate with a capacitive structure (e.g.. the capacitive structure 400), and / or vice versa, the width wf and the spacing sr of the resistive structure and the capacitive structure are nominally the same. An example width wf of the resistive structure and the capacitive structure may be between approximately 0.15 pm and approximately 0.25 pm. An example spacing sf of the resistive structure and the capacitive structure may be between approximately 0. 15 pm and approximately 0.25 pm. Whereas the width wf and the spacing Sf of the resistive structure 200 and the capacitive structure 400 are nominally the same to facilitate correlation, the length and total width of the resistive structure and the capacitive structure correlated with the resistive structure may vary’ from each other and may be based on desired resistance and desired capacitance, respectively. An example length (e.g., along the y-direction) of the resistive structure may be between approximately 30 pm and approximately 35 pm. An example length (e.g., along the y-direction) of the capacitive structure that correlates with the resistive structure may be between 20 pm and 25 pm.

[0060] Although in the foregoing (e.g., in FIGS. 2 and 4) each conductive layer has (e.g., substantially / nominally has) the same width wf and the same spacing Sf, in some embodiments, each conductive layer may have its own respective width and / or its own respective spacing that may be the same or different as those of other conductive layers. In such embodiments, each conductive layer of a resistive structure may have (e.g., substantially / nominally have) the same width and the same spacing as the corresponding conductive layer of a capacitive structure correlated with the resistive structure.

[0061] Furthermore, although the foregoing illustrates a resistive structure and a capacitive structure having uniform widths wr and spacing Sf, the pattern may include nonuniform widths and spacing and / or different patterns in different conductive layers. For better correlation, the nonuniform widths and / or spacing may be consistent between the resistive structure and the capacitive structure.

[0062] FIG. 5 illustrates a cross-sectional view of two layers of a capacitive structure 500 in accordance with one or more embodiments of the present disclosure. The capacitive structure 500 includes conductive layers 505 and 510. It is noted the cross-sectional view of FIG. 5 shows a portion of the capacitive structure 500. The conductive layer 505 includes a6165864WO01 PER-557-PCT conductive line 530 and conductive fingers extending from the conductive line 530. Each of the conductive fingers have a width wf. As examples of the conductive fingers, conductive fingers 540A and 540B are two of the fingers that extend from the conductive line 530. Conductive fingers 545A and 545B may be two of the fingers that extend from another conductive line (not shown) of the conductive layer 505. Sidewalls (e.g., the closest sidewalls) of two adjacent conductive fingers associated with different conductive lines (e.g., the conductive fingers 540A and 545A are adjacent to each other) are spaced apart (e.g., along the x-direction) by a spacing sf.

[0063] The conductive layer 510 is separated from the conductive layer 505 by a distance d. The conductive layer 510 has components similar / corresponding to those of the conductive layer 505. The conductive layer 510 includes a conductive line 550 and conductive fingers extending from the conductive line 550. Each of the conductive fingers have a width wf. As examples of the conductive fingers, conductive fingers 560A and 560B are two of the fingers that extend from the conductive line 550. Conductive fingers 565A and 565B may be two of the fingers that extend from another conductive line (not shown) of the conductive layer 510. Sidewalls (e.g., the closest sidewalls) of two adjacent conductive fingers associated with different conductive lines (e.g., the conductive fingers 565A and 560B are adjacent to each other) are spaced apart (e.g., along the x-direction) by a spacing sf. As shown in FIG. 5, the conductive line 530 and the conductive fingers (e.g., 540 A, 540B) extending from the conductive line 530 may be an integral / continuous structure / material, and the conductive line 550 and the conductive fingers (e.g., 560 A, 560B) extending from the conductive line 550 may be an integral / continuous structure / material.

[0064] Dielectric material (e.g., also referred to as a dielectric layer) is disposed between corresponding conductive fingers of the conductive layers 505 and 510. These corresponding conductive fingers are displaced from each other only along the z-direction. As examples, the conductive finger 540A of the conductive layer 505 corresponds to the conductive finger 560A of the conductive layer 510, the conductive finger 545A of the conductive layer 505 corresponds to the conductive finger 565 A of the conductive layer 510, and so forth. As an example, a dielectric layer 580 (e.g., an interlayer dielectric) is between the conductive layers 505 and 510 within the spacing / separation d between the conductive layers 505 and 510. Other pairs of corresponding conductive fingers (e.g., 545A and 565 A, 540B and 560B, etc.) may also have a dielectric layer between them. Although not shown in FIG. 5. dielectric material may be optionally disposed between adjacent conductive fingers of the conductive6165864WO01 PER-557-PCT layer 505 and / or between adjacent conductive fingers of the conductive layer 510. A capacitance of the capacitive structure 500 may be produced by a capacitive coupling effect between the conductive layers 505 and 510. In some cases, the capacitive coupling effect may include intralayer coupling (e.g., predominantly in some cases) and interlayer coupling. Furthermore, although not shown in FIG. 5, a via may be disposed betw een the conductive lines 530 and 550 of the conductive layers 505 and 510. respectively, to connect the conductive layers 505 and 510.

[0065] The capacitive structure 500 may include more than two layers. In this regard, the capacitive structure 500 may include one or more conductive layers and dielectric material above the conductive layer 510 and / or one or more conductive layers and dielectric material below' the conductive layer 505. In some cases, as with the adjacent conductive layers 505 and 510, any two adjacent conductive layers may include dielectric material between the adjacent conductive layers and / or dielectric layers between features (e.g., fingers) of the conductive layers.

[0066] The description of the capacitive structure 400 of FIG. 4 generally applies to the capacitive structure 500 of FIG. 5. In some embodiments, the capacitive structure 500 may be, or may correspond to, a portion of the capacitive structure 400. In this regard, the conductive layers 505 and 510 may be, or may correspond to. any two adjacent conductive layers among the conductive layers 405, 410, and 415 of the capacitive structure 400. In this case, an example width wf may be between approximately 0.15 pm and approximately 0.25 pm. An example spacing sr may be betw een approximately 0.15 pm and approximately 0.25 pm. An example thickness t of the conductive layers 505 and 510 may be betw een approximately 0.25 pm and approximately 0.4 pm. As shown in FIG. 5, the conductive lines 530 and 550 and their associated conductive fingers may have the same thickness t. An example distance d may be between approximately 0.30 pm and approximately 0.70 pm. In some IC technologies, the intermetal layer spacing d may be approximately 0.5 pm.

[0067] FIG. 6 illustrates a top view' 600 of a layout of a resistive structure of a resistor in accordance with one or more embodiments. The top view- 600 shows a topmost conductive layer 615 and ends 630 and 635 of the resistive structure. In some embodiments, the resistive structure of FIG. 6 may have two or more conductive layers that are aligned and overlap each other, such that one or more conductive layers are below (e.g., along the z-direction) the topmost conductive layer 615 and thus obscured / covered in the top view 500 by the topmost conductive layer 615. Adjacent conductive layers may be connected using an interlayer via.6165864WO01 PER-557-PCTEach of the topmost conductive layer 615 and the conductive layer(s) below the topmost conductive layer 615 may have features (e.g., fingers) having a width wf and a spacing sf.

[0068] An example length LR (e g., along the y-direction) of the resistive structure may be between approximately 30 pm and approximately 35 pm. An example width WR (e.g., along the x-direction) of the resistive structure may be between approximately 5 pm and approximately 10 pm. Each of the ends 630 and 635 may be or may be coupled to a pin. The end 630 may be a part of and / or may be coupled to a bottommost conductive layer of the resistive structure. The end 635 may be a part of and / or may be coupled to the topmost conductive layer 615. The resistive structure associated with the top view 600 of FIG. 6 has a serpentine pattern similar to that of the resistive structure 200 of FIG. 2, with the resistive structure associated with the top view 600 of FIG. 6 having more bends and turns than the resistive structure 200. In this regard, the resistive structure 200 of FIG. 2 may be associated with a layout having a top view similar to the top view 600 except with fewer bends and turns than the serpentine pattern shown in the top view 600. As such, the description of FIG. 2 generally applies to FIG. 6. In some cases, example ranges of the width wf, the spacing sr, and the interlayer spacing (e.g., cZi, di, etc.) of the resistive structure associated with the top view 600 may correspond with those example dimensions provided with respect to the resistive structure 200.

[0069] FIG. 7 illustrates a top view 700 of a layout of a capacitive structure of a capacitor that correlates with (e.g., corresponds to) the resistive structure of the resistor of FIG. 6 in accordance with one or more embodiments of the present disclosure. The description of FIG. 2 pertaining to the resistive structure 200 generally applies to FIG. 6 and the description of FIG. 4 pertaining to the capacitive structure 400 generally applies to FIG. 7. The top view 700 shows a topmost conductive layer of the capacitive structure. The topmost conductive layer forms a part of capacitor terminals 705 and 710 and includes interdigitated fingers. The terminals 705 and 710 may be a cathode and an anode, respectively, of the capacitive structure. In some embodiments, the capacitive structure of FIG. 6 may have two or more conductive layers that are aligned and overlap each other, such that one or more conductive layers are below (e.g., along the z-direction) the topmost conductive layer and thus obscured / covered in the top view 600 by the topmost conductive layer.

[0070] An example length Lc (e.g., along the y-direction) of the capacitive structure may be between approximately 20 pm and approximately 25 pm. For each conductive layer, the interdigitated fingers of the conductive layer extend from conductive lines of the capacitor6165864WO01 PER-557-PCT terminals 705 and 710. As examples, fingers 715A and 715B are two of the fingers that extend from a conductive line of the capacitor terminal 705, fingers 720A and 720B are two of the fingers that extend from a conductive line of the capacitor terminal 710, and so forth for other fingers of the capacitive structure.

[0071] As shown in FIG. 7, the topmost conductive layer has interdigitated fingers having the same width wr and the same distance / spacing sr as the features / fingers of the topmost conductive layer 615 of the resistive structure associated with the top view 600. As examples, each of the fingers 715A, 715B, 720A, and 720B may have (e.g., nominally / substantially have) the same width wf, the finger 715 A and the finger 720A are adjacent fingers spaced / separated apart by the spacing sr, and the finger 715B and the finger 720B are adjacent fingers spaced / separated apart by the spacing sr. Similarly, the conductive layers below (e.g., along the z-direction) the topmost conductive layer also have interdigitated fingers having (e.g., substantially / nominally having) the width wf and the distance / spacing sr

[0072] Adjacent conductive layers may be connected using a pair of interlayer via. A first interlayer via may be part of the capacitor terminal 705 and a second interlayer via may be part of the capacitor terminal 710. Each of the topmost conductive layer 715 and the conductive layer(s) below the topmost conductive layer 715 may have features (e.g., fingers) having a width wf and a spacing Sf. In some embodiments, the number of conductive layers of the capacitive structure associated with the top view 700 is the same as the number of conductive layers of the resistive structure associated with the top view 600 of FIG. 6 (e.g., to allow better correlation).

[0073] FIG. 8 illustrates an example system 800 for determining a resistance value of a resistor Are in accordance with one or more embodiments of the present disclosure. Not all of the depicted components may be required, however, and one or more embodiments may include additional components not shown in the figure. Variations in the arrangement and type of the components may be made without departing from the spirit or scope of the claims as set forth herein. Additional, fewer, and / or different components may be provided.

[0074] The system 800 includes the resistor Are, a measurement circuit 805, and a voltage source 810. The resistor Aramay be considered as and / or referred to as a part of the measurement circuit 805 (as shown in FIG. 8) and / or coupled to the measurement circuit 805. In some embodiments, the resistor / G may have the resistive structure 200 of FIG. 2 and / or a6165864WO01 PER-557-PCT resistive structure associated with the top view 600 of FIG. 6. In some aspects, the measurement circuit 805 may be a part of a test multiplexer (mux). In other aspects, the measurement circuit 805 and the voltage source 810 may be part of the test mux. A resistor RPmay represent an external parasitic resistance.

[0075] The measurement circuit 805 includes transistors Ti and T2. The transistors Ti and T2 may be operated as switches that may be in an on state (e.g., also referred to as a conducting state) or an off state (e g., also referred to as a non-conducting state) based on a control signal applied to terminals 825 and 830, respectively. When the transistors Ti and T2 are turned on (e.g., set to the on state), the transistors Ti and T2 have an on state resistance Ron (e.g., also referred to simply as an on resistance). In some aspects, the transistors Ti and T2 may be substantially / nominally identical transistors such that they can be considered to have identical properties, such as the same on resistance. As a non-limiting example, the transistors may be n-type metal-oxide-semiconductor field effect transistors (NMOSFETs), as shown in FIG. 8, p-type MOSFETs, and / or other transistors. In such an example, the transistors Ti and T2 may be referred to as switch FETs and the terminals 825 and 830 are gate terminals of the transistors Ti and T2, respectively. A state of each of the transistors Ti and T2 may be controlled by a control circuit. The control circuit may include drivers (e.g., gate drivers that provide control voltages to the terminals 825 and 830 for the transistors Ti and T2, respectively), level shifters, and logic for controlling the drivers and the level shifters. For a given driver (e g., gate driver), the driver is generally disposed in proximity to the transistor whose state is controlled by the driver.

[0076] The measurement circuit 805 includes pins 815 and 820. The pin 820 may be a ground pin coupled to ground. The measurement circuit 805 includes current paths (e.g., also referred to as current branches, test paths, test branches, paths, branches) connected betw een the pins 815 and 820. A first current path includes the resistor R,sand the transistor Ti. A second current path includes the transistor T2. The second current path is connected in parallel with the first current path.

[0077] The measurement circuit 805 may facilitate determination (e.g., measurement) of the resistance of the resistor Rrsusing IV measurements. The voltage source 810 may be coupled to the pins 815 and 820 and apply a direct current (DC) voltage V across the pins 815 and 820 to allow?determination of the resistance of the resistor R,s. The voltage source 810 may be test equipment selectively coupled to the pins 815 and 820 when the resistance of the resistor / ty is to be determined. During a measurement mode (e.g., also referred to as a test6165864WO01 PER-557-PCT mode), the DC voltage stimulus V may be applied to the pin 815. In a first state / phase of the measurement mode, the transistor Ti is on and the transistor T2 is off. In a second state / phase of the measurement mode, the transistor Ti is off and the transistor T2 is on. It is noted that the index / identifier associated with a state / phase (e.g., a first state / phase, a second state / phase) may be arbitrary and utilized for convenience. In this regard, the first state / phase of the measurement mode may be performed before or after the second state / phase of the measurement mode.

[0078] For explanatory’ purposes, the transistors Ti and T2 may be considered to be substantially / nominally identical transistors such that they can be considered to have identical properties, such as the same on resistance Ron. In the first state / phase of the measurement mode, the transistor Ti is on and the transistor T2 is off to allow a current flow7Zi through the first current path and substantially / nominally no current flow through the second current path. The current Zi may be measured using appropriate test equipment coupled to the first current path. In the first state / phase, the current / 1 may be related to the applied voltage V and resistances of the first current path through the following equation: Equation (1)

[0079] Using Equation ( 1), a resistance Ri may be defined as an equivalent resistance associated with the first current path and provided by: Equation (2)

[0080] In the second state / phase of the measurement mode, the transistor Ti is off and the transistor T2 is on to allow a current flow 72 through the second current path and substantially / nominally no current flow through the first current path. The current I2 may be measured using appropriate test equipment coupled to the second current path. In the second state / phase, the current h may be related to the applied voltage V and resistance of the second current path through the following equation: Equation (3)

[0081] As such, from Equation (3), the on-resistance of the transistor T2 (and the transistor Ti) may be provided by: Equation (4)6165864WO01 PER-557-PCT

[0082] Using the measured currents h and h and the known voltage value V applied by the voltage supply 810, the resistance of the resistor Rrsmay be provided by:Rrs=i ~ on Equation (5)

[0083] In Equation (5), the resistance Ron may be subtracted from the / i to zero out any external series resistance in the measurement path in addition to correcting for the resistance of the transistors Ti and T2. The resistance of the resistor Rrsmay then be used to determine a capacitance associated with a capacitor that correlates with (e.g., corresponds to) the resistor Rrs. In some aspects, a correlation / relationship between the resistance of the resistor / G and the capacitance of the capacitor may be provided via an equation(s), a lookup table(s), and / or others. In some cases, the correlation / relationship may be based on calibration data, such as data obtained through measurements of resistances of resistors as well as measurements of capacitances of corresponding capacitors, as further described herein.

[0084] FIG. 9 illustrates a flow diagram of an example process 900 for measuring a resistance of a resistor (e.g., MOM resistor) and correlating the resistance to a capacitance of a capacitor (e.g., MOM capacitor) in accordance with one or more embodiments of the present disclosure. For explanatory purposes, the process 900 is primarily described herein with reference to the system 800, although the process 900 can be performed in relation to other systems. Note that one or more operations in FIG. 9 may be combined, omitted, and / or performed in a different order as desired.

[0085] At block 905, the current h through the resistor Rrsis measured. The current Zi may be measured when the voltage V from the voltage source 805 is applied across the pins 810 and 815, the transistor Ti is turned on, and the transistor T2 is turned off. The current measurement may be performed by test equipment coupled to the first test path that includes the resistor Rrsand the transistor Ti. At block 910, the current h through the second test path is measured. The current h may be measured when the voltage V from the voltage source 805 is applied across the pins 810 and 815, the transistor Ti is turned off. and the transistor T2 is turned on. The current measurement may be performed by test equipment coupled to the second test path that includes the transistor T2.

[0086] At block 915, the resistance of the resistor Rrsis determined based on the currents h and h. In some cases, the resistance of the resistor Rrsmay be determined by determining 7?i based on the known voltage V and the measured current Zi according to Equation (2), determining Ron based on the known voltage V and the measured cunent h according to6165864WO01 PER-557-PCTEquation (4), and then determining the resistance of the resistor Rrsaccording to / i and Ron according to Equation (5). At block 920, the capacitance of the capacitor associated with the resistor is determined based on the resistance of the resistor ™ determined at block 915. In some aspects, the capacitance may be determined using a correlation / relationship (e.g., an equation(s), a lookup table(s), etc.) between resistances of resistors (e.g., MOM resistors) and capacitances of capacitors (e.g., MOM capacitors).

[0087] In some embodiments, to correlate a resistive structure of a resistor with a corresponding capacitive structure of a capacitor, measurements may be performed on the resistance of the resistor and the capacitance of the capacitor. In some aspects, a correlation(s) / relationship(s) between the resistance of the resistive structure and the capacitance of the capacitive structure may be determined from such measurements and provided via an equation(s), a lookup table(s). and / or others. In an embodiment, such correlation(s) / relationship(s) may then be used to determine capacitances of capacitors based on resistances of corresponding resistors and without measuring the capacitors.

[0088] FIG. 10 illustrates an example system 1000 for determining a capacitance of a capacitive structure of a capacitor 1005 in accordance with one or more embodiments of the present disclosure. In some embodiments, the capacitance of the capacitor 1005 may correlate with a resistance of the resistor Rrsdetermined through measurements performed using the system 800 of FIG. 8. Not all of the depicted components may be required, however, and one or more embodiments may include additional components not shown in the figure. Variations in the arrangement and type of the components may be made without departing from the spirit or scope of the claims as set forth herein. Additional, fewer, and / or different components may be provided.

[0089] The system 1000 includes an analog portion 1010 that includes the capacitor 905 and a digital portion 1015 of an external digital block. The analog portion 1010 may include a voltage divider 1020 and an oscillator circuit 1025 including the capacitor 1005. The digital portion 1015 may include a counter circuit 1030 that receives an output of the oscillator circuit 1025. The output of the oscillator circuit 1025 may also be received by a test mux. In some aspects, the analog portion 1010 and the digital portion 1015 are on chip.

[0090] The voltage divider 1020 may provide a high threshold voltage Vth and a low threshold voltage Vti to the oscillator circuit 1025. In some cases, the voltage divider 1020 may include a resistor ladder. The oscillator circuit 1025 and the counter circuit 1030 may be6165864WO01 PER-557-PCT operated to determine a capacitance of the capacitor 1005. In some cases, the oscillator circuit 1025 may include a feedback-based oscillator circuit (e.g.. a capacitor-based (relaxation) oscillator circuit) that converts capacitance into a frequency that is measured as a digital number / count. In some cases, the oscillator circuit 1025 may be operated to charge and discharge the capacitor 1005 between the high and low threshold voltage to generate clock pulses that are provided to the digital portion 1015. As an example, aside from the capacitor 1005, the oscillator circuit 1025 may also include components such as an oscillator, a charge pump, a comparator, and a flip-flop. In some cases, the voltage divider 1020 may be a part of the oscillator circuit 1025. The flip-flop may be at an end (e.g., downstream of other components) to convert an output of the comparator inside an oscillator cell into a clock pulse.

[0091] A test mux block may be used to measure all currents and voltages from the oscillator circuit 1025. Test mux outputs may be accessed from external to the chip. The counter circuit 1030 may determine (e.g., count) the number of clock pulses within a known time period Tsampie to provide the digital number / count. The counter circuit 1030 may be an N bit counter circuit, where N is application dependent. An example range of values for N may be between 8 bits and 12 bits. This digital number / count output by the counter circuit 1030 may be indicative of the capacitance of the capacitor 1005.

[0092] Measurements of the capacitance of the capacitor 1005 using the system 1000 may generally involve multiple current and voltage measurements (e.g., through the test mux), followed by separate functional tests to read counts within a predetermined time window Tsampie to compute the capacitance of the capacitor 1005. Such measurements consume test time. In addition, the analog portion 1010 generally occupies substantial area in a chip and cannot be standalone (e.g., needs to be implemented in conjunction with the test mux). As such, the system 1000 may be utilized to determine correlations between resistors (e.g., MOM resistors) and corresponding capacitors (e.g., MOM capacitors) in accordance with embodiments of the present disclosure. With such correlations, a capacitance of other capacitors (e.g., other MOM capacitors) may be determined using these correlations by measuring a resistance of corresponding resistors (e.g., MOM resistors) and mapping the resistance to a capacitance value such that a system for measuring the capacitance of the capacitors, such as the system 1000, is not needed and does not need to be included on chip.

[0093] By determining the capacitance based on resistance measurements, fewer IV measurements in product test may need to be performed to determine a resistance of resistors6165864WO01 PER-557-PCT(e.g., MOM resistors), thus consuming less time, relative to performing capacitance measurements (e.g., using the system 1000) on capacitors (e.g.. MOM capacitors). In addition, a net area (cost) savings may be achieved over performing capacitance measurements (e.g., using the system 1000) on capacitors. In some cases, while inclusion of a resistor (e.g., MOM resistor) in a test mux area may increase the text mux, removal of the analog portion 1010 of the system 1000 allowed for by the inclusion and use of the resistor is associated with a net area savings.

[0094] FIG. 11 illustrates a graph showing a relationship between a resistance of a resistor (e.g., MOM resistor) and a capacitance of a corresponding / correlated capacitor (e.g., MOM capacitor) in accordance with one or more embodiments of the present disclosure. In some embodiments to generate the graph, resistance measurements and capacitance measurements may be performed on one or more wafers that each include dies. Each die (e.g., each IC) has a resistor and a corresponding / correlated capacitor and associated measurement circuitry. In some embodiments, each die may include a system, such as the system 800, for measuring the resistance of the resistor and a system, such as the system 1000, for measuring the capacitance of the capacitor corresponding to the resistor.

[0095] For each die, the resistance and the capacitance of the resistor and the capacitor, respectively, of the die may be determined such that each point on the graph is associated with the resistor’s resistance along the horizontal axis and the capacitor’s capacitance along the vertical axis. As examples, a resistance value of 630 Q and 730 Q may be associated with (e.g., correlated with) a capacitance value of 0.61 pF and 0.55 pF, respectively. In some aspects, to get higher resistance values and capacitance values, a larger resistor and a larger capacitor may be employed.

[0096] As shown by the graph 1100, a range of capacitance values and resistance values may be correlated with each other. A regression line 1105 may be determined from the points on the graph 1100. In some cases, the regression line 1105 may have the form y = a + bx and involve determining constants a and b, where x is the resistance of the resistor, y is the capacitance of the capacitor, a is a y-intercept, and b is a slope in which a and b are constants. A correlation, denoted as r, and a square of the correlation, denoted as r2. among other statistical measures may, may be determined from the points on the graph 1100.

[0097] In some embodiments, the range of capacitance values and resistance values may show correlations across different wafers, different processes, different finger widths (e.g.,6165864WO01 PER-557-PCT wf), different spacings (e.g., sr), different metal thicknesses, and / or different intermetal layer distances (e.g., <7i, di, etc.). In general, a range of resistances and a range of capacitances and corresponding resistive structures and capacitive structures are dependent on application.

[0098] Where applicable, various embodiments provided by the present disclosure can be implemented using hardware, software, or combinations of hardware and software. Also, where applicable, the various hardware components and / or software components set forth herein can be combined into composite components comprising software, hardware, and / or both without departing from the spirit of the present disclosure. Where applicable, the various hardware components and / or software components set forth herein can be separated into sub-components comprising software, hardware, or both without departing from the spirit of the present disclosure. In addition, where applicable, it is contemplated that software components can be implemented as hardware components, and vice-versa.

[0099] Software in accordance with the present disclosure, such as non-transitory instructions, program code, and / or data, can be stored on one or more non-transitory machine-readable mediums. It is also contemplated that software identified herein can be implemented using one or more general purpose or specific purpose computers and / or computer systems, networked and / or otherwise. Where applicable, the ordering of various steps described herein can be changed, combined into composite steps, and / or separated into sub-steps to provide features described herein.

[0100] Embodiments described above illustrate but do not limit the present disclosure. It should also be understood that numerous modifications and variations are possible in accordance with the principles of the present disclosure. Accordingly, the scope of the invention is defined only by the following claims.

Claims

61658.64WO01 PER-557-PCTCLAIMSWhat is claimed is:

1. An integrated circuit (IC) comprising: a resistor comprising a resistive structure disposed on a plurality of IC metal layers and having a pattern, the resistive structure comprising: a first conductive layer with the pattern; a second conductive layer with the pattern; and a first via connecting the first and second conductive layers serially, wherein the patterns on the first and second conductive layers are aligned and overlap each other.

2. The IC of claim 1, wherein the first conductive layer and the second conductive layer are disposed on adjacent IC metal layers.

3. The IC of claim 1, wherein the pattern is a serpentine pattern.

4. The IC of claim 1, wherein the resistive structure further comprises: a third conductive layer with the pattern; and a second via connecting the second and third conductive layers serially, wherein the patterns on the first, second, and third conductive layers are aligned and overlap each other.

5. The IC of claim 1, further comprising a measurement circuit comprising: a first current path through the resistive structure and configured to selectively allow current flow through the resistive structure; and a second current path not through the resistive structure.

6. The IC of claim 5, wherein: the measurement circuit further comprises a first pin and a second pin; the first current path is connected between the first pin and the second pin, wherein the first current path comprises: the resistive structure; and61658.64WO01 PER-557-PCT a first transistor connected in series with the resistive structure; and the second current path is connected between the first pin and the second pin and connected in parallel with the first current path, wherein the second current path comprises a second transistor.

7. The IC of claim 6, wherein: the first current path is configured to allow current flow through the resistive structure and the first transistor responsive to an applied voltage across the first pin and the second pin when the first transistor is in an on state; and the second current path is configured to allow current flow through the second transistor responsive to an applied voltage across the first pin and the second pin when the second transistor is in an on state.

8. The IC of claim 1, further comprising: a capacitor comprising a capacitive structure disposed on the plurality of IC metal layers, the capacitive structure comprising: a first layer of interdigitated conductive fingers; a second layer of interdigitated conductive fingers; a first interlayer via connecting a first end of the first layer of interdigitated conductive fingers and a first end of the second layer of interdigitated conductive fingers; and a second interlayer via connecting a second end of the first layer of interdigitated conductive fingers and a second end of the second layer of interdigitated conductive fingers, wherein the first and second layers of interdigitated conductive fingers are aligned and overlap each other.

9. The IC of claim 8, wherein: the pattern is a serpentine pattern; the first and second conductive layers form a stack of conductive layers along a first direction; the serpentine pattern of each of the first conductive layer and the second conductive layer extends along a second direction and a third direction substantially parallel to the second direction;61658.64WO01 PER-557-PCT the first direction is substantially perpendicular to the second direction and the third direction; the first conductive layer and the second conductive layer have substantially the same width extending along the second direction and substantially the same sidewall spacing extending along the second direction; each conductive finger of the first and second layers of interdigitated conductive fingers has a finger width substantially the same as the width of the first and second conductive layers; and a finger spacing between adjacent conductive fingers of each of the first layer of interdigitated conductive fingers and the second layer of interdigitated conductive fingers is substantially the same as the sidewall spacing of the first and second conductive layers.

10. The IC of claim 8, wherein: the first layer of interdigitated conductive fingers comprises: a first conductive line forming the first end of the first layer of conductive fingers; a first plurality of conductive fingers extending from the first conductive line; a second conductive line forming the second end of the first layer of interdigitated conductive fingers; and a second plurality of conductive fingers extending from the second conductive line; and the second layer of interdigitated conductive fingers comprises: a third conductive line forming the first end of the second layer of interdigitated conductive fingers; a third plurality of conductive fingers extending from the third conductive line; a fourth conductive line forming the second end of the second layer of interdigitated conductive fingers, wherein the first interlayer via connects the first conductive line and the third conductive line, and wherein the second interlayer via connects the second conductive line and the fourth conductive line; and a fourth plurality of conductive fingers extending from the fourth conductive line.

11. The IC of claim 8, wherein: the resistive structure further comprises: a third conductive layer with the pattern; and61658.64WO01 PER-557-PCT a second via connecting the second and third conductive layers serially, wherein the patterns on the first, second, and third conductive layers are aligned and overlap each other; and the capacitive structure further comprises: a third layer of interdigitated conductive fingers; a third interlayer via connecting the first end of the second layer of interdigitated conductive fingers and a first end of the third layer of interdigitated conductive fingers; and a fourth interlayer via connecting the second end of the second layer of interdigitated conductive fingers and a second end of the third layer of interdigitated conductive fingers.

12. The IC of claim 11, wherein the first conductive layer and the first layer of interdigitated conductive fingers are disposed on a first IC metal layer, wherein the second conductive layer and the second layer of interdigitated conductive fingers are disposed on a second IC metal layer, and wherein the third conductive layer and the third layer of interdigitated conductive fingers are disposed on a third IC metal layer.

13. A method comprising: measuring a first current through a resistor on an integrated circuit (IC), wherein the resistor comprises a resistive structure disposed on a plurality of integrated circuit (IC) metal layers and having a pattern, the resistive structure comprising: a first conductive layer with the pattern; a second conductive layer with the pattern; and a first via connecting the first and second conductive layers serially, wherein the patterns on the first and second conductive layers are aligned and overlap each other; measuring a second current through a test path; and determining a resistance associated with the resistor based at least on the first current and the second current.

14. The method of claim 13, wherein a first transistor is connected in series with the resistive structure, wherein the test path comprises a second transistor, and wherein the method further comprises:61658.64WO01 PER-557-PCT applying a first voltage across a first pin and a second pin when the first transistor is in an on state and the second transistor is in an off state, wherein the first current flows through the first transistor and the resistive structure based on the first voltage; and applying a second voltage across the first pin and the second pin when the first transistor is in an off state and the second transistor is in an on state, wherein the second current flows through the second transistor based on the second voltage, and wherein the resistance is further based on the first voltage and the second voltage.

15. The method of claim 14, wherein the resistive structure and the first transistor are in parallel with the second transistor.

16. The method of claim 13, further comprising determining a capacitance associated with a capacitor on the IC based on the resistance.

17. The method of claim 16, wherein the capacitor comprises a capacitive structure disposed on the plurality of IC metal layers, the capacitive structure comprising: a first layer of interdigitated conductive fingers; a second layer of interdigitated conductive fingers; a first interlayer via connecting a first end of the first layer of interdigitated conductive fingers and a first end of the second layer of interdigitated conductive fingers; and a second interlayer via connecting a second end of the first layer of interdigitated conductive fingers and a second end of the second layer of interdigitated conductive fingers, wherein the first and second layers of interdigitated conductive fingers are aligned and overlap each other.

18. The method of claim 17, wherein: the pattern is a serpentine pattern; the first and second conductive layers form a stack of conductive layers along a first direction; the serpentine pattern of each of the first conductive layer and the second conductive layer extends along a second direction and a third direction substantially parallel to the second direction; the first direction is substantially perpendicular to both the second direction and the third direction;61658.64WO01 PER-557-PCT the first conductive layer and the second conductive layer have substantially the same width extending along the second direction and substantially the same sidewall spacing extending along the second direction; each conductive finger of the first and second layers of interdigitated conductive fingers has a finger width substantially the same as the width of the first and second conductive layers; and a finger spacing between adjacent conductive fingers of each of the first layer of interdigitated conductive fingers and the second layer of interdigitated conductive fingers is substantially the same as the sidewall spacing of the first and second conductive layers.

19. The method of claim 17, wherein: the resistive structure further comprises: a third conductive layer with the pattern; and a second via connecting the second and third conductive layers serially, wherein the patterns on the first, second, and third conductive layers are aligned and overlap each other; and the capacitive structure further comprises: a third layer of interdigitated conductive fingers; a third interlayer via connecting the first end of the second layer of interdigitated conductive fingers and a first end of the third layer of interdigitated conductive fingers; and a fourth interlayer via connecting the second end of the second layer of interdigitated conductive fingers and a second end of the third layer of interdigitated conductive fingers.

20. The method of claim 19, wherein the first conductive layer and the first layer of interdigitated conductive fingers are disposed on a first IC metal layer, wherein the second conductive layer and the second layer of interdigitated conductive fingers are disposed on a second IC metal layer, and wherein the third conductive layer and the third layer of interdigitated conductive fingers are disposed on a third IC metal layer.

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