Battery management integrated circuit, battery pack, and energy storage system

Abstract

The present application relates to the technical field of batteries, and provides a battery management integrated circuit (BMIC), a battery pack, and an energy storage system. In the BMIC provided in the present application, a non-inverting input terminal and an inverting input terminal of a differential amplifier are respectively connected to a positive electrode and a negative electrode of a battery cell, an output terminal is connected to a first input terminal of a subtraction circuit, a second input terminal of the subtraction circuit receives a reference voltage, and an output terminal of the subtraction circuit is connected to an EIS detection circuit. The differential amplifier can output a voltage difference across two terminals of the battery cell. The subtraction circuit can calculate a difference between the voltage difference and the reference voltage, so as to obtain a response voltage generated by an excitation current at the two terminals of the battery cell. Because the solution provided in the present application enables extraction of the response voltage by means of the subtraction circuit, there is no need to provide a high-voltage-resistant DC blocking capacitor in the BMU of the battery pack. Therefore, the volume of the BMU can be effectively reduced, and the structural complexity and cost of the BMU can also be reduced.

Description

Battery management chips, battery packs and energy storage systems

[0001] This application claims priority to Chinese Patent Application No. 202411934065.3, filed on December 25, 2024, entitled “Battery Management Chip, Battery Pack and Energy Storage System”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of battery technology, and in particular to a battery management chip, a battery pack, and an energy storage system. Background Technology

[0003] Energy storage systems mainly consist of a battery pack, a battery management system (BMS), and a power conversion system (PCS). The BMS includes a battery control unit (BCU) and a battery monitor unit (BMU). The core of the BMU is the battery management integrated circuit (BMIC). The BMIC monitors information such as the voltage and temperature of the battery cells within the battery pack, while the BCU monitors and manages the charging and discharging process of the battery pack based on the information monitored by the BMIC.

[0004] To improve the reliability of energy storage systems, it is necessary to detect the electrochemical impedance spectroscopy (EIS) of the battery cells. During EIS detection, alternating excitation currents can be supplied to multiple cells in the battery pack. The BMIC in the BMU can sample this excitation current and the response voltage generated by the excitation current on the cells, and calculate the EIS of the cells based on the sampled excitation current and response voltage.

[0005] Because the internal resistance of the battery cell is relatively low, the amplitude of the alternating response voltage generated by the alternating excitation current is also relatively small. This response voltage, superimposed on the larger-amplitude battery cell voltage, is difficult to detect directly. To achieve effective detection of the response voltage, the BMIC needs to sample the voltage across the battery cell using a high-voltage DC-blocking capacitor in the BMU. This high-voltage DC-blocking capacitor filters out the DC component (i.e., the battery cell voltage), thus enabling effective extraction of the small-amplitude response voltage. However, the aforementioned high-voltage DC-blocking capacitor is relatively large, increasing the size and structural complexity of the BMU. Summary of the Invention

[0006] This application provides a BMIC, a battery pack, and an energy storage system that can solve the technical problem of increasing the size and structural complexity of the BMU by sampling the voltage across the battery cell using a high-voltage DC blocking capacitor.

[0007] Firstly, a battery-controlled intelligent circuit (BMIC) is provided, comprising a voltage sampling circuit, a current sampling circuit, and an energy-independent standard (EIS) detection circuit. The voltage sampling circuit includes a differential amplifier and a subtraction circuit. The non-inverting input of the differential amplifier is connected to the positive terminal of the battery cell, and the inverting input is connected to the negative terminal. The output of the differential amplifier is connected to the first input of the subtraction circuit, the second input of the subtraction circuit is used to receive a reference voltage, and the output of the subtraction circuit is connected to the EIS detection circuit. The battery cell includes one or more cells connected in series. The current sampling circuit samples the excitation current flowing through the battery cell and outputs it to the EIS detection circuit. The EIS detection circuit receives the outputs of the subtraction circuit and the current sampling circuit, and detects the EIS of the battery cell.

[0008] Understandably, the output voltage of a differential amplifier is proportional to the voltage difference between its non-inverting and inverting inputs. This subtraction circuit outputs a differential voltage to the EIS detection circuit, which is the voltage difference between the differential amplifier's output voltage and a reference voltage determined based on the battery cell voltage.

[0009] It is also understood that the output voltage of the differential amplifier contains both DC and AC components. The DC component is generated by the cell voltage of the battery cell, while the AC component is generated by the response voltage of the battery cell. The response voltage refers to the response voltage generated by the excitation current energizing the battery cell. Furthermore, the magnitude of the reference voltage received at the second input terminal of the subtraction circuit can be equal to the magnitude of this DC component. Accordingly, the difference voltage obtained by subtracting the output voltage of the differential amplifier from the reference voltage using the subtraction circuit is the response voltage of the battery cell. Since the solution provided in this application can extract the response voltage through the subtraction circuit, there is no need to install high-voltage DC blocking capacitors in the battery pack (e.g., in the BMU). Consequently, the size of the BMU can be effectively reduced, lowering its structural complexity and cost.

[0010] Optionally, the voltage sampling circuit further includes a low-pass filter. This low-pass filter is connected to both the output of the differential amplifier and the second input of the subtraction circuit, and is used to provide the reference voltage to the second input of the subtraction circuit.

[0011] Understandably, a low-pass filter can filter the output voltage of a differential amplifier to remove the AC component, leaving only the DC component. This DC component represents the cell voltage of the battery cell. Since the cell voltage varies under different conditions, using a low-pass filter to provide a reference voltage ensures that this reference voltage changes in accordance with the cell voltage variations. This ensures that the subtraction circuit can accurately sample the battery cell's response voltage, thereby guaranteeing the accuracy of EIS detection.

[0012] Optionally, the voltage sampling circuit further includes a switching circuit. This switching circuit has multiple pairs of input terminals, each pair of which is used to connect the positive and negative terminals of a battery cell. Furthermore, the switching circuit is configured to connect only the positive terminal of one battery cell to the non-inverting input of the differential amplifier and the negative terminal of that battery cell to the inverting input of the differential amplifier at any given time.

[0013] In the solution provided in this application, the switching circuit can transmit the voltages across different battery cells to the non-inverting and inverting inputs of the differential amplifier at different time periods. This ensures that the differential amplifier can output the voltage difference across different battery cells at different time periods. The subtraction circuit can then subtract the voltage difference across different battery cells from a reference voltage at different time periods and output the result, meaning the subtraction circuit can output the response voltage of different battery cells at different time periods. Therefore, the voltage sampling circuit, through a set of differential amplifiers and subtraction circuits, can sequentially sample the response voltages of multiple battery cells, effectively reducing the cost, size, and structural complexity of the BMIC.

[0014] Optionally, the voltage sampling circuit includes multiple differential amplifiers connected one-to-one with multiple battery cells. Furthermore, the voltage sampling circuit also includes a switching circuit. The switching circuit has multiple input terminals, each of which is used to connect to the output terminal of one differential amplifier. The switching circuit is used to connect only the output terminal of one differential amplifier to the first input terminal of the subtraction circuit at any given time.

[0015] In the solution provided in this application, the switching circuit can transmit the output voltages of different differential amplifiers (i.e., the voltage difference across different battery cells) to the subtraction circuit at different time periods. This ensures that the subtraction circuit can output the response voltage of different battery cells at different time periods after subtracting the voltage difference across the different battery cells from the reference voltage. Therefore, the subtraction circuit can output the response voltage of different battery cells at different time periods. It can be seen that the voltage sampling circuit can sample the response voltages of multiple battery cells through a single subtraction circuit, thereby effectively reducing the cost, size, and structural complexity of the BMIC.

[0016] Optionally, the voltage sampling circuit includes: a plurality of differential amplifiers connected one-to-one with a plurality of battery cells, and a plurality of subtraction circuits connected one-to-one with the output terminals of the plurality of differential amplifiers.

[0017] In other words, in the solution provided in this application, each battery cell in the battery pack corresponds to a set of differential amplifiers and subtraction circuits, which can independently sample the response voltage of a battery cell. Therefore, parallel sampling of the response voltages of multiple battery cells can be achieved, thereby effectively improving the sampling efficiency of the response voltage and thus improving the EIS detection efficiency of the battery cell.

[0018] Secondly, another type of battery control microphone (BMIC) is provided, which includes a voltage sampling circuit, a current sampling circuit, and an EIS detection circuit. The voltage sampling circuit includes a differential amplifier and a DC blocking capacitor. The non-inverting input of the differential amplifier is connected to the positive terminal of the battery cell, and the inverting input is connected to the negative terminal. The output of the differential amplifier is connected to the EIS detection circuit via the DC blocking capacitor. The current sampling circuit samples the excitation current flowing through the battery cell and outputs it to the EIS detection circuit. The EIS detection circuit receives the output of the DC blocking capacitor and the output of the current sampling circuit, and detects the EIS of the battery cell.

[0019] It is understandable that the output voltage of a differential amplifier is proportional to the voltage difference between its non-inverting and inverting inputs. The DC blocking capacitor filters out the DC component from the differential amplifier's output voltage and outputs the AC component to the EIS detection circuit. The AC component is the response voltage generated by the excitation current stimulating the battery cell.

[0020] Based on the connection relationship between the differential amplifier and the battery cell, and the working principle of the differential amplifier, it can be seen that this differential amplifier can remove the high common-mode voltage on the battery cell and output the differential-mode voltage on the battery cell. Since the differential-mode voltage output by the differential amplifier is close to the voltage of a single battery cell, the voltage rating requirement of the DC blocking capacitor can be effectively reduced. That is, the DC blocking capacitor can be a low-voltage capacitor. Because low-voltage capacitors are smaller and less expensive, the size and cost of the BMU can be effectively reduced.

[0021] Optionally, the withstand voltage of the DC blocking capacitor is greater than the cell voltage of the battery cell. For example, if each battery cell includes one cell, the withstand voltage of the DC blocking capacitor can be greater than the cell voltage of a single cell, but less than or equal to 5V. Since the cell voltage of a single cell in a battery pack is typically around 3.65V, the DC blocking capacitor can be a capacitor with a withstand voltage greater than 3.65V and less than or equal to 5V. Therefore, while ensuring that the DC blocking capacitor can effectively filter out the DC component in the first voltage, the size and cost of the DC blocking capacitor can be effectively reduced.

[0022] Optionally, the voltage sampling circuit further includes a switching circuit. The switching circuit has multiple pairs of input terminals, each pair of which is used to connect the positive and negative terminals of a battery cell. Furthermore, the switching circuit is configured to connect only the positive terminal of one battery cell to the non-inverting input of the differential amplifier and the negative terminal of that battery cell to the inverting input of the differential amplifier at any given time.

[0023] The switching circuit can transmit the voltages across different battery cells to the non-inverting and inverting inputs of the differential amplifier at different times. This ensures that the differential amplifier can output the voltage difference across different battery cells at different times. The DC blocking capacitor can then filter out the DC component from the voltage difference across different battery cells at different times, meaning it can output the response voltage of different battery cells at different times. Therefore, the voltage sampling circuit, using a set of differential amplifiers and DC blocking capacitors, can sequentially sample the response voltages of multiple battery cells, effectively reducing the cost, size, and structural complexity of the BMU.

[0024] Optionally, the voltage sampling circuit includes multiple differential amplifiers connected one-to-one with multiple battery cells. Furthermore, the voltage sampling circuit also includes a switching circuit. The switching circuit has multiple input terminals, each of which is used to connect to the output terminal of one differential amplifier. The switching circuit is used to connect only the output terminal of one differential amplifier to the DC blocking capacitor at any given time.

[0025] The switching circuit can transmit the output voltages of different differential amplifiers (e.g., the voltage difference across different battery cells) to the DC blocking capacitor at different times. This ensures that the DC blocking capacitor can filter out the DC component from different voltage differences at different times, meaning it can output the response voltage of different battery cells at different times. Therefore, the voltage sampling circuit can sample the response voltages of multiple battery cells using only a single DC blocking capacitor, effectively reducing the cost, size, and structural complexity of the BMU.

[0026] Optionally, the voltage sampling circuit further includes: a plurality of differential amplifiers connected one-to-one with the plurality of battery cells, and a plurality of DC blocking capacitors connected one-to-one with the output terminals of the plurality of differential amplifiers.

[0027] In the solution provided in this application, each battery cell in the battery pack can correspond to a set of differential amplifiers and DC blocking capacitors. This set of differential amplifiers and DC blocking capacitors enables independent sampling of the response voltage of a single battery cell. Therefore, parallel sampling of the response voltages of multiple battery cells can be achieved, effectively improving the sampling efficiency of the response voltage and thus enhancing the detection efficiency of EIS.

[0028] Thirdly, another type of battery control system (BMIC) is provided, comprising a voltage sampling circuit, a current sampling circuit, and an EIS detection circuit. The voltage sampling circuit includes a differential amplifier and an analog-to-digital converter (ADC). The non-inverting input of the differential amplifier is connected to the positive terminal of the battery cell, and the inverting input is connected to the negative terminal. The output of the differential amplifier is connected to the EIS detection circuit via the ADC. The battery cell comprises one or more cells connected in series, and the ADC has a resolution greater than a threshold. The current sampling circuit samples the excitation current flowing through the battery cell and outputs it to the EIS detection circuit. The EIS detection circuit receives the output of the ADC and the output of the current sampling circuit and detects the EIS of the battery cell.

[0029] It is understandable that the output voltage of a differential amplifier contains both DC and AC components. The DC component is generated by the cell voltage of the battery cell, while the AC component is generated by the response voltage of the battery cell. The response voltage refers to the voltage generated by the excitation current energizing the battery cell, and its amplitude is typically much smaller than the amplitude of the cell voltage.

[0030] In the solution provided in this application, to achieve accurate sampling of the response voltage, the resolution of the ADC is greater than a threshold, meaning the ADC can be a high-resolution ADC. For example, if the threshold is 14 bits, then the resolution of the ADC can be greater than 14 bits, such as 16 bits. This high-resolution ADC enables accurate sampling of the output voltage of the differential amplifier, thereby ensuring that the EIS detection circuit can accurately extract the small-amplitude response voltage from the output voltage of the differential amplifier for subsequent EIS detection. Furthermore, since the high-resolution ADC enables accurate sampling of the output voltage of the differential amplifier, and thus accurate sampling of the response voltage, there is no need to set a DC blocking capacitor in the BMU of the battery pack, thereby effectively reducing the size and structural complexity of the BMU.

[0031] Fourthly, a battery pack is provided, comprising: at least one battery cell, and a BMIC as provided in any of the preceding aspects, the BMIC being connected to the at least one battery cell and used to detect the EIS of the at least one battery cell.

[0032] Fifthly, an energy storage system is provided, comprising: a plurality of battery packs as provided in the fourth aspect above.

[0033] In summary, this application provides a battery microcontroller (BMIC), a battery pack, and an energy storage system. The BMIC provided in this application includes a differential amplifier and a subtraction circuit. The non-inverting and inverting inputs of the differential amplifier are connected to the positive and negative terminals of the battery cell, respectively. The output is connected to one input of the subtraction circuit, the other input of which receives a reference voltage. The output of the subtraction circuit is connected to an EIS detection circuit. The differential amplifier outputs the voltage difference across the battery cell, i.e., the differential-mode voltage of the battery cell. The subtraction circuit subtracts this differential-mode voltage from the reference voltage to obtain the response voltage generated across the battery cell by the excitation current. Since the solution provided in this application can extract the response voltage through the subtraction circuit, a high-voltage DC blocking capacitor is no longer needed in the battery pack (e.g., in the BMU). Consequently, the size of the BMU can be effectively reduced, lowering its structural complexity and cost. Attached Figure Description

[0034] Figure 1 is a schematic diagram of an energy storage system provided in an embodiment of this application;

[0035] Figure 2 is a schematic diagram of an application scenario of an energy storage system provided in an embodiment of this application;

[0036] Figure 3 is a schematic diagram of another energy storage system provided in an embodiment of this application;

[0037] Figure 4 is a schematic diagram of an EIS detection architecture provided in an embodiment of this application;

[0038] Figure 5 is a schematic diagram of the structure of a BMIC provided in an embodiment of this application;

[0039] Figure 6 is a schematic diagram of another BMIC structure provided in an embodiment of this application;

[0040] Figure 7 is a schematic diagram of another BMIC provided in an embodiment of this application;

[0041] Figure 8 is a schematic diagram of another BMIC provided in an embodiment of this application;

[0042] Figure 9 is a schematic diagram of another BMIC provided in an embodiment of this application;

[0043] Figure 10 is a schematic diagram of another BMIC provided in an embodiment of this application;

[0044] Figure 11 is a schematic diagram of another BMIC provided in an embodiment of this application;

[0045] Figure 12 is a schematic diagram of another BMIC provided in an embodiment of this application;

[0046] Figure 13 is a schematic diagram of another BMIC structure provided in an embodiment of this application. Detailed Implementation

[0047] The BMIC, battery pack, and energy storage system provided in the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0048] Figure 1 is a schematic diagram of an energy storage system provided in an embodiment of this application. As shown in Figure 1, the energy storage system may include multiple battery packs, a battery management system (BMS), and a power supply system (PCS). The multiple battery packs can be connected in series. The PCS is used to convert the direct current (DC) from the multiple battery packs into alternating current (AC) and output it to the power grid or load. The PCS also converts the AC power from the power grid into DC to charge the multiple battery packs. For example, referring to Figure 1, the PCS may include a DC / DC power converter and a DC / DC controller. The DC / DC power converter is connected to the multiple battery packs through a cluster controller. Under the control of the DC / DC controller, the DC / DC power converter charges or discharges the multiple battery packs through the cluster controller. It is understood that the PCS also includes an AC / DC converter, which is used to convert AC power to DC power.

[0049] Each battery pack may include multiple battery cells connected in series, and each battery cell may be a lithium-ion battery cell. Furthermore, each battery pack may also include a fuse, with multiple battery cells and the fuse connected in series between the positive terminal (BAT+) and the negative terminal (BAT-) of the battery pack.

[0050] Referring again to Figure 1, the BMS includes a Battery Control Unit (BCU) and multiple Battery Monitoring Units (BMUs). One or more BMUs can be installed within a battery pack. Each BMU establishes a communication connection with both the battery pack and the BCU, enabling signal transmission. The core of the BMU is the Battery Microcontroller (BMIC), which monitors the voltage, current, and temperature of each cell within the battery pack, as well as the temperature of the copper busbars, and estimates the cell's state. The cell's state includes, but is not limited to, state of charge (SOC), state of health (SOH), internal temperature, and electrode state. The BCU collects data from the multiple BMUs and other key data, and based on this data, monitors and manages the charging and discharging processes of multiple battery packs, ensuring that the battery packs operate safely and efficiently.

[0051] It is understandable that in the energy storage system shown in Figure 1, each BMU can be a single board (i.e., a BMU board), and the BMIC is mounted on the BMU board. The BMU board also houses peripheral devices of the BMIC (such as capacitors). Furthermore, the BMU board can be located inside the battery pack. For example, each battery pack can contain one or more BMU boards. The BCU, on the other hand, is located independently of the battery pack; for example, the BCU can be located within the cluster controller.

[0052] Figure 2 is a schematic diagram of an application scenario for an energy storage system provided in an embodiment of this application. This application scenario is a photovoltaic-energy storage system. As shown in Figure 2, the energy storage system may include multiple energy storage cabinets, each of which may house a battery pack, a DC / DC power converter, and a power distribution unit (PCS). Referring to Figure 2, the DC / DC power converter may be integrated into the PCS. Alternatively, the DC / DC power converter may be set up independently of the PCS. Multiple energy storage cabinets in the energy storage system are connected to an AC bus via an AC distribution box, for example, a 400-volt (V) AC bus. This application scenario may also include photovoltaic panels and an inverter. The inverter is connected to both the photovoltaic panels and the AC bus, and is used to convert the DC power from the photovoltaic panels into AC power before outputting it to the AC bus. The AC bus may also be connected to a load (such as an industrial or commercial load) and supply power to the load. Continuing to refer to Figure 2, this application scenario may also include an electricity meter and a transformer. The AC bus can be connected to the power grid via the electricity meter and transformer, for example, to a 10 kV power grid.

[0053] It is understood that the energy storage system provided in this application embodiment can be applied not only to the photovoltaic energy storage scenario shown in Figure 2, but also to related scenarios that require monitoring of cell status, such as photovoltaic power plants, industrial and commercial energy storage cabinets, residential energy storage, site lithium batteries, data center lithium batteries, and vehicle power PACKs.

[0054] To improve the reliability of energy storage systems, it is necessary to monitor the state of each cell in the battery pack. A cell in a battery pack can be considered an equivalent circuit system containing resistors, inductors, and capacitors. When the state of a cell changes, the equivalent circuit system also changes. The industry typically uses EIS (Electronic Information System) to infer the state of the cells. The detection principle of EIS is as follows: applying sinusoidal current (or voltage) signals of different frequencies to the cells in the battery pack will cause the cells to generate a series of sinusoidal voltage (or current) responses of different frequencies. The change in the ratio of the excitation signal to the response signal is the EIS of the equivalent circuit system of the cell.

[0055] The excitation signal applied to the battery cell is typically a current signal, also known as the excitation current. This excitation current can be provided in several ways, including cell-by-cell excitation, pack-level excitation, or cluster-level excitation. Referring to Figure 3, taking cluster-level excitation as an example, and assuming a battery cluster comprises m (m is an integer greater than 1) battery packs, the cluster-level excitation current can be generated by the DC / DC power converter in the PCS. For example, the BCU can send control information (such as frequency and current information) to the DC / DC power converter, which can then regulate the current loop and voltage loop based on this control information to generate the cluster-level excitation current. The frequency range of this cluster-level excitation current can be from 0.01 Hz to 4 kHz. Furthermore, this cluster-level excitation battery can simultaneously excite all the cells in the m battery packs within a battery cluster. Referring to Figure 4, the BMIC in the BMU can sample the excitation current applied to the battery cell, for example, through a current sensor in the cluster controller. Furthermore, the BMIC can sample the cell's response signal (i.e., response voltage). Then, the BMIC can perform a Fast Fourier Transform (FFT) on the sampled excitation current and response voltage, and calculate the cell's EIS based on the FFT-generated current and voltage.

[0056] Referring to Figure 3, it can be seen that the BCU can be set in the cluster controller, and the cluster controller also includes a rack power control board (RPCB), which can be used to control the charging and discharging of multiple battery packs in the battery cluster.

[0057] It is understandable that the amplitude of the cell's response voltage equals the excitation current multiplied by the cell's internal resistance, and its magnitude is typically several hundred microvolts (µV). This small-amplitude AC signal superimposed on the cell voltage is difficult to detect and amplify effectively. Taking a 280 ampere-hour (AH) cell as an example, the cell's internal resistance is approximately 0.2 milliohms (mΩ). If the excitation current is 1 ampere (A), the amplitude of the response voltage is approximately 200µV. This 200µV AC voltage signal, superimposed on the 3.65V cell voltage, is difficult to detect. In some embodiments, as shown in Figure 4, a DC blocking capacitor is typically used to remove the DC component from the voltage across the cell, obtaining the AC component (i.e., the response voltage). This response voltage is then amplified by a programmable gain amplifier (PGA) and subjected to EIS detection.

[0058] Because battery packs typically include multiple cells connected in series, the voltage of these cells will be relatively high. For example, assuming a single cell has a voltage of 3.65V, the 10th cell would have a voltage of 36.5V, and the 16th cell would have a voltage of 58.4V. Therefore, the aforementioned DC blocking capacitors usually require high-voltage capacitors, such as those with a withstand voltage of 100V. These high-voltage capacitors are large and expensive, significantly increasing the size and cost of the BMU (Battery Management Unit), thus hindering their engineering application.

[0059] In addition, BMICs typically include an amplifier (such as a PGA) for amplifying the response voltage, with a bias resistor connected to its input. A DC blocking capacitor, together with this bias resistor, forms a high-pass filter. Because the capacitance of this high-voltage DC blocking capacitor is usually small, for example, only 10 microfarads (µF), the cutoff frequency of the high-pass filter is relatively high. This results in a significant attenuation of the response voltage generated by the low-frequency excitation current, affecting the accuracy of EIS detection. The low-frequency excitation current can refer to an excitation current with a frequency between 0.01 Hz and 1 Hz.

[0060] This application provides a BMIC that can be applied to application scenarios such as those shown in Figures 1 to 3. As shown in Figure 5, the BMIC includes a voltage sampling circuit 10, a current sampling circuit 20, and an EIS detection circuit 30. The voltage sampling circuit 10 includes a differential amplifier A1 and a subtraction circuit 11.

[0061] In this circuit, the non-inverting input (+) of differential amplifier A1 is connected to the positive terminal of battery cell 01 in the battery pack, and the inverting input (-) of differential amplifier A1 is connected to the negative terminal of battery cell 01. The output of differential amplifier A1 is connected to the first input (e.g., the positive input) of subtraction circuit 11. The second input (e.g., the negative input) of subtraction circuit 11 is used to receive the reference voltage Vref1, and the output of subtraction circuit 11 is connected to EIS detection circuit 30. Battery cell 01 includes one or more cells connected in series. Figure 5 illustrates this with an example of battery cell 01 consisting of one cell. It is understood that the battery pack may include multiple battery cells connected in series, and battery cell 01 can be any one of these multiple battery cells.

[0062] In this embodiment, the reference voltage Vref1 received at the second input terminal of the subtraction circuit 11 is determined based on the cell voltage of the battery cell 01. For example, the reference voltage Vref1 can be equal to the cell voltage of the battery cell 01. If the battery cell 01 includes multiple cells connected in series, the cell voltage of the battery cell 01 can refer to the sum of the cell voltages of the multiple cells connected in series.

[0063] The current sampling circuit 20 samples the excitation current flowing through the battery cell 01 and outputs it to the EIS detection circuit 30. The EIS detection circuit 30 receives the output of the subtraction circuit 11 and the output of the current sampling circuit 20, and detects the EIS of the battery cell 01. The excitation current is an alternating current, and its frequency is variable. For example, the frequency of the excitation current can vary from 0.01 Hz to 4 kHz.

[0064] Understandably, the differential amplifier A1 is used to output a first voltage, which is proportional to the voltage difference between the non-inverting and inverting input terminals of the differential amplifier A1. For example, the differential amplifier A1 can amplify the voltage difference between its non-inverting and inverting input terminals before outputting it, or the differential amplifier A1 can directly output the voltage difference between its non-inverting and inverting input terminals. The subtraction circuit 11 is used to output a difference voltage to the EIS detection circuit 30. This difference voltage is the voltage difference between the first voltage and the reference voltage Vref1, that is, the difference voltage is the output voltage of the differential amplifier A1 minus the reference voltage Vref1.

[0065] It is also understood that the first voltage output by differential amplifier A1 contains both a DC component and an AC component. The DC component is generated by the cell voltage of battery cell 01, and the AC component is generated by the response voltage of battery cell 01. The response voltage refers to the response voltage generated by the excitation current energizing battery cell 01. Furthermore, the magnitude of the reference voltage Vref1 received at the second input terminal of subtraction circuit 11 can be equal to the magnitude of this DC component. Accordingly, the difference voltage obtained by subtracting the first voltage and the reference voltage Vref1 by subtraction circuit 11 is the response voltage generated by the excitation current energizing battery cell 01. Further, EIS detection circuit 30 can detect the EIS of battery cell 01 based on the received response voltage and excitation current.

[0066] Since the solution provided in this application embodiment can extract the response voltage through a subtraction circuit, there is no need to set a high-voltage DC blocking capacitor in the battery pack's BMU. Accordingly, the size of the BMU can be effectively reduced, the structural complexity and cost of the BMU can be reduced, and thus the cost, size and structural complexity of the battery pack can be effectively reduced.

[0067] It is also understood that if battery cell 01 includes a single cell, the EIS detection circuit 30 can achieve accurate EIS detection of the individual cell. If battery cell 01 includes multiple (e.g., two) cells connected in series, these multiple cells connected in series can serve as the smallest unit for EIS detection, thereby improving the EIS detection efficiency of the battery pack.

[0068] Optionally, the second input terminal of the subtraction circuit 11 can be connected to a reference power supply terminal, which provides a fixed reference voltage Vref1. This reference voltage Vref1 can be equal to the cell voltage of battery cell 01 when fully charged. For example, assuming battery cell 01 comprises one cell, the reference voltage Vref1 can be equal to 3.65V. Alternatively, the reference voltage Vref1 can be equal to the intermediate voltage of battery cell 01, such as 3.2V. In scenarios where the reference voltage Vref1 is the full-charge voltage, to ensure the accuracy of EIS detection, the EIS detection process can be performed when battery cell 01 is fully charged.

[0069] Optionally, as shown in Figure 6, the voltage sampling circuit 10 may further include a low-pass filter 12. The low-pass filter 12 is connected to both the output of the differential amplifier A1 and the second input of the subtraction circuit 11. The low-pass filter 12 provides a reference voltage Vref1 to the second input of the subtraction circuit 11. For example, the low-pass filter 12 may be a resistance-capacitance (RC) filter.

[0070] Understandably, the low-pass filter 12 performs low-pass filtering on the first voltage output by the differential amplifier A1 to filter out the AC component of the first voltage and output the DC component of the first voltage. This DC component is the cell voltage of battery cell 01, or the cell voltage of battery cell 01 amplified by the differential amplifier A1. Since the cell voltage of battery cell 01 varies in different states, for example, the cell voltage of battery cell 01 is 3.65V when fully charged, but may only be 2V when the cell voltage is low, the low-pass filter 12 provides a reference voltage Vref1 to ensure that the reference voltage Vref1 changes with the cell voltage of battery cell 01. Therefore, the subtraction circuit 11 can accurately sample the response voltage of battery cell 01, thereby ensuring the accuracy of EIS detection.

[0071] As a first optional implementation, as shown in Figure 6, the voltage sampling circuit 10 may further include a switching circuit 13. This switching circuit 13 has multiple pairs of input terminals, each pair of which is used to connect to the positive and negative terminals of a battery cell. For example, referring to Figure 6, the first pair of input terminals of the switching circuit 13 is used to connect to the positive and negative terminals of battery cell 01, and the last pair of input terminals is used to connect to the positive and negative terminals of battery cell 02. The output terminal of the switching circuit 13 is connected to the non-inverting input terminal and the inverting input terminal of the differential amplifier A1, respectively.

[0072] Furthermore, the switching circuit 13 is used to connect the positive terminal of only one battery cell to the non-inverting input terminal of the differential amplifier A1 at the same time period, and to connect the negative terminal of the same battery cell to the inverting input terminal of the differential amplifier A1.

[0073] For example, in a first time period, the switching circuit 13 connects the positive and negative terminals of battery cell 01 to the non-inverting and inverting input terminals of differential amplifier A1, respectively, thereby transmitting the voltage across battery cell 01 to the non-inverting and inverting input terminals of differential amplifier A1. Furthermore, in a second time period, the switching circuit 13 connects the positive and negative terminals of battery cell 02 to the non-inverting and inverting input terminals of differential amplifier A1, respectively, thereby transmitting the voltage across battery cell 02 to the non-inverting and inverting input terminals of differential amplifier A1. The first and second time periods do not overlap.

[0074] Accordingly, differential amplifier A1 is capable of outputting a first voltage during a first time period, which is proportional to the voltage difference between the non-inverting and inverting input terminals of differential amplifier A1 during the first time period. Differential amplifier A1 is also used to output a second voltage during a second time period. This second voltage is proportional to the voltage difference between the non-inverting and inverting input terminals of differential amplifier A1 during the second time period.

[0075] The subtraction circuit 11 is used to output a first difference voltage to the EIS detection circuit 30 in a first time period and a second difference voltage to the EIS detection circuit 30 in a second time period. The first difference voltage is the voltage difference between a first voltage and a reference voltage Vref1, and the second difference voltage is the voltage difference between a second voltage and the reference voltage Vref1.

[0076] Furthermore, the current sampling circuit 20 is also used to sample the excitation current flowing through the battery cell 02 and output it to the EIS detection circuit 30. The excitation current flowing through the battery cell 02 can be the same as or different from the excitation current flowing through the battery cell 01; this embodiment does not limit this. The EIS detection circuit 30 can also detect the EIS of the battery cell 02 based on the received second difference voltage and the excitation current output by the current sampling circuit 20. The second difference voltage is the response voltage generated by the excitation current stimulating the battery cell 02.

[0077] In this first implementation, the switching circuit 13 in the voltage sampling circuit 10 can transmit the voltages across different battery cells to the non-inverting and inverting inputs of the differential amplifier A1 at different time periods. This ensures that the differential amplifier A1 can amplify and output (or directly output) the voltage differences across different battery cells at different time periods. Furthermore, the subtraction circuit 11 can subtract the reference voltage Vref1 from the voltage differences at different time periods, i.e., the subtraction circuit 11 can output the response voltages of different battery cells at different time periods. Therefore, based on this first implementation, the voltage sampling circuit 10, through a set of differential amplifiers A1 and subtraction circuits 11, can sequentially sample the response voltages of multiple battery cells, thereby effectively reducing the cost, size, and structural complexity of the BMIC.

[0078] Understandably, the number of battery cells n in the battery pack can be greater than or equal to 2, for example, n can be equal to 16. Correspondingly, the switching circuit 13 can have n pairs of input terminals and one pair of output terminals. Each pair of input terminals is used to connect the positive and negative terminals of one battery cell, and the pair of output terminals of the switching circuit 13 can be connected to the non-inverting and inverting input terminals of the differential amplifier A1. Furthermore, the switching circuit 13 can switch the voltage across each of the n battery cells to the non-inverting and inverting input terminals of the differential amplifier A1, so that the differential amplifier A1 can sequentially detect and output the voltage difference across each of the n battery cells. Correspondingly, the subtraction circuit 11 can sequentially subtract different voltage differences from the reference voltage Vref1 and output the result; that is, the subtraction circuit 11 can sequentially output the response voltages of the n battery cells.

[0079] As a second optional implementation, as shown in Figure 7, the voltage sampling circuit 10 may further include a switching circuit 13. Furthermore, the voltage sampling circuit 10 may include multiple differential amplifiers, the input terminals of which are connected one-to-one with multiple battery cells in the battery pack. For example, Figure 7 shows differential amplifiers A1 and A2. The non-inverting input (+) of differential amplifier A2 is connected to the positive terminal of battery cell O2 in the battery pack, and the inverting input (-) of differential amplifier A2 is connected to the negative terminal of battery cell O2. Differential amplifier A1 outputs a first voltage, and differential amplifier A2 outputs a second voltage. The first voltage is proportional to the voltage difference between the non-inverting and inverting input terminals of differential amplifier A1, and the second voltage is proportional to the voltage difference between the non-inverting and inverting input terminals of differential amplifier A2.

[0080] The switching circuit 13 has multiple input terminals and one output terminal. Each of the multiple input terminals is used to connect to the output terminal of a differential amplifier, and the output terminal of the switching circuit 13 is connected to the first input terminal of the subtraction circuit 11. Furthermore, the switching circuit 13 is configured to connect only one output terminal of the differential amplifier to the first input terminal of the subtraction circuit 11 at any given time.

[0081] For example, in a first time period, the switching circuit 13 connects the output terminal of the differential amplifier A1 to the first input terminal of the subtraction circuit 11, thereby transmitting a first voltage output from the differential amplifier A1 to the subtraction circuit 11. Furthermore, in a second time period, the switching circuit 13 connects the output terminal of the differential amplifier A2 to the first input terminal of the subtraction circuit 11, thereby transmitting a second voltage output from the differential amplifier A2 to the subtraction circuit 11. The first and second time periods do not overlap.

[0082] Accordingly, the subtraction circuit 11 is used to output a first difference voltage to the EIS detection circuit 30 in the first time period, and to output a second difference voltage to the EIS detection circuit 30 in the second time period. The first difference voltage is the voltage difference between the first voltage and the reference voltage Vref1, and the second difference voltage is the voltage difference between the second voltage and the reference voltage Vref1.

[0083] Furthermore, the current sampling circuit 20 is also used to sample the excitation current flowing through the battery cell 02 and output it to the EIS detection circuit 30. The EIS detection circuit 30 is also used to receive the second difference voltage output by the subtraction circuit 11, and detect the EIS of the battery cell 02 based on the second difference voltage and the excitation current sampled by the current sampling circuit 20.

[0084] It is understandable that the second voltage output by differential amplifier A2 also contains both DC and AC components. The DC component is generated by the cell voltage of battery cell 02, and the AC component is generated by the response voltage of battery cell 02. The response voltage of battery cell 02 refers to the response voltage generated by the excitation current energizing battery cell 02. Furthermore, the magnitude of the reference voltage Vref1 received at the second input terminal of subtraction circuit 11 can be equal to the magnitude of this DC component. Accordingly, the second difference voltage obtained by subtracting the second voltage from the reference voltage Vref1 by subtraction circuit 11 is the response voltage generated by the excitation current energizing battery cell 01.

[0085] In this second implementation, the switching circuit 13 in the voltage sampling circuit 10 can transmit the voltages output by different differential amplifiers (e.g., the amplified voltage difference across different battery cells) to the subtraction circuit 11 at different time periods. This ensures that the subtraction circuit 11 can output the subtraction of different voltage differences with the reference voltage Vref1 at different time periods, meaning the subtraction circuit 11 can output the response voltages of different battery cells at different time periods. Therefore, based on this second implementation, the voltage sampling circuit 10 can sample the response voltages of multiple battery cells through a single subtraction circuit 11, effectively reducing the cost, size, and structural complexity of the BMIC.

[0086] Understandably, the number of battery cells n in the battery pack can be greater than or equal to 2, for example, n can be equal to 16. Correspondingly, the voltage sampling circuit 10 can include n differential amplifiers, each corresponding to one of the n battery cells. The non-inverting input of each differential amplifier is connected to the positive terminal of a corresponding battery cell, the inverting input is connected to the negative terminal of a corresponding battery cell, and the output is connected to the input of the switching circuit 13. The output of the switching circuit 13 can then be connected to the first input of the subtraction circuit 11.

[0087] Each differential amplifier amplifies and outputs the voltage difference across the connected battery cell, or it can directly output the voltage difference across the connected battery cell. The switching circuit 13 can switch the voltage difference output from the n differential amplifiers to the subtraction circuit 11, so that the subtraction circuit 11 can sequentially subtract the voltage difference across each of the n battery cells from the reference voltage Vref1 and output the result. That is, the subtraction circuit 11 can sequentially output the response voltage of the n battery cells.

[0088] Optionally, the switching circuit 13 in the first and second implementations described above can be a single-pole multi-throw switch, or a gating switch.

[0089] As a third optional implementation, as shown in Figure 8, the voltage sampling circuit 10 may include multiple differential amplifiers and multiple subtraction circuits. The non-inverting and inverting inputs of the multiple differential amplifiers are connected one-to-one with the positive and negative terminals of the multiple battery cells, and the outputs of the multiple differential amplifiers are connected one-to-one with the first inputs of the multiple subtraction circuits. The second input of the multiple subtraction circuits is used to receive a reference voltage, and the outputs of the multiple subtraction circuits are all connected to the EIS detection circuit 30.

[0090] For example, Figure 8 schematically shows two differential amplifiers A1 and A2, and two subtraction circuits 11 and 14. The non-inverting input (+) of differential amplifier A2 is connected to the positive terminal of battery cell O2 in the battery pack, and the inverting input (-) of differential amplifier A2 is connected to the negative terminal of battery cell O2. The output of differential amplifier A2 is connected to the first input of subtraction circuit 14, the second input of subtraction circuit 14 is used to receive a reference voltage Vref2, and the output of subtraction circuit 14 is connected to EIS detection circuit 30. The reference voltage Vref2 is determined based on the cell voltage of battery cell O2; for example, the reference voltage Vref2 can be equal to the cell voltage of battery cell O2.

[0091] Understandably, the differential amplifier A2 is used to output a second voltage, which is proportional to the voltage difference between the non-inverting and inverting input terminals of the differential amplifier A2. For example, the differential amplifier A2 can amplify the voltage difference between its non-inverting and inverting input terminals before outputting it, or the differential amplifier A2 can directly output the voltage difference between its non-inverting and inverting input terminals. The subtraction circuit 14 is used to output a second difference voltage to the EIS detection circuit 30, which is the voltage difference between the second voltage and the reference voltage Vref2.

[0092] The current sampling circuit 20 is also used to sample the excitation current flowing through the battery cell 02 and output it to the EIS detection circuit 30. The EIS detection circuit 30 is also used to receive the second difference voltage output by the subtraction circuit 14 and the excitation current sampled by the current sampling circuit 20, and to detect the EIS of the battery cell 02.

[0093] It is understandable that the second voltage output by differential amplifier A2 contains both DC and AC components. The DC component is generated by the cell voltage of battery cell 02, and the AC component is generated by the response voltage of battery cell 02. The response voltage of battery cell 02 refers to the response voltage generated by the excitation current energizing battery cell 02. Furthermore, the magnitude of the reference voltage Vref2 received at the second input terminal of subtraction circuit 14 can be equal to the magnitude of this DC component. Accordingly, the second difference voltage obtained by subtracting the second voltage from the reference voltage Vref2 by subtraction circuit 14 is the response voltage generated by the excitation current energizing battery cell 02.

[0094] In this third implementation, each battery cell in the battery pack corresponds to a set of differential amplifiers and subtraction circuits, which enable independent sampling of the response voltage of a single battery cell. This allows for parallel sampling of the response voltages of multiple battery cells, effectively improving the sampling efficiency of the response voltage and consequently enhancing the EIS detection efficiency of the battery cell.

[0095] Understandably, the number of battery cells n in the battery pack can be greater than or equal to 2, for example, n can be equal to 16. Correspondingly, the voltage sampling circuit 10 can include n differential amplifiers corresponding one-to-one with the n battery cells, and n corresponding subtraction circuits. The non-inverting input of each differential amplifier is connected to the positive terminal of a corresponding battery cell, the inverting input is connected to the negative terminal of a corresponding battery cell, and the output is connected to the first input of a corresponding subtraction circuit. The second input of the n subtraction circuits is used to receive a reference voltage. Each differential amplifier can amplify and output the voltage difference across its connected battery cell, or it can directly output the voltage difference across its connected battery cell. Each subtraction circuit can subtract the voltage difference output by its connected differential amplifier from the corresponding reference voltage and then output the result.

[0096] Optionally, the second input terminals of the n subtraction circuits can be connected to the same reference power supply terminal and used to receive a high-precision reference voltage. This reference voltage can be equal to the cell voltage of each battery cell in the battery pack when fully charged. For example, it can be equal to 3.65V.

[0097] Alternatively, the voltage sampling circuit 10 may further include n low-pass filters, each corresponding to one of the n battery cells. Each low-pass filter is connected to the output of its corresponding differential amplifier and the second input of its corresponding subtraction circuit. It is used to low-pass filter the voltage difference output from the differential amplifier to obtain a reference voltage, which is then output to the second input of the corresponding subtraction circuit. This ensures that the reference voltage received at the second input of each subtraction circuit accurately follows the cell voltage of its corresponding battery cell, thereby ensuring accurate extraction of the response voltage of each cell and guaranteeing the detection accuracy of the EIS.

[0098] Optionally, as shown in Figures 6 to 8, the voltage sampling circuit 10 may further include a PGA and an ADC. The output of the subtraction circuit 11 is connected to the EIS detection circuit 30 through the PGA and the ADC. The PGA amplifies the response voltage output by the subtraction circuit 11 and outputs it to the ADC, while the ADC performs analog-to-digital conversion on the amplified response voltage and outputs it to the EIS detection circuit 30.

[0099] It is understood that, for the first and second implementation methods described above, referring to Figures 6 and 7, the voltage sampling circuit 10 may include a PGA and an ADC. The subtraction circuit 11 can output the response voltage of different battery cells at different time periods, the PGA can amplify the response voltage of different battery cells at different time periods, and the ADC can perform analog-to-digital conversion on the amplified response voltage of different battery cells at different time periods and output it to the EIS detection circuit 30.

[0100] For the third implementation described above, referring to Figure 8, the voltage sampling circuit 10 may include n PGAs and n ADCs, each corresponding to one of the n battery cells. The input of each PGA is connected to the output of a corresponding subtraction circuit, and the output of each PGA is connected to the input of a corresponding ADC. The outputs of the n ADCs are connected to the EIS detection circuit 30. Each PGA amplifies the response voltage of its corresponding battery cell, and each ADC performs analog-to-digital conversion on the amplified response voltage of its corresponding battery cell before outputting it to the EIS detection circuit 30.

[0101] Optionally, as shown in Figures 5 and 6, the current sampling circuit 20 can be connected to a current sensor 03 (such as a resistor) and used to sample the excitation current flowing through the battery cell. For example, the current sensor 03 can be connected in series with the battery cell to be tested. The current sampling circuit 20 can sample the excitation current flowing through the battery cell through the current sensor 03.

[0102] For example, referring to Figure 6, the current sampling circuit 20 may include a PGA, an ADC, a bias resistor R3, and a bias resistor R4. The PGA amplifies the sampled excitation current, and the ADC performs analog-to-digital conversion on the amplified excitation current before outputting it to the EIS detection circuit 30. One end of the bias resistor R3 and one end of the bias resistor R4 are connected to the input terminal of the PGA, and the other ends of the bias resistor R3 and the other ends of the bias resistor R4 are both connected to the bias power supply terminal V1.

[0103] As mentioned earlier, the excitation current can be provided in several ways, including cell-by-cell excitation, pack-level excitation, or cluster-level excitation. In the cell-by-cell excitation scenario, the current sampling circuit 20 can be connected to a current sensor 03, which can be connected in series with different battery cells among the n battery cells in the battery pack via a switching circuit. Accordingly, the current sampling circuit 20 can sample the excitation current flowing through different battery cells using the current sensor 03. Furthermore, the excitation current flowing through different battery cells can be the same or different.

[0104] For both pack-level and cluster-level excitation scenarios, the current sampling circuit 20 can be connected to a current sensor 03. Furthermore, the current sampling circuit 20 can simultaneously sample the excitation current flowing through the n battery cells via this single current sensor 03. The excitation current flowing through different battery cells can be the same. Specifically, for the pack-level excitation scenario, referring to Figure 6, the current sensor 03 can be connected in series with the n battery cells in the battery pack. For the cluster-level excitation scenario, referring to Figure 3, the current sensor can be connected in series with all the cells in the m battery packs included in a battery cluster. For example, this current sensor can be a current sensor in a cluster controller.

[0105] Alternatively, the subtraction circuit in the voltage sampling circuit 10 can also be implemented using a differential amplifier. Furthermore, since the voltages received at both inputs of the subtraction circuit are relatively low, for example, approximately equal to the cell voltage of a single battery cell (e.g., 3.65V), the subtraction circuit can be implemented using a common low-voltage differential amplifier. This low-voltage differential amplifier has a relatively simple structure and low cost.

[0106] In summary, this application provides a battery memory chip (BMIC) comprising a differential amplifier and a subtraction circuit. The non-inverting and inverting inputs of the differential amplifier are connected to the positive and negative terminals of the battery cell, respectively. The output is connected to the first input of the subtraction circuit, which receives a reference voltage. The output of the subtraction circuit is connected to an EIS detection circuit. The differential amplifier outputs the voltage difference across the battery cell, and the subtraction circuit subtracts this voltage difference from the reference voltage to obtain the response voltage generated by the excitation current across the battery cell. Since the solution provided in this application can extract the response voltage through the subtraction circuit, a high-voltage DC blocking capacitor is no longer needed in the battery pack (e.g., in the BMU). Consequently, the size of the BMU can be effectively reduced, lowering its structural complexity and cost.

[0107] This application also provides another BMIC, which can be applied to application scenarios such as those shown in Figures 1 to 3. As shown in Figure 9, the BMIC includes: a voltage sampling circuit 10, a current sampling circuit 20, and an EIS detection circuit 30. The voltage sampling circuit 10 includes: a differential amplifier A1 and a DC blocking capacitor C1.

[0108] The non-inverting input (+) of differential amplifier A1 is connected to the positive terminal of battery cell 01 in the battery pack, and the inverting input (-) of differential amplifier A1 is connected to the negative terminal of battery cell 01. The output of differential amplifier A1 is connected to EIS detection circuit 30 through DC blocking capacitor C1. Battery cell 01 includes one or more cells connected in series. Figure 9 illustrates an example where battery cell 01 includes one cell.

[0109] The current sampling circuit 20 samples the excitation current flowing through the battery cell 01 and outputs it to the EIS detection circuit 30. The EIS detection circuit 30 receives the output of the differential amplifier A1 and the output of the current sampling circuit 20, and detects the EIS of the battery cell 01.

[0110] It is understood that the differential amplifier A1 is used to output a first voltage, which is proportional to the voltage difference between the non-inverting and inverting input terminals of the differential amplifier A1. For example, the differential amplifier A1 can amplify the voltage difference between its non-inverting and inverting input terminals before outputting it, or the differential amplifier A1 can directly output the voltage difference between its non-inverting and inverting input terminals. The DC blocking capacitor C1 is used to filter out the DC component in the first voltage before outputting it to the EIS detection circuit 30. That is, the DC blocking capacitor C1 can output the AC component in the first voltage to the EIS detection circuit 30. The AC component output by the DC blocking capacitor C1 is the response voltage generated by the excitation current to the battery cell 01. Or it can be understood that the first voltage after filtering out the DC component is the response voltage generated by the excitation current to the battery cell 01.

[0111] It is also understood that the battery pack may include multiple battery cells connected in series, and the aforementioned battery cell 01 can be any one of these multiple battery cells. Based on the principle of a differential amplifier, by connecting the non-inverting and inverting input terminals of differential amplifier A1 to the positive and negative terminals of battery cell 01 respectively, differential amplifier A1 can remove the higher common-mode voltage on battery cell 01. Furthermore, differential amplifier A1 can amplify and output the differential-mode voltage on battery cell 01, or it can directly output the differential-mode voltage. As shown in Figure 9, since the differential-mode voltage output by differential amplifier A1 (i.e., the aforementioned first voltage) is close to the voltage of a single battery cell (e.g., 3.65V), the voltage rating requirement for the DC blocking capacitor C1 can be effectively reduced. That is, the DC blocking capacitor C1 can be a low-voltage capacitor. For example, the voltage rating of the DC blocking capacitor C1 only needs to be greater than the voltage of a single battery cell in the battery pack (e.g., 3.65V).

[0112] It is also understood that low-voltage capacitors are not only smaller and less expensive, but also have a wider range of capacitance values ​​to choose from. Accordingly, in this embodiment, a high-capacitance capacitor can be selected as the DC blocking capacitor C1. Therefore, the cutoff frequency of the high-pass filter formed by the DC blocking capacitor C1 and the bias resistor in the BMIC is relatively low, which effectively reduces the attenuation of the response voltage generated by low-frequency excitation current, ensuring the accuracy of EIS detection. For example, the capacitance value of the DC blocking capacitor C1 can be greater than 15uF, such as 20uF, 30uF, or 50uF.

[0113] It's also understandable that the differential-mode voltage of a battery cell can refer to the voltage difference between the positive and negative terminals of the cell. The common-mode voltage of a battery cell can refer to the voltage of the positive or negative terminal of the cell relative to a reference point (e.g., common ground). Therefore, in scenarios with multiple battery cells connected in series, the common-mode voltages of different battery cells are different, and some battery cells have higher common-mode voltages. For example, assuming each battery cell includes one cell with a single cell voltage of 3.65V, then the voltage at the positive terminal of the first cell is 3.65V, the voltage at the negative terminal is 0V, and its common-mode voltage at the positive terminal is 1.825V. As shown in Figure 9, the voltage at the positive terminal of the 16th cell is 58.4V, the voltage at the negative terminal is 54.75V, and its common-mode voltage at the positive terminal is 58.4V, while its common-mode voltage at the negative terminal is 54.75V.

[0114] Optionally, the withstand voltage of the DC blocking capacitor C1 can be less than or equal to 5V. It is understood that, for a scenario where the cell voltage of a single battery cell is approximately 3.65V, the withstand voltage of the DC blocking capacitor C1 can be greater than 3.65V and less than or equal to 5V. Therefore, the withstand voltage of the DC blocking capacitor C1 can be minimized while ensuring effective filtering of the DC component in the first voltage. This, in turn, effectively reduces the cost and size of the battery pack.

[0115] As a first optional implementation, as shown in Figure 10, the voltage sampling circuit 10 may further include a switching circuit 13. The switching circuit 13 has multiple pairs of input terminals, each pair of which is used to connect the positive and negative terminals of a battery cell. For example, referring to Figure 10, the first pair of input terminals of the switching circuit 13 is used to connect the positive and negative terminals of battery cell 01, and the last pair of input terminals is used to connect the positive and negative terminals of battery cell 02. The output terminal of the switching circuit 13 is connected to the non-inverting input (+) and the inverting input (-) of the differential amplifier A1, respectively. Furthermore, the switching circuit 13 is used to connect only the positive terminal of one battery cell to the non-inverting input of the differential amplifier A1 and the negative terminal of that battery cell to the inverting input of the differential amplifier A1 at any given time.

[0116] For example, in a first time period, switching circuit 13 connects the positive and negative terminals of battery cell 01 to the non-inverting and inverting input terminals of differential amplifier A1, respectively, thereby transferring the voltage across battery cell 01 to the non-inverting and inverting input terminals of differential amplifier A1. Furthermore, in a second time period, switching circuit 13 connects the positive and negative terminals of battery cell 02 to the non-inverting and inverting input terminals of differential amplifier A1, respectively, thereby transferring the voltage across battery cell 02 to the non-inverting and inverting input terminals of differential amplifier A1. The first and second time periods do not overlap.

[0117] Accordingly, differential amplifier A1 can output a first voltage during a first time period, which is proportional to the voltage difference between the non-inverting and inverting input terminals of differential amplifier A1 during the first time period. Differential amplifier A1 is also used to output a second voltage during a second time period. This second voltage is proportional to the voltage difference between the non-inverting and inverting input terminals of differential amplifier A1 during the second time period. DC blocking capacitor C1 is also used to filter out the DC component in the second voltage before outputting it to the EIS detection circuit 30.

[0118] The current sampling circuit 20 is also used to sample the excitation current flowing through the battery cell 02 and output it to the EIS detection circuit 30. The excitation current flowing through the battery cell 02 can be the same as or different from the excitation current flowing through the battery cell 01; this embodiment does not limit this. The EIS detection circuit 30 is also used to detect the EIS of the battery cell 02 based on the second voltage after filtering out the DC component and the excitation current sampled by the current sampling circuit 20. The second voltage after filtering out the DC component is the response voltage generated by the excitation current stimulating the battery cell 02.

[0119] In this first implementation, the switching circuit 13 in the voltage sampling circuit 10 can transmit the voltages across different battery cells to the non-inverting and inverting inputs of the differential amplifier A1 at different time periods. This ensures that the differential amplifier A1 can amplify and output (or directly output) the voltage differences across different battery cells at different time periods. Furthermore, the DC blocking capacitor C1 can filter out the DC component in different voltage differences at different time periods before outputting, meaning that the DC blocking capacitor C1 can output the response voltages of different battery cells at different time periods. Therefore, based on this first implementation, the voltage sampling circuit 10 can sequentially sample the response voltages of multiple battery cells using a set of differential amplifiers A1 and DC blocking capacitors C1, thereby effectively reducing the cost, size, and structural complexity of the battery pack.

[0120] Understandably, the number n of battery cells included in the battery pack can be greater than or equal to 2, for example, n can be equal to 16. Correspondingly, the switching circuit 13 can have n pairs of input terminals and one pair of output terminals. Each pair of input terminals is used to connect the positive and negative terminals of one battery cell, and the pair of output terminals of the switching circuit 13 can be connected to the non-inverting and inverting input terminals of the differential amplifier A1. Furthermore, the switching circuit 13 can switch the voltage across each of the n battery cells to the non-inverting and inverting input terminals of the differential amplifier A1, so that the differential amplifier A1 can sequentially amplify the voltage difference across each of the n battery cells before outputting (or sequentially output the voltage differences across the n battery cells). Correspondingly, the DC blocking capacitor C1 can sequentially filter out the DC component in different voltage differences before outputting, that is, the DC blocking capacitor C1 can sequentially output the response voltages of the n battery cells.

[0121] As mentioned earlier, the common-mode voltages of different battery cells in the battery pack are different. If the scheme shown in Figure 4 is used to directly sample the voltage of the battery cells through the DC blocking capacitor, the different common-mode voltages of the different battery cells will cause the DC bias voltages of the DC blocking capacitors connected to the different battery cells to be different, resulting in different degrees of capacitance attenuation of the different DC blocking capacitors. Consequently, the filtering characteristics (such as cutoff frequency) of the high-pass filters formed by the different DC blocking capacitors will be different, that is, the filtering characteristics of the voltage sampling channels of different battery cells will be different, and the filtering characteristics of each voltage sampling channel need to be calibrated through a hardware calibration loop. This significantly increases the design and structural complexity of the battery pack. Here, the voltage sampling channel of the battery cell can refer to the signal processing channel composed of various devices used to sample the response voltage of the battery cell, and this voltage sampling channel can include devices such as DC blocking capacitors, amplifiers, and ADCs.

[0122] In this embodiment, since the common-mode voltage on the battery cells can be removed by a differential amplifier, the DC bias voltage applied to the DC blocking capacitor C1 can be kept constant at the voltage of a single battery cell (e.g., 3.65V). This effectively avoids the problem of different filtering characteristics in the voltage sampling channels of different battery cells. Consequently, there is no need to set up a hardware calibration loop in the battery pack, thereby effectively reducing the design and structural complexity of the battery pack and lowering its cost.

[0123] It is understandable that in the scenario shown in Figure 4, if a switching circuit is used to connect multiple battery cells to the DC blocking capacitor, the DC bias voltage applied to the DC blocking capacitor by some battery cells will be relatively high, resulting in a longer charging and stabilization time for the DC blocking capacitor. Consequently, the switching circuit cannot achieve high-speed switching. However, in this embodiment, since the DC bias voltage applied to the DC blocking capacitor C1 is low, the charging and stabilization time of the DC blocking capacitor C1 is shorter. Accordingly, high-speed switching sampling of the response voltages of n battery cells can be achieved through the pre-switching circuit 13, thereby ensuring high detection efficiency of EIS.

[0124] As a second optional implementation, as shown in Figure 11, the voltage sampling circuit 10 may further include a switching circuit 13. Furthermore, the voltage sampling circuit 10 may include multiple differential amplifiers, the input terminals of which are connected one-to-one with multiple battery cells in the battery pack. For example, Figure 11 shows differential amplifiers A1 and A2. The non-inverting input (+) of differential amplifier A2 is connected to the positive terminal of battery cell O2 in the battery pack, and the inverting input (-) of differential amplifier A2 is connected to the negative terminal of battery cell O2. Differential amplifier A1 outputs a first voltage, and differential amplifier A2 outputs a second voltage. The first voltage is proportional to the voltage difference between the non-inverting and inverting input terminals of differential amplifier A1, and the second voltage is proportional to the voltage difference between the non-inverting and inverting input terminals of differential amplifier A2.

[0125] The switching circuit 13 has multiple input terminals and one output terminal. Each of the multiple input terminals is used to connect to the output terminal of a differential amplifier, and the output terminal of the switching circuit 13 is connected to the DC blocking capacitor C1. Furthermore, the switching circuit 13 is configured to connect only one differential amplifier output terminal to the DC blocking capacitor C1 at any given time.

[0126] For example, in a first time period, switching circuit 13 connects the output terminal of differential amplifier A1 to DC blocking capacitor C1, thereby transmitting the first voltage output by differential amplifier A1 to DC blocking capacitor C1. Furthermore, switching circuit 13 connects the output terminal of differential amplifier A2 to DC blocking capacitor C1 in a second time period, thereby transmitting the second voltage output by differential amplifier A2 to DC blocking capacitor C1. DC blocking capacitor C1 also filters out the DC component in the second voltage before outputting it to EIS detection circuit 30. The first and second time periods do not overlap, meaning that switching circuit 13 can transmit voltages output by different differential amplifiers to DC blocking capacitor C1 in different time periods.

[0127] The current sampling circuit 20 is also used to sample the excitation current flowing through the battery cell 02 and output it to the EIS detection circuit 30. The EIS detection circuit 30 is also used to receive the second voltage after filtering out the DC component output by the DC blocking capacitor C1, and to detect the EIS of the battery cell 02 based on the second voltage after filtering out the DC component and the excitation current sampled by the current sampling circuit 20. The second voltage after filtering out the DC component is the response voltage generated by the excitation current in the battery cell 02.

[0128] In this second implementation, the switching circuit 13 in the voltage sampling circuit 10 can transmit the voltages output by different differential amplifiers (e.g., the voltage difference across different battery cells) to the DC blocking capacitor C1 at different time periods. This ensures that the DC blocking capacitor C1 can filter out the DC component in different voltage differences at different time periods, meaning that the DC blocking capacitor C1 can output the response voltage of different battery cells at different time periods. Therefore, based on this second implementation, the voltage sampling circuit 10 can sample the response voltages of multiple battery cells using only one DC blocking capacitor C1, effectively reducing the cost, size, and structural complexity of the battery pack.

[0129] It is understood that the number of battery cells n in the battery pack can be greater than or equal to 2, for example, n can be equal to 16. Correspondingly, the voltage sampling circuit 10 can include n differential amplifiers, each corresponding to one of the n battery cells. The non-inverting input of each differential amplifier is connected to the positive terminal of a corresponding battery cell, the inverting input is connected to the negative terminal of a corresponding battery cell, and the output is connected to one input of the switching circuit 13. The output of the switching circuit 13 can be connected to the DC blocking capacitor C1. Each differential amplifier can amplify and output the voltage difference across its connected battery cell, or it can directly output the voltage difference across its connected battery cell. The switching circuit 13 can switch the voltage difference output from the n differential amplifiers to the DC blocking capacitor C1, so that the DC blocking capacitor C1 can sequentially filter out the DC component of the voltage difference across each of the n battery cells and sequentially output the response voltage of the n battery cells.

[0130] Optionally, the switching circuit 13 in the first and second implementations described above can be a single-pole multi-throw switch, or a gating switch.

[0131] As a third optional implementation, as shown in Figure 12, the voltage sampling circuit 10 may further include: multiple differential amplifiers and multiple DC blocking capacitors. The non-inverting and inverting input terminals of the multiple differential amplifiers are connected one-to-one with the positive and negative terminals of the multiple battery cells, and the output terminals of the multiple differential amplifiers are connected one-to-one with one end of the multiple DC blocking capacitors. The other ends of the multiple DC blocking capacitors are all connected to the EIS detection circuit 30.

[0132] For example, Figure 12 schematically shows two differential amplifiers A1 and A2, and two DC blocking capacitors C1 and C2. The non-inverting input (+) of differential amplifier A2 is connected to the positive terminal of battery cell O2 in the battery pack, and the inverting input (-) of differential amplifier A2 is connected to the negative terminal of battery cell O2. The output of differential amplifier A2 is connected to the EIS detection circuit 30 through the DC blocking capacitor C2.

[0133] The differential amplifier A2 is used to output a second voltage, which is proportional to the voltage difference between the non-inverting and inverting input terminals of the differential amplifier A2. The DC blocking capacitor C2 is used to filter out the DC component in the second voltage before it is output to the EIS detection circuit 30.

[0134] The current sampling circuit 20 is also used to sample the excitation current flowing through the battery cell 02 and output it to the EIS detection circuit 30. The EIS detection circuit 30 is used to receive the second voltage after filtering out the DC component output by the DC blocking capacitor C2, and to detect the EIS of the battery cell 02 based on the second voltage after filtering out the DC component and the excitation current sampled by the current sampling circuit 20. The second voltage after filtering out the DC component is the response voltage generated by the excitation current in the battery cell 02.

[0135] In this third implementation, each battery cell in the battery pack corresponds to a set of differential amplifiers and DC blocking capacitors. This set of differential amplifiers and DC blocking capacitors enables independent sampling of the response voltage of a single battery cell. Therefore, parallel sampling of the response voltages of multiple battery cells can be achieved, effectively improving the sampling efficiency of the response voltage and thus enhancing the detection efficiency of EIS.

[0136] Understandably, the number of battery cells n in the battery pack can be greater than or equal to 2, for example, n can be equal to 16. Correspondingly, the voltage sampling circuit 10 can include n differential amplifiers corresponding one-to-one with the n battery cells, and n DC blocking capacitors corresponding one-to-one with each other. The non-inverting input of each differential amplifier is connected to the positive terminal of a corresponding battery cell, the inverting input is connected to the negative terminal of a corresponding battery cell, and the output is connected to a corresponding DC blocking capacitor. Each differential amplifier can amplify and output the voltage difference across its connected battery cell, or it can directly output the voltage difference across its connected battery cell. Each DC blocking capacitor can filter out the DC component of the voltage difference output by the differential amplifier it is connected to; that is, each DC blocking capacitor can extract the response voltage of its corresponding battery cell.

[0137] Optionally, as shown in Figures 10 to 12, the voltage sampling circuit 10 may further include a PGA and an ADC. The DC blocking capacitor C1 is connected to the EIS detection circuit 30 through the PGA and the ADC. The PGA amplifies the response voltage output by the DC blocking capacitor C1 and outputs it to the ADC, while the ADC performs analog-to-digital conversion on the amplified response voltage and outputs it to the EIS detection circuit 30.

[0138] It is understood that, for the first and second implementation methods described above, referring to Figures 10 and 11, the voltage sampling circuit 10 may include a PGA and an ADC. Since the DC blocking capacitor C1 can output the response voltage of different battery cells at different times, the PGA can amplify the response voltage of different battery cells at different times, and the ADC can perform analog-to-digital conversion on the amplified response voltage of different battery cells at different times and output it to the EIS detection circuit 30.

[0139] For the third implementation described above, referring to Figure 12, the voltage sampling circuit 10 may include n PGAs and n ADCs, each corresponding to one of the n battery cells. The input terminal of each PGA is connected to a corresponding DC blocking capacitor, and the output terminal of each PGA is connected to the input terminal of a corresponding ADC. The output terminals of all n ADCs are connected to the EIS detection circuit 30. Each PGA amplifies the response voltage output by its corresponding DC blocking capacitor, and each ADC performs analog-to-digital conversion on the amplified response voltage before outputting it to the EIS detection circuit 30.

[0140] Optionally, as shown in Figures 10 to 12, the voltage sampling circuit 10 may further include a bias resistor connected to the input terminal of the PGA. For example, in the implementation shown in Figures 10 and 11, the voltage sampling circuit 10 may further include a bias resistor R1. One end of the bias resistor R1 is connected to the input terminal of the PGA, and the other end is connected to the bias power supply terminal V1. Furthermore, the bias resistor R1 and the DC blocking capacitor C1 can form a high-pass filter, which can perform high-pass filtering on the voltage output of the differential amplifier to filter out the DC component in the voltage output of the differential amplifier.

[0141] In the implementation shown in Figure 12, the voltage sampling circuit 10 may further include bias resistors R1 and R2. One end of bias resistor R1 is connected to the input terminal of one PGA, and one end of bias resistor R2 is connected to the input terminal of another PGA. The other ends of both bias resistors R1 and R2 are connected to the bias power supply terminal V1. Furthermore, bias resistor R1 can form a high-pass filter with DC blocking capacitor C1, which can perform high-pass filtering on the first voltage output by differential amplifier A1 to remove the DC component from the first voltage. Similarly, bias resistor R2 can form a high-pass filter with DC blocking capacitor C2, which can perform high-pass filtering on the second voltage output by differential amplifier A2 to remove the DC component from the second voltage.

[0142] It is understandable that, for the implementation shown in Figure 12, since the voltage sampling circuit 10 can include n PGAs, it can also include n bias resistors corresponding one-to-one with each of the n PGAs. Each bias resistor is connected to the input terminal of a corresponding PGA and can form a high-pass filter with a corresponding DC blocking capacitor.

[0143] It is also understandable that, as mentioned earlier, in scenarios where multiple battery cells are connected in series, some battery cells will have higher voltages; for example, the voltage at the positive terminal of the 16th battery cell may reach 58.4V. Therefore, the differential amplifier in this embodiment can be a high-voltage differential amplifier to ensure effective detection and output of the voltage difference across each battery cell in the battery pack. This differential amplifier can also be referred to as a buffer or voltage buffer. Correspondingly, the high-voltage differential amplifier can also be referred to as a high-voltage buffer.

[0144] Optionally, as shown in Figure 10, the current sampling circuit 20 can be connected to the battery cells in the battery pack via a current sensor 03 (such as a resistor). For example, the current sensor 03 can be connected in series with the battery cell to be tested. The current sampling circuit 20 can sample the excitation current flowing through the battery cell via the current sensor 03. The implementation of the current sensor 03 and the current sampling circuit 20 can be referred to the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0145] In summary, this application provides a battery microcontroller (BMIC) whose voltage sampling circuit includes a differential amplifier and a DC blocking capacitor. The non-inverting and inverting inputs of the differential amplifier are connected to the positive and negative terminals of the battery cells in the battery pack, respectively, and the output is connected to the EIS detection circuit via the DC blocking capacitor. This differential amplifier effectively removes the high common-mode voltage on the battery cells and outputs the differential-mode voltage. Since the differential-mode voltage output by the differential amplifier is close to the voltage of a single battery cell, the required voltage rating of the DC blocking capacitor is effectively reduced. That is, the DC blocking capacitor can be a low-voltage capacitor, whose voltage rating only needs to be greater than the voltage of a single battery cell in the battery pack. This low-voltage capacitor is small in size and low in cost, thus effectively reducing the size and cost of the BMU.

[0146] Furthermore, low-voltage capacitors offer a wider range of capacitance values ​​to choose from. Accordingly, the solution provided in this application embodiment can select a high-capacitance capacitor as the DC blocking capacitor. The high-pass filter formed by this DC blocking capacitor and the bias resistor in the BMIC has a relatively low cutoff frequency, which effectively reduces the attenuation of the response voltage generated by the low-frequency excitation current, ensuring the accuracy of EIS detection.

[0147] This application also provides another type of BMIC, which can be applied to application scenarios such as those shown in Figures 1 to 3. As shown in Figure 13, the BMIC includes: a voltage sampling circuit 10, a current sampling circuit 20, and an EIS detection circuit 30. The voltage sampling circuit 10 includes: a differential amplifier A1 and an ADC.

[0148] In this circuit, the non-inverting input (+) of differential amplifier A1 is connected to the positive terminal of battery cell 01 in the battery pack, and the inverting input (-) of differential amplifier A1 is connected to the negative terminal of battery cell 01. The output of differential amplifier A1 is connected to EIS detection circuit 30 via ADC. Battery cell 01 may consist of one battery cell or multiple battery cells connected in series. Figure 13 illustrates an example where battery cell 01 consists of one battery cell.

[0149] In this embodiment, differential amplifier A1 is used to output a first voltage, which is proportional to the voltage difference between the non-inverting and inverting input terminals of differential amplifier A1. For example, differential amplifier A1 can amplify the voltage difference between its non-inverting and inverting input terminals before outputting it, or differential amplifier A1 can directly output the voltage difference between its non-inverting and inverting input terminals.

[0150] The ADC is used to perform analog-to-digital conversion on the first voltage and output it to the EIS detection circuit 30, and the resolution of the ADC is greater than a threshold. The current sampling circuit 20 is used to sample the excitation current flowing through the battery cell 01 and output it to the EIS detection circuit 30. The EIS detection circuit 30 is used to receive the output of the ADC and the output of the current sampling circuit 20, and detect the EIS of the battery cell 01.

[0151] Understandably, differential amplifier A1 can remove the higher common-mode voltage on battery cell 01. Furthermore, differential amplifier A1 can amplify and output the differential-mode voltage on battery cell 01, or it can directly output the differential-mode voltage. Since the differential-mode voltage output by differential amplifier A1 (i.e., the aforementioned first voltage) is close to the voltage of a single battery cell (e.g., 3.65V), it meets the input voltage range requirements of the ADC, ensuring that the ADC performs effective analog-to-digital conversion on this first voltage.

[0152] As mentioned earlier, the first voltage output by differential amplifier A1 contains both DC and AC components. The DC component is generated by the cell voltage of battery cell 01, while the AC component is generated by the response voltage of battery cell 01. The response voltage refers to the voltage generated by the excitation current energizing battery cell 01; its amplitude is typically much smaller than the amplitude of the cell voltage.

[0153] In the solution provided in this application embodiment, in order to achieve accurate sampling of the response voltage, the resolution of the ADC needs to be greater than a threshold, that is, the ADC can be a high-resolution (i.e., high-precision) ADC. For example, the threshold can be 14 bits, then the resolution of the ADC can be greater than 14 bits, such as 16 bits or higher. This high-resolution ADC can achieve accurate sampling of the first voltage, thereby ensuring that the EIS detection circuit 30 can accurately extract the response voltage with a small amplitude from the first voltage and perform subsequent EIS detection. In addition, since the high-resolution ADC can achieve accurate sampling of the first voltage, and thus achieve accurate sampling of the response voltage, there is no need to set a DC blocking capacitor in the battery pack, thereby effectively reducing the size and structural complexity of the BMU.

[0154] For example, assume that the DC component amplitude of the first voltage output by differential amplifier A1 is approximately 3.65V, and the AC component amplitude is approximately 200uV. If the ADC reference voltage is 5V (which needs to be greater than the cell voltage of a single battery cell) and the resolution is 14 bits, then when the ADC performs analog-to-digital conversion on this first voltage, the sampling voltage corresponding to one AD value is approximately: 5V / (2 14 -1)≈305.2uV. Here, the AD value refers to the value after the analog signal is converted to a digital signal. If the ADC resolution is 16 bits, then when the ADC performs analog-to-digital conversion on this first voltage, the sampling voltage corresponding to one AD value is approximately: 5V / (2 16 -1)≈76.3uV. This sampling voltage of 76.3uV is much smaller than the amplitude of the AC component (i.e., the response voltage) of 200uV in the first voltage, so accurate sampling of the response voltage can be achieved.

[0155] As a first optional implementation, the voltage sampling circuit 10 may also include a switching circuit 13 as shown in Figure 6 or Figure 10. The connection relationships and functions of the switching circuit 13 can be found in the descriptions of the embodiments shown in Figure 6 or Figure 10, and will not be repeated here. In this first implementation, the switching circuit 13 can transmit the voltages across different battery cells to the non-inverting and inverting inputs of the differential amplifier A1 at different time periods. This ensures that the differential amplifier A1 can amplify and output (or output the voltage differences across different battery cells) the voltage differences at different time periods. Furthermore, the ADC can perform analog-to-digital conversion on the voltage differences of different battery cells at different time periods and then output the results. Therefore, the voltage sampling circuit 10, through a set of differential amplifiers A1 and ADC, can sequentially sample the response voltages of multiple battery cells, thereby effectively reducing the cost, size, and structural complexity of the BMIC.

[0156] As a second optional implementation, the voltage sampling circuit 10 may further include a switching circuit 13 as shown in Figures 7 and 11, and the voltage sampling circuit 10 may include multiple differential amplifiers connected one-to-one with multiple battery cells. The connection relationship and function of the multiple differential amplifiers, as well as the connection relationship and function of the switching circuit 13, can be referred to the relevant descriptions of the embodiments shown in Figures 7 or 11, and will not be repeated here. In this second implementation, the switching circuit 13 in the voltage sampling circuit 10 can transmit the voltages output by different differential amplifiers (e.g., the voltage difference across different battery cells) to the ADC at different time periods. Thus, it can be ensured that the ADC can output the voltage difference of different battery cells after analog-to-digital conversion at different time periods. Therefore, based on this second implementation, the voltage sampling circuit 10 can sample the response voltages of multiple battery cells through a single ADC, thereby effectively reducing the cost, size, and structural complexity of the BMIC.

[0157] As a third optional implementation, the voltage sampling circuit 10 may further include multiple differential amplifiers, such as those shown in Figures 8 and 12. Furthermore, the voltage sampling circuit 10 may include multiple ADCs. The input terminals of these multiple differential amplifiers are connected one-to-one with multiple battery cells, and the output terminals of these multiple differential amplifiers are connected one-to-one with multiple ADCs. The functions of these multiple differential amplifiers can be referred to the relevant descriptions of the embodiments shown in Figures 8 or 12, and will not be repeated here.

[0158] In this third implementation, each battery cell in the battery pack corresponds to a set of differential amplifiers and ADCs, which enable independent sampling of the response voltage of a single battery cell. This allows for parallel sampling of the response voltages of multiple battery cells, effectively improving the sampling efficiency of the response voltage and consequently enhancing the detection efficiency of EIS.

[0159] Optionally, as shown in Figures 6 to 8 and Figures 10 to 12, the voltage sampling circuit 10 may further include a PGA. The output of the differential amplifier A1 is connected to the ADC through the PGA. The PGA is used to amplify the first voltage output by the differential amplifier A1 before outputting it to the ADC. It is understood that after the PGA amplifies the first voltage, both the DC and AC components in the first voltage will be amplified. This can effectively reduce the resolution requirement of the ADC; for example, the ADC resolution can be 14 bits. Of course, if the resolution of the ADC in the voltage sampling circuit 10 is high enough, the voltage sampling circuit 10 may not need to include a PGA, thereby effectively reducing the size and structural complexity of the BMIC.

[0160] This application also provides a battery pack comprising: at least one battery cell, and a battery microcontroller (BMIC) as described in the above embodiments. For example, the BMIC may be as shown in any of Figures 5 to 13. The BMIC is connected to the at least one battery cell and is used to detect the energy index (EIS) of the at least one battery cell. For example, the BMIC may detect the EIS of each battery cell in the at least one battery cell.

[0161] This application also provides an energy storage system, as shown in FIG1, which includes multiple battery packs. Each battery pack can be the battery pack provided in the above embodiments.

[0162] As can be understood, as mentioned above, the energy storage system may also include a BMS, which may include a battery control unit (BCU) and multiple battery monitoring units (BMUs). Each battery pack contains one or more BMUs (also called BMU boards), and these BMU boards include the BMICs provided in the embodiments described above.

[0163] Optionally, the DC blocking capacitors (such as DC blocking capacitors C1 and C2) in the BMIC provided in the above embodiments can be integrated within the BMIC. Alternatively, the DC blocking capacitors can also be placed on the BMU board and connected to the differential amplifier and PGA in the BMIC. That is, the BMU in the battery pack includes the BMIC and the DC blocking capacitors, with one end of the DC blocking capacitor connected to the output terminal of the differential amplifier in the BMIC and the other end connected to the input terminal of the PGA in the BMIC. Alternatively, it can be understood that the output terminal of the differential amplifier in the BMIC and the input terminal of the PGA are connected through a DC blocking capacitor outside the BMIC.

[0164] In the embodiments of this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" refers to one or more, and "multiple" refers to two or more.

[0165] The above description is merely an optional implementation of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A battery management chip, characterized in that, The battery management chip includes: a voltage sampling circuit, a current sampling circuit, and an electrochemical impedance spectroscopy detection circuit; wherein, the voltage sampling circuit includes: a differential amplifier and a subtraction circuit; The non-inverting input of the differential amplifier is connected to the positive terminal of the battery cell, the inverting input of the differential amplifier is connected to the negative terminal of the battery cell, the output of the differential amplifier is connected to the first input of the subtraction circuit, the second input of the subtraction circuit is used to receive a reference voltage, and the output of the subtraction circuit is connected to the electrochemical impedance spectroscopy detection circuit; the battery cell includes one or more cells connected in series. The current sampling circuit is used to sample the excitation current flowing through the battery cell and output it to the electrochemical impedance spectroscopy detection circuit. The electrochemical impedance spectroscopy detection circuit is used to receive the output of the subtraction circuit and the output of the current sampling circuit, and to detect the electrochemical impedance spectrum of the battery cell.

2. The battery management chip of claim 1, wherein, The voltage sampling circuit further includes: a low-pass filter; The low-pass filter is connected to the output terminal of the differential amplifier and the second input terminal of the subtraction circuit, respectively, and the low-pass filter is used to provide the reference voltage to the second input terminal of the subtraction circuit.

3. The battery management chip according to claim 1 or 2, characterized in that, The voltage sampling circuit further includes: a switching circuit; The switching circuit has multiple pairs of input terminals, each of which is used to connect the positive and negative terminals of a battery cell. The switching circuit is used to connect the positive terminal of only one battery cell to the non-inverting input terminal of the differential amplifier and the negative terminal of the battery cell to the inverting input terminal of the differential amplifier at the same time.

4. The battery management chip according to claim 1 or 2, characterized in that, The voltage sampling circuit includes multiple differential amplifiers connected one-to-one with multiple battery cells, and the voltage sampling circuit also includes a switching circuit; The switching circuit has multiple input terminals, each of which is used to connect to the output terminal of one of the differential amplifiers; the switching circuit is used to connect only the output terminal of one of the differential amplifiers to the first input terminal of the subtraction circuit at the same time.

5. The battery management chip according to claim 1 or 2, characterized in that, The voltage sampling circuit includes: a plurality of differential amplifiers connected one-to-one with a plurality of battery cells, and a plurality of subtraction circuits connected one-to-one with the output terminals of the plurality of differential amplifiers.

6. A battery management chip, characterized in that, The battery management chip includes: a voltage sampling circuit, a current sampling circuit, and an electrochemical impedance spectroscopy detection circuit; wherein, the voltage sampling circuit includes: a differential amplifier and a DC blocking capacitor; The non-inverting input of the differential amplifier is used to connect to the positive terminal of the battery cell, and the inverting input of the differential amplifier is used to connect to the negative terminal of the battery cell. The output of the differential amplifier is connected to the electrochemical impedance spectroscopy detection circuit through the DC blocking capacitor. The battery cell includes one or more cells connected in series. The current sampling circuit is used to sample the excitation current flowing through the battery cell and output it to the electrochemical impedance spectroscopy detection circuit. The electrochemical impedance spectroscopy detection circuit is used to receive the output of the DC blocking capacitor and the output of the current sampling circuit, and to detect the electrochemical impedance spectrum of the battery cell.

7. The battery management chip of claim 6, wherein, The voltage sampling circuit further includes: a switching circuit; The switching circuit has multiple pairs of input terminals, each of which is used to connect the positive and negative terminals of a battery cell. The switching circuit is used to connect the positive terminal of only one battery cell to the non-inverting input terminal of the differential amplifier and the negative terminal of the battery cell to the inverting input terminal of the differential amplifier at the same time.

8. The battery management chip according to claim 6, characterized in that, The voltage sampling circuit includes multiple differential amplifiers connected one-to-one with multiple battery cells, and the voltage sampling circuit also includes a switching circuit; The switching circuit has multiple input terminals, each of which is used to connect to the output terminal of one of the differential amplifiers; the switching circuit is used to connect only the output terminal of one of the differential amplifiers to the DC blocking capacitor at the same time.

9. The battery management chip according to claim 6, characterized in that, The voltage sampling circuit includes: a plurality of differential amplifiers connected one-to-one with a plurality of battery cells, and a plurality of DC blocking capacitors connected one-to-one with the output terminals of the plurality of differential amplifiers.

10. The battery management chip according to any one of claims 6 to 9, characterized in that, The battery unit includes a cell, and the withstand voltage of the DC blocking capacitor is greater than the cell voltage and less than or equal to 5V.

11. A battery management chip, characterized in that, The battery management chip includes: a voltage sampling circuit, a current sampling circuit, and an electrochemical impedance spectroscopy detection circuit; wherein, the voltage sampling circuit includes: a differential amplifier and an analog-to-digital converter; The non-inverting input of the differential amplifier is connected to the positive terminal of the battery cell, and the inverting input of the differential amplifier is connected to the negative terminal of the battery cell. The output of the differential amplifier is connected to the electrochemical impedance spectroscopy detection circuit through the analog-to-digital converter. The battery cell includes one or more cells connected in series. The resolution of the analog-to-digital converter is greater than a threshold. The current sampling circuit is used to sample the excitation current flowing through the battery cell and output it to the electrochemical impedance spectroscopy detection circuit. The electrochemical impedance spectroscopy detection circuit is used to receive the output of the analog-to-digital converter and the output of the current sampling circuit, and to detect the electrochemical impedance spectrum of the battery cell.

12. A battery pack, characterized in that, The battery pack includes: at least one battery cell, and a battery management chip as described in any one of claims 1 to 11, wherein the battery management chip is connected to the at least one battery cell and is used to detect the electrochemical impedance spectroscopy of the at least one battery cell; Each of the at least one battery cell comprises one or more cells connected in series.

13. An energy storage system, characterized in that, The energy storage system includes: a plurality of battery packs as described in claim 12.

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