Modular MOS transistor layout structure having standard cell, and usage method
By dividing the MOSFET layout into NMOS and PMOS modules and introducing placement and routing boundaries and power and ground rails, the problem of the lack of a standard structure for MOSFET layouts is solved, and automated placement and routing and efficient layout generation are achieved.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- NINGBO QINGYUN CHUANGXIN TECHNOLOGY CO LTD
- Filing Date
- 2025-10-31
- Publication Date
- 2026-07-02
AI Technical Summary
In the existing technology, the layout design of MOSFETs lacks a standard structure, which makes it impossible to achieve automated layout and routing. Furthermore, MOSFETs of different sizes and parameters cannot be directly adjacent to each other without violating design rules, resulting in large layout area and low efficiency.
The standard cell-modular MOSFET layout structure is adopted, which divides the layout into NMOS modules and PMOS modules. The modules are composed of standard cells of the same type. The layout structure of the MOSFET is regularized by the layout and routing boundaries, power rails and ground rails, and is compatible with EDA tools to realize automated layout and routing.
It improves the utilization rate of the layout area, reduces the area required for layout, improves the layout and routing efficiency, and can be recognized and utilized by existing EDA tools, realizing the automatic generation of MOSFET layouts in analog and mixed circuits.
Smart Images
Figure CN2025131818_02072026_PF_FP_ABST
Abstract
Description
A standard cell-modular MOS transistor layout structure and its usage method Technical Field
[0001] This invention relates to automated generation technology for analog and mixed-signal circuit layouts, and in particular to a layout structure with standard cells—modular MOS transistors—and its usage method. Background Technology
[0002] For the past four decades or even longer, analog circuit layout design technology has seen little innovation beyond parametric cells (PCELLs). PCELLs are advanced, programmable cell design technologies supported by EDA platforms. They can generate different device layouts based on the dimensions and parameters set by the physical layout designer. Designers must manually place and route these layouts to construct the complete circuit layout. While PCELLs offer advantages such as programmability, flexibility, and adjustable parameters, the generated MOSFET layouts have irregular shapes and sizes, and the positions of the source, gate, drain, and body terminals are not fixed, offering a high degree of freedom. This high degree of freedom also brings two main problems:
[0003] 1. Because the MOSFET layouts generated by PCELL have different shapes and sizes, two MOSFET layouts of different sizes and parameters cannot be directly adjacent without violating design rules (DR). Therefore, the layout occupies a large area, has an irregular shape, and has low area utilization.
[0004] 2. The highly flexible and irregular MOSFET layouts generated by PCELL are difficult to be identified and utilized by existing automated design tools (EDA), resulting in the layout of MOSFETs in analog and mixed-signal circuits mainly relying on manual operation, which makes the efficiency of drawing analog and mixed-signal circuit layouts low. Summary of the Invention
[0005] The purpose of this invention is to provide a standard cell-modular MOS transistor layout structure and its usage method to solve the problem that existing automatically generated MOS transistor layouts lack a standard structure and cannot be adjacent, resulting in the inability to automate layout generation, placement and routing.
[0006] To achieve the above objectives, the present invention employs the following technical means:
[0007] A standard cell-modular MOS transistor layout structure is disclosed, wherein the layout is divided into NMOS modules and PMOS modules, with a gap between the NMOS modules and PMOS modules. The NMOS modules contain only standard NMOS cells, and the PMOS modules contain only standard PMOS cells. The standard NMOS cells and the standard PMOS cells are collectively referred to as standard cells. Each standard cell has two virtual polysilicon terminals, a layout and wiring boundary, a power rail, and a ground rail. The layout and wiring boundary, the power rail, and the ground rail are used to allow the standard cells to be arbitrarily adjacent and to make the MOS transistor layout structure compatible with EDA tools. The layout and wiring boundary is also used to make the shape and size of the standard cells regular. The two virtual polysilicon terminals are used to separate adjacent standard cells.
[0008] The standard NMOS cell structure includes an N-type injection region, an active region, a source port, a gate port, a drain port, n identical gate polysilicon cells, two dummy polysilicon cells, a layout and wiring boundary, a power rail and a ground rail, and parameters such as the transistor's channel length, channel width, and number of intercalation gates, where n is equal to the number of intercalation gates in the standard cell. The standard PMOS cell structure includes an N-well, a P-type injection region, an active region, a source port, a gate port, a drain port, n identical gate polysilicon cells, two dummy polysilicon cells, a layout and wiring boundary, a power rail and a ground rail, and parameters such as the transistor's channel length, channel width, and number of intercalation gates, where n is equal to the number of intercalation gates in the standard cell. The active region, the source port, the gate port, the drain port, and the n gate polysilicon cells are all rectangular structures. The direction parallel to the power rail and the ground rail is called the "lateral direction", and the direction perpendicular to the power rail and the ground rail is called the "vertical direction". The lateral direction is defined as the left-right direction, and the vertical direction is defined as the front-back direction. The two adjacent sides of the active region, the source port, the gate port, the drain port, and the n gate polysilicon cells are respectively along the lateral and vertical directions.
[0009] The gate port is implemented using a first metal layer, and the gate port is connected to each of the gate polysilicon via at least one contact hole; the source port and the drain port are each connected to each other using a second metal layer; the MOS transistor structure also includes n+1 identical first metal layers, each of which is rectangular, with its two adjacent sides along the horizontal and vertical directions respectively, and its horizontal width equal to the minimum value within the allowable range of DR. The n+1 first metal layers are evenly spaced from left to right, and the spacing between any two adjacent first metal layers is equal to the minimum value within the allowable range of DR. The n+1 first metal layers are numbered sequentially from left to right as 1 to n+1. The first metal layer numbered h is called the h-th first metal layer, where h = 1, 2, ..., n+1. In the n+1 first metal layers, each odd-numbered first metal layer is connected to the source port through at least one via, and each even-numbered first metal layer is connected to the drain port through at least one via. Each of the n+1 first metal layers is connected to the active region through at least one contact hole. The longitudinal lengths of the source port and the drain port are equal, and both are equal to the minimum metal width allowed by the DR (Drain Diameter). The front edges of the source port and the drain port are respectively horizontally aligned with the front edge of a standard trace track of the process node where the standard cell is located; if the source port, the drain port, and the active region are projected onto the same plane, the source port and the drain port will be located between the straight line containing the left side and the straight line containing the right side of the active region, respectively; if the gate port and the active region are projected onto the same plane, the spacing between the gate port and the active region is equal to the minimum value within the allowable range of DR; the longitudinal length of each gate polysilicon is equal to the minimum value within the allowable range of DR.
[0010] In the standard cell structure, n gate polysilicon cells are evenly spaced laterally, and the center-to-center distance between two adjacent gate polysilicon cells is equal to the CPP (Contact Poly Pitch, defined as the lateral width of the gate polysilicon + 2 × (the distance from the contact hole to the gate polysilicon + the contact hole width / 2)) of the process node where the standard cell is located. The lateral width of each gate polysilicon cell is equal to the channel length, and the longitudinal length of the active region is equal to the channel width. If the channel width is less than or equal to the maximum channel width of the digital standard cell library at the process node where the standard cell is located, then the front boundary of the active region of the standard PMOS cell coincides with the rear boundary of the power rail, and the rear boundary of the active region of the standard NMOS cell coincides with the front boundary of the ground rail; otherwise, the distance between the front boundary of the active region of the standard PMOS cell and the rear boundary of the power rail is the minimum value allowed by DR, and the distance between the rear boundary of the active region of the standard NMOS cell and the front boundary of the ground rail is the minimum value allowed by DR. If the channel length is less than or equal to the maximum channel width of the digital standard cell library at the process node where the standard cell is located, then the front boundary of the active region of the standard PMOS cell coincides with the rear boundary of the power rail, and the rear boundary of the active region of the standard NMOS cell coincides with the front boundary of the ground rail. For the maximum channel length of the cell, the front boundary of the gate polysilicon of the standard PMOS cell coincides with the front boundary of the placement and wiring boundary, and the rear boundary of the gate polysilicon of the standard NMOS cell coincides with the rear boundary of the placement and wiring boundary. Otherwise, the distance between the front boundary of the gate polysilicon of the standard PMOS cell and the front boundary of the placement and wiring boundary is the minimum value allowed by DR, and the distance between the rear boundary of the gate polysilicon of the standard NMOS cell and the rear boundary of the placement and wiring boundary is the maximum value allowed by DR. Regardless of the channel length range, the distance of the rear boundary of the gate polysilicon of the standard PMOS cell beyond the active region is the minimum value allowed by DR, and the distance of the front boundary of the gate polysilicon of the standard NMOS cell beyond the active region is the minimum value allowed by DR.
[0011] If the n+1 first metal layers and the n gate polysilicon cells are projected onto the same plane, the n gate polysilicon cells are located one-to-one at the n gaps between the n+1 first metal layers, and there is an equal spacing between each gate polysilicon cell and the first metal layers on its left and right sides, which is the minimum value within the allowable range of DR.
[0012] In the standard cell structure, two virtual polysilicon cells are spaced apart, one on the left and one on the right. The virtual polysilicon on the left is called the left virtual polysilicon, and the virtual polysilicon on the right is called the right virtual polysilicon. The left and right virtual polysilicon cells are symmetrical about the longitudinal center line of the layout and wiring boundary. The left virtual polysilicon is located to the left of the leftmost gate polysilicon among the n gate polysilicon cells, and the center distance between them is equal to CPP. When the left boundary of the layout and wiring boundary is projected onto the plane where the left virtual polysilicon is located, it coincides with the longitudinal center line of the left virtual polysilicon. The right virtual polysilicon is located to the right of the rightmost gate polysilicon among the n gate polysilicon cells, and the center distance between them is equal to CPP. When the right boundary of the layout and wiring boundary is projected onto the plane where the right virtual polysilicon is located, it coincides with the longitudinal center line of the right virtual polysilicon. The lateral width of the virtual polysilicon is the same as that of the gate polysilicon, and the longitudinal length of both is equal to a positive integer multiple of the center-to-center spacing between the power and ground rails in the digital standard cell at the process node of the standard cell. The virtual polysilicon is not connected to any other part of the standard cell layout structure.
[0013] The layout and wiring boundary is a frame structure formed by connecting the front boundary, left boundary, rear boundary and right boundary in sequence according to the front, left, back and right distribution. Its cross-section is rectangular, and the two adjacent sides of its cross-section are respectively along the horizontal and vertical directions. The vertical length of the cross-section of the layout and wiring boundary is equal to a positive integer multiple of the center distance between the power and ground rails in the digital standard cell under the process node of the standard cell. The horizontal width is a positive integer multiple of the CPP (Contact Poly Pitch, defined as the horizontal width of the gate polysilicon + 2 × (the distance from the contact hole to the gate polysilicon + the contact hole width / 2)) under the process node of the standard cell.
[0014] If the standard cell is a standard NMOS cell, the N-type injection region is formed inside the layout and wiring boundary. The front edge of the N-type injection region coincides with the front boundary of the layout and wiring boundary, the left edge of the N-type injection region coincides with the left boundary of the layout and wiring boundary, the rear edge of the N-type injection region coincides with the rear boundary of the layout and wiring boundary, and the right edge of the N-type injection region coincides with the right boundary of the layout and wiring boundary.
[0015] If the standard cell is a standard PMOS cell, the P-type injection region is formed inside the layout and wiring boundary. The front edge of the P-type injection region coincides with the front boundary of the layout and wiring boundary, the left edge of the P-type injection region coincides with the left boundary of the layout and wiring boundary, the rear edge of the P-type injection region coincides with the rear boundary of the layout and wiring boundary, and the right edge of the P-type injection region coincides with the right boundary of the layout and wiring boundary.
[0016] In the PMOS module, all standard PMOS cells share a single N-well. The P-type injection regions of these standard PMOS cells are interconnected when laterally adjacent. If the N-well, the active region, and the P-type injection region are projected onto the same plane, the P-type injection region is entirely within the N-well, and the active region is entirely within the P-type injection region. Similarly, in the NMOS module, the N-type injection regions of the standard NMOS cells are interconnected when laterally adjacent. If the active region and the N-type injection region are projected onto the same plane, the active region is entirely within the N-type injection region.
[0017] The layout of the standard NMOS cell in this invention does not contain an N-well or a P-type injection region, and the layout of the PMOS cell in this invention does not contain an N-type injection region. Its advantages are that it improves the area utilization of the standard cell layout. This is because the N-well and P-type injection regions in the NMOS layout, and the N-type injection region in the PMOS layout, are redundant structures that do not actually carry current or conduct signals. The standard cell layout involved in this invention does not have these redundant structures. Furthermore, the standard cell no longer needs a buffer structure and can be directly adjacent to other cells of the same type (meaning NMOS cells are adjacent to NMOS cells, and PMOS cells are adjacent to PMOS cells) without violating the DR (Design Ratio), thus achieving higher area utilization. Another advantage is that after placement and routing, the N-well portions of all PMOS layouts will be interconnected, forming a large, unified, and complete N-well. This ensures that the active regions of all PMOS transistors are far from the edge of the N-well, thereby reducing the well proximity effect. The well proximity effect increases the threshold voltage of the MOSFET, thus causing performance degradation.
[0018] Furthermore, the power rail and the ground rail are both rectangular structures, with their two adjacent sides along the horizontal and vertical directions, respectively; the metal layer where the power rail is located is the same as the power rail in the digital standard unit under the process node of the standard unit, and the vertical length of the power rail is equal to the width of the power rail in the digital standard unit under the process node of the standard unit (the digital standard unit is another module with fixed power rail width and other parameters, and it needs to conform to its fixed parameters in order to use its existing software).
[0019] The metal layer where the ground track is located is the same as the ground track in the digital standard cell under the process node of the standard cell. The longitudinal length of the ground track is equal to the width of the ground track in the digital standard cell under the process node of the standard cell. If the power track, the ground track, and the layout and wiring boundary are projected onto the same plane, the horizontal center line of the power track coincides with the front boundary of the layout and wiring boundary, the horizontal center line of the ground track coincides with the rear boundary of the layout and wiring boundary, the left side of the power track and the left side of the ground track are on the same straight line as the left boundary of the layout and wiring boundary, and the right side of the power track and the right side of the ground track are on the same straight line as the right boundary of the layout and wiring boundary.
[0020] If each of the n+1 first metal layers of the standard PMOS cell is connected to the power rail, the source of the standard PMOS cell can be connected to the power supply; if each of the first metal layers of the standard NMOS cell is connected to the ground rail, the source of the standard NMOS cell can be grounded.
[0021] Compared with existing technologies, the standard cell-modular MOSFET layout structure of this invention has the advantage of dividing the layout structure into NMOS modules and PMOS modules. The modules have regular shapes, gaps between modules, and can be adjacent to digital standard cell modules of the same process. Each module is composed of standard cells of the same type. The standard cell structure includes two virtual polysilicon blocks, a placement and routing boundary, power rails, and ground rails. The two virtual polysilicon blocks separate adjacent standard cells, ensuring that direct left-right adjacency between two standard cells does not violate routing rules. The placement and routing boundary, power rails, and ground rails enable the MOSFET layout structure to be compatible with EDA tools, and the placement and routing boundary ensures the regularity of the layout structure's shape and size. Therefore, the standard cell-modular MOSFET layout structure of this invention can improve the overall area utilization of the circuit layout; and it can be recognized and utilized by existing EDA tools, thus enabling the automatic generation of circuit layouts composed of MOSFETs in analog and mixed-signal circuits, improving layout efficiency.
[0022] The second technical problem to be solved by this invention is to provide a method for using a standard cell-modular MOS transistor layout structure. This method uses EDA tools to automatically place and route the layout structure according to the circuit schematic, thereby realizing the automatic generation of circuit structure layouts composed of MOS transistors in analog and mixed circuits. The final generated layout ensures that it does not violate DR and has a small area, thus improving the layout generation efficiency.
[0023] The technical solution adopted by this invention to solve the second technical problem mentioned above is: a method for using a standard cell-modular MOS transistor layout structure, comprising the following steps:
[0024] Step (1): Set the parameters of each MOS transistor in the circuit structure composed of MOS transistors in the simulation and hybrid circuit of automatic placement and routing as required. Set the relevant parameters of the standard unit-modular MOS transistor layout structure, and describe the layout structure of each MOS transistor in GDS format and LEF format to obtain the corresponding GDS file and LEF file.
[0025] Step (2): Divide the circuit diagram of the circuit structure composed of MOS transistors in the analog and hybrid circuits that need to be automatically placed and routed into two parts. One part is composed entirely of NMOS, called the NMOS module, and the other part is composed entirely of PMOS, called the PMOS module. Both circuit diagrams are described using Verilog language to form two Verilog files. The connection relationship between the NMOS module and the PMOS module is also described using Verilog language to form a third Verilog file.
[0026] Step (3): Input the obtained GDS file, LEF file and Verilog file describing the NMOS module into the EDA tool;
[0027] Step (4): Run the EDA tool to perform automatic placement and routing to obtain the layout of the NMOS module and the GDS file and LEF file describing the layout;
[0028] Step (5): Input the obtained GDS file, LEF file and Verilog file describing the PMOS module into the EDA tool;
[0029] Step (6): Run the EDA tool to perform automatic placement and routing to obtain the layout of the PMOS module and the GDS file and LEF file describing the layout;
[0030] Step (7): Input all the previously obtained GDS files, LEF files, and Verilog files describing the connection relationship between the two circuit parts into the EDA tool;
[0031] Step (8): Run the EDA tool to perform automatic placement and routing to obtain the complete circuit layout.
[0032] Through modular design, this invention achieves a standard cell-modular MOS transistor layout structure, solving the problem that existing automatically generated MOS transistor layouts lack a standard structure and cannot achieve automated placement and routing. Specific technical effects are analyzed below:
[0033] Modular design: By dividing the layout into NMOS and PMOS modules, each module consists of standard cells of the same type. This allows any two identical MOS transistor cells to be directly adjacent without violating design rules (DR). Compared to existing technologies, this design reduces redundant structures in the MOS cell layout, significantly reducing the area required for layout. Dividing the circuit into two modules does not inherently reduce area, but by having each module contain only the same type of MOS transistor, the internal structure of each MOS transistor layout can be simpler and more efficient in terms of area utilization while maintaining adjacency, thus reducing the overall area.
[0034] Standard cell structure: The standard cell structure includes virtual polysilicon, placement and routing boundaries, power rails and ground rails. Standard cells inside the module do not violate DR when directly adjacent, making the MOSFET layout structure compatible with existing EDA tools and improving the efficiency of placement and routing.
[0035] The role of placement and routing boundaries: Placement and routing boundaries not only make the shape and size of standard cells regular, but also ensure that standard cells can be recognized and utilized by existing EDA tools, thereby realizing the automatic generation of circuit structure layouts composed of MOS transistors in analog and mixed circuits.
[0036] Metal layer optimization: The standard cell contains n+1 first metal layers, and the lateral width of each first metal layer is equal to the minimum value within the allowed range of DR. This allows the standard cell to make full use of space during layout, further reducing the layout area.
[0037] Power and ground rail settings: The settings of power rail VDD and ground rail VSS enable standard cells to be regularly arranged in an array by EDA tools, which improves both layout efficiency and power supply stability of the circuit.
[0038] Simplified Usage: The standard cell-modular MOS transistor layout structure is made available through EDA tools, which enables automatic placement and routing. This simplifies the process of generating circuit layouts composed of MOS transistors in analog and mixed circuits and improves layout generation efficiency.
[0039] Overall, compared with existing technologies, the advantages of the standard cell-modular MOSFET layout structure method of this invention are that the generated standard cell structure is regular and can be recognized and utilized by existing EDA tools. The EDA tools automatically place and route the MOSFET layout structure according to the circuit schematic. The automated placement and routing by the EDA tools takes very little time, usually no more than 1 hour. The layout automatically generated by the EDA tools ensures that it does not violate the DR (Design Rule), and each MOSFET is placed between alternating power rails and ground rails, improving the power supply stability of the circuit. MOSFETs in the same row can share the same well contact cell (the well contact cell is outside the MOSFET) to connect the body to the power or ground, reducing the layout area. During the layout stage, the MOSFET layouts are placed as close as possible to each other to reduce the layout area. Users can freely adjust the aspect ratio, size, metal layers used for routing, input / output port positions, and layout and routing priorities of each node in the circuit of the final generated layout. Attached Figure Description
[0040] Figure 1 is a schematic diagram of the structure of a standard NMOS cell in the NMOS module of Embodiment 1 of the present invention;
[0041] Figure 2 is a schematic diagram of the structure of a standard PMOS cell in the PMOS module of Embodiment 2 of the present invention;
[0042] Figure 3 is a schematic diagram of the standard NMOS cell layout structure of Embodiment 3 of the present invention;
[0043] Figure 4 is a schematic diagram of the standard PMOS cell layout structure of Embodiment 4 of the present invention;
[0044] Figure 5 is a schematic diagram of the structure of the standard unit adjacent to each other in Embodiment 5 of the present invention;
[0045] Figure 6 is a schematic diagram of the structure of the standard unit connected vertically in Embodiment 6 of the present invention;
[0046] Figure 7 is a circuit diagram of a circuit structure composed of MOS transistors in an analog and hybrid circuit that requires automatic placement and routing.
[0047] Figure 8 shows an intermediate layout generated by the method of using the standard cell-modular MOS transistor layout structure of the present invention;
[0048] Figure 9 shows the final layout generated by the method of using the standard cell-modular MOS transistor layout structure of the present invention. Embodiments of the present invention
[0049] One of the technical problems this invention aims to solve is that existing automatically generated MOSFET layouts lack a standard structure, making it impossible to automate layout generation and placement / routing. The technical solution provided by this invention is a MOSFET layout structure with a standard cell-modular structure. This layout structure is generally divided into two modules: an NMOS module and a PMOS module. The modules have regular shapes and are composed of standard cells of the same type, allowing any two MOSFET cells to be directly adjacent without violating routing limits (DR). This MOSFET layout design is compatible with existing EDA tools, automatically generating circuit layouts composed of MOSFETs in analog and mixed-signal circuits while ensuring DR compliance and optimizing layout area, effectively improving layout design efficiency.
[0050] This invention discloses a standard cell-modular MOS transistor layout structure. The main body of the layout is divided into NMOS modules and PMOS modules, with a gap between the NMOS modules and PMOS modules, the distance being the minimum value within the allowable range of DR (Distribution Reduction). The standard cell-modular MOS transistor layout structure of this invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0051] Example 1: As shown in Figure 1, this example is a schematic diagram of the structure of a standard NMOS cell inside an NMOS module. In this example, the standard NMOS cell has four intercalation gates. The main layout structure of the standard NMOS cell includes two virtual polysilicon cells 6, a layout wiring boundary 1, a power rail VDD, a ground rail VSS, an active region 5, a source port S, a gate port G, a drain port D, an N-type injection region 4, and four identical gate polysilicon cells 3. The active region 5, the source port S, the gate port G, the drain port D, and the four gate polysilicon cells 3 are all rectangular structures. The direction parallel to the power rail VDD and the ground rail VSS is called the "lateral direction," and the direction perpendicular to the power rail VDD and the ground rail VSS is called the "vertical direction." The lateral direction is considered as the left-right direction, and the vertical direction is considered as the front-back direction. The virtual polysilicon cells 6, the active region 5, the source port S, the gate port G, the drain port D, and the four gate polysilicon cells are all rectangular structures. Each of the three adjacent sides is along the horizontal and vertical axes, respectively. The gate port G is implemented using a first metal layer, and the gate port G is connected to each gate polysilicon 3 through at least one contact hole 2. The source port S and drain port D are each implemented using a second metal layer. The front side of the source port S is horizontally aligned with the front side of the 6th standard routing track out of the 9 standard routing tracks under the process node of the standard NMOS cell, and its vertical length is equal to that of the 6th standard routing track. The front side of the drain port D is horizontally aligned with the front side of the 8th standard routing track out of the 9 standard routing tracks under the process node of the standard NMOS cell, and its vertical length is equal to that of the 8th standard routing track. This ensures that the routing implemented by the subsequent EDA tools will not violate the metal-dependent DR. If the layout and wiring boundary 1 is projected onto the plane where the first and second metal layers are located, all the first and second metal layer structures are inside the layout and wiring boundary 1 and their dimensions are the minimum allowed by DR, so that the two standard NMOS cells do not violate the metal-dependent DR when they are adjacent to each other.
[0052] If the source port S, drain port D, and active region 5 are projected onto the same plane, the source port S and drain port D will be located between the straight line containing the left side and the straight line containing the right side of the active region 5, respectively. If the gate port G and active region 5 are projected onto the same plane, the spacing between the gate port G and the active region 5 is equal to the minimum value allowed by DR. The longitudinal length of the active region 5 is equal to the channel width of the standard NMOS cell. The four gate polysilicon cells 3 are evenly spaced laterally, and the center spacing between two adjacent gate polysilicon cells 3 is equal to the CPP (Contact Poly Pitch, defined as the lateral width of the gate polysilicon + 2 × (the spacing between the contact hole and the gate polysilicon + the contact hole width / 2)) of the process node where the standard NMOS cell is located. The lateral length of each gate polysilicon cell 3 is equal to the channel length of the standard NMOS cell. The longitudinal length of each gate polysilicon cell 3 is equal to the minimum value allowed by DR. The rear side of each gate polysilicon cell coincides with the rear side of the layout wiring boundary 1.
[0053] In this embodiment, the standard NMOS cell main structure also includes five first metal layers 7. Each of the five first metal layers 7 is a rectangular structure, with its two adjacent sides extending laterally and longitudinally, respectively. The lateral width of each first metal layer 7 is equal to the minimum value within the allowable range of DR (Distribution Limit). The five first metal layers are evenly spaced from left to right, and the spacing between any two adjacent first metal layers is also equal to the minimum value within the allowable range of DR. The five first metal layers are numbered sequentially from left to right as 1 to 5. The first metal layer numbered h is called the h-th first metal layer, where h = 1, 2, 3, 4, 5. In the first metal layer 7, each odd-numbered first metal layer 7 is connected to the source port S through at least one via 8, and each even-numbered first metal layer 7 is connected to the drain port D through at least one via 9. The five first metal layers 7 are respectively connected to the active region 5 through at least one contact hole 10. If the five first metal layers 7 and the four gate polysilicon cells 3 are projected onto the same plane, the four gate polysilicon cells 3 are located one-to-one in the four gaps formed between the five first metal layers 7, and there is an equal spacing between each gate polysilicon cell 3 and the first metal layers 7 on its left and right sides.
[0054] In this embodiment, the layout and wiring boundary 1 is a frame structure formed by connecting the front boundary, left boundary, rear boundary and right boundary in sequence according to the front, left, rear and right distribution. Its cross-section is rectangular, and the two adjacent sides of its cross-section are respectively along the horizontal and vertical directions. The vertical length of the cross-section of the layout and wiring boundary 1 is equal to 1 times the center distance between the power and ground rails in the digital standard cell under the process node of the standard NMOS cell. The horizontal width is 5 times the CPP (Contact Poly Pitch, defined as the horizontal width of the gate polysilicon + 2 × (the distance from the contact hole to the gate polysilicon + the contact hole width / 2)) under the process node of the standard NMOS cell. The front boundary is the front side of the layout and wiring boundary 1, the rear boundary is the rear side of the layout and wiring boundary 1, the left boundary is the left side of the layout and wiring boundary 1, and the right boundary is the right side of the layout and wiring boundary 1. The interior of the placement and routing boundary 1 is an N-type injection region 4. The front edge of the N-type injection region 4 coincides with the front boundary of the placement and routing boundary 1, the left edge of the N-type injection region 4 coincides with the left boundary of the placement and routing boundary 1, the rear edge of the N-type injection region 4 coincides with the rear boundary of the placement and routing boundary 1, and the right edge of the N-type injection region 4 coincides with the right boundary of the placement and routing boundary 1. If the active region 5 and the N-type injection region 4 are projected onto the same plane, the active region 5 is completely inside the N-type injection region 4.
[0055] In this embodiment, it is worth noting that the "power rail VDD" and the "power rail VDD in the digital standard cell of the process node of the standard NMOS cell" are different, but have the same width. The former corresponds to the latter. The power rail VDD and the ground rail VSS are both rectangular structures, with their two adjacent sides along the horizontal and vertical directions, respectively. The metal layer where the power rail VDD is located is the same as that of the power rail VDD in the digital standard cell of the process node of the standard NMOS cell. The vertical length of the power rail VDD is equal to the width of the power rail VDD in the digital standard cell of the process node of the standard NMOS cell. The metal layer where the ground rail VSS is located is the same as that of the power rail VDD in the digital standard cell of the process node of the standard NMOS cell. The ground rails VSS in the digital standard cell are identical, and the longitudinal length of the ground rail VSS is equal to the width of the ground rail VSS in the digital standard cell at the process node of the standard NMOS cell. If the power rail VDD, ground rail VSS, and place-and-route boundary 1 are projected onto the same plane, the power rail VDD coincides with the front boundary of the place-and-route boundary 1 along the transverse centerline, the ground rail VSS coincides with the rear boundary of the place-and-route boundary 1 along the transverse centerline, the left side of the power rail VDD and the left side of the ground rail VSS are both on the same straight line as the left boundary of the place-and-route boundary 1, and the right side of the power rail VDD and the right side of the ground rail VSS are both on the same straight line as the right boundary of the place-and-route boundary 1.
[0056] In this embodiment, two virtual polysilicon 6 are arranged at intervals from left to right. The virtual polysilicon located on the left is called the left virtual polysilicon 6, and the virtual polysilicon located on the right is called the right virtual polysilicon 6. The left virtual polysilicon 6 and the right virtual polysilicon 6 are symmetrical about each other along the longitudinal center line with respect to the layout wiring boundary 1.
[0057] The left virtual polysilicon 6 is located to the left of the leftmost gate polysilicon 3 among the four gate polysilicon 3s, and the center distance between the two is equal to CPP. When the left boundary of the layout wiring boundary 1 is projected onto the plane where the left virtual polysilicon 6 is located, it will coincide with the center line of the left virtual polysilicon along the longitudinal direction.
[0058] The right virtual polysilicon 6 is located to the right of the rightmost gate polysilicon 3 among the four gate polysilicon 3s, and the center distance between the two is equal to CPP. When the right boundary of the layout wiring boundary 1 is projected onto the plane where the right virtual polysilicon 6 is located, it will coincide with the center line of the right virtual polysilicon along the longitudinal direction.
[0059] The lateral width of the virtual polysilicon 6 is the same as that of the gate polysilicon 3. The longitudinal length of the virtual polysilicon 6 is equal to a positive integer multiple of the center-to-center distance between the power and ground rails in the digital standard cell at the process node of the standard NMOS cell. The virtual polysilicon 6 is not connected to any other part of the standard NMOS cell.
[0060] In this embodiment, the standard NMOS cell does not have a body port. By placing the standard NMOS cell layout structure parallel to the well-tap cells in the digital standard cell library of its process node, the front boundary of the placement and routing boundary 1 of the standard NMOS cell is aligned with the front boundary of the placement and routing boundary of the well-tap cell, and the rear boundary of the placement and routing boundary 1 of the standard NMOS cell is aligned with the rear boundary of the placement and routing boundary of the well-tap cell. Thus, the body of the standard NMOS cell can be connected to ground. Since the standard NMOS cell layout structure in this embodiment does not have a body port, simply placing the standard NMOS cell parallel to the well-tap cell is sufficient to connect the body of the standard NMOS cell to the corresponding power supply or ground. No additional body port design is required, and no additional structure is needed to connect the body of the standard NMOS cell. Furthermore, multiple standard NMOS cells can share the same well-tap cell. Therefore, the layout area obtained after placement and routing using the standard NMOS cells in this embodiment is smaller.
[0061] In this embodiment, the layout and routing boundary 1, power rail VDD, and ground rail VSS are used to enable the MOS transistor layout structure to be recognized by the EDA tool for layout and to allow it to be adjacent to adjacent standard cells. The layout and routing boundary 1 is also used to ensure that the shape and size of the standard NMOS cells are regular. When adjacent to each other on the left and right, two adjacent standard NMOS cells share a virtual polysilicon 6. When adjacent to each other on the top and bottom, two adjacent standard NMOS cells share either power rail VDD or ground rail VSS, so that any two standard NMOS cells will not violate the DR when adjacent in any direction. Since the EDA tool places all cells between the alternating power rail VDD and ground rail VSS during layout, the setting of power rail VDD and ground rail VSS allows the standard NMOS cells to be placed by the EDA tool in a regular manner.
[0062] Example 2: This example is basically the same as Example 1, except that, as shown in Figure 2, this example is a schematic diagram of the structure of a standard PMOS cell inside a PMOS module. In this example, the standard PMOS cell has 4 intercalation gates. The main layout structure of the standard PMOS cell includes two virtual polysilicon cells 6, a layout wiring boundary 1, a power rail VDD, a ground rail VSS, an active region 5, a source port S, a gate port G, a drain port D, an N-well 11, a P-type injection region 12, and four identical gate polysilicon cells 3. The gate port G is implemented using a first metal layer, and the gate port G is connected to each gate polysilicon cell 3 through at least one contact hole 2. The source port S and drain port D are each implemented using a first metal layer 11, a first metal layer 2, a first metal layer 2, and a first metal layer 3. The second metal layer is implemented such that the front side of the source port S is horizontally aligned with the front side of the second standard trace of the nine standard traces in the process node of the standard PMOS cell, and the vertical length is equal to the vertical length of the second standard trace. The front side of the drain port D is horizontally aligned with the front side of the fourth standard trace of the nine standard traces in the process node of the standard PMOS cell, and the vertical length is equal to the vertical length of the fourth standard trace. This ensures that the traces implemented by the subsequent EDA tools will not violate the metal-related DR.
[0063] If the source port S, drain port D, and active region 5 are projected onto the same plane, the source port S and drain port D will be located between the straight line containing the left side and the straight line containing the right side of the active region 5, respectively. If the gate port G and active region 5 are projected onto the same plane, the spacing between the gate port G and the active region 5 is equal to the minimum value allowed by DR. The longitudinal length of the active region 5 is equal to the channel width of the standard PMOS cell. The four gate polysilicon cells 3 are evenly spaced laterally, and the center spacing between two adjacent gate polysilicon cells 3 is equal to the CPP (Contact Poly Pitch, defined as the lateral width of the gate polysilicon + 2 × (the spacing between the contact hole and the gate polysilicon + the contact hole width / 2)) of the process node where the standard PMOS cell is located. The lateral length of each gate polysilicon cell 3 is equal to the channel length of the standard PMOS cell. The longitudinal length of each gate polysilicon cell 3 is equal to the minimum value allowed by DR. The front side of each gate polysilicon cell 3 coincides with the front side of the layout wiring boundary 1.
[0064] In this embodiment, the layout and wiring boundary 1 is a frame structure formed by connecting the front boundary, left boundary, rear boundary and right boundary in sequence according to the front, left, rear and right distribution. Its cross-section is rectangular, and the two adjacent sides of its cross-section are respectively along the horizontal and vertical directions. The vertical length of the cross-section of the layout and wiring boundary 1 is equal to 1 times the center distance between the power and ground rails in the digital standard cell under the process node of the standard PMOS cell. The horizontal width is 5 times the CPP (Contact Poly Pitch, defined as the horizontal width of the gate polysilicon + 2 × (the distance from the contact hole to the gate polysilicon + the contact hole width / 2)) under the process node of the standard PMOS cell. The front boundary is the front side of the layout and wiring boundary 1, the rear boundary is the rear side of the layout and wiring boundary 1, the left boundary is the left side of the layout and wiring boundary 1, and the right boundary is the right side of the layout and wiring boundary 1. The interior of the placement and routing boundary 1 is a P-type injection region 12. The front edge of the P-type injection region 12 coincides with the front boundary of the placement and routing boundary 1, the left edge of the P-type injection region 12 coincides with the left boundary of the placement and routing boundary 1, the rear edge of the P-type injection region 12 coincides with the rear boundary of the placement and routing boundary 1, and the right edge of the P-type injection region 12 coincides with the right boundary of the placement and routing boundary 1. If the active region 5 and the P-type injection region 12 are projected onto the same plane, the active region 5 is completely inside the P-type injection region 12. If the N-well 11 and the P-type injection region 12 are projected onto the same plane, the P-type injection region 12 is completely inside the N-well 11.
[0065] Example 3: Based on Example 1, in this example, each of the five first metal layers 7 with an odd number is connected to the ground rail VSS, as shown in Figure 3. In this case, the standard NMOS cell of this example can directly ground the source of the NMOS transistor, and its source port S can be omitted.
[0066] Example 4: Based on Example 2, in this example, each of the five first metal layers 7 with an odd number is connected to the power rail VDD, as shown in Figure 4. At this time, the standard PMOS unit of this example can directly realize the connection between the source of the PMOS transistor and the power supply, and its source port S can be omitted.
[0067] Example 5: Based on Example 1, this example shows a layout structure in which standard NMOS cells are adjacent to each other along the left and right boundaries of the layout wiring boundary 1, and two standard NMOS cells share a virtual polysilicon 6.
[0068] Example 6: Based on Example 1, this example shows a layout structure in which standard NMOS cells are adjacent to each other along the front and rear boundaries of the layout wiring boundary 1, and the two standard NMOS cells share a power rail or ground rail.
[0069] The present invention also discloses a method for using the above-mentioned standard cell-modular MOS transistor layout structure. The following describes in further detail the method for using the standard cell-modular MOS transistor layout structure of the present invention with reference to the accompanying drawings and embodiments.
[0070] Example: A method for using a standard cell-modular MOS transistor layout structure, comprising the following steps:
[0071] Step (1): Set the parameters of each MOS transistor in the circuit composed of MOS transistors in the simulation and hybrid circuit of automatic placement and routing as required. Set the relevant parameters of the standard cell-modular MOS transistor layout structure, and describe the standard cell layout structure of each MOS transistor in GDS format and LEF format to obtain the corresponding GDS file and LEF file.
[0072] Step (2): Divide the circuit diagram of the circuit structure composed of MOS transistors in the analog and hybrid circuits that need to be automatically placed and routed into two parts. One part is composed entirely of NMOS, called the NMOS module, and the other part is composed entirely of PMOS, called the PMOS module. Both circuit diagrams are described using Verilog language to form two Verilog files. The connection relationship between the NMOS module and the PMOS module is also described using Verilog language to form a third Verilog file.
[0073] Step (3): Input the obtained GDS file, LEF file and Verilog file describing the NMOS module into the EDA tool;
[0074] Step (4): Run the EDA tool to perform automatic placement and routing to obtain the layout of the NMOS module and the GDS file and LEF file describing the layout.
[0075] Step (5): Input the obtained GDS file, LEF file and Verilog file describing the PMOS module into the EDA tool;
[0076] Step (6): Run the EDA tool to perform automatic placement and routing to obtain the layout of the PMOS module and the GDS file and LEF file describing the layout.
[0077] Step (7): Input all the previously obtained GDS files, LEF files, and Verilog files describing the connection relationship between the two circuit parts into the EDA tool;
[0078] Step (8): Run the EDA tool to perform automatic placement and routing to obtain the complete circuit layout.
[0079] In this embodiment, the circuit structure composed of MOS transistors in the analog and hybrid circuit requiring automatic placement and routing involves five MOS transistors, labeled M1, M2, M3, M4, and M5 from bottom to top and left to right. M1, M2, and M3 are PMOS transistors, forming a PMOS module, while M4 and M5 are NMOS transistors, forming an NMOS module. There are a total of six input / output ports, labeled VIN1, VIN2, VOUT1, VOUT2, Vbl, and Vb2. The connection relationships between these ports and devices are shown in Figure 7. After designing the standard cell layout of the five MOS transistors according to their parameter requirements, the layout is described using GDS and LEF formats, resulting in corresponding GDS and LEF files. The circuit diagram of this structure is then described using Verilog language, forming three Verilog files. The resulting GDS and LEF files are then input into the EDA tool. First, input the Verilog file of the NMOS module into the EDA tool. The EDA tool will automatically call the corresponding standard cell layout of the MOS transistors and arrange the standard cell layouts of the three NMOS transistors, namely M1, M2, and M3, in an array between the alternating power rails VDD and ground rails VSS, and add well contact cells and fill cells. The resulting NMOS module layout is described in GDS and LEF formats, generating the corresponding GDS and LEF files. Next, input the Verilog file of the PMOS module into the EDA tool. The EDA tool will automatically call the corresponding standard cell layout of the MOS transistors and arrange the standard cell layouts of the two PMOS transistors, namely M4 and M5, in an array between the alternating power rails VDD and ground rails VSS, and add well contact cells and fill cells. The resulting PMOS module layout is described in GDS and LEF formats, generating the corresponding GDS and LEF files, as shown in Figure 8. Input all the GDS files, LEF files, and Verilog files describing the connection relationship between the NMOS and PMOS modules into the EDA tool. The EDA tool will automatically route the NMOS and PMOS modules, complete the connection between the NMOS and PMOS modules, and determine the input / output port positions 13 according to the user-specified method, as shown in Figure 9.
Claims
1. A layout structure with standard cell-modular MOS transistors, characterized in that, The main layout is divided into NMOS modules and PMOS modules, with empty spaces between them. The NMOS modules and PMOS modules are composed of standard cells of the same type. The structure of the standard cell includes two virtual polysilicon (6), a layout and wiring boundary (1), a power rail VDD and a ground rail VSS. The virtual polysilicon (6) is used to separate adjacent standard cells. The layout and wiring boundary (1), the power rail VDD and the ground rail VSS are used to enable the MOS transistor layout structure to be recognized by EDA tools for layout, and to enable the NMOS modules and PMOS modules to be adjacent to the digital standard cell modules in the process of the standard cells. The layout and wiring boundary (1) is also used to make the shape and size of the standard cells regular. The standard cells are divided into the following two types: standard NMOS cells: located in the NMOS module, the standard cells also include an N-type injection region; standard PMOS cells: located in the PMOS module, the standard cells also include an N-well and a P-type injection region.
2. The standard unit-modular MOS transistor layout structure according to claim 1, characterized in that, The main layout structure of the standard NMOS cell includes an active region (5), a source port (S), a gate port (G), a drain port (D), an N-type injection region (4), and the same n gate polysilicon cells (3), as well as the transistor's channel length, channel width, and interpolation gate number parameters; the main layout structure of the standard PMOS cell includes an active region (5), a source port (S), a gate port (G), a drain port (D), an N-well (11), a P-type injection region (12), and the same n gate polysilicon cells (3), as well as the transistor's channel length, channel width, and interpolation gate number parameters; n is equal to the number of interpolation gates in the standard cell, the active region (5), the source port (S), the gate port (D ... The source (G), drain (D), and n gate polysilicon cells (3) are rectangular structures. The direction parallel to the power rail VDD and ground rail VSS is called "lateral", and the direction perpendicular to the power rail VDD and ground rail VSS is called "vertical". The lateral direction is defined as left-right, and the vertical direction as front-back. The adjacent two sides of the active region (5), the source (S), the gate (G), the drain (D), and the n gate polysilicon cells (3) are respectively along the lateral and vertical directions. The vertical length of the active region (5) is equal to the channel width, and the lateral width of each gate polysilicon cell (3) is equal to the channel length. If the channel width is less than or equal to the standard... If the maximum channel width of the digital standard cell library at the process node where the quasi-cell is located is equal to the maximum channel width of the digital standard cell library at the process node where the quasi-cell is located, then the front boundary of the active region (5) of the standard PMOS cell coincides with the rear boundary of the power rail VDD, and the rear boundary of the active region (5) of the standard NMOS cell coincides with the front boundary of the ground rail VSS. Otherwise, the distance between the front boundary of the active region (5) of the standard PMOS cell and the rear boundary of the power rail VDD is the minimum value allowed by DR, and the distance between the rear boundary of the active region (5) of the standard NMOS cell and the front boundary of the ground rail VSS is the minimum value allowed by DR. If the channel length is less than or equal to the maximum channel length of the digital standard cell library at the process node where the standard cell is located, then the front boundary of the gate polysilicon (3) of the standard PMOS cell coincides with the rear boundary of the power rail VDD, and the rear boundary of the active region (5) of the standard NMOS cell coincides with the front boundary of the ground rail VSS. The front boundary of the layout wiring boundary (1) coincides with the rear boundary of the gate polysilicon (3) of the standard NMOS cell. Otherwise, the distance between the front boundary of the gate polysilicon (3) of the standard PMOS cell and the front boundary of the layout wiring boundary (1) is the minimum value allowed by DR. The distance between the rear boundary of the gate polysilicon (3) of the standard NMOS cell and the rear boundary of the layout wiring boundary (1) is the maximum value allowed by DR. Regardless of the channel length, the distance between the rear boundary of the gate polysilicon (3) of the standard PMOS cell and the active region (5) is the minimum value allowed by DR. The distance between the front boundary of the gate polysilicon (3) of the standard NMOS cell and the active region (5) is the minimum value allowed by DR.
3. The standard unit-modular MOS transistor layout structure according to claim 2, characterized in that, The gate port (G) is implemented using a first metal layer, and the gate port (G) is connected to each of the gate polysilicon (3) through at least one contact hole (2); the source port (S) and the drain port (D) are both implemented using a second metal layer; the main layout structure of the standard cell also includes n+1 first metal layers (7), each of the n+1 first metal layers (7) is a rectangular structure, and its two adjacent sides are respectively along the horizontal and vertical directions. The horizontal width of each first metal layer (7) is equal to the minimum value within the allowable range of DR. Layers (7) are evenly spaced from left to right, and the spacing between any two adjacent first metal layers is equal to the minimum value within the allowable range of DR. The n+1 first metal layers are numbered sequentially from left to right according to 1 to n+1. The first metal layer numbered h is called the h-th first metal layer; h = 1, 2, ..., n+1; among the n+1 first metal layers, each first metal layer (7) with an odd number is connected to the source port (S) through at least one via, and each first metal layer (7) with an even number is connected to the drain port (D) through at least one via; n+1 first metal layers (7) Connected to the active region (5) through at least one contact hole respectively; the longitudinal lengths of the source port (S) and the drain port (D) are equal, and both are equal to the minimum metal width allowed by DR; the front sides of the source port (S) and the drain port (D) are respectively horizontally flush with the front side of a standard trace track of the process node where the standard cell is located; if the source port (S), the drain port (D) and the active region (5) are projected onto the same plane, the source port (S) and the drain port (D) will be located in the active region (5) respectively. Between the left and right sides of the line containing the gate port (G) and the active region (5) if the gate port (G) and the active region (5) are projected onto the same plane, the distance between the gate port (G) and the active region (5) is equal to the minimum value within the allowable range of DR; the longitudinal length of each gate polysilicon (3) is equal to the minimum value within the allowable range of DR; the rear side of each gate polysilicon (3) of the standard NMOS cell coincides with the rear side of the layout wiring boundary (1); the front side of each gate polysilicon (3) of the standard PMOS cell coincides with the front side of the layout wiring boundary.
4. A standard unit-modular MOS transistor layout structure according to claim 3, characterized in that, The layout and wiring boundary (1) is a frame structure formed by connecting the front boundary, left boundary, rear boundary and right boundary in sequence according to the front, left, rear and right distribution. Its cross-section is rectangular, and the two adjacent sides of its cross-section are respectively along the horizontal and vertical directions. The vertical length of the cross-section of the layout and wiring boundary (1) is equal to a positive integer multiple of the distance between the power and ground rails in the digital standard cell under the process node of the standard cell. The horizontal width is a positive integer multiple of the CPP under the process node of the standard cell. Wherein, CPP = horizontal width of gate polysilicon + 2 × (distance from contact hole to gate polysilicon + contact hole width / 2).
5. A standard cell-modular MOS transistor layout structure according to claim 4, characterized in that, The standard NMOS cell further includes an N-type injection region (4), the front edge of which coincides with the front boundary of the layout wiring boundary (1), the left edge of which coincides with the left boundary of the layout wiring boundary (1), the rear edge of which coincides with the rear boundary of the layout wiring boundary (1), and the right edge of which coincides with the right boundary of the layout wiring boundary (1); the standard PMOS cell further includes an N-well (11) and a P-type injection region (12). The N-well (11) is shared by the standard PMOS cells in the PMOS module. Each standard PMOS cell has a P-type injection region (12). The front edge of the P-type injection region (12) coincides with the front boundary of the layout and wiring boundary (1). The left edge of the P-type injection region (12) coincides with the left boundary of the layout and wiring boundary (1). The rear edge of the P-type injection region (12) coincides with the rear boundary of the layout and wiring boundary (1). The right edge of the P-type injection region (12) coincides with the right boundary of the layout and wiring boundary (1).
6. A standard unit-modular MOS transistor layout structure according to claim 5, characterized in that, If the N-type injection region (4) and the active region (5) in the NMOS module are projected onto the same plane, the active region (5) is completely inside the N-type injection region (4); if the N-well (11), the P-type injection region (12) and the active region (5) in the PMOS module are projected onto the same plane, the P-type injection region (12) is completely inside the N-well (11), and the active region (5) is completely inside the P-type injection region (12).
7. A standard unit-modular MOS transistor layout structure according to claim 6, characterized in that, The power track VDD and the ground track VSS are both rectangular structures, with their two adjacent sides along the horizontal and vertical directions, respectively. The metal layer where the power track VDD is located is the same as the power track VDD in the digital standard cell under the process node of the standard cell, and the vertical length of the power track VDD is equal to the width of the power track VDD in the digital standard cell under the process node of the standard cell. The metal layer where the ground track VSS is located is the same as the ground track VSS in the digital standard cell under the process node of the standard cell, and the vertical length of the ground track VSS is equal to the width of the ground track VSS in the digital standard cell under the process node of the standard cell. If the power track VDD, the ground track VSS, and the layout wiring boundary (1) are projected onto the same plane, the power track VDD along the horizontal centerline is the same as the layout wiring boundary (1). The front boundary of the layout wiring boundary (1) coincides with the front boundary of the layout wiring boundary (1), the ground rail VSS coincides with the rear boundary of the layout wiring boundary (1) along the horizontal center line, the left side of the power rail VDD and the left side of the ground rail VSS are both on the same straight line as the left boundary of the layout wiring boundary (1), the right side of the power rail VDD and the right side of the ground rail VSS are both on the same straight line as the right boundary of the layout wiring boundary (1); if the source of the MOS transistor in the circuit is connected to VDD or VSS, then in the n+1 first metal layers of the standard PMOS cell, each first metal layer with an odd number is connected to the power rail VDD, realizing the connection between the source of the PMOS transistor and the power rail VDD; in the first metal layers of the standard NMOS cell, each first metal layer with an odd number is connected to the ground rail VSS, realizing the grounding of the source of the NMOS transistor.
8. A standard unit-modular MOS transistor layout structure according to claim 7, characterized in that, n gate polysilicon cells (3) are evenly spaced laterally, and the center-to-center spacing between two adjacent gate polysilicon cells (3) is taken as the default value of the process in which the standard cell is located. The lateral width of each gate polysilicon cell (3) is equal to the channel length, and the longitudinal length of the active region is equal to the channel width. If n+1 first metal layers and n gate polysilicon cells (3) are projected onto the same plane, then the n gate polysilicon cells (3) are located one-to-one at the n gaps formed between the n+1 first metal layers, and there is an equal spacing between each gate polysilicon cell (3) and the first metal layers on its left and right sides.
9. A standard unit-modular MOS transistor layout structure according to claim 8, characterized in that, Two virtual polysilicon cells (6) are spaced apart. The virtual polysilicon cell (3) located on the left is called the left virtual polysilicon, and the virtual polysilicon cell (3) located on the right is called the right virtual polysilicon. The left virtual polysilicon and the right virtual polysilicon are symmetrical about the longitudinal center line of the layout wiring boundary (1). The left virtual polysilicon is located to the left of the leftmost gate polysilicon among the n gate polysilicon cells (3), and the center distance between the two is equal to CPP. When the left boundary of the layout wiring boundary (1) is projected onto the plane where the left virtual polysilicon is located, it will coincide with the longitudinal center line of the left virtual polysilicon. The right virtual polysilicon is located to the right of the rightmost gate polysilicon (3) among the n gate polysilicons (3), and the center distance between the two is equal to CPP. When the right boundary of the layout wiring boundary (1) is projected onto the plane where the right virtual polysilicon is located, it will coincide with the center line of the right virtual polysilicon along the longitudinal direction. The lateral width of the two virtual polysilicons (3) is the same as the lateral width of the gate polysilicon (3), and the longitudinal length is equal to a positive integer multiple of the center distance between the power and ground rails in the digital standard cell under the process node of the standard cell. The two virtual polysilicons (6) are not connected to other parts of the standard cell.
10. A method of using a standard cell-modular MOS transistor layout structure according to any one of claims 1 to 9, characterized in that, Includes the following steps: Step (1): Set the parameters of each MOS transistor in the circuit structure composed of MOS transistors in the simulation and hybrid circuit of automatic placement and routing as required. Set the relevant parameters of the standard unit-modular MOS transistor layout structure, and describe the layout structure of each MOS transistor in GDS format and LEF format to obtain the corresponding GDS file and LEF file. Step (2): Divide the circuit diagram of the circuit structure composed of MOS transistors in the analog and hybrid circuits that need to be automatically placed and routed into two parts. One part is composed entirely of NMOS, called the NMOS module, and the other part is composed entirely of PMOS, called the PMOS module. Both circuit diagrams are described using Verilog language to form two Verilog files. The connection relationship between the NMOS module and the PMOS module is also described using Verilog language to form a third Verilog file. Step (3): Input the obtained GDS file, LEF file and Verilog file describing the NMOS module into the EDA tool; Step (4): Run the EDA tool to perform automatic placement and routing to obtain the layout of the NMOS module and the GDS file and LEF file describing the layout; Step (5): Input the obtained GDS file, LEF file and Verilog file describing the PMOS module into the EDA tool; Step (6): Run the EDA tool to perform automatic placement and routing to obtain the layout of the PMOS module and the GDS file and LEF file describing the layout; Step (7): Input all the previously obtained GDS files, LEF files, and Verilog files describing the connection relationship between the two circuit parts into the EDA tool; Step (8): Run the EDA tool to perform automatic placement and routing to obtain the complete circuit layout.