Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a base, and a plurality of sub-pixels (Pxij), a driving circuit layer and a pixel definition layer on the base. The driving circuit layer is located between the base and the pixel definition layer, the driving circuit layer comprises a plurality of conductive layers, a plurality of pixel openings (K) are formed in the pixel definition layer, and each sub-pixel (Pxij) comprises at least one pixel opening (K); and in at least one conductive layer among the plurality of conductive layers, at least one signal line (SL) in a same conductive layer corresponds to at least one pixel opening (K), there is an overlapping region between the at least one signal line (SL) and the corresponding pixel opening (K), in a region corresponding to a same pixel opening (K), the at least one signal line (SL) is symmetrical with respect to a first center line of the pixel opening (K), and the first center line is the center line of the pixel opening (K) extending in a second direction Y.

Description

Display substrate, display device

[0001] This application claims priority to Chinese Patent Application No. 202411962340.2, filed on December 27, 2024, entitled “Display Substrate, Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide a display substrate, including: a substrate and a plurality of sub-pixels, a driving circuit layer, and a pixel definition layer disposed on the substrate. In a direction perpendicular to the plane of the display substrate, the driving circuit layer is located between the substrate and the pixel definition layer. The driving circuit layer includes a plurality of conductive layers. A plurality of pixel openings are formed in the pixel definition layer. The sub-pixels include at least one pixel opening.

[0006] In at least one of the plurality of conductive layers, at least one signal line in the same conductive layer corresponds to at least one pixel opening, and the at least one signal line and the corresponding pixel opening have an overlapping area. In the area corresponding to the same pixel opening, the at least one signal line is symmetrical with respect to a first center line of the pixel opening, and the first center line is the center line of the pixel opening extending along a second direction.

[0007] In an exemplary embodiment, the at least one conductive layer includes the conductive layer in the driving circuit layer that is closest to the pixel definition layer, and the at least one signal line is located in the conductive layer that is closest to the pixel definition layer.

[0008] In an exemplary embodiment, the display substrate further includes an anode conductive layer. In a direction perpendicular to the plane of the display substrate, the anode conductive layer is located between the driving circuit layer and the pixel definition layer. The anode conductive layer includes a plurality of anodes, and the plurality of anodes correspond one-to-one with the plurality of pixel openings. The orthographic projection of the pixel opening on the substrate is located within the range of the orthographic projection of the corresponding anode on the substrate.

[0009] At least one signal line corresponds to at least one anode, and the at least one signal line and the corresponding anode have an overlapping region. In the region corresponding to the same anode, the at least one signal line is symmetrical with respect to the second center line of the anode body, and the second center line is the center line of the anode body extending along the second direction. In the same sub-pixel, the orthographic projections of the first center line and the second center line on the substrate overlap.

[0010] In an exemplary embodiment, the at least one signal line includes at least one first type signal line and at least one second type signal line. The at least one first type signal line and the at least one second type signal line are arranged at intervals along a first direction and extend along a second direction. In the first direction, the size of the first type signal line is larger than the size of the second type signal line. In a plane parallel to the substrate, the first direction intersects the second direction.

[0011] At least a portion of the structure of the region corresponding to the pixel opening of the first type of signal line is set as a hollow structure. The hollow structure divides the first type of signal line into a plurality of lines arranged at intervals along the first direction. In the region corresponding to the same pixel opening, in the first direction, the size of at least a portion of the plurality of lines and the at least one second type of signal line is the same as the size of at least a portion of the second type of signal line.

[0012] In an exemplary embodiment, in the region corresponding to the same pixel opening: a plurality of first spacings are provided between the plurality of lines and the at least one second type signal line, the plurality of first spacings having the same size, and the first spacing being the distance between two adjacent lines among the plurality of lines and the at least one second type signal line.

[0013] In an exemplary embodiment, the plurality of lines and the at least one second-type signal line are uniformly arranged along the first direction in the region corresponding to the same pixel opening.

[0014] In an exemplary embodiment, in the region corresponding to the pixel opening, the dimensions of the line and the second type of signal line along the first direction are both greater than or equal to 1 micrometer and less than or equal to 15 micrometers, and the dimensions of the first spacing along the first direction are greater than or equal to 1 micrometer and less than or equal to 15 micrometers.

[0015] In an exemplary embodiment, the substrate includes a display area, the plurality of sub-pixels are located in the display area, the same first type of signal line is provided with at least one connection node in the display area, and the plurality of lines in the same first type of signal line are interconnected at the connection node location.

[0016] In an exemplary embodiment, the display substrate further includes a border region surrounding the display area and a plurality of first connection structures. In the second direction, the first connection structures are located on the side of the display area near the border region. In at least some of the plurality of first connection structures, each first connection structure corresponds to one of the first type signal lines. Multiple lines of the same first type signal line are interconnected on the side near the border region through the corresponding first connection structures.

[0017] In an exemplary embodiment, the display substrate further includes a plurality of first connection structures. In at least a portion of the plurality of first connection structures, each first connection structure corresponds to one of the first type signal lines. In the second direction, the first connection structure is located between two adjacent pixel openings. In at least a portion of the plurality of pixel openings, at least one first connection structure is provided on both sides of each pixel opening. Multiple lines in the same first type signal line located between two adjacent pixel openings are interconnected through corresponding first connection structures.

[0018] In an exemplary embodiment, at least one of the sub-pixels includes a pixel driving circuit located in the driving circuit layer; at least one of the pixel driving circuits includes a plurality of transistors and at least one capacitor, the plurality of transistors including at least one first type transistor and at least one second type transistor.

[0019] In a direction perpendicular to the plane of the substrate, the capacitor includes: a first electrode plate located on one side of the substrate, and a second electrode plate located on the side of the first electrode plate away from the substrate; the first type of transistor includes: an active layer located on the side of the first electrode plate close to the substrate, a control electrode disposed on the same layer as the first electrode plate, and a first electrode and a second electrode located on the side of the control electrode away from the substrate; the second type of transistor includes: an active layer located on the side of the second electrode plate away from the substrate, a control electrode located on the side of the active layer away from the substrate, and a first electrode and a second electrode located on the side of the control electrode away from the substrate; the first electrode and the second electrode of the first type of transistor are disposed on the same layer as the first electrode and the second electrode of the second type of transistor, and the at least one signal line is located on the side of the first electrode and the second electrode away from the substrate.

[0020] In an exemplary embodiment, the at least one signal line includes a plurality of first power lines and a plurality of first initial signal connection lines, the at least one signal line extends along the second direction and is arranged along the first direction; the plurality of sub-pixels include at least a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels, the plurality of sub-pixels form a plurality of pixel units, and the pixel unit includes at least one first sub-pixel, one second sub-pixel and one third sub-pixel;

[0021] In the same pixel unit: in the second direction, the pixel openings of the second sub-pixel and the pixel openings of the third sub-pixel are arranged alternately; in the first direction, the pixel driving circuits of the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged alternately, the pixel openings of the second sub-pixel and the third sub-pixel are located on the same side of the pixel opening of the first sub-pixel, the first initial signal connection line is located between the pixel driving circuits of the second sub-pixel and the third sub-pixel, and in the region corresponding to the pixel openings of the second sub-pixel and the third sub-pixel, the two first power lines in the second sub-pixel and the third sub-pixel are symmetrical with respect to the first initial signal connection line.

[0022] In an exemplary embodiment, the at least one signal line further includes a plurality of first second initial signal connection lines and a plurality of second power supply lines;

[0023] The first type of second initial signal line is located in the pixel driving circuit of the first sub-pixel. Each sub-pixel's pixel driving circuit is provided with a second power line. In the same pixel unit: in the region corresponding to the pixel opening of the first sub-pixel, the first type of second initial signal line and the second power line in the first sub-pixel are relative to the third center line, which is the center line of the pixel opening of the first sub-pixel extending along the second direction.

[0024] In an exemplary embodiment, the display substrate further includes a plurality of anode connection electrodes, a plurality of data signal lines, and a plurality of anodes. In a direction perpendicular to the plane of the display substrate, the plurality of anodes are located between the driving circuit layer and the pixel opening. The plurality of anode connection electrodes correspond one-to-one with the plurality of anodes. The sub-pixel further includes at least one anode connection electrode and at least one anode. In the same sub-pixel, the pixel driving circuit is electrically connected to the corresponding anode through the corresponding anode connection electrode. The at least one signal line further includes the plurality of anode connection electrodes.

[0025] In the same pixel unit: in the region corresponding to the pixel opening of the first sub-pixel, the data signal line and the anode connection electrode of the first sub-pixel are symmetrical with respect to the third center line. In the first direction, the data signal line is located on the side of the first type of second initial signal connection line away from the second power line, and the anode connection electrode of the first sub-pixel is located on the side of the second power line away from the first type of second initial signal connection line.

[0026] In an exemplary embodiment, within the same pixel unit: in the region corresponding to the anode of the second sub-pixel, the anode connection electrodes in the second sub-pixel and the third sub-pixel are symmetrical with respect to the first initial signal connection line; in the first direction, in either the second sub-pixel or the third sub-pixel, the anode connection electrode is located on the side of the first power line away from the first initial signal connection line.

[0027] In an exemplary embodiment, the at least one signal line includes a plurality of first-type signal lines and a plurality of second-type signal lines, wherein in the first direction, the size of the first-type signal lines is larger than the size of the second-type signal lines;

[0028] The plurality of first-type signal lines include: a first second initial signal line and a second power line located in the pixel driving circuit of the first sub-pixel, and a first power line located in the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel; the plurality of second-type signal lines include: a data signal line and an anode connection electrode located in the pixel driving circuit of the first sub-pixel, and a first initial signal connection line located between the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel;

[0029] The area corresponding to the pixel opening of the first type of signal line is set as a hollow structure. The hollow structure divides the first type of signal line into multiple lines arranged at intervals along the first direction. In the area corresponding to the same pixel opening, in the first direction, the size of the multiple lines is the same as the size of the second type of signal line.

[0030] In an exemplary embodiment, the display substrate further includes a plurality of second power connection lines, the second power connection lines extending along the first direction, and the second power connection lines being disposed in the same layer as the first electrode and the second electrode;

[0031] The plurality of second power lines and the plurality of second power connection lines are interconnected through second power vias to form a grid structure. The pixel opening of the first sub-pixel overlaps with the second power via. In the region corresponding to the pixel opening of the first sub-pixel, the dimension of the line in the second power connection line along the first direction at the position of the second power via is greater than the dimension along the first direction at the position where no second power via is provided.

[0032] In an exemplary embodiment, the at least one signal line includes a plurality of first-type signal lines. In the same sub-pixel, a plurality of anode vias are provided. The plurality of anode vias include a first anode via and a second anode via. The anode connection electrode is electrically connected to the corresponding pixel driving circuit through the first anode via and electrically connected to the corresponding anode through the second anode via. The lines of the first-type signal lines adjacent to the anode via bend away from the anode via in a direction away from the anode via.

[0033] In an exemplary embodiment, within the same pixel unit: in the second power line corresponding to the anode of the first sub-pixel, in the first direction, at least one line of the second power line corresponding to the anode via position in the first sub-pixel bends in a direction away from the corresponding anode via and merges with the line of the second power line on the side away from the corresponding anode via; in the first power line corresponding to the anode of the second sub-pixel, in the first direction, at least one line of the first power line corresponding to the anode via position in the second sub-pixel bends in a direction away from the corresponding anode via and merges with the line of the first power line on the side away from the corresponding anode via.

[0034] Secondly, this disclosure also provides a display device, including the display substrate described in any of the above embodiments.

[0035] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0036] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0037] Figure 1 is a schematic diagram of the structure of a display device;

[0038] Figure 2a is a schematic diagram of a display substrate;

[0039] Figure 2b shows a schematic diagram of a display substrate;

[0040] Figure 2c shows an enlarged structural diagram of the first border region;

[0041] Figure 3 is a schematic cross-sectional view of a display substrate;

[0042] Figure 4 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0043] Figure 5a shows a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0044] Figure 5b shows a schematic diagram of a planar structure of the fifth conductive layer, the anode conductive layer, and the pixel opening in Figure 5a.

[0045] Figure 5c shows a cross-sectional structural diagram of the M1-M1 position in Figure 5b;

[0046] Figure 5d shows a cross-sectional structure at position M2-M2 in Figure 5b;

[0047] Figure 5e shows a cross-sectional structural diagram of the M3-M3 position in Figure 5b;

[0048] Figure 5f shows a cross-sectional structural diagram of the M4-M4 position in Figure 5b;

[0049] Figure 6a shows a schematic diagram of a planar structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0050] Figure 6b shows a schematic diagram of a planar structure of the fifth conductive layer, the anode conductive layer, and the pixel opening in Figure 6a.

[0051] Figure 6c shows a cross-sectional structural diagram of the M5-M5 position in Figure 6b;

[0052] Figure 6d shows a schematic diagram of a planar structure of a fifth conductive layer, an anode conductive layer, and a pixel opening provided in an exemplary embodiment of the present disclosure.

[0053] Figure 6e shows a schematic diagram of a planar structure of a fifth conductive layer, an anode conductive layer, and a pixel opening provided in an exemplary embodiment of the present disclosure.

[0054] Figure 7a shows a schematic diagram of a planar structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0055] Figure 7b shows a schematic diagram of a planar structure of the fifth conductive layer, the anode conductive layer, and the pixel opening in Figure 7a.

[0056] Figure 8 is a schematic diagram of a display substrate after a first semiconductor layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0057] Figure 9a is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0058] Figure 9b is a schematic diagram of the first conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0059] Figure 10a is a schematic diagram of a display substrate after the formation of a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0060] Figure 10b is a schematic diagram of the second conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0061] Figure 11a is a schematic diagram of a display substrate after a second semiconductor layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0062] Figure 11b is a schematic diagram of the second semiconductor layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0063] Figure 12a is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0064] Figure 12b is a schematic diagram of the third conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0065] Figure 13 is a schematic diagram of a display substrate after the fifth insulating layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0066] Figure 14a is a schematic diagram of a display substrate after the fourth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0067] Figure 14b is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0068] Figure 15 is a schematic diagram showing the formation of a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0069] Figure 16a shows a schematic diagram of a display substrate after the fifth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0070] Figure 16b is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0071] Figure 17 is a schematic diagram of a display substrate after the formation of a second planarization layer according to an exemplary embodiment of the present disclosure;

[0072] Figure 18a is a schematic diagram of a display substrate after an anode conductive layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0073] Figure 18b is a schematic diagram of the anode conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0074] Figure 19a is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0075] Figure 19b is a schematic diagram of a pixel definition layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0076] Figure 20a is a schematic diagram of a display substrate after the fifth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0077] Figure 20b is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0078] Figure 20c shows a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0079] Figure 20d is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0080] Figure 21a is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0081] Figure 21b is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0082] Figure 21c is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0083] Figure 22a is a schematic diagram of a display substrate after the fifth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0084] Figure 22b is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0085] Figure 23 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0086] Figure 24 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0087] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0088] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted according to actual conditions. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0089] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0090] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0091] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0092] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0093] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged. In embodiments of this disclosure, the gate electrode can be referred to as the control electrode.

[0094] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0095] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0096] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0097] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0098] In the embodiments of this disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0099] Figure 1 shows a schematic diagram of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is connected to multiple data signal lines (D1 to Dn), the scan signal driving circuit is connected to multiple scan signal lines (G1 to Gm), and the light emission signal driving circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines (which may be referred to as data lines). In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driving circuit to the data signal driving circuit, clock signals, scan start signals, etc. of specifications suitable for the scan signal driving circuit to the scan signal driving circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driving circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driving circuit can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driving circuit can sequentially provide scan signals with conduction level pulses to scan signal lines G1 to Gm. For example, a scan signal driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A light-emitting signal driving circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, a light-emitting signal driving circuit can sequentially provide transmit signals with cutoff level pulses to light-emitting signal lines E1 to Eo. For example, a light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0100] Figure 2a is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2a, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0101] In an exemplary embodiment, a pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0102] Figure 2b shows a schematic diagram of a display panel structure. As shown in Figure 2b, the display panel may include a display area AA and a border area BB surrounding the display area AA. In some examples, the border area BB may include: a first border area (bottom border) B1 and a second border area (top border) arranged opposite each other in the second direction Y, and a third border area (left border) B3 and a fourth border area (right border) B4 arranged opposite each other in the first direction X. The first border area B1 is connected to the third border area B3 and the fourth border area B4, and the second border area B2 is connected to the third border area B3 and the fourth border area B4. In some examples, the display area AA may include a first edge (bottom edge) and a second edge (top edge) arranged opposite each other in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) arranged opposite each other in the first direction X. The display area AA may include multiple sub-pixels Pxij arranged in a regular pattern. Each sub-pixel may include a pixel driving circuit and a light-emitting device. The first border area B1 may include a bonding circuit that connects signal lines to an external driving device. The third border area B3 and the fourth border area B4 may include a gate driving circuit and a second power supply line VSS that transmits voltage signals to the multiple sub-pixels.

[0103] Figure 2c shows a schematic diagram of the planar structure of the first bezel region B1. In a plane parallel to the display substrate, the first bezel region B1 may include a first fan-out area 11, a bending area 12, a second fan-out area 13, and a bonding area 14 arranged sequentially along the direction away from the display area AA. The bonding area 14 may include a driver chip area 141, a third fan-out area 142, and a bonding electrode area 143 arranged sequentially along the direction away from the bending area 12 of the second fan-out area 13. The first fan-out area 11 may include a data fan-out line, a first power line, and a second power line VSS. The data fan-out line is located in the middle of the first fan-out area 11 and includes multiple data connection lines. The multiple data connection lines are configured to connect the data signal lines (Data Line) of the display area AA in a fan-out routing manner. The first power line is configured to connect the high-voltage power line (VDD) of the display area AA. The second power line is a low-voltage power line (VSS) located in the third bezel region B3 and the fourth bezel region B4. The bending area 12 may include a composite insulating layer with grooves, configured to bend the bonding area 14 to the back of the display area AA. The second fan-out area 13 includes multiple data connection lines led out in a fan-out routing manner. The driver chip area 141 may house an integrated circuit (IC) 20, configured to connect to the multiple data connection lines. The bonding electrode area 143 includes multiple bonding pads, configured to bond to the flexible printed circuit (FPC) 30. In an exemplary embodiment, the integrated circuit (IC) 20 may be bonded to the driver chip area 141, and the flexible printed circuit (FPC) 30 may be bonded to the bonding electrode area 142. In an exemplary embodiment, the integrated circuit 20 (which may be referred to as a data driving circuit or driving circuit) may generate driving signals required to drive sub-pixels and may provide the driving signals to the sub-pixel Pxij located in the display area AA. For example, the driving signal may be a data signal controlling the brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode area 143 may be provided with a pad including a plurality of pins, and the flexible circuit board 30 may be bonded to the pad.

[0104] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0105] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 for each sub-pixel may include multiple transistors and storage capacitors constituting the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, an organic light-emitting layer 302, and a cathode 303. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 emits light of a corresponding color under the driving force of the anode 301 and the cathode 303. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first and third encapsulation layers 401 and 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first and third encapsulation layers 401 and 403, ensuring that external moisture cannot enter the light-emitting structure layer 103.

[0106] In an exemplary embodiment, the organic light-emitting layer 302 may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0107] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, 8T1C, or 7T2C structure. As shown in Figure 4, the pixel driving circuit can include seven transistors (first transistor T1 to seventh transistor T76) and two capacitors C (first capacitor C1 and second capacitor C2). The pixel driving circuit can be connected to ten signal lines (data signal line DL, scan control line Gate, first reset control line Reset1, second reset control line Reset2, third reset control line Reset3, first light emission control line EM1, second light emission control line EM2, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD, and second power supply line VSS). In an exemplary embodiment, the third reset control line Reset3 can receive the signal from the first reset control line Reset1, which can reduce the number of gate driving circuits (GOA circuits) and is beneficial for narrowing the bezel. The pixel driving circuit will be described below with reference to Figure 4:

[0108] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the control electrode of the third transistor T3, the first terminal of the first capacitor C1, and the second electrode of the first transistor T1. The second node N2 is connected to the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5. The third node N3 is connected to the second terminal of the first capacitor C1, the first terminal of the second capacitor C2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The fourth node N4 is connected to the second terminal of the second capacitor C2, the second electrode of the second transistor T2, and the second electrode of the fourth transistor T4. The fifth node N5 is connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the anode of the light-emitting device EL.

[0109] In an exemplary embodiment, the first end of the first capacitor C1 is connected to the first node N1, and the second end of the first capacitor C1 is connected to the third node N3; the first end of the second capacitor C2 is connected to the third node N3, and the second end of the second capacitor C2 may be connected to the fourth node N4.

[0110] The control electrode of the first transistor T1 is connected to the first reset control line Reset1, the first terminal of the first transistor T1 is connected to the first initial signal line Vinit1, and the second terminal of the first transistor is connected to the first node N1. When a conduction-level reset signal is applied to the first reset control line Reset1, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the charge on the control electrode of the third transistor T3.

[0111] The control electrode of the second transistor T2 is connected to the third reset control line Reset3, the first electrode of the second transistor T2 is connected to the first initial signal line Vinit1, and the second electrode of the second transistor T2 is connected to the fourth node N4. When a conduction-level reset signal is applied to the third reset control line Reset3, the second transistor T2 transmits an initialization voltage to the fourth node N4 to initialize or release the accumulated charge in the fourth node N4.

[0112] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.

[0113] The control electrode of the fourth transistor T4 is connected to the scan control line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line DL, and the second electrode of the fourth transistor T4 is connected to the fourth node N4. The fourth transistor T4 can be called a switching transistor. When a conduction-level scan signal is applied to the scan control line Gate, the fourth transistor T4 causes the data voltage of the data signal line DL to be input to the pixel driving circuit.

[0114] The control electrode of the fifth transistor T5 is connected to the first light-emitting control line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the second light-emitting control line M2E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device (also the fifth node N5). The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors (or light-emitting control transistors). When a conduction-level light-emitting signal is applied to the first light-emitting control line EM1 and the second light-emitting control line EM2, the fifth transistor T5 and the sixth transistor T6 conduct, forming a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device to emit light.

[0115] The control electrode of the seventh transistor T7 is connected to the second reset control line Reset2, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device (also the fifth node N5). When a conduction-level reset signal is applied to the second reset control line Reset2, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device EL, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device EL.

[0116] In an exemplary embodiment, the second electrode of the light-emitting device EL is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal.

[0117] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polycrystalline silicon thin-film transistors (also known as P-type transistors), or oxide thin-film transistors (also known as N-type transistors), or a combination of low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors. For example, in Figure 4, the first transistor T1 to the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 can be oxide thin-film transistors, and the fifth transistor T5 can be a low-temperature polycrystalline silicon thin-film transistor. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves the product yield. The active layer of the low-temperature polycrystalline silicon thin-film transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide semiconductor. Low-temperature polycrystalline silicon thin-film transistors (LTPTs) have advantages such as high mobility and fast charging, while oxide thin-film transistors (OTTs) have advantages such as low leakage current, low-frequency drive capability, and low power consumption. Integrating LTPTs and OTTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate allows for the utilization of the advantages of both, enabling low-frequency drive, reducing power consumption, and improving display quality.

[0118] In an exemplary embodiment, the light-emitting device EL can be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0119] In a direction perpendicular to the plane of the display substrate, a planarization layer is provided between the anode and the second source / drain metal layer (the conductive layer closest to the anode in the driving circuit layer). The second source / drain metal layer has multiple traces. The traces at the overlap positions of the second source / drain metal layer and the anode at the pixel opening are unevenly arranged (for example, some traces have larger areas, and some traces have smaller areas; the planarization layer corresponding to the larger area trace will have a bulge on the side near the anode, causing the corresponding anode to bulge, and the surface of the anode away from the planarization layer will have a higher height relative to the substrate; the surface of the planarization layer corresponding to the smaller area trace and the gap between the traces will have a lower height relative to the substrate on the side near the anode, causing the surface of the anode away from the planarization layer to have a lower height relative to the substrate). This results in the side of the anode away from the planarization layer exhibiting a height-uneven distribution according to the shape of the second source / drain metal layer traces. Due to the inconsistent height of the surface of the anode away from the planarization layer relative to the substrate, the pixel openings of the display substrate often exhibit symmetrical color shift problems, i.e., color asymmetry, which affects the visual effect. This color asymmetry problem is particularly serious in display substrates with medium and large-sized Real RGB pixel architectures.

[0120] An exemplary embodiment of this disclosure provides a display substrate, which may include: a substrate and a plurality of sub-pixels, a driving circuit layer, and a pixel definition layer disposed on the substrate. In a direction perpendicular to the plane of the display substrate, the driving circuit layer is located between the substrate and the pixel definition layer. The driving circuit layer includes a plurality of conductive layers. A plurality of pixel openings are formed in the pixel definition layer. The sub-pixels include at least one pixel opening.

[0121] In at least one of the plurality of conductive layers, at least one signal line in the same conductive layer corresponds to at least one pixel opening, and the at least one signal line and the corresponding pixel opening have an overlapping area. In the area corresponding to the same pixel opening, the at least one signal line is symmetrical with respect to a first center line of the pixel opening, and the first center line is the center line of the pixel opening extending along a second direction.

[0122] The display substrate provided in this embodiment includes a driving circuit layer comprising multiple conductive layers. At least one signal line in the same conductive layer corresponds to at least one pixel opening. At least one signal line and the corresponding pixel opening have an overlapping area. In the area corresponding to the same pixel opening, at least one signal line is symmetrical with respect to the first center line of the pixel opening. The first center line is the center line of the pixel opening extending along a second direction. This can improve asymmetric color shift and solve the problem of color shift asymmetry to a certain extent, thereby improving the display effect.

[0123] As shown in Figures 5a, 6a and 7a, this is a schematic diagram of a planar structure of a display substrate provided in an embodiment of the present disclosure. The display substrate provided in this embodiment may include: a substrate and a plurality of sub-pixels Pxij disposed on the substrate, a driving circuit layer and a pixel definition layer. In the direction perpendicular to the plane of the display substrate, the driving circuit layer is located between the substrate and the pixel definition layer. The driving circuit layer may include a plurality of conductive layers. A plurality of pixel openings K are formed in the pixel definition layer. The sub-pixel Pxij includes at least one pixel opening K.

[0124] In at least one of the multiple conductive layers, at least one signal line SL in the same conductive layer corresponds to at least one pixel opening K. At least one signal line SL and the corresponding pixel opening K have an overlapping area. In the area corresponding to the same pixel opening K, the at least one signal line SL is symmetrical with respect to the first center line Q1-Q1 of the pixel opening K (as shown in Figure 5a). The first center line Q1-Q1 is the center line of the pixel opening K extending along the second direction Y.

[0125] In an exemplary embodiment, in the region corresponding to the same pixel opening K, the at least one signal line SL is symmetrical with respect to the first center line Q1-Q1 of the pixel opening K, which makes the side of the anode in the pixel opening away from the substrate symmetrical with respect to the height of the substrate, thereby reducing asymmetric color shift.

[0126] In an exemplary embodiment, at least one conductive layer may include the conductive layer in the driving circuit layer that is closest to the pixel definition layer, and the at least one signal line SL may be located in the conductive layer in the driving circuit layer that is closest to the pixel definition layer. For example, the conductive layer in the driving circuit layer that is closest to the pixel definition layer is a second source-drain metal layer (typically located in the fifth conductive layer of the pixel driving circuit), and the at least one signal line may be located in the second source-drain metal layer.

[0127] In an exemplary embodiment, as shown in Figures 5b to 5f, Figure 5b is a planar schematic diagram of the second source / drain metal layer, anode conductive layer, and pixel definition layer in Figure 5a; Figure 5c is a cross-sectional schematic diagram along position M1-M1 in Figure 5b; Figure 5d is a cross-sectional schematic diagram along position M2-M2 in Figure 5b; Figure 5e is a cross-sectional schematic diagram along position M3-M3 in Figure 5b; and Figure 5f is a cross-sectional schematic diagram along position M4-M4 in Figure 5b. The display substrate may further include an anode conductive layer. In a direction perpendicular to the plane of the display substrate, the anode conductive layer may be located between the driving circuit layer and the pixel definition layer. The anode conductive layer may include multiple anodes AN, and the multiple anodes AN correspond one-to-one with multiple pixel openings K. The orthographic projection of the pixel opening K on the substrate may be located within the range of the orthographic projection of the corresponding anode AN on the substrate.

[0128] At least one signal line SL corresponds to at least one anode AN, and at least one signal line SL and the corresponding anode AN have an overlapping region. In the region corresponding to the same anode AN, at least one signal line SL is symmetrical with respect to the second center line Q2-Q2 of the main body of the anode AN. The second center line Q2-Q2 is the center line of the main body of the anode AN extending along the second direction Y. In the same sub-pixel Pxij, the first center line Q1-Q1 can overlap with the orthographic projection of the second center line Q2-Q2 on the substrate, as shown in Figure 5a, where the first center line Q1-Q1 overlaps with the second center line Q2-Q2.

[0129] In an exemplary embodiment, in the region corresponding to the same anode AN, at least one signal line SL is symmetrical with respect to the second center line Q2-Q2 of the anode AN body, which can improve the flatness of the anode away from the substrate, reduce color asymmetry, and improve display uniformity.

[0130] In an exemplary embodiment, FIG5c is a cross-sectional view of the pixel opening K01 position of the first sub-pixel P1 in FIG5b, FIG5d is a cross-sectional view of the pixel opening K02 position of the second sub-pixel P2 in FIG5b, FIG5e is a cross-sectional view of the pixel opening K03 position of the third sub-pixel P3 in FIG5b, and FIG5f is a cross-sectional view of the M4-M4 position of the second sub-pixel P2 in FIG5b. It is not difficult to see from the plan view of FIG5b and the cross-sectional views of FIG5c to FIG5f that when the first type of signal line SL1 is not provided with a hollow structure KL, the multiple signal lines SL in the region corresponding to the pixel opening K in each first sub-pixel Pxij are symmetrical with respect to the midline extending along the second direction Y of the corresponding pixel opening K. This can improve the flatness of the anode side away from the substrate corresponding to the pixel opening K, thereby reducing color shift asymmetry. In the structure shown in Figure 5c, in the first direction X, the dimensions of distance a1 and distance b1 are substantially the same, the dimensions of distance a2 and distance b2 are substantially the same, the dimensions of distance a3 and distance b3 are substantially the same, the dimensions of distance a4 and distance b5 are substantially the same, and the dimensions of distance a5 and distance b5 are substantially the same. In an exemplary embodiment, in Figures 5c to 5f, PDL is a pixel definition layer, and PLN2 is a second planarization layer.

[0131] In an exemplary embodiment, as shown in Figures 5a, 6a, and 7a, at least one signal line SL may include at least one first type signal line SL1 and at least one second type signal line SL2. The at least one first type signal line SL1 and at least one second type signal line SL2 are arranged at intervals along a first direction X and extend along a second direction Y, as shown in Figures 5b and 5c. Figure 5c is a cross-sectional structural schematic diagram of the position M1-M1 in Figure 5b. In the first direction X, the size f1 of the first type signal line SL1 is larger than the size f2 of the second type signal line SL2. In a plane parallel to the substrate, the first direction X intersects the second direction Y.

[0132] In an exemplary embodiment, as shown in Figures 6b and 7b, Figure 6b is a planar structural diagram of the second source / drain metal layer, anode conductive layer, and pixel definition layer in Figure 6a, and Figure 7b is a planar structural diagram of the second source / drain metal layer, anode conductive layer, and pixel definition layer in Figure 7a. At least a portion of the structure of the region corresponding to at least a portion of the first type signal lines SL1 and the pixel opening K can be set as a cutout structure LK. The cutout structure LK can divide the first type signal lines SL1 into multiple lines L0 arranged at intervals along the first direction X. In the region corresponding to the same pixel opening K, in the first direction X, among the multiple lines L0 and at least one second type signal line SL2, the size w1 of at least a portion of the lines L0 is consistent with the size w2 of at least a portion of the second type signal lines SL2. As shown in Figure 6c, a cross-sectional structural diagram along position M5-M5 in Figure 6b is shown. In the region corresponding to the same pixel opening K, in the first direction X, the size w1 of the line L0 is consistent with the size w2 of the second type signal line SL2. The cross-sectional structural diagram along position M6-M6 in Figure 7b is the same as that in Figure 6c.

[0133] In an exemplary embodiment, as shown in Figures 6b and 6c, in the region corresponding to the same pixel opening K, a plurality of first spacings h1 are provided between a plurality of lines L0 and at least one second type signal line SL2. The plurality of first spacings h1 have the same size. The first spacing h1 is the distance between two adjacent lines L0 and at least one second type signal line SL2. For example, the first spacing h1 may include s2, s3, s4, s5, and s6 in Figure 6c.

[0134] In an exemplary embodiment, as shown in FIG6c, in the region corresponding to the same pixel opening K, multiple lines L0 and at least one second type signal line SL2 are uniformly arranged along the first direction X, which can improve the flatness of the anode away from the substrate and reduce color asymmetry to a certain extent.

[0135] In an exemplary embodiment, as shown in FIG6c, in the region corresponding to the same pixel opening K, in the first direction X, the size w1 of line L0 is consistent with the size w2 of the second type signal line SL, and the sizes of multiple first spacings h1 are consistent (consistency can be substantially the same or have a certain error). This makes multiple lines L0 and at least one second type signal line SL2 evenly distributed along the first direction X, which can improve the flatness of the side of the anode away from the substrate and help reduce color shift asymmetry. In actual design, s1 is usually the same as s7, the value of pixel opening K along the first direction X is fixed, the closer the values ​​of w1 and w2 are, the better the color shift asymmetry problem is solved, and the closer the values ​​of s2, s3, s4, s5, and s6 are, the better the color shift asymmetry problem is solved. The number of lines L0 corresponding to each pixel opening K can be set according to the values ​​of s2 to s6 and the value of w1. As shown in Figure 6c, the pixel opening K01 of the first sub-pixel P1 corresponds to four lines L0, one anode connecting electrode ZL, and one data signal line DL, but it is not limited to this. It can be designed in combination with the pixel opening size and the size of the signal line SL corresponding to the pixel opening.

[0136] In an exemplary embodiment, as shown in FIG6c, in the region corresponding to the pixel opening K, the dimension w1 of line L0 along the first direction X and the dimension w2 of the second type signal line SL2 along the first direction X are both greater than or equal to 1 micrometer and less than or equal to 15 micrometers, and the dimension h1 of the first spacing along the first direction X is greater than or equal to 1 micrometer and less than or equal to 15 micrometers. For example, as shown in FIG6c, the dimension w1 of line L0 along the first direction X can be greater than or equal to 1.5 micrometers and less than or equal to 10 micrometers, the dimension w2 of the second type signal line SL2 along the first direction X can be greater than or equal to 1.5 micrometers and less than or equal to 10 micrometers, and the dimension h1 of the first spacing along the first direction X can be greater than or equal to 2 micrometers and less than or equal to 12 micrometers. For example, the values ​​of w1 and w2 are around 2 micrometers, and the value of h1 is around 3 micrometers.

[0137] In an exemplary embodiment, as shown in FIG2b, the substrate may include a display area AA, and multiple sub-pixels Pxij may be located in the display area AA. As shown in FIG6b, the same first type signal line SL may have at least one connection node L1 in the display area AA, and multiple lines L0 in the same first type signal line SL1 may be connected to each other at the connection node L1. This can prevent the resistance of the corresponding first type signal line SL1 from increasing due to the breakage of one or more lines L0. In the event of a line breakage at a certain point, the impedance of the corresponding first type signal line SL1 can be reduced, thereby improving display uniformity.

[0138] In an exemplary embodiment, as shown in Figures 2b, 6e, and 6d, the display substrate may further include a border region BB surrounding the display area AA and a plurality of first connection structures LH1. In the second direction Y: the first connection structure LH1 may be located on the side of the display area AA near the border region BB. In at least some of the multiple first connection structures LH1, each first connection structure LH1 corresponds to one of the first type signal lines SL1. Multiple lines L0 in the same first type signal line SL1 are interconnected on the side near the border region BB through the corresponding first connection structure LH1, which can avoid the impedance of the corresponding first type signal line SL1 from increasing due to the breakage of line L0 at a certain position. For example, Figure 6d shows the side of the first row of sub-pixels near the second border region B2. Each first type signal line SL1 has a corresponding first connection structure LH1. At the position near the second border region B2, the first connection structure LH1 connects multiple lines L0 in the corresponding first type signal line SL1 into a single structure. Figure 6e shows the side of the last row of sub-pixels near the first border region B1. Each first type signal line SL1 has a corresponding first connection structure LH1. At the position near the first border region B1, the first connection structure LH1 connects multiple lines L0 in the corresponding first type signal line SL1 into a single structure.

[0139] In an exemplary embodiment, as shown in FIG7b, FIG7b is a schematic diagram of the planar structure of the second source / drain metal layer, the anode conductive layer, and the pixel definition layer in FIG7a. The display substrate may further include a plurality of first connection structures LH1. In at least a portion of the plurality of first connection structures LH1, each first connection structure LH1 corresponds to one of the first type signal lines SL1. In the second direction Y: the first connection structure LH1 may be located between two adjacent pixel openings K. In at least a portion of the plurality of pixel openings K, at least one first connection structure LH1 is provided on both sides of each pixel opening K. Multiple lines L0 located between two adjacent pixel openings K in the same first type signal line SL1 are connected to each other through the corresponding first connection structure LH1. In other words, multiple lines can be connected to each other through the first connection structure LH1 in the area where the first type signal line SL1 extends beyond the corresponding pixel opening K. This can avoid the impedance of the corresponding first type signal box SL1 from increasing after a line is broken, and can improve display uniformity.

[0140] The difference between Figures 6d, 6e and 7b is that in Figures 6d and 6e, multiple lines L0 in the corresponding first type signal line SL1 are connected by the first connection structure LH1 on the side of the display area AA near the border area AA. In the structure shown in Figure 7b, not only on the side of the display area AA near the border area BB, but also on both sides of the opening K of each pixel in the display area AA along the second direction Y, multiple lines L0 in the corresponding first type signal line SL1 can be connected by the first connection structure LH1.

[0141] In an exemplary embodiment, at least one sub-pixel Pxij may include a pixel driving circuit, which may be located in a driving circuit layer; the at least one pixel driving circuit includes a plurality of transistors and at least one capacitor, the plurality of transistors including at least one first type transistor and at least one second type transistor.

[0142] In a direction perpendicular to the plane of the substrate, the capacitor includes: a first electrode plate located on one side of the substrate, and a second electrode plate located on the side of the first electrode plate away from the substrate; a first type of transistor includes: an active layer located on the side of the first electrode plate close to the substrate, a control electrode disposed on the same layer as the first electrode plate, and a first electrode and a second electrode located on the side of the control electrode away from the substrate; a second type of transistor includes: an active layer located on the side of the second electrode plate away from the substrate, a control electrode located on the side of the active layer away from the substrate, and a first electrode and a second electrode located on the side of the control electrode away from the substrate; the first electrode and the second electrode of the first type of transistor are disposed on the same layer as the first electrode and the second electrode of the second type of transistor, and the at least one signal line SL is located on the side of the first electrode and the second electrode away from the substrate.

[0143] In an exemplary embodiment, the first type of transistor can be a P-type transistor, and the second type of transistor can be an N-type transistor.

[0144] In an exemplary embodiment, as shown in Figures 5a, 6a, and 7a, which are schematic diagrams of several planar structures of the pixel driving circuit shown in Figure 4, the first type of transistor may include a fifth transistor T5 as a light-emitting control transistor, and the second type of transistor includes a first transistor T1 as a reset transistor, a second transistor T2 as a reset transistor, a third transistor T3 as a control transistor, a fourth transistor T4 as a data writing transistor, a sixth transistor T6 as a light-emitting control transistor, and a seventh transistor T7 as a reset transistor; in the same sub-pixel, in the first direction X, the fifth transistor T5, the first transistor T1, the second transistor T2, and the fourth transistor T4 Located on the same side as the third transistor T3, in the second direction Y, the seventh transistor T7, the sixth transistor T6, the fourth transistor T4, the sixth transistor T6, the third transistor T3, and the fifth transistor T5 are arranged sequentially along the second direction Y. The capacitors in the pixel driving circuit may include a first capacitor C1 and a second capacitor C2. In the first direction X, the fifth transistor T5, the first transistor T1, the second transistor T2, and the fourth transistor T4 are located on the same side as the first capacitor C1 and the second capacitor C2. In the second direction Y, the second capacitor C2 and the first capacitor C1 are arranged sequentially. The orthographic projection of the third transistor T3 onto the substrate can be within the range of the orthographic projection of the first capacitor C1 onto the substrate. The connection relationship between the first transistor T1 to the seventh transistor T7, the first capacitor C1, and the second capacitor C2 can be referred to the previous description of Figure 4.

[0145] In an exemplary embodiment, as shown in FIG5b, FIG6b and FIG7b, at least one signal line SL may include a plurality of first power lines VDD and a plurality of first initial signal connection lines Vinit1L, wherein the at least one signal line SL extends along the second direction Y and is arranged along the first direction X; the plurality of sub-pixels Pxij include at least a plurality of first sub-pixels P1, a plurality of second sub-pixels P2 and a plurality of third sub-pixels P3, the plurality of sub-pixels Pxij form a plurality of pixel units P, wherein the pixel unit P includes at least one first sub-pixel P1, one second sub-pixel P2 and one third sub-pixel P3;

[0146] In the same pixel unit P: in the second direction Y, the pixel opening K02 of the second sub-pixel P2 and the pixel opening K03 of the third sub-pixel P3 can be arranged alternately; in the first direction X, the pixel driving circuit of the first sub-pixel P1, the pixel driving circuit of the second sub-pixel P2, and the pixel driving circuit of the third sub-pixel P3 can be arranged alternately, the pixel opening K02 of the second sub-pixel P2 and the pixel opening K03 of the third sub-pixel P3 can be located on the same side of the pixel opening K01 of the first sub-pixel P1, and the first initial signal connection line Vinit1L can be located between the pixel driving circuit of the second sub-pixel P1 and the pixel driving circuit of the third sub-pixel P2. In the region corresponding to the pixel opening K02 of the second sub-pixel P2 and the pixel opening K03 of the third sub-pixel P3, the two first power lines VDD in the second sub-pixel P2 and the third sub-pixel P3 are symmetrical with respect to the first initial signal connection line Vinit1L.

[0147] In the structures shown in Figures 5a, 6a, and 7a, the pixel driving circuits of multiple sub-pixels can form multiple columns. Figures 5a, 6a, and 7a show the pixel driving circuits of columns N to N+5 in the Mth row of sub-pixels.

[0148] In an exemplary embodiment, as shown in FIG5b, FIG6b and FIG7b, at least one signal line SL may further include a plurality of first second initial signal connection lines Vinit2L-B and a plurality of second power lines VSS;

[0149] The first type of second initial signal line Vinit2L-B can be located in the pixel driving circuit of the first sub-pixel P1. Each pixel driving circuit of sub-pixel P1 is provided with a second power supply line VSS. In the same pixel unit P: in the region corresponding to the pixel opening K01 of the first sub-pixel P1, the first type of second initial signal line Vinit2L-B and the second power supply line VSS in the first sub-pixel P1 are relative to the third center line Q3-Q3. The third center line Q3-Q3 (as shown in Figure 7a) is the center line of the pixel opening K01 of the first sub-pixel Pxij extending along the second direction Y.

[0150] In an exemplary embodiment, as shown in Figures 5a, 6a, and 7a, the display substrate may further include multiple anode connection electrodes ZL, multiple data signal lines DL, and multiple anodes AN. In a direction perpendicular to the plane of the display substrate, the multiple anodes AN may be located between the driving circuit layer and the pixel opening K. The multiple anode connection electrodes ZL and the multiple anodes AN may correspond one-to-one. The sub-pixel Pxij may further include at least one anode AN connection electrode ZL and at least one anode AN. In the same sub-pixel Pxij, the pixel driving circuit is electrically connected to the corresponding anode AN through the corresponding anode connection electrode ZL. At least one signal line SL may further include multiple anode connection electrodes ZL.

[0151] In the same pixel unit P: in the region corresponding to the pixel opening K01 of the first sub-pixel P1, the data signal line DL and the anode connection electrode ZL of the first sub-pixel P1 are symmetrical with respect to the third center line Q3-Q3. In the first direction X, the data signal line DL can be located on the side of the first second initial signal connection line Vinit2L-B away from the second power line VSS, and the anode connection electrode ZL of the first sub-pixel P1 can be located on the side of the second power line VSS away from the first second initial signal connection line Vinit2L-B.

[0152] In an exemplary embodiment, as shown in Figures 5a, 6a, and 7a, within the same pixel unit P: in the region corresponding to the anode AN2 of the second sub-pixel P2, the anode connection electrode ZL in the second sub-pixel P2 and the third sub-pixel P3 can be symmetrical with respect to the first initial signal connection line Vinit2L-B; in the first direction X, in either sub-pixel Pxij of the second sub-pixel P2 and the third sub-pixel P2, the anode connection electrode ZL is located on the side of the first power line VDD away from the first initial signal connection line Vinit2L-B. For example, in the first direction X, in the second sub-pixel P2, the anode connection electrode ZL is located on the side of the first power line VDD away from the first initial signal connection line Vinit2L-B, and in the third sub-pixel P2, the anode connection electrode ZL is located on the side of the first power line VDD away from the first initial signal connection line Vinit2L-B.

[0153] In an exemplary embodiment, as shown in Figures 5a, 5c, 6a, and 7a, at least one signal line SL may include a plurality of first-type signal lines SL1 and a plurality of second-type signal lines SL2. As shown in Figure 5c, in the first direction X, the size f1 of the first-type signal line SL1 is larger than the size f2 of the second-type signal line SL2.

[0154] In an exemplary embodiment, as shown in Figures 5a, 6a, and 7a, the plurality of first-type signal lines SL1 may include: a first second initial signal line Vinit2L-B and a second power supply line VSS located in the pixel driving circuit of the first sub-pixel P1, and a first power supply line VDD located in the pixel driving circuits of the second sub-pixel P2 and the third sub-pixel P3; the plurality of second-type signal lines SL2 may include: a data signal line DL and an anode connection electrode ZL located in the pixel driving circuit of the first sub-pixel P1, and a first initial signal connection line Vinit1L located between the pixel driving circuits of the second sub-pixel P2 and the pixel driving circuits of the third sub-pixel P3;

[0155] As shown in Figures 6b, 6c, and 7b, the area corresponding to the first type of signal line SL1 and the pixel opening K can be set as a cutout structure LK. The cutout structure LK can divide the first type of signal line SL1 into multiple lines L0 arranged at intervals along the first direction X. In the area corresponding to the same pixel opening K, in the first direction X, the size w1 of the multiple lines L0 is consistent with the size w2 of the second type of signal line SL. In the same sub-pixel, the flatness of the anode away from the substrate can be improved, and the color shift asymmetry will be reduced to a certain extent.

[0156] In an exemplary embodiment, as shown in FIG5a, FIG6a and FIG7a, the display substrate may further include a plurality of second power connection lines VSSL, the second power connection lines VSSL may extend along the first direction X, and the second power connection lines VSSL may be disposed in the same layer as the first electrode and the second electrode.

[0157] As shown in Figures 6a and 7a, multiple second power lines VSS and multiple second power connection lines VSSL are interconnected through second power vias KVSS to form a grid structure, which can reduce the voltage drop of the second power lines VSS. The pixel opening K01 of the first sub-pixel P overlaps with the second power via KVSS. In the area corresponding to the pixel opening K01 of the first sub-pixel P1, the line L0 in the second power connection line VSSL has a larger dimension along the first direction X at the position of the second power via KVSS than the dimension along the first direction at the position where no second power via KVSS is provided.

[0158] In an exemplary embodiment, as shown in Figures 6a and 7a, at least one signal line SL may include multiple first-type signal lines SL1. In the same sub-pixel Pxij, multiple anode vias KAN are provided. The multiple anode vias KAN may include first anode vias KAN1 and second anode vias KAN2. The anode connection electrode ZL is electrically connected to the corresponding pixel driving circuit through the first anode via KAN1 and electrically connected to the corresponding anode AN through the second anode via KAN2. The line L0 of the first-type signal line SL1 and the anode via KAN adjacent to the anode via KAN may be bent away from the anode via KAN in a direction away from the anode via KAN.

[0159] In an exemplary embodiment, within the same pixel unit P: in the second power line VSS corresponding to the anode AN1 of the first sub-pixel P1, in the first direction X, at least one line L0 of the second power line VSS corresponding to the position of the anode via KAN in the first sub-pixel P1 is bent in a direction away from the corresponding anode via KAN and merged with the line L0 of the second power line VSS on the side away from the corresponding anode via KAN; in the first power line VDD corresponding to the anode AN2 of the second sub-pixel P2, in the first direction X, at least one line L0 of the first power line VDD corresponding to the position of the anode via KAN in the second sub-pixel P1 is bent in a direction away from the corresponding anode via KAN and merged with the line L0 of the first power line VDD on the side away from the corresponding anode via KAN.

[0160] In an exemplary embodiment, in Figures 5c to 5f and Figure 6c, the direction represented by Z is the direction perpendicular to the plane where the base is located.

[0161] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate (or substrate plate) using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0162] In an exemplary embodiment, taking six sub-pixels (one sub-pixel row, six sub-pixel columns, and the pixel driving circuit adopts the 7T2C structure shown in Figure 4) in the display area (AA) as an example, the fabrication process of one display substrate may include the following operations:

[0163] (101) A substrate is prepared on a glass substrate. In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, an adhesive layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers, and the material of the adhesive layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible material (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible material (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0164] (102) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: depositing a first semiconductor thin film on a substrate, and patterning the semiconductor thin film by a patterning process to form a first semiconductor layer pattern, as shown in FIG8, FIG8 is a planar schematic diagram of the six sub-pixels after forming the first semiconductor layer.

[0165] In an exemplary embodiment, the first semiconductor layer pattern in at least a portion of the sub-pixels includes at least: the active layer AT5 of the fifth transistor T5.

[0166] In an exemplary embodiment, the active layer AT5 of the fifth transistor T5 can be L-shaped.

[0167] In an exemplary embodiment, the active layer of at least some of the transistors may include a first region, a second region, and a channel region located between the first region and the second region. The first region AT51 and the second region AT52 of the active layer AT5 of the fifth transistor T5 may be separately provided.

[0168] In an exemplary embodiment, pixel driving circuits of multiple sub-pixels form multiple rows and multiple columns, and the multiple pixel driving circuits form multiple circuit units. Among pixel driving circuits in the same row, three adjacent pixel driving circuits may constitute a circuit unit, and the multiple circuit units may form multiple rows and multiple columns.

[0169] In an exemplary embodiment, in the same row of circuit units, the first semiconductor layer in the two closest pixel driving circuits of two adjacent circuit units is mirror-symmetric with respect to a first center line. The first center line may be a straight line along which two adjacent circuit units extend in the second direction Y. Taking M rows of pixel driving circuits as an example: Three pixel driving circuits, namely the Nth column pixel driving circuit, the (N + 1)th column pixel driving circuit, and the (N + 2)th column pixel driving circuit, constitute a circuit unit, and three pixel driving circuits, namely the (N + 3)th column pixel driving circuit, the (N + 4)th column pixel driving circuit, and the (N + 5)th column pixel driving circuit, constitute another circuit unit. The two closest pixel driving circuits of two adjacent circuit units are the (N + 2)th column pixel driving circuit and the (N + 3)th column pixel driving circuit. The first semiconductor layer in the (N + 2)th column pixel driving circuit and the first semiconductor layer in the (N + 3)th column pixel driving circuit may be symmetric with respect to the first center line between the (N + 2)th column pixel driving circuit and the (N + 3)th column pixel driving circuit.

[0170] In an exemplary embodiment, the active layers AT5 of the two closest fifth transistors T5 in two adjacent circuit units are connected to each other to form a "Ji" (Chinese character for "several") shaped structure. For example, in the Mth row of pixel driving circuits, the active layer AT5 of the fifth transistor T5 in the (N + 2)th column pixel driving circuit and the active layer AT5 of the fifth transistor T5 in the (N + 2)th column pixel driving circuit are connected to each other to form a "Ji" shaped structure.

[0171] In an exemplary embodiment, a pixel driving circuit of a first sub-pixel, a pixel driving circuit of a second sub-pixel, and a pixel driving circuit of a third sub-pixel may be included in the same circuit unit.

[0172] In an exemplary embodiment, the first semiconductor layer may be polycrystalline silicon (p-Si), meaning the fifth transistor T5 may be an LTPS thin-film transistor. In another exemplary embodiment, patterning the first semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; then performing a hydrogen removal treatment on the amorphous silicon thin film; and finally performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the pattern of the first semiconductor layer.

[0173] (103) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed, and patterning the first conductive film using a patterning process to form a first conductive layer pattern covering the first semiconductor layer pattern, as shown in Figures 9a and 9b. Figure 9a is a planar structural schematic diagram of six sub-pixels after the formation of the first conductive layer, and Figure 9b is a planar schematic diagram of the first conductive layer in Figure 9a. The first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0174] In an exemplary embodiment, the first conductive layer pattern may include at least: the first electrode C11 of the first capacitor C1, the first electrode C21 of the second capacitor C2, the first second initial signal line Vinit2-B, and the control electrode T5g of the fifth transistor T5.

[0175] In an exemplary embodiment, the first type of second initial signal line Vinit2-B can be a broken line structure or a strip structure extending along the first direction X; in the same sub-pixel, in the second direction Y, the first type of second initial signal line Vinit2-B can be located on the side of the first plate C21 of the second capacitor C2 away from the first plate C11 of the first capacitor C1.

[0176] In an exemplary embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be block structures, and the shape of the block structure can be polygonal, for example, it can be approximately rectangular. In an exemplary embodiment, in the same sub-pixel, in the second direction Y, the first plate C21 of the second capacitor C2 and the first plate C11 of the first capacitor C1 can be arranged sequentially.

[0177] In an exemplary embodiment, the first plate C11 of the first capacitor C1 may be provided with a first connection portion CL1. The first connection portion CL1 is configured to accommodate a subsequently formed twelfth via. The orthographic projection of the twelfth via on the substrate is within the range of the orthographic projection of the first connection portion CL1 on the substrate, and exposes the surface of the first connection portion CL1, so that the second electrode of the subsequently formed first transistor T1 is connected to the first plate C11 of the first capacitor C1 through the twelfth via and the first connection portion CL1.

[0178] In an exemplary embodiment, the first plate C21 of the second capacitor C2 may be provided with a second connection portion CL2. The second connection portion CL2 is configured to accommodate a subsequently formed thirteenth via. The orthographic projection of the thirteenth via on the substrate is within the range of the orthographic projection of the second connection portion CL2 on the substrate, and exposes the surface of the second connection portion CL2, so that the second electrode of the subsequently formed second transistor T2 and the second electrode of the fourth transistor T4 are connected to the first plate C21 of the second capacitor C2 through the thirteenth via and the second connection portion CL2.

[0179] Taking the Mth row and Nth column sub-pixel as an example: In the second direction Y, the first plate C11 of the first capacitor C1 in the Mth row can be located on the side of the first plate C21 of the second capacitor C2 of the same sub-pixel near the (M-1)th row sub-pixel, and the control electrode T5g of the fifth transistor T5 can be located on the side of the main body of the first plate C11 of the first capacitor C1 of the same sub-pixel near the (M-1)th row sub-pixel; In the first direction X, the control electrode T5g of the fifth transistor T5 is located on at least part of the structure of the first plate C11 of the first capacitor C1 and the side of the first plate C21 of the second capacitor C2 near the (N-1)th column sub-pixel.

[0180] In an exemplary embodiment, the control electrode T5g of the fifth transistor T5 at least partially overlaps with the active layer AT5 of the fifth transistor T5. For example, the control electrode T5g of the fifth transistor T5 overlaps with the channel region of the active layer AT5 of the fifth transistor T5. Within the same sub-pixel, in the first direction X, the control electrode T5g of the fifth transistor T5 may be located on one side of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2. In the second direction Y, the control electrode T5g of the fifth transistor T5 may be located on the side of the first connection portion CL1 away from the first plate C21 of the second capacitor C2.

[0181] In an exemplary embodiment, in the same row of circuit units, the first conductive layer in the two nearest pixel driving circuits of two adjacent circuit units can be mirror-symmetrical with respect to the first center line. For example, the first conductive layer in the N+2th column pixel driving circuit and the first conductive layer in the N+3th column pixel driving circuit can be symmetrical with respect to the first center line between the N+2th column pixel driving circuit and the N+3th column pixel driving circuit.

[0182] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the fifth transistor T5, and the first semiconductor layer in the area not shielded by the first conductive layer is conducted. That is, the first region and the second region of the active layer AT5 of the fifth transistor T5 are both conducted.

[0183] (104) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a second insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the second insulating layer, as shown in Figures 10a and 10b. Figure 10a is a planar structural diagram of six sub-pixels after the formation of the second conductive layer, and Figure 10b is a planar schematic diagram of the second conductive layer in Figure 10a. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0184] In an exemplary embodiment, the second conductive layer pattern may include at least: the second electrode C12 of the first capacitor C1, the second electrode C22 of the second capacitor C2, and the third connecting portion CL3.

[0185] In an exemplary embodiment, the outline of the second plate C12 of the first capacitor C1 can be consistent with the outline of the first plate C11 of the first capacitor C1, and the outline of the second plate C22 of the second capacitor C2 can be consistent with the outline of the first plate C21 of the second capacitor C2. For example, the outlines of the second plates C12 of the first capacitor C1 and C22 of the second capacitor C2 can be polygons (e.g., rectangles). In an exemplary embodiment, the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate overlaps with the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate, and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate overlaps with the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate. For example, the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate can cover the orthographic projection of the main body of the first plate C11 of the first capacitor C1 on the substrate, and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate can cover the orthographic projection of the main body of the first plate C21 of the second capacitor C2 on the substrate. In an exemplary embodiment, the first plate C11 and the second plate C12 of the first capacitor C1 constitute the first capacitor C1, and the first plate C21 and the second plate C22 of the second capacitor C2 constitute the second capacitor C2.

[0186] In an exemplary embodiment, the second plate C22 of the second capacitor C2 is provided with a receiving opening K0. The orthographic projection of the receiving opening K0 on the substrate at least partially overlaps with the second connection portion CL2. The receiving opening K0 is configured to accommodate a subsequently formed thirteenth via. The orthographic projection of the thirteenth via on the substrate is within the range of the orthographic projection of the receiving opening K0 on the substrate, and exposes the surface of the second connection portion CL2, so that the second electrode of the subsequently formed second transistor T2 and the second electrode of the fourth transistor T4 are connected to the first plate C21 of the second capacitor C2 through the thirteenth via and the second connection portion CL2.

[0187] In an exemplary embodiment, in the same sub-pixel, in the second direction Y, the second plate C22 of the second capacitor C2 and the second plate C12 of the first capacitor C1 can be arranged sequentially. The second plate C22 of the second capacitor C2 can be connected to the second plate C12 of the first capacitor C1 through the third connecting part CL3. In an exemplary embodiment, the second plate C22 of the second capacitor C2, the third connecting part CL3, and the second plate C12 of the first capacitor C1 can be integrally formed.

[0188] In an exemplary embodiment, the first plate C11 of the first capacitor C1 can block the channel of the third body tube T3, thereby ensuring the electrical performance of the oxide third body tube T3.

[0189] In an exemplary embodiment, in the same row of circuit units, the second conductive layers in the two nearest pixel driving circuits of two adjacent circuit units can be mirror-symmetrical with respect to the first center line. For example, the second conductive layers in the N+2 column pixel driving circuit and the second conductive layers in the N+3 column pixel driving circuit can be symmetrical with respect to the first center line between the N+2 column pixel driving circuit and the N+3 column pixel driving circuit.

[0190] (105) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing a third insulating film and a second semiconductor film on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film using a patterning process to form a third insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the second insulating layer, as shown in Figures 11a and 11b. Figure 11a is a planar structural diagram of six sub-pixels after the formation of the second semiconductor layer, and Figure 11b is a planar schematic diagram of the semiconductor layer in Figure 11a.

[0191] In an exemplary embodiment, the second semiconductor layer pattern in at least some of the sub-pixels includes at least: the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, the active layer AT6 of the sixth transistor T6, and the active layer AT7 of the seventh transistor T7.

[0192] In an exemplary embodiment, within the same sub-pixel, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 can be interconnected. For example, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 can be an interconnected integral structure.

[0193] In an exemplary embodiment, within the same sub-pixel, in the first direction X, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT4 of the fourth transistor T4, and the active layer AT5 of the fifth transistor T5 can be located on the same side of the active layer AT3 of the third transistor T3; in the second direction Y, the active layers AT1 of the first transistor T1, AT2 of the second transistor T2, AT4 of the fourth transistor T4, AT5 of the fifth transistor T5, and AT3 of the third transistor T3 can be located away from the active layer AT6 of the sixth transistor T6. On one side of the active layer AT7 of transistor T7, the active layers AT1 of the first transistor T1, AT2 of the second transistor T2, AT4 of the fourth transistor T4, and AT6 of the sixth transistor T6 can be located between the active layers AT5 of the fifth transistor T5 and the active layer AT7 of the seventh transistor T7. The active layer AT2 of the second transistor T2 can be located between the active layers AT1 of the first transistor T1 and AT4 of the fourth transistor T4. The active layer AT3 of the third transistor T3 can be located on the side of the active layer AT1 of the first transistor T1 away from the active layer AT2 of the second transistor T2.

[0194] In an exemplary embodiment, taking the sub-pixel in the Mth row and Nth column as an example: In the first direction X, the active layer of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT4 of the fourth transistor T4, and the active layer AT5 of the fifth transistor T5 can be located on the side of the active layer AT3 of the third transistor T3 away from the N+1th column sub-pixel; In the second direction Y, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5, and the active layer AT3 of the third transistor T3 can be located on the side of the active layer AT3 of the sixth transistor T1. The active layer AT6 of transistor 6 is located on the side of the sub-pixel in row M-1. The active layer AT1 of the first transistor T1 and the active layer AT2 of the second transistor T2 are located on the side of the sub-pixel in row M+1. The active layer AT4 of the fourth transistor T4 is located on the side of the active layer AT2 of the second transistor T2, which is close to the sub-pixel in row M+1. The active layer AT5 of the fifth transistor T5 and the active layer AT3 of the third transistor T3 are located on the side of the active layer AT6 of the sixth transistor T6, which is far from the sub-pixel in row M+1. The active layer AT7 of the seventh transistor T7 is located on the side of the active layer AT6 of the sixth transistor T6, which is close to the sub-pixel in row M+1.

[0195] In an exemplary embodiment, the active layers AT1 of the first transistor T1, the active layers AT2 of the second transistor T2, the active layers AT4 of the fourth transistor T4, and the active layers AT6 of the sixth transistor T6 may be in an "I" shape or a strip shape, and the active layer AT3 of the third transistor T3 is in a "middle" shape, or a strip shape or a broken line shape extending along the second direction Y.

[0196] In an exemplary embodiment, the active layers of at least some of the transistors may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region AT11 of the active layer AT1 of the first transistor T1 may serve as the first region AT21 of the active layer AT2 of the second transistor T2, the second region AT22 of the active layer AT2 of the second transistor T2 may serve as the second region AT42 of the active layer AT4 of the fourth transistor T4, the second region AT62 of the active layer AT6 of the sixth transistor T6 may serve as the second region AT72 of the active layer AT7 of the seventh transistor T7, and the second region AT12 of the active layer AT1 of the first transistor T1, the first region AT31 and the second region AT32 of the active layer AT3 of the third transistor T3, the first region AT41 of the active layer AT4 of the fourth transistor T4, the first region AT61 of the active layer AT6 of the sixth transistor T6, and the first region AT71 of the active layer AT7 of the seventh transistor T7 may be provided independently.

[0197] In an exemplary embodiment, the second semiconductor layer may be made of an oxide, that is, the first transistor T1 to the fourth transistor T4, the sixth transistor T6 to the seventh transistor T7 are oxide thin film transistors. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride oxide (InGaZnON), zinc oxide (ZnO), zinc nitride oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfur oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementation manners, the semiconductor thin film may be made of indium gallium zinc oxide (IGZO), and the electron mobility of indium gallium zinc oxide (IGZO) is higher than that of amorphous silicon.

[0198] (106) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a fourth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a fourth insulating layer covering the second semiconductor layer; and a third conductive layer pattern disposed on the third insulating layer, as shown in Figures 12a and 12b. Figure 12a is a planar structural diagram of six sub-pixels after the formation of the third conductive layer, and Figure 12b is a planar schematic diagram of the third conductive layer in Figure 12a. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0199] In an exemplary embodiment, the third conductive layer pattern includes at least: a second reset control line Reset2, a second light emission control line EM2, a third reset control line Reset3, a control electrode T1g of the first transistor T1, a control electrode T3g of the third transistor T3, and a control electrode T4g of the fourth transistor T4.

[0200] In an exemplary embodiment, the second light-emitting control line EM2 can be a zigzag or strip shape extending along the first direction X of the main body. In the same sub-pixel row, in the second direction Y, the second reset control line Reset2 and the third reset control line Reset3 can be located on opposite sides of the second light-emitting control line EM2. The control electrode T3g of the third transistor T3 can be located on the side of the control electrode T1g of the first transistor T1 away from the third reset control line Reset3. The control electrode T4g of the fourth transistor T4 can be located between the second reset control line Reset2 and the third reset control line Reset3. In the first direction X, the control electrode T4g of the fourth transistor T4 and the control electrode T1g of the first transistor T1 can be located on the same side of the control electrode T3g of the third transistor T3. Taking the Mth row and Nth column sub-pixel as an example: in the second direction Y... In the first direction X, the control electrode T1g of the first transistor T1 can be located on the side of the third reset control line Reset3 away from the (M+1)th row sub-pixel, the control electrode T3g of the third transistor T3 can be located on the side of the first transistor T1's control electrode T1g away from the (M+1)th row sub-pixel, the control electrode T4g of the fourth transistor T4 can be located on the side of the third reset control line Reset3 close to the (M+1)th row sub-pixel, the second light emission control line EM2 can be located on the side of the fourth transistor T4's control electrode T4g close to the (M+1)th row sub-pixel, and the second reset control line Reset2 can be located on the side of the second light emission control line EM2 close to the (M+1)th row sub-pixel; in the first direction X, the control electrode T4g of the fourth transistor T4 and the control electrode T1g of the first transistor T1 can be located on the side of the third transistor T3's control electrode T3g close to the (N-1)th column sub-pixel.

[0201] In an exemplary embodiment, the region where the second light-emitting control line EM2 overlaps with the active layer AT6 of the sixth transistor T6 can serve as the control electrode T6g of the sixth transistor T6.

[0202] In an exemplary embodiment, the orthographic projection of the control electrode T1g of the first transistor T1 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate; the orthographic projection of the control electrode T3g of the third transistor T3 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT3 of the third transistor T3 onto the substrate; and the orthographic projection of the control electrode T4g of the fourth transistor T4 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT4 of the fourth transistor T4 onto the substrate.

[0203] In an exemplary embodiment, after the third conductive layer pattern is formed, the third conductive layer can be used as a shield to conduct the second semiconductor layer. The second semiconductor layer in the area shielded by the third conductive layer forms the channel regions of the first transistor T1 to the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7. The semiconductor layer in the area not shielded by the third conductive layer is conducted, that is, the first region and the second region of the active layer AT1 of the first transistor T1 to the active layer AT4 of the fourth transistor T4 and the active layer AT6 of the sixth transistor T6 are all conducted.

[0204] (107) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering a third conductive layer. The fifth insulating layer has a plurality of vias, as shown in FIG13, FIG13 being a planar structural diagram of six sub-pixels after the formation of the fifth insulating layer.

[0205] In an exemplary embodiment, at least some of the vias in the sub-pixels include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, and a twentieth via V20.

[0206] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The fifth and fourth insulating layers within the first via V1 are etched away, exposing the surface of the first region AT11 of the active layer AT1 of the first transistor T1 (which is also the surface of the first region AT21 of the active layer AT2 of the second transistor T2). The first via V1 is configured to connect the first electrode of the subsequently formed first transistor T1 to the active layer AT1 of the first transistor T1 through the via, and the first electrode of the subsequently formed second transistor T2 to the active layer AT2 of the second transistor T2 through the via.

[0207] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The fifth and fourth insulating layers within the second via V2 are etched away, exposing the surface of the second region AT12 of the active layer AT1 of the first transistor T1. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the active layer AT1 of the first transistor T1 through the via.

[0208] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate. The fifth and fourth insulating layers within the third via V3 are etched away, exposing the surface of the second region AT22 of the active layer AT2 of the second transistor T2 (which is also the second region AT42 of the active layer AT4 of the fourth transistor T4). The third via V3 is configured to connect the second electrode of the subsequently formed second transistor T2 to the active layer AT2 of the second transistor T2 through the via, and to connect the second electrode of the subsequently formed fourth transistor T4 to the active layer AT4 of the fourth transistor T4 through the via.

[0209] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the active layer AT3 of the third transistor T3 onto the substrate. The fifth and fourth insulating layers within the fifth via V5 are etched away, exposing the surface of the first region AT31 of the active layer AT3 of the third transistor T3. The fifth via V5 is configured to allow the first electrode of the subsequently formed third transistor T3 to be connected to the active layer AT3 of the third transistor T3 through this via.

[0210] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the substrate lies within the orthogonal projection of the active layer AT3 of the third transistor T3 onto the substrate. The fifth insulating layer and the fourth insulating layer within the fifth via V5 are etched away, exposing the surface of the second region AT32 of the active layer AT3 of the third transistor T3. The fifth via V5 is configured to allow the second electrode of the subsequently formed third transistor T3 to be connected to the active layer AT3 of the third transistor T3 through the via.

[0211] In an exemplary embodiment, the orthogonal projection of the sixth via V6 onto the substrate lies within the orthogonal projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The fifth and fourth insulating layers within the sixth via V6 are etched away, exposing the surface of the first region AT41 of the active layer AT4 of the fourth transistor T4. The sixth via V6 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the active layer AT4 of the fourth transistor T4 through this via.

[0212] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The fifth and fourth insulating layers within the seventh via V7 are etched away, exposing the surface of the second region AT42 of the active layer AT4 of the fourth transistor T4. The seventh via V7 is configured to allow the second electrode of the subsequently formed fourth transistor T4 to be connected to the active layer AT4 of the fourth transistor T4 through this via.

[0213] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the substrate lies within the orthogonal projection of the active layer AT5 of the fifth transistor T5 onto the substrate. The fifth, fourth, third, second, and first insulating layers within the seventh via V7 are etched away, exposing the surface of the first region AT51 of the active layer AT5 of the fifth transistor T5. The seventh via V7 is configured to allow the second electrode of the subsequently formed fifth transistor T5 to be connected to the active layer AT5 of the fifth transistor T5 through this via.

[0214] In an exemplary embodiment, the orthogonal projection of the eighth via V8 onto the substrate lies within the orthogonal projection of the active layer AT5 of the fifth transistor T5 onto the substrate. The fifth, fourth, third, second, and first insulating layers within the eighth via V8 are etched away, exposing the surface of the second region AT52 of the active layer AT5 of the fifth transistor T5. The eighth via V8 is configured to allow the second electrode of the subsequently formed fifth transistor T5 to be connected to the active layer AT5 of the fifth transistor T5 through this via.

[0215] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the substrate lies within the orthogonal projection of the active layer AT6 of the sixth transistor T6 onto the substrate. The fifth and fourth insulating layers within the ninth via V9 are etched away, exposing the surface of the first region AT61 of the active layer AT6 of the sixth transistor T6. The ninth via V9 is configured to allow the first electrode of the subsequently formed sixth transistor T6 to be connected to the active layer AT6 of the sixth transistor T6 through this via.

[0216] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate lies within the orthographic projection of the active layer AT6 of the sixth transistor T6 onto the substrate. The fifth and fourth insulating layers within the tenth via V10 are etched away, exposing the surface of the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT72 of the active layer AT7 of the seventh transistor T7). The tenth via V10 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer AT6 of the sixth transistor T6 through the via, and to connect the second electrode of the subsequently formed seventh transistor T7 to the active layer AT7 of the seventh transistor T7 through the via.

[0217] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the orthographic projection of the active layer AT7 of the seventh transistor T7 onto the substrate. The fifth and fourth insulating layers within the eleventh via V11 are etched away, exposing the surface of the second region AT72 of the active layer AT7 of the seventh transistor T7. The eleventh via V11 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the active layer AT7 of the seventh transistor T7 through the via.

[0218] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the range of the orthographic projection of the first electrode C11 of the first capacitor C1 onto the substrate (the orthographic projection of the fourteenth via V14 onto the substrate may be within the range of the orthographic projection of the first connecting portion CL1 onto the substrate). The fifth, fourth, third, and second insulating layers within the fourteenth via V14 are etched away, exposing the surface of the first electrode C11 of the first capacitor C1. The fourteenth via V14 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the first electrode C11 of the first capacitor C1 through this via.

[0219] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate lies within the range of the orthographic projection of the first electrode C21 of the second capacitor C2 onto the substrate (the orthographic projection of the thirteenth via V13 onto the substrate may lie within the range of the orthographic projection of the second connection CL2 onto the substrate). The fifth, fourth, third, and second insulating layers within the thirteenth via V13 are etched away, exposing the surface of the first electrode C21 of the second capacitor C2. The thirteenth via V13 is configured to allow the second electrode of the subsequently formed second transistor T2 and the second electrode of the fourth transistor T4 to be connected to the first electrode C21 of the second capacitor C2 through this via.

[0220] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate lies within the range of the orthographic projection of the first second initial signal line Vinit2-B onto the substrate. The fifth, fourth, third, and second insulating layers within the fourteenth via V14 are etched away, exposing the surface of the first second initial signal line Vinit2-B. The fourteenth via V14 is configured to connect the first electrode of the seventh transistor T7 in the subsequently formed first sub-pixel to the first second initial signal line Vinit2-B through this via. In an exemplary embodiment, the fourteenth via V14 may be disposed in the first sub-pixel, while the second and third sub-pixels may not have the fourteenth via V14 disposed therein.

[0221] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the orthographic projection of the second electrode C12 of the first capacitor C1 onto the substrate. The fifth, fourth, and third insulating layers within the fifteenth via V15 are etched away, exposing the surface of the second electrode C12 of the first capacitor C1. The fifteenth via V15 is configured to allow the second electrode of the subsequently formed third transistor T3 to be connected to the second electrode C12 of the first capacitor C1 through this via.

[0222] In an exemplary embodiment, the orthogonal projection of the sixteenth via V16 onto the substrate lies within the orthogonal projection of the second electrode C22 of the second capacitor C2 onto the substrate. The fifth, fourth, and third insulating layers within the sixteenth via V16 are etched away, exposing the surface of the second electrode C22 of the second capacitor C2. The sixteenth via V16 is configured to allow the first electrode of the subsequently formed sixth transistor T6 to be connected to the second electrode C22 of the second capacitor C2 through this via.

[0223] In an exemplary embodiment, the orthogonal projection of the seventeenth via V17 onto the substrate lies within the orthogonal projection of the control electrode T1g of the first transistor T1 onto the substrate. The fifth insulating layer within the seventeenth via V17 is etched away, exposing the surface of the control electrode T1g of the first transistor T1. The seventeenth via V17 is configured to allow the subsequently formed first reset control line Reset1 to be connected to the control electrode T1g of the first transistor T1 through this via.

[0224] In an exemplary embodiment, the orthogonal projection of the eighteenth via V18 onto the substrate lies within the orthogonal projection of the control electrode T4g of the fourth transistor T4 onto the substrate. The fifth insulating layer within the eighteenth via V18 is etched away, exposing the surface of the control electrode T4g of the fourth transistor T4. The eighteenth via V18 is configured to allow the subsequently formed scan control line Gate to be connected to the control electrode T4g of the fourth transistor T4 through this via.

[0225] In an exemplary embodiment, the orthogonal projection of the nineteenth via V19 onto the substrate lies within the orthogonal projection of the control electrode T5g of the fifth transistor T5 onto the substrate. The fifth, fourth, third, and second insulating layers within the nineteenth via V19 are etched away, exposing the surface of the control electrode T5g of the fifth transistor T5. The nineteenth via V19 is configured to allow the subsequently formed first light-emitting control line EM1 to connect to the control electrode T5g of the fifth transistor T5 through this via.

[0226] In an exemplary embodiment, the orthogonal projection of the twentieth via V20 onto the substrate lies within the orthogonal projection of the control electrode T3g of the third transistor T3 onto the substrate. The fifth insulating layer within the twentieth via V20 is etched away, exposing the surface of the control electrode T3g of the third transistor T3. The twentieth via V20 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the control electrode T3g of the third transistor T3 through the via.

[0227] (108) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on a fifth insulating layer, as shown in Figures 14a and 14b. Figure 14a is a planar structural diagram of six sub-pixels after the formation of the fourth conductive layer, and Figure 14b is a planar schematic diagram of the fourth conductive layer in Figure 14a. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0228] In an exemplary embodiment, the fourth conductive layer includes at least: a second initial signal line Vinit2-RG, a scan control line Gate, a second power connection line VSSL, a first initial signal line Vinit1, a first reset control line Reset1, a first light emission control line EM1, a first power connection line VDDL, a first connection electrode L1, a second connection electrode L2, a third connection electrode L3, a fourth connection electrode L4, a fifth connection electrode L5, a sixth connection electrode L6, a seventh connection electrode L7, and an eighth connection electrode L8.

[0229] In an exemplary embodiment, the main body of the second initial signal line Vinit2-RG, the scan control line Gate, the second power connection line VSSL, the first initial signal line Vinit1, the first reset control line Reset1, the first light emission control line EM1, and the first power connection line VDDL can be a strip-shaped structure or a zigzag structure extending along the first direction X. In the same row of sub-pixels, the two types of second initial signal lines Vinit2-RG, the scan control line Gate, the second power connection line VSSL, the first initial signal line Vinit1, the first reset control line Reset1, the first light emission control line EM1, and the first power connection line VDDL can be arranged sequentially at intervals along the second direction Y.

[0230] In an exemplary embodiment, within the same sub-pixel, in the second direction Y, the first connecting electrode L1, the third connecting electrode L3, and the sixth connecting electrode L6 may be located between the first reset control line Reset1 and the first light emission control line EM1, the first connecting electrode L1 may be located between the third connecting electrode L3 and the sixth connecting electrode L6, and the third connecting electrode L3 may be located between the first connecting electrode L1 and the first reset control line Reset1; the second connecting electrode L2, the fourth connecting electrode L4, the seventh connecting electrode L7, and the eighth connecting electrode L8 may be located between the scan control line Gate and the second type of second initial signal line Vinit2-RG, and the fourth connecting electrode L4 and the seventh connecting electrode L7 may be located on the side of the second connecting electrode L2 and the eighth connecting electrode L8 away from the second type of second initial signal line Vinit2-RG; the fifth connecting electrode L5 may be located between the scan control line Gate and the second power connection line VSSL; in the first direction X, the fourth connecting electrode L4 and the eighth connecting electrode L8 may be located on the same side of the second connecting electrode L2, the third connecting electrode L3, and the seventh connecting electrode L7.

[0231] In an exemplary embodiment, the second initial signal line Vinit2-RG can be connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 located in the second and third sub-pixels of a row of sub-pixels via the eleventh via V1 in the second and third sub-pixels of that row, thereby providing a second initial signal to the seventh transistor T7 of the second and third sub-pixels in that row of sub-pixels. In an exemplary embodiment, the second initial signal line Vinit2-RG can serve as the first electrode of the second transistor T2 in the second and third sub-pixels.

[0232] In an exemplary embodiment, the scan control line Gate can be connected to the control electrode T4g of the fourth transistor T4 in a row of sub-pixels through the eighteenth via V18 in that row of sub-pixels, and is configured to provide scan signals to the control electrodes T4g of the plurality of fourth transistors T4 in that row of sub-pixels.

[0233] In an exemplary embodiment, the main body of the second power connection line VSSL can extend along the first direction X, and multiple second power connection lines VSSL are arranged at intervals along the second direction Y. These multiple second power connection lines VSSL are interconnected with subsequently formed multiple second power lines to form a grid structure, which can reduce the voltage drop of the second power lines and improve display uniformity. In an exemplary embodiment, the second power connection line VSSL is provided with multiple blocking structures ZD. The blocking structures ZD can be located in the first sub-pixel, and the orthographic projection of the blocking structure ZD on the substrate at least partially overlaps with the orthographic projection of the second capacitor on the substrate. The blocking structure ZD can be a strip structure or a zigzag structure extending along the second direction Y. In the same first sub-pixel, in the second direction Y, the blocking structure ZD can be located on the side of the second power connection line VSSL closer to the scan control line Gate.

[0234] In an exemplary embodiment, the first initial signal line Vinit1 can be connected to the first region AT11 of the active layer AT1 of the first transistor T1 in that row of sub-pixels (which is also the first region AT21 of the active layer AT2 of the second transistor T2) via a first via V1 in that row of sub-pixels, thus providing a first initial signal to the first transistor T1 and the second transistor T2 in that row of sub-pixels. In an exemplary embodiment, the first initial signal line Vinit1 can serve as the first electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0235] In an exemplary embodiment, the first reset control line Reset1 can be connected to the control electrode T1g of the first transistor T1 in a row of sub-pixels through the seventeenth via V17 in that row of sub-pixels, and is configured to provide a first reset control signal to the control electrodes T1g of the plurality of first transistors T1 in that row of sub-pixels.

[0236] In an exemplary embodiment, the first light-emitting control line EM1 can be connected to the control electrode T5g of the fifth transistor T5 in the row of sub-pixels through the nineteenth via V19 in the row of sub-pixels, and is configured to provide light-emitting control signals to the control electrodes T5g of the plurality of fifth transistors T5 in the row of sub-pixels.

[0237] In an exemplary embodiment, the first power connection line VDDL can be connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 in that row of sub-pixels via the seventh via V7 in that row of sub-pixels, thereby providing a first power signal to the active layer AT5 of the plurality of fifth transistors T5 in that row of sub-pixels. In an exemplary embodiment, the first power connection line VDDL can serve as the first electrode of the fifth transistor T5.

[0238] In an exemplary embodiment, the first connecting electrode L1 is approximately L-shaped, rotated 90° clockwise. The first connecting electrode L1 can be connected to the second region AT12 of the active layer AT1 of the first transistor T1 via the second via V2, to the first electrode C11 (the first connection portion CL1 on the first electrode C11 of the first capacitor C1) via the twelfth via V12, and to the control electrode T3g of the third transistor T3 via the twentieth via V20. The second region AT12 of the active layer AT1 of the first transistor T1, the first electrode C11 of the first capacitor C1, and the control electrode T3g of the third transistor T3 can be electrically connected via the first connecting electrode L1, so that the second electrode of the first transistor T1, the first electrode C11 of the first capacitor C1, and the control electrode T3g of the third transistor T3 in the same sub-pixel have the same potential. In an exemplary embodiment, the first connecting electrode L1 can serve as the second electrode of the first transistor T1.

[0239] In an exemplary embodiment, the second connection electrode L2 is generally shaped as a strip or a broken line extending along the first direction X. The second connection electrode L2 can be connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT72 of the active layer AT7 of the seventh transistor T7) through the tenth via V10. In an exemplary embodiment, the second connection electrode L2 can serve as the second electrode of both the sixth transistor T6 and the seventh transistor T7. The second connection electrode L2 is configured to be connected to the anode connection electrode of a subsequently formed light-emitting element.

[0240] In an exemplary embodiment, the third connecting electrode L3 is generally a strip-shaped structure or a zigzag structure extending along the first direction X. The third connecting electrode L3 can be connected to the second region AT32 of the active layer AT3 of the third transistor T3 through the fifth via V5, and to the second electrode C12 of the first capacitor C1 through the fifteenth via V15, so that the second region AT32 of the active layer AT3 of the third transistor T3 and the second electrode C12 of the first capacitor C1 in the same sub-pixel have the same potential. In an exemplary embodiment, the third connecting electrode L3 can serve as the second electrode of the third transistor T3.

[0241] In an exemplary embodiment, the fourth connection electrode L4 is generally a block structure or a strip structure or a zigzag structure extending along the first direction X. The fourth connection electrode L4 can be connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the sixth via V6. In an exemplary embodiment, the first connection electrode L1 can serve as the first electrode of the fourth transistor T4 and is configured to be connected to the subsequently formed data signal line.

[0242] In an exemplary embodiment, the fifth connecting electrode L5 is generally a strip-shaped structure or a zigzag structure extending along the first direction X. The fifth connecting electrode L5 can be connected to the second region AT42 of the active layer AT4 of the fourth transistor T4 (which is also the second region AT22 of the active layer AT2 of the second transistor T2) through the third via V3, and to the first electrode C21 of the second capacitor C2 (the second connecting portion CL2 on the first electrode C21 of the second capacitor C2) through the thirteenth via V13, so that the second region AT22 of the active layer AT2 of the second transistor T2, the first electrode C21 of the second capacitor C2, and the second region AT42 of the active layer AT4 of the fourth transistor T4 in the same sub-pixel have the same potential. In an exemplary embodiment, the fifth connecting electrode L5 can serve as the second electrode of both the second transistor T2 and the fourth transistor T4.

[0243] In an exemplary embodiment, the sixth connecting electrode L6 is generally strip-shaped or zigzag-shaped extending along the first direction X. The sixth connecting electrode L6 can be connected to the second region AT52 of the active layer AT5 of the fifth transistor T5 in that row of sub-pixels via the eighth via V8, and to the first region AT31 of the active layer AT3 of the third transistor T3 in that row of sub-pixels via the fourth via V4. In an exemplary embodiment, the sixth connecting electrode L6 can serve as the second electrode of the fifth transistor T5. In the same sub-pixel, the second region AT52 of the active layer AT5 of the fifth transistor T5 and the first region AT31 of the active layer AT3 of the third transistor T3 can be electrically connected via the sixth connecting electrode L6, so that the second region AT52 of the active layer AT5 of the fifth transistor T5 and the first region AT31 of the active layer AT3 of the third transistor T3 in the same sub-pixel have the same potential.

[0244] In an exemplary embodiment, the seventh connection electrode L7 can be a strip structure or a zigzag structure extending along the first direction X. The seventh connection electrode L7 can be connected to the first region AT61 of the active layer AT6 of the sixth transistor T6 through the ninth via V9, and to the second electrode C22 of the second capacitor C2 through the sixteenth via V16. In an exemplary embodiment, the seventh connection electrode L7 can serve as the first electrode of the sixth transistor T6. In the same sub-pixel, the first region AT61 of the active layer AT6 of the sixth transistor T6 and the second plate C22 of the second capacitor C2 can be electrically connected through the seventh connecting electrode L7, so that the first region AT61 of the active layer AT6 of the sixth transistor T6 and the second plate C22 of the second capacitor C2 in the same sub-pixel have the same potential. Since the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are connected through the third connecting part CL3, and the second plate C12 of the first capacitor C1 is connected to the second region AT32 of the active layer AT3 of the third transistor T3 through the third connecting electrode L3, the second plate C12 of the first capacitor C1, the second plate C22 of the second capacitor C2, the second region AT32 of the active layer AT3 of the third transistor T3, and the first region AT61 of the active layer AT6 of the sixth transistor T6 have the same potential.

[0245] In an exemplary embodiment, the eighth connection electrode L8 is generally strip-shaped or zigzag-shaped extending along the first direction X. The eighth connection electrode L8 can be connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 in the first sub-pixel through an eleventh via V11 located in the first sub-pixel of a row of sub-pixels, and to the first type of second initial signal line Vinit2-B in the first sub-pixel of the row of sub-pixels through a fourteenth via V14 located in the first sub-pixel of the row of sub-pixels. In an exemplary embodiment, the eighth connection electrode L8 can serve as the first electrode of the seventh transistor T7 in the first sub-pixel. In an exemplary embodiment, the eighth connection electrode L8 is located in the first sub-pixel, while the second and third sub-pixels do not have the eighth connection electrode L8.

[0246] (109) Forming a sixth insulating layer and a first planarization layer pattern. In an exemplary embodiment, forming a sixth insulating layer and a first planarization layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and patterning the first planarization film and the sixth insulating film using a patterning process to form a sixth insulating layer covering the fourth conductive layer pattern and a first planarization layer disposed on the sixth insulating layer. A plurality of vias are provided on the sixth insulating layer and the first planarization layer, as shown in FIG15. FIG15 is a planar structural diagram of six sub-pixels after the formation of the first planarization layer.

[0247] In an exemplary embodiment, the plurality of vias on the sixth insulating layer and the first planarization layer may include at least: a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, and a twenty-sixth via V26.

[0248] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 onto the substrate lies within the range of the orthographic projection of the first power connection line VDDL onto the substrate. The first planarization layer and the sixth insulating layer within the twenty-first via V21 are etched away, exposing the surface of the first power connection line VDDL. The twenty-first via V21 is configured to allow a subsequently formed first power line to be electrically connected to the first power connection line VDDL through this via. In an exemplary embodiment, the twenty-first via V21 may be disposed in the second sub-pixel and the third sub-pixel.

[0249] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate lies within the range of the orthographic projection of the second power connection line VSSL onto the substrate. The first planarization layer and the sixth insulating layer within the 22nd via V22 are etched away, exposing the surface of the second power connection line VSSL. The 22nd via V22 is configured to allow a subsequently formed second power line to be electrically connected to the second power connection line VSSL through this via. In an exemplary embodiment, the 22nd via V22 may be disposed in the first sub-pixel and the second sub-pixel. In an exemplary embodiment, the 22nd via V22 may serve as the aforementioned second power via KVSS.

[0250] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 onto the substrate lies within the range of the orthographic projection of the first initial signal line Vinit1 onto the substrate. The first planarization layer and the sixth insulating layer within the twenty-third via V23 are etched away, exposing the surface of the first initial signal line Vinit1. The twenty-third via V23 is configured to allow a subsequently formed first initial signal connection line to be electrically connected to the first initial signal line Vinit1 through this via. In an exemplary embodiment, the twenty-third via V23 may be disposed between the second sub-pixel and the third sub-pixel.

[0251] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate lies within the range of the orthographic projection of the second initial signal line Vinit2-RG onto the substrate. The first planarization layer and the sixth insulating layer within the 24th via V24 are etched away, exposing the surface of the second initial signal line Vinit2-RG. The 24th via V24 is configured to allow a subsequently formed second initial signal connection line to be electrically connected to the second initial signal line Vinit2-RG through this via. In an exemplary embodiment, the 24th via V24 may be disposed in a third sub-pixel.

[0252] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate lies within the range of the orthographic projection of the eighth connecting electrode L8 onto the substrate. The first planarization layer and the sixth insulating layer within the 25th via V25 are etched away, exposing the surface of the eighth connecting electrode L8. The 25th via V25 is configured to allow a subsequently formed first type second initial signal connection line to be electrically connected to the first type second initial signal line Vinit2-B through this via. In an exemplary embodiment, the 25th via V25 may be disposed within the first sub-pixel.

[0253] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate lies within the range of the orthographic projection of the second connecting electrode L2 onto the substrate. The first planarization layer and the sixth insulating layer within the 26th via V26 are etched away, exposing the surface of the second connecting electrode L2. The 26th via V26 is configured to electrically connect the anode connecting electrode of a subsequently formed light-emitting element to the second connecting electrode L2 through this via. In an exemplary embodiment, the 26th via V26 can serve as the aforementioned first anode via KAN1.

[0254] (110) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on a first planarization layer, as shown in Figures 16a and 16b. Figure 16a is a planar structural diagram of six sub-pixels after the formation of the fifth conductive layer, and Figure 16b is a planar schematic diagram of the fifth conductive layer in Figure 16a. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0255] In an exemplary embodiment, the fifth conductive layer includes at least: a data signal line DL, a first power line VDD, a second power line VSS, an anode connection electrode ZL, a first initial signal connection line Vinit1L, a first type of second initial signal connection line Vinit2L-B, and a second type of second initial signal connection line Vinit2L-RG.

[0256] In an exemplary embodiment, the data signal line DL is a zigzag or strip-shaped portion extending along the second direction Y. The data signal line DL is connected to the fourth connection electrode L4 through the twenty-first via V21. Since the fourth connection electrode L4 is connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the via, the connection between the data signal line DL and the first electrode of the fourth transistor T4 is realized, and the data signal is written to the fourth transistor T4. In an exemplary embodiment, in the same pixel unit, the orthographic projection of at least a portion of the occlusion structure ZD in the first sub-pixel onto the substrate is located between the orthographic projection of the second capacitor in the first sub-pixel onto the substrate and the orthographic projection of the data signal line DL in the second sub-pixel onto the substrate. This can shield the signal interference of the data signal line DL in the second sub-pixel to the second capacitor C2 in the first sub-pixel to a certain extent, thereby reducing signal crosstalk and improving the display effect.

[0257] In an exemplary embodiment, the first power line VDD is a zigzag or strip-shaped portion extending along the second direction Y. The first power line VDD is connected to the first power connection line VDDL through the twenty-first via V21. Since the first power connection line VDDL is connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 through the via, the connection between the first power line VDD and the fifth transistor T5 is realized, and the power signal is written to the first terminal of the fifth transistor T5.

[0258] In an exemplary embodiment, the anode connection electrode ZL can be in the shape of an "I" or a strip structure or a zigzag structure extending along the second direction Y. The anode connection electrode ZL can be connected to the second connection electrode L2 through the twenty-sixth via V26. Since the second connection electrode L2 is connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT72 of the active layer AT7 of the seventh transistor T7) through the via, the connection between the anode connection electrode ZL and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 is realized.

[0259] In an exemplary embodiment, the first initial signal connection line Vinit1L can be a zigzag or strip shape extending along the second direction Y of the main body. The first initial signal connection line Vinit1L can be connected to the first initial signal line Vinit1 through the twenty-third via V23. Since the first initial signal line Vinit1 is connected to the first region AT11 of the active layer AT1 of the first transistor T1 and the first region AT21 of the active layer AT2 of the second transistor T2 through the via, the connection between the first initial signal connection line Vinit1L and the first region AT11 of the active layer AT1 of the first transistor T1 and the first region AT21 of the active layer AT2 of the second transistor T2 is realized, and the initial signal is written into the first region AT11 of the active layer AT1 of the first transistor T1 and the first region AT21 of the active layer AT2 of the second transistor T2. Multiple first initial signal connection lines Vinit1L and multiple first initial signal lines Vinit1 are interconnected to form a grid structure, so that the first initial signals received by adjacent first transistors T1 and second transistors T2 are basically consistent, which helps to improve the uniformity of panel display, avoid display defects of display substrate, and ensure the display effect of display substrate.

[0260] In an exemplary embodiment, the first type of second initial signal connection line Vinit2L-B can be a zigzag or strip shape extending along the second direction Y of the main body. The first type of second initial signal connection line Vinit2L-B can be connected to the eighth connection electrode L8 in the first sub-pixel through the twenty-fifth via V25. Since the eighth connection electrode L8 is connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 in the first sub-pixel and the first type of second initial signal line Vinit2-B through the via, the connection between the first type of second initial signal connection line Vinit2L-B and the first region AT71 of the active layer AT7 of the seventh transistor T7 in the first sub-pixel and the first type of second initial signal line Vinit2-B is realized. Multiple first type of second initial signal connection lines Vinit2L-B interconnect to form a grid structure, ensuring that the second initial signals received by the seventh transistor T7 in adjacent first sub-pixels are essentially consistent. This is beneficial for improving the uniformity of the panel display, avoiding display defects in the display substrate, and ensuring the display effect of the display substrate.

[0261] In an exemplary embodiment, the second type of second initial signal connection line Vinit2L-RG can be a zigzag or strip shape extending along the second direction Y of the main body. The second type of second initial signal connection line Vinit2L-RG can be connected to the second type of second initial signal line Vinit2-RG through the twenty-fourth via V24. Since the second type of second initial signal line Vinit2-RG is connected to the first region AT1 of the active layer AT7 of the seventh transistor T7 in the second and third sub-pixels through the via, the connection between the second type of second initial signal connection line Vinit2L-RG and the first region AT71 of the active layer AT7 of the seventh transistor T7 in the second and third sub-pixels is realized, and the initial signal is written into the first region AT71 of the active layer AT7 of the seventh transistor T7 in the second and third sub-pixels. Multiple second-type second initial signal connection lines Vinit2L-RG are interconnected to form a grid structure, which makes the second initial signals received by the seventh transistor T7 in adjacent second and third sub-pixels basically consistent. This helps to improve the uniformity of the panel display, avoid display defects in the display substrate, and ensure the display effect of the display substrate.

[0262] In an exemplary embodiment, within the same pixel unit, in the first direction X, the first initial signal connection line Vinit1L can be located between the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel, and the signal lines closest to both sides of the first initial signal connection line Vinit1L are the first power line VDD. The pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel are respectively provided with a first power line VDD, and the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel are respectively provided with a second power line VSS. The second type of second initial signal connection line Vinit2L-RG can be located in the pixel driving circuit of the third sub-pixel, and the first type of second initial signal connection line Vinit2L-B can be located in the pixel driving circuit of the first sub-pixel.

[0263] In an exemplary embodiment, within the same pixel unit, in a first direction: the pixel driving circuit of the first sub-pixel, the pixel driving circuit of the second sub-pixel, and the pixel driving circuit of the third sub-pixel are arranged sequentially. In the first sub-pixel, the data signal line DL, the first type of second initial signal connection line Vinit2L-B, and the second power line VSS can be arranged sequentially at intervals along the first direction X, and the anode connection electrode ZL can be located on the side of the second power line VSS away from the first type of second initial signal connection line Vinit2L-B. In the second sub-pixel, the data signal line DL, the second power line VSS, and the first power line VDD can be arranged sequentially at intervals along the first direction X, and the anode connection electrode ZL can be located between the second power line VSS and the first power line VDD. In the third sub-pixel, the first power line VDD and the second type of second initial signal connection line Vinit2L-RG can be arranged sequentially at intervals along the first direction X, and the anode connection electrode ZL can be located between the second type of second initial signal connection line Vinit2L-RG and the first power line VDD.

[0264] Thus, the driving circuit layer is fabricated on the substrate. The driving circuit layer has pixel driving circuits for multiple sub-pixels. Figures 8 to 16b show schematic diagrams of the planar structure of the pixel driving circuits for sub-pixels in the display substrate. In an exemplary embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer may include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate.

[0265] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, and a first planarization layer. The first insulating layer is disposed between the first semiconductor layer and the first conductive layer, the second insulating layer is disposed between the first conductive layer and the second conductive layer, the third insulating layer is disposed between the second conductive layer and the second semiconductor layer, the fourth insulating layer is disposed between the second semiconductor layer and the third conductive layer, the fifth insulating layer is disposed between the third conductive layer and the fourth conductive layer, and the sixth insulating layer and the first planarization layer are disposed between the fourth conductive layer and the fifth conductive layer.

[0266] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations: forming a second planarization layer pattern, wherein at least an anode via is provided on the second planarization layer; forming an anode pattern (i.e., an anode conductive layer), wherein the anode is connected to the anode connecting electrode through the anode via; forming an anode pixel definition layer, wherein a pixel opening is provided on the pixel definition layer, and the pixel opening exposes the anode; forming an organic light-emitting layer using a vapor deposition or inkjet printing process, wherein a cathode is formed on the organic light-emitting layer; and forming an encapsulation layer, wherein the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, wherein the first and third encapsulation layers may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer. The steps for fabricating the light-emitting structure layer are as follows:

[0267] (111) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form a second planarization layer covering the pattern of the fifth conductive layer. The second planarization layer is provided with a plurality of vias, as shown in FIG17, FIG17 being a planar structural diagram of six sub-pixels after the formation of the second planarization layer.

[0268] In an exemplary embodiment, the plurality of vias may include at least: a twenty-seventh via V27.

[0269] In an exemplary embodiment, each sub-pixel's via includes at least a twenty-seventh via V27. The orthographic projection of the twenty-seventh via V27 onto the substrate lies within the range of the orthographic projection of the anode connection electrode ZL onto the substrate. The second planarization layer within the twenty-seventh via V27 is removed, exposing the surface of the anode connection electrode ZL. The twenty-seventh via V27 is configured to allow a subsequently formed anode to be electrically connected to the anode connection electrode ZL through the via.

[0270] In an exemplary embodiment, the twenty-seventh via V27 can serve as the aforementioned second anode via KAN2.

[0271] (112) Forming an anode conductive layer pattern. In an exemplary embodiment, forming an anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on a second planarization layer, as shown in Figures 18a to 18b. Figure 18a is a planar structural schematic diagram of six sub-pixels after the anode conductive layer is formed, and Figure 18b is a planar schematic diagram of the anode conductive layer in Figure 18a.

[0272] In an exemplary embodiment, the anode conductive layer pattern may include at least a plurality of anodes AN, which may include: a first anode AN1, a second anode AN2 and a third anode AN3. The area where the first anode AN1 is located may form a blue light-emitting unit that emits blue light, the area where the second anode AN2 is located may form a green light-emitting unit that emits green light, and the area where the third anode AN3 is located may form a red light-emitting unit that emits red light.

[0273] In an exemplary embodiment, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the anode connection electrode ZL in the corresponding sub-pixel through the twenty-seventh via V27. Since the anode connection electrode ZL in the sub-pixel is electrically connected to the second electrode of the sixth transistor T6 (which is also the second electrode of the seventh transistor T7) through the via, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through the anode connection electrode ZL, respectively, thereby enabling the pixel driving circuit to drive the light-emitting device to emit light.

[0274] In an exemplary embodiment, the anode AN may include an anode body portion AN01 and an anode connecting portion AN02. The anode body portion AN01 may be a rectangular structure. One end of the anode connecting portion AN02 is connected to the anode body portion AN01, and the other end is electrically connected to the anode connecting electrode ZL through a twenty-seventh via V27. The anode connecting portion AN02 may be a strip-shaped structure or a block-shaped structure extending along a first direction X or a second direction Y. The anode connecting portion AN02 may be configured to compensate for the differences in parasitic capacitance between multiple sub-pixels caused by signal traces. By setting the anode connecting portion AN02, the parasitic capacitance of multiple sub-pixels can be kept basically consistent, thereby improving the display uniformity of the display substrate.

[0275] (113) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: depositing a pixel definition layer film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition layer using a patterning process to form a pixel definition layer pattern disposed on an anode conductive layer, as shown in Figures 19a and 19b. Figure 19a is a schematic diagram of the planar structure of six sub-pixels after the pixel definition layer is formed, and Figure 19b is a schematic diagram of the planar structure of the pixel definition layer in Figure 19a.

[0276] In an exemplary embodiment, the pixel definition layer pattern may include multiple pixel openings K, each exposing an anode AN. In an exemplary embodiment, the orthographic projection of a pixel opening K onto the substrate lies within the range of the orthographic projection of the anode AN onto the substrate. In an exemplary embodiment, the pixel opening K may include a first sub-pixel pixel opening K01, a second sub-pixel pixel opening K02, and a third sub-pixel pixel opening K03. The orthographic projection of the first sub-pixel pixel opening K01 onto the substrate overlaps with the orthographic projection of the first anode AN1 onto the substrate; the orthographic projection of the second sub-pixel pixel opening K02 onto the substrate overlaps with the orthographic projection of the second anode AN2 onto the substrate; and the orthographic projection of the third sub-pixel pixel opening K03 onto the substrate overlaps with the orthographic projection of the third anode AN3 onto the substrate.

[0277] In an exemplary embodiment, the first conductive layer, second conductive layer, third conductive layer, fourth conductive layer, and fifth conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, and fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers.

[0278] In an exemplary embodiment, taking six sub-pixels (one sub-pixel row, six sub-pixel columns, and the pixel driving circuit adopts the 7T2C structure shown in Figure 4) in the display area (AA) as an example, the fabrication process of another display substrate can be the same as steps (101) to (113) above, with the following differences:

[0279] The fifth conductive layer formed in step (110) above can be shown in Figures 20a to 20d. Figure 20a is a planar structure diagram of the six sub-pixels after the formation of the fifth conductive layer. Figures 20b to 20d are schematic diagrams of the structure of the fifth conductive layer in Figure 20a. The difference between the fifth conductive layer shown in Figure 20b and the fifth conductive layer shown in Figure 16b is that: in the pattern of the fifth conductive layer shown in Figure 20b, at least some of the signal traces corresponding to the pixel opening K in the fifth conductive layer are set with a hollow structure. That is, the signal traces in the overlapping area of ​​the fifth conductive layer with the pixel opening are uniformly arranged strip structures (slit-shaped), so that the signal traces in the area of ​​the pixel opening K are roughly uniformly arranged, which can reduce asymmetric color shift. At the edge of the display area, the same signal line can be connected to each other. As shown in Figure 20c, the fifth conductive layer in the first row of sub-pixels is connected to each other at the edge of the display area. As shown in Figure 20d, the fifth conductive layer in the last row of sub-pixels is connected to each other at the edge of the display area. The structure after forming the second planarization layer, the anode conductive layer, and the pixel definition layer in sequence based on Figure 20a is shown in Figure 21a. The structure after forming the second planarization layer, the anode conductive layer, and the pixel definition layer in sequence based on the fifth conductive layer shown in Figure 20c is shown in Figure 21b. The structure after forming the second planarization layer, the anode conductive layer, and the pixel definition layer in sequence based on the fifth conductive layer shown in Figure 20d is shown in Figure 21c.

[0280] In an exemplary embodiment, taking six sub-pixels (one sub-pixel row, six sub-pixel columns, and the pixel driving circuit adopts the 7T2C structure shown in Figure 4) in the display area (AA) as an example, the fabrication process of another display substrate can be the same as steps (101) to (113) above, with the following differences:

[0281] The fifth conductive layer formed in step (110) above can be shown in Figures 22a and 22b. Figure 22a is a planar structure diagram of the six sub-pixels after the formation of the fifth conductive layer, and Figure 22b is a schematic diagram of the structure of the fifth conductive layer in Figure 20a. The difference between the fifth conductive layer shown in Figure 22b and the fifth conductive layer shown in Figure 20b is that in the pattern of the fifth conductive layer shown in Figure 22b, the signal lines are connected into a single structure in the area where they do not overlap with the pixel opening. Under the premise of reducing asymmetric color shift, the risk of signal floating caused by local breakage can be avoided to a certain extent. This can avoid the problem of increased resistance of the broken signal line after the signal line is broken at a certain position, and can reduce resistance and improve display uniformity to a certain extent. The structure after forming the second planarization layer, the anode conductive layer and the pixel definition layer in sequence based on Figure 22a is shown in Figure 23.

[0282] In exemplary embodiments, the sub-pixel rows and sub-pixel columns described in this disclosure can be understood as the rows and columns of pixel driving circuits in a sub-pixel. The anode in a sub-pixel is connected to the pixel driving circuit in the corresponding sub-pixel, but the position of the anode of a sub-pixel does not necessarily correspond completely to the row and column of the pixel driving circuit it is connected to. For example, the orthographic projection of the anode AN3 of the third sub-pixel on the substrate may overlap with the orthographic projections of the pixel driving circuits of the second and third sub-pixels on the substrate. The orthographic projection of the anode AN2 of the second sub-pixel on the substrate may overlap with the orthographic projections of the pixel driving circuits of the second and third sub-pixels on the substrate. The orthographic projection of the anode AN1 of the first sub-pixel on the substrate may overlap with the orthographic projection of the pixel driving circuit of the first sub-pixel on the substrate.

[0283] The structures and fabrication processes described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced as needed. The display substrates in this disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc. This disclosure does not limit them.

[0284] This disclosure also provides a display device, as shown in FIG24. The display device may include the display substrate of any of the foregoing embodiments. The display device may be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0285] The display substrate and display device provided in this disclosure embodiment include a driving circuit layer comprising multiple conductive layers. At least one signal line in the same conductive layer corresponds to at least one pixel opening. The at least one signal line and the corresponding pixel opening have an overlapping area. In the area corresponding to the same pixel opening, at least one signal line is symmetrical with respect to the first center line of the pixel opening. The first center line is the center line of the pixel opening extending along a second direction. This can improve asymmetric color shift and solve the problem of color shift asymmetry to a certain extent, thereby improving the display effect.

[0286] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0287] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0288] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit the scope of these embodiments. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The substrate and a plurality of sub-pixels, a driving circuit layer, and a pixel definition layer disposed on the substrate, wherein, in a direction perpendicular to the plane of the display substrate, the driving circuit layer is located between the substrate and the pixel definition layer, the driving circuit layer includes a plurality of conductive layers, the pixel definition layer has a plurality of pixel openings formed therein, and the sub-pixel includes at least one pixel opening; In at least one of the plurality of conductive layers, at least one signal line in the same conductive layer corresponds to at least one pixel opening, and the at least one signal line and the corresponding pixel opening have an overlapping area. In the area corresponding to the same pixel opening, the at least one signal line is symmetrical with respect to a first center line of the pixel opening, and the first center line is the center line of the pixel opening extending along a second direction.

2. The display substrate according to claim 1, wherein, The at least one conductive layer includes the conductive layer in the driving circuit layer that is closest to the pixel definition layer, and the at least one signal line is located in the conductive layer that is closest to the pixel definition layer.

3. The display substrate according to claim 1 or 2 further includes an anode conductive layer, wherein the anode conductive layer is located between the driving circuit layer and the pixel definition layer in a direction perpendicular to the plane of the display substrate, the anode conductive layer includes a plurality of anodes, the plurality of anodes correspond one-to-one with the plurality of pixel openings, and the orthographic projection of the pixel opening on the substrate is located within the range of the orthographic projection of the corresponding anode on the substrate; At least one signal line corresponds to at least one anode, and the at least one signal line and the corresponding anode have an overlapping area. In the area corresponding to the same anode, the at least one signal line is symmetrical with respect to the second center line of the anode body, and the second center line is the center line of the anode body extending along the second direction. Within the same sub-pixel, the orthographic projections of the first center line and the second center line on the substrate overlap.

4. The display substrate according to claim 1 or 2, wherein, The at least one signal line includes at least one first type signal line and at least one second type signal line. The at least one first type signal line and the at least one second type signal line are arranged at intervals along a first direction and extend along a second direction. In the first direction, the size of the first type signal line is larger than the size of the second type signal line. In a plane parallel to the substrate, the first direction intersects the second direction. At least a portion of the structure of the region corresponding to the pixel opening of the first type of signal line is set as a hollow structure. The hollow structure divides the first type of signal line into a plurality of lines arranged at intervals along the first direction. In the region corresponding to the same pixel opening, in the first direction, the size of at least a portion of the plurality of lines and the at least one second type of signal line is the same as the size of at least a portion of the second type of signal line.

5. The display substrate according to claim 4, wherein, In the region corresponding to the same pixel opening: a plurality of first spacings are provided between the plurality of lines and the at least one second type signal line, the plurality of first spacings having the same size, and the first spacing being the distance between two adjacent lines among the plurality of lines and the at least one second type signal line.

6. The display substrate according to claim 5, wherein, In the region corresponding to the same pixel opening, the plurality of lines and the at least one second-type signal line are uniformly arranged along the first direction.

7. The display substrate according to claim 5, wherein, In the region corresponding to the pixel opening, the dimensions of the line and the second type of signal line along the first direction are both greater than or equal to 1 micrometer and less than or equal to 15 micrometers, and the dimensions of the first spacing along the first direction are greater than or equal to 1 micrometer and less than or equal to 15 micrometers.

8. The display substrate according to claim 4, wherein, The substrate includes a display area, the plurality of sub-pixels are located in the display area, the same first type of signal line has at least one connection node in the display area, and the plurality of lines in the same first type of signal line are connected to each other at the connection node.

9. The display substrate according to claim 8, further comprising a border region surrounding the display area and a plurality of first connection structures, wherein in the second direction: the first connection structure is located on the side of the display area near the border region, and in at least some of the plurality of first connection structures, each first connection structure corresponds to one of the first type signal lines, and multiple lines of the same first type signal line are interconnected on the side near the border region through corresponding first connection structures.

10. The display substrate according to claim 8 further includes a plurality of first connection structures, wherein in at least a portion of the plurality of first connection structures, each first connection structure corresponds to one of the first type signal lines, and in the second direction: the first connection structure is located between two adjacent pixel openings, and in at least a portion of the plurality of pixel openings, at least one first connection structure is provided on both sides of each pixel opening, and multiple lines in the same first type signal line located between two adjacent pixel openings are interconnected through corresponding first connection structures.

11. The display substrate according to claim 1, wherein, At least one of the sub-pixels includes a pixel driving circuit located in the driving circuit layer; at least one of the pixel driving circuits includes a plurality of transistors and at least one capacitor, the plurality of transistors including at least one first-type transistor and at least one second-type transistor. In a direction perpendicular to the plane of the substrate, the capacitor includes: a first electrode plate located on one side of the substrate, and a second electrode plate located on the side of the first electrode plate away from the substrate; the first type of transistor includes: an active layer located on the side of the first electrode plate close to the substrate, a control electrode disposed on the same layer as the first electrode plate, and a first electrode and a second electrode located on the side of the control electrode away from the substrate; the second type of transistor includes: an active layer located on the side of the second electrode plate away from the substrate, a control electrode located on the side of the active layer away from the substrate, and a first electrode and a second electrode located on the side of the control electrode away from the substrate; the first electrode and the second electrode of the first type of transistor are disposed on the same layer as the first electrode and the second electrode of the second type of transistor, and the at least one signal line is located on the side of the first electrode and the second electrode away from the substrate.

12. The display substrate according to claim 11, wherein, The at least one signal line includes a plurality of first power lines and a plurality of first initial signal connection lines, the at least one signal line extends along the second direction and is arranged along the first direction; the plurality of sub-pixels include at least a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels, the plurality of sub-pixels form a plurality of pixel units, the pixel unit includes at least one first sub-pixel, one second sub-pixel and one third sub-pixel; In the same pixel unit: in the second direction, the pixel openings of the second sub-pixel and the pixel openings of the third sub-pixel are arranged alternately; in the first direction, the pixel driving circuits of the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged alternately, the pixel openings of the second sub-pixel and the third sub-pixel are located on the same side of the pixel opening of the first sub-pixel, the first initial signal connection line is located between the pixel driving circuits of the second sub-pixel and the third sub-pixel, and in the region corresponding to the pixel openings of the second sub-pixel and the third sub-pixel, the two first power lines in the second sub-pixel and the third sub-pixel are symmetrical with respect to the first initial signal connection line.

13. The display substrate according to claim 12, wherein, The at least one signal line also includes a plurality of first type second initial signal connection lines and a plurality of second power lines; The first type of second initial signal line is located in the pixel driving circuit of the first sub-pixel. Each sub-pixel's pixel driving circuit is provided with a second power line. In the same pixel unit: in the region corresponding to the pixel opening of the first sub-pixel, the first type of second initial signal line and the second power line in the first sub-pixel are relative to the third center line, which is the center line of the pixel opening of the first sub-pixel extending along the second direction.

14. The display substrate according to claim 13, further comprising a plurality of anode connection electrodes, a plurality of data signal lines, and a plurality of anodes, wherein the plurality of anodes are located between the driving circuit layer and the pixel opening in a direction perpendicular to the plane of the display substrate, the plurality of anode connection electrodes correspond one-to-one with the plurality of anodes, the sub-pixel further comprising at least one anode connection electrode and at least one anode, and in the same sub-pixel, the pixel driving circuit is electrically connected to the corresponding anode through the corresponding anode connection electrode; the at least one signal line further comprises the plurality of anode connection electrodes; In the same pixel unit: in the region corresponding to the pixel opening of the first sub-pixel, the data signal line and the anode connection electrode of the first sub-pixel are symmetrical with respect to the third center line. In the first direction, the data signal line is located on the side of the first type of second initial signal connection line away from the second power line, and the anode connection electrode of the first sub-pixel is located on the side of the second power line away from the first type of second initial signal connection line.

15. The display substrate according to claim 14, wherein, In the same pixel unit: in the region corresponding to the anode of the second sub-pixel, the anode connection electrodes in the second sub-pixel and the third sub-pixel are symmetrical with respect to the first initial signal connection line; in the first direction, in either the second sub-pixel or the third sub-pixel, the anode connection electrode is located on the side of the first power line away from the first initial signal connection line.

16. The display substrate according to claim 14, wherein, The at least one signal line includes a plurality of first-type signal lines and a plurality of second-type signal lines, wherein in the first direction, the size of the first-type signal lines is larger than the size of the second-type signal lines; The plurality of first-type signal lines include: a first second initial signal line and a second power line located in the pixel driving circuit of the first sub-pixel, and a first power line located in the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel; the plurality of second-type signal lines include: a data signal line and an anode connection electrode located in the pixel driving circuit of the first sub-pixel, and a first initial signal connection line located between the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel; The area corresponding to the pixel opening of the first type of signal line is set as a hollow structure. The hollow structure divides the first type of signal line into multiple lines arranged at intervals along the first direction. In the area corresponding to the same pixel opening, in the first direction, the size of the multiple lines is the same as the size of the second type of signal line.

17. The display substrate according to claim 16, further comprising a plurality of second power connection lines, the second power connection lines extending along the first direction, and the second power connection lines being disposed in the same layer as the first electrode and the second electrode; The plurality of second power lines and the plurality of second power connection lines are interconnected through second power vias to form a grid structure. The pixel opening of the first sub-pixel overlaps with the second power via. In the region corresponding to the pixel opening of the first sub-pixel, the dimension of the line in the second power connection line along the first direction at the position of the second power via is greater than the dimension along the first direction at the position where no second power via is provided.

18. The display substrate according to claim 14, wherein, The at least one signal line includes a plurality of first-type signal lines. In the same sub-pixel, a plurality of anode vias are provided. The plurality of anode vias include a first anode via and a second anode via. The anode connection electrode is electrically connected to the corresponding pixel driving circuit through the first anode via and electrically connected to the corresponding anode through the second anode via. The lines of the first-type signal lines adjacent to the anode via bend away from the anode via in a direction away from the anode via.

19. The display substrate according to claim 18, wherein, In the same pixel unit: in the second power line corresponding to the anode of the first sub-pixel, in the first direction, at least one line of the second power line corresponding to the anode via position in the first sub-pixel bends in a direction away from the corresponding anode via and merges with the line of the second power line away from the corresponding anode via. In the first power line corresponding to the anode of the second sub-pixel, in the first direction, at least one line of the first power line corresponding to the anode via position in the second sub-pixel bends in a direction away from the corresponding anode via and merges with the line of the first power line on the side away from the corresponding anode via.

20. A display device comprising a display substrate as described in any one of claims 1 to 19.

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