Method for manufacturing back-side se-structured battery
By employing a novel back-side SE structure and patterned masking process in the TOPCon structure, the parasitic absorption of light by the doped polycrystalline silicon layer was solved, improving battery performance and reducing manufacturing costs.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- CHANGZHOU SHICHUANG ENERGY CO LTD
- Filing Date
- 2025-12-02
- Publication Date
- 2026-07-02
AI Technical Summary
The existing TOPCon structure has severe parasitic absorption of light by the back-side doped polycrystalline silicon layer, which leads to a decrease in battery performance. Furthermore, the existing process makes it difficult to avoid slurry burn-through when doping polycrystalline silicon in a thin layer.
A novel back-side SE structure is adopted, which consists of a tunneling oxide layer and a doped polysilicon structure in the metal region and a silicon substrate and a passivation film in the non-metal region. The polysilicon layer in the non-metal region is removed by a patterned mask process, and the PSG removal process is integrated into the de-coating process.
This effectively reduces the absorption of light by the polycrystalline silicon layer in the non-metallic region, improving battery performance while reducing manufacturing costs.
Smart Images
Figure CN2025139173_02072026_PF_FP_ABST
Abstract
Description
A method for manufacturing a back-side SE structure battery Technical Field
[0001] This invention relates to the field of photovoltaic technology, specifically to a method for manufacturing a back-side SE structure solar cell. Background Technology
[0002] Currently, the TOPCon structure adopts a tunneling oxide structure on the back side, which involves depositing an ultrathin tunneling oxide layer and a doped polycrystalline silicon layer on the back side. By utilizing the chemical passivation and majority carrier tunneling effect of silicon oxide, as well as the field passivation of the doped polycrystalline silicon layer, the surface recombination on the back side is greatly reduced, thereby improving the conversion efficiency of the battery.
[0003] While the TOPCon structure offers excellent passivation, the introduced doped polysilicon exhibits severe parasitic absorption of light. According to experimental data, the doped polysilicon on the back side can cause an absorption of approximately 0.004 mA / cm² / nm. A 30nm doped polysilicon layer already meets the current passivation requirements. However, due to limitations in the current back-side paste, when the thickness is less than 80nm, the back-side polysilicon layer will experience paste burn-through, thus affecting electrical performance. Summary of the Invention
[0004] The purpose of this invention is to provide a method for fabricating a back-side SE structure solar cell, in order to solve the problem of severe parasitic absorption of light caused by the doped polycrystalline silicon introduced by the back-side TOPCon structure.
[0005] To achieve the above objectives, the present invention provides the following technical solution:
[0006] In a first aspect, the present invention provides a method for manufacturing a rear-side SE structure battery, comprising the following steps:
[0007] S1. First alkaline etching: Select an N-type silicon wafer for alkaline etching texturing to obtain a texturized silicon wafer;
[0008] S2, Boron diffusion: Boron diffusion is performed on the texturized silicon wafer in a back-to-back manner;
[0009] S3, Secondary Alkaline Etching: Removing the BSG and PN junction on the back and edges of the silicon wafer using alkaline etching;
[0010] S4. First deposition: A tunneling oxide layer and a poly layer are deposited sequentially on the back side of the silicon wafer, and then phosphorus diffusion is performed to form a doped poly layer;
[0011] S5. Forming a mask: A mask material is coated on the back of the silicon wafer, and the mask material is patterned and modified. The modified areas form a patterned mask layer, while the unmodified areas do not form a mask layer. The modified mask layer is resistant to acids and alkalis, while the unmodified mask material is not resistant to acids and alkalis.
[0012] S6, Acid Etching: HF is used to remove the mask material and PSG from the unmodified area on the back side. The mask layer in the modified area is acid-resistant and acts as a sacrificial layer to protect the PSG underneath from acid etching during the acid etching process.
[0013] S7, Three-stage alkaline etching: The poly layer in the unmodified area on the back side is removed by alkaline etching, while the PSG retained in the modified area on the back side preserves the poly layer underneath.
[0014] S8, RCA cleaning: RCA cleaning removes the mask layer and PSG from the modified area on the back of the silicon wafer;
[0015] S9. Secondary deposition: Depositing a functional layer on the back side of the silicon wafer;
[0016] S10, Electrode Formation: An electrode is formed in the modified region to form the back SE structure.
[0017] Preferably, in step S3, the BSG and PN junction on the back and edge of the silicon wafer are removed while the front BSG is retained.
[0018] Preferably, in step S5, the patterning modification method used is laser scanning heating, wherein the mask material reacts under heating to generate a mask layer.
[0019] More preferably, in step S5, the coated mask material is tetraethyl orthosilicate, silane, etc.
[0020] More preferably, the laser is one of ultraviolet, green light, and infrared light, with a power of 5-100W, a repetition frequency of 100-1000KHZ, and a speed of 10000-70000mm / min.
[0021] Preferably, in step S7, the poly layer coated on the front side is removed simultaneously by alkaline etching.
[0022] Preferably, in step S8, the RCA cleaning removes the front-side BSG simultaneously.
[0023] Preferably, in step S9, the functional layer can be a passivation layer, an antireflection layer, or a passivation and antireflection layer, and the material of the functional layer can be alumina, silicon nitride, silicon oxynitride, silicon oxide, etc.
[0024] Preferably, in step S10, the electrode is formed by printing silver paste on the electrode area using screen printing and sintering to form a metallized structure.
[0025] In a second aspect, the present invention also provides a rear SE structure battery, the battery comprising a rear SE structure manufactured using the method described above.
[0026] Compared with the prior art, the beneficial effects of the present invention are: compared with the traditional back structure with poly thickness difference, the present invention has a tunnel oxide layer + doped poly layer in the back metal area and a silicon substrate + passivation film in the non-metal area, which completely solves the poly light absorption problem in the non-metal area. At the same time, by using the process flow provided by this patent, the PSG removal process can be integrated into the de-coating process, and only an HF tank needs to be added before the de-coating, which reduces the manufacturing cost. Attached Figure Description
[0027] Figure 1 is a structural diagram of a back-side SE structure TOPCon battery prepared according to the method of the present invention;
[0028] Figure 2 is a topographic image of the metal and non-metal regions of the silicon wafer obtained by reverse etching according to the method of Example 1;
[0029] Figure 3 is an ECV curve showing the height difference between the metal and non-metal regions of the silicon wafer after reverse etching, obtained according to the method of Example 1;
[0030] Figure 4 is a topographic image of the metal and non-metal regions of the silicon wafer obtained by reverse etching according to the method of Example 2;
[0031] Figure 5 is an ECV curve showing the height difference between the metal and non-metal regions of the silicon wafer after reverse etching, obtained according to the method of Example 2;
[0032] Figure 6 is a topographic image of the metal and non-metal regions of the silicon wafer obtained by reverse etching according to the method of Example 3;
[0033] Figure 7 is an ECV curve showing the height difference between the metal and non-metal regions of the silicon wafer after reverse etching, obtained according to the method of Example 3.
[0034] In the diagram: 1. Front silicon nitride; 2. Aluminum oxide; 3. P-type emitter; 4. N-type silicon substrate; 5. Tunneling oxide layer; 6. Phosphorus-doped polycrystalline silicon layer; 7. Back silicon nitride; 8. Front electrode; 9. Back electrode. Detailed Implementation
[0035] This paper proposes a novel back-side TOPCon cell structure, which consists of a tunneling oxide layer and doped polycrystalline silicon in the metal region, while the non-metal region is composed of a silicon substrate, aluminum oxide, and silicon nitride passivation film. This structure eliminates the poly in the non-metal region, significantly reducing the low current problem caused by poly parasitic absorption. At the same time, compared with the conventional process flow of current production lines, the PSG removal process can be integrated into the de-coating process, requiring only the addition of an HF tank before de-coating, thus reducing manufacturing costs.
[0036] In an exemplary embodiment, the solution of the present invention includes the following steps:
[0037] 1. Select N-type silicon wafers with a thickness of 100-160μm and a resistivity of 0.2-2.1mΩ*cm. Then, perform alkaline texturing in a trough to achieve a reflectivity of 9-11% and a weight reduction of 0.3-0.5g.
[0038] 2. The silicon wafers processed in step 1 are subjected to boron diffusion in a back-to-back manner for 3 hours and 30 minutes, with a sheet resistance of 200-450 ohms / sq.
[0039] 3. After step 2, the silicon wafer is treated with a tank alkaline polishing machine to remove the BSG and PN junction on the back and edges, while retaining the BSG on the front.
[0040] 4. The silicon wafer processed in step 3 is deposited with a tunneling oxide layer and a poly layer using LPCVD. After high-temperature phosphorus diffusion, a doped poly layer is formed. The thicknesses of the two layers are 1-2 nm and 100-200 nm, respectively.
[0041] 5. Coat the surface of the silicon wafer processed in step 4 with a masking material solution such as tetraethyl orthosilicate and silane nitride. After drying, a thin film is formed. The surface of the thin film is heated by a laser. The film in the heated area will react under the high temperature of laser irradiation to generate masking layers such as silicon oxide / silicon nitride / silicon oxynitride / silicon carbide and other types of oxides, nitrides and carbides. The laser is one of ultraviolet / green light / infrared light, with a power of 5-100W, a repetition frequency of 100-1000KHZ, and a speed of 10000-70000mm / min.
[0042] 6. The silicon wafer processed in step 5 is etched using a tank-type alkaline polishing machine. The etching process is as follows: First, HF is used to remove the PSG on the front side and the mask material in the non-laser area on the back side, as well as the PSG under the mask material. Since the formed mask layer has a certain acid resistance, it can act as a sacrificial layer to protect the PSG underneath from being etched. Then, alkali and additives are used to remove the poly around the front side and the poly in the non-laser area. After etching, a height difference of about 3-5 μm will be formed between the laser area and the non-laser area to ensure that the poly in the non-laser area is completely removed. This forms the novel back-side TOPCon structure described above. The mask layer in the laser area, as well as the PSG and the front-side BSG, will be completely removed in the subsequent RCA cleaning.
[0043] 7. Apply ALD double-sided aluminum oxide coating to the silicon wafer processed in step 6, with a thickness of 3-10 nm.
[0044] 8. The silicon wafer processed in step 7 is subjected to PECVD to deposit silicon nitride on both the front and back sides, with a thickness of 80-120nm.
[0045] 9. Using screen printing, print silver-aluminum paste on the front and silver paste on the back of the silicon wafer processed in step 8.
[0046] The method of this invention, after depositing a tunneling oxide layer and a poly layer on the back side, uses a patterned mask to form a corresponding patterned POLO structure. This method features a POLO structure only in the metallized regions, while the non-metallized regions consist only of a silicon substrate and a passivation film, thus avoiding the severe photoparasitic absorption problem caused by the poly layer in the non-metallized regions. Using this method, the PSG removal process can be integrated into the de-coating process, requiring only the addition of an HF bath before de-coating, reducing manufacturing costs.
[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0048] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," "front end," "rear end," "both ends," "one end," and "the other end," etc., indicating orientation or positional relationships, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0049] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. Specific Implementation Example 1
[0050] 1. Select an N-type 182*91 rectangular silicon wafer with a thickness of 100-160μm and a resistivity of 0.2-2.1mΩ*cm. Then, perform alkaline texturing in a groove to achieve a reflectivity of 9-11% and a weight reduction of 0.3-0.5g.
[0051] 2. The silicon wafers processed in step 1 are subjected to boron diffusion in a back-to-back manner for 3 hours and 30 minutes, with a sheet resistance of 200-450 ohms / sq.
[0052] 3. After step 2, the silicon wafer is treated with a tank alkaline polishing machine to remove the BSG and PN junction on the back and edges, while retaining the BSG on the front.
[0053] 4. The silicon wafer processed in step 3 is deposited with a tunneling oxide layer and a poly layer using LPCVD. After high-temperature phosphorus diffusion, a doped poly layer is finally formed. The thicknesses of the two layers are 1.5 nm and 100 nm, respectively.
[0054] 5. Coat the surface of the silicon wafer processed in step 4 with a layer of tetraethyl orthosilicate mask material solution, dry it to form a thin film, and heat the surface of the thin film with a laser. The film in the heated area will react to generate silicon oxide and other types of oxides as mask layers. The laser is green light with a power of 50W, a repetition frequency of 500KHZ, and a speed of 50000mm / min.
[0055] 6. The silicon wafer processed in step 5 is etched using a tank-type alkaline polishing machine. The etching process is as follows: First, HF is used to remove the PSG on the front side and the mask in the non-laser area on the back side, as well as the PSG under the mask. Since the formed mask has a certain acid resistance, it can act as a sacrificial layer to protect the PSG below from being etched. Then, alkali and additives are used to remove the poly around the front side and the poly in the non-laser area. After etching, a height difference of about 3-5 μm will be formed between the laser area and the non-laser area to ensure that the poly in the non-laser area is completely removed. This forms the novel back-side TOPCon structure described above. The mask in the laser area, as well as the PSG and the front-side BSG, will be completely removed in the subsequent RCA cleaning. The results are shown in Figures 2 and 3.
[0056] 7. The silicon wafer processed in step 6 is subjected to ALD double-sided aluminum oxide coating with a thickness of 3.5nm;
[0057] 8. The silicon wafer processed in step 7 is subjected to PECVD to deposit silicon nitride on both the front and back sides, with a thickness of 90nm;
[0058] 9. After processing in step 8, the silicon wafer is screen-printed with silver-aluminum paste on the front and silver paste on the back. After sintering, the electrical performance is tested. Specific Implementation Example 2
[0059] 1. Select an N-type 182*91 rectangular silicon wafer with a thickness of 100-160μm and a resistivity of 0.2-2.1mΩ*cm. Then, perform alkaline texturing in a groove to achieve a reflectivity of 9-11% and a weight reduction of 0.3-0.5g.
[0060] 2. The silicon wafers processed in step 1 are subjected to boron diffusion in a back-to-back manner for 3 hours and 30 minutes, with a sheet resistance of 200-450 ohms / sq.
[0061] 3. After step 2, the silicon wafer is treated with a tank alkaline polishing machine to remove the BSG and PN junction on the back and edges, while retaining the BSG on the front.
[0062] 4. The silicon wafer processed in step 3 is deposited with a tunneling oxide layer and a poly layer using LPCVD. After high-temperature phosphorus diffusion, a doped poly layer is finally formed. The thicknesses of the two layers are 1.5 nm and 120 nm, respectively.
[0063] 5. Coat the surface of the silicon wafer processed in step 4 with a layer of nitrosilane masking material solution, dry it to form a thin film, and use a laser to heat the surface of the thin film. The thin film in the heated area will react to generate silicon nitride and other types of nitride masking layers. The laser is an infrared laser with a power of 15W, a repetition frequency of 200KHZ, and a speed of 20000mm / min.
[0064] 6. The silicon wafer processed in step 5 is etched using a tank-type alkaline polishing machine. The etching process is as follows: First, HF is used to remove the PSG on the front side and the mask in the non-laser area on the back side, as well as the PSG under the mask. Since the formed mask has a certain acid resistance, it can act as a sacrificial layer to protect the PSG below from being etched. Then, alkali and additives are used to remove the poly around the front side and the poly in the non-laser area. After etching, a height difference of about 3-5 μm will be formed between the laser area and the non-laser area to ensure that the poly in the non-laser area is completely removed. This forms the novel back-side TOPCon structure described above. The mask in the laser area, as well as the PSG and the front-side BSG, will be completely removed in the subsequent RCA cleaning. The results are shown in Figures 4 and 5.
[0065] 7. The silicon wafer processed in step 6 is subjected to ALD double-sided aluminum oxide coating with a thickness of 3.5nm;
[0066] 8. The silicon wafer processed in step 7 is subjected to PECVD to deposit silicon nitride on both the front and back sides, with a thickness of 90nm;
[0067] 9. After processing in step 8, the silicon wafer is screen-printed with silver-aluminum paste on the front and silver paste on the back. After sintering, the electrical performance is tested. Specific Implementation Example 3
[0068] 1. Select an N-type 182*91 rectangular silicon wafer with a thickness of 100-160μm and a resistivity of 0.2-2.1mΩ*cm. Then, perform alkaline texturing in a groove to achieve a reflectivity of 9-11% and a weight reduction of 0.3-0.5g.
[0069] 2. The silicon wafers processed in step 1 are subjected to boron diffusion in a back-to-back manner for 3 hours and 30 minutes, with a sheet resistance of 200-450 ohms / sq.
[0070] 3. After step 2, the silicon wafer is treated with a tank alkaline polishing machine to remove the BSG and PN junction on the back and edges, while retaining the BSG on the front.
[0071] 4. The silicon wafer processed in step 3 is deposited with a tunneling oxide layer and a poly layer using LPCVD. After high-temperature phosphorus diffusion, a doped poly layer is finally formed. The thicknesses of the two layers are 1.5 nm and 120 nm, respectively.
[0072] 5. Coat the surface of the silicon wafer processed in step 4 with a layer of tetraethyl orthosilicate mask material solution, dry it to form a thin film, and heat the surface of the thin film with a laser. The film in the heated area will react to generate silicon nitride and other types of nitride mask layers. The laser is an ultraviolet laser with a power of 25W, a repetition frequency of 300KHZ, and a speed of 30000mm / min.
[0073] 6. The silicon wafer processed in step 5 is etched using a tank-type alkaline polishing machine. The etching process is as follows: First, HF is used to remove the PSG on the front side and the mask in the non-laser area on the back side, as well as the PSG under the mask. Since the formed mask has a certain acid resistance, it can act as a sacrificial layer to protect the PSG below from being etched. Then, alkali and additives are used to remove the poly around the front side and the poly in the non-laser area. After etching, a height difference of about 3-5 μm will be formed between the laser area and the non-laser area to ensure that the poly in the non-laser area is completely removed. This forms the novel back-side TOPCon structure described above. The mask in the laser area, as well as the PSG and the front-side BSG, will be completely removed in the subsequent RCA cleaning. The results are shown in Figures 6 and 7.
[0074] 7. The silicon wafer processed in step 6 is subjected to ALD double-sided aluminum oxide coating with a thickness of 3.5nm;
[0075] 8. The silicon wafer processed in step 7 is subjected to PECVD to deposit silicon nitride on both the front and back sides, with a thickness of 90nm;
[0076] 9. After processing in step 8, the silicon wafer is screen-printed with silver-aluminum paste on the front and silver paste on the back. After sintering, the electrical performance is tested.
[0077] The electrical properties of Examples 1 to 3 are shown in Table 1 below:
[0078] Table 1
[0079] Compared to the control group, GAP000c(V)Isc(A)RserRshuntFF(%)Eta(%) Example 1: -0.0005 0.042 0.00004 -228 -0.159 0.089 Example 2: -0.0004 0.039 0.00002 -98 -0.034 0.115 Example 3: -0.0012 0.035 0.0000123 -0.070 0.065
[0080] Any aspects of this invention not described in detail are well-known to those skilled in the art.
[0081] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications and equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A method for fabricating a backside SE structure battery, characterized in that, The method includes the following steps: S1. First alkaline etching: Select an N-type silicon wafer for alkaline etching texturing to obtain a texturized silicon wafer; S2, Boron diffusion: Boron diffusion is performed on the texturized silicon wafer in a back-to-back manner; S3, Secondary Alkaline Etching: Removing the BSG and PN junction on the back and edges of the silicon wafer using alkaline etching; S4. First deposition: A tunneling oxide layer and a poly layer are deposited sequentially on the back side of the silicon wafer, and then phosphorus diffusion is performed to form a doped poly layer; S5. Forming a mask: A mask material is coated on the back of the silicon wafer, and the mask material is patterned and modified. The modified areas form a patterned mask layer, while the unmodified areas do not form a mask layer. The modified mask layer is resistant to acids and alkalis, while the unmodified mask material is not resistant to acids and alkalis. S6, Acid Etching: HF is used to remove the mask material and PSG from the unmodified area on the back side. The mask layer in the modified area is acid-resistant and acts as a sacrificial layer to protect the PSG underneath from acid etching during the acid etching process. S7, Three-stage alkaline etching: The poly layer in the unmodified area on the back side is removed by alkaline etching, while the PSG retained in the modified area on the back side preserves the poly layer underneath. S8, RCA cleaning: RCA cleaning removes the mask layer and PSG from the modified area on the back of the silicon wafer; S9. Secondary deposition: Depositing a functional layer on the back side of the silicon wafer; S10, Electrode Formation: An electrode is formed in the modified region to form the back SE structure.
2. The method of manufacturing a backside SE structure battery according to claim 1, wherein In step S3, the BSG and PN junction on the back and edges of the silicon wafer are removed while the front BSG is retained.
3. The method of claim 1, wherein the back SE structure battery is formed by the steps of: In step S5, the patterning modification method used is laser scanning heating, wherein the mask material reacts under heating to generate a mask layer.
4. The method of manufacturing a backside SE structure battery according to claim 3, wherein In step S5, the mask material is tetraethyl orthosilicate or nitrosilane.
5. The method for manufacturing the rear SE structure battery as described in claim 3, characterized in that, The laser is one of ultraviolet, green, or infrared light, with a power of 5-100W, a repetition frequency of 100-1000kHz, and a speed of 10000-70000mm / min.
6. The method of fabricating a backside SE-structure battery of claim 1, wherein, In step S7, alkaline etching simultaneously removes the poly layer coated on the front side.
7. The method of fabricating a backside SE-structure battery of claim 2, wherein, In step S8, RCA cleaning removes the front-side BSG simultaneously.
8. The method of fabricating a backside SE-structure battery of claim 1, wherein, In step S9, the functional layer may be a passivation layer, an antireflection layer, or a passivation and antireflection layer.
9. The method of fabricating a backside SE-structure battery of claim 1, wherein, In step S10, the electrode is formed by printing silver paste on the electrode area using screen printing and sintering it to form a metallized structure.
10. A backside SE structure battery, characterized by, It includes a back-side SE structure manufactured using the method described in any one of claims 1 to 9.