Optoelectronic device arrangement, optoelectronic device and method

Abstract

The invention concerns an optoelectronic device arrangement comprising a bonding wafer comprising a plurality of anchoring posts and a plurality of optoelectronic devices arranged on the bonding wafer, each of the plurality of optoelectronic devices having a mesa structured layer stack, said layer stack comprising an active layer arranged between a first doped semiconductor layer and a second doped semiconductor layer, whereas a surface of the second doped semiconductor layer is facing the bonding wafer. Each of the plurality of optoelectronic devices further comprises a conductive contact layer being in electrical contact with one of the first and second semiconductor layer and extending at least across a portion of a sidewall of the respective mesa structured layer stack. The conductive contact layer forms a resting region, said resting region laterally displaced from the portion of the sidewall and each anchoring post of the plurality of anchoring posts is attached to the resting region.

Description

[0001] 2024PF01085

[0002] OPTOELECTRONIC DEVICE ARRANGEMENT AND METHOD

[0003] The present application claims priority from German patent application DE 10 2024 139 655 .5 dated Dezember 23 , 2024 , the disclosure of which is incorporated herein by reference in its entirety.

[0004] The present invention concerns an optoelectronic device arrangement and an optoelectronic device . The method also concerns a method for processing such arrangement .

[0005] BACKGROUND

[0006] Optoelectronic devices are implemented either as single individual devices on a growth wafer or as monolithically integrated devices . The former individual devices are often transferred to a display pcb and the like . Such transfer is usually performed by a stamp that picks up one or more devices simultaneously and places them on a target . In the case of pLEDs such procedures may be challenging due to the small size of pLEDs . pLEDs are optoelectronic devices with a length or diameter smaller than 70pm and down to approximately 10pm or even down to 2 pm. Hence, the overall size of an pLED lies in the range of approximately 5000pm2down to 4pm2.

[0007] pLEDs are implemented as horizontal devices , whereas the two n- and p-contacts are implemented on one side opposing an emission surface or as vertical pLEDs with the two contacts being on opposed sides . For a transfer, the pLED is usually placed on an anchoring post, said post often arranged centrally below the pLED. This may be suitable in some cases but increases the risk that residuals being left on the surface of the device during or after the transfer either damages devices or affects the electrical connection to the device .

[0008] It is therefore an obj ect of the present application to reduce damages of an optoelectronic device during or after transfer and avoid deterioration of the contact area of such devices .

[0009] SUMMARY OF THE INVENTION2024PF01085

[0010] This and other obj ects are addressed by the subject matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0011] The inventors propose a new arrangement and design for the anchoring posts . Particularly, the posts for optoelectronic devices are not vertically applied below the chip but laterally shifted adjacent to the chip . To prevent damages to the semiconductor material, it is further proposed to laterally extend the contact metal in order to create direct contact between post and chip . In other words , the anchoring post is adhered not to the chip itself but to a lateral extension of the metallic contact, said extension adj acent to the chip, but also displaced therefrom.

[0012] In addition, no semiconductor material is present above or below the contact material, that is, in a proj ection of the extension towards the emission surface . The anchoring post only rests on the metallic contact . A sacrificial layer may be present above the metallic contact and surround the anchoring posit for additional stability. After removal of the sacrificial layer (s ) , the device is held only by the extension of the metallic contact to the anchoring post .

[0013] This extension, also referred to as the resting region, is displaced from the semiconductor material of the optoelectronic device . During separation, the resting area is separated from the metallic contact, a separation edge is created and remains on the device . Alternatively, the resting area is separated from the anchoring post and remains on the device . However, in any case the resting area is separated from the contact area, such that any anchoring post residuals does not tamper with the contact .

[0014] In some aspects , an optoelectronic device arrangement is proposed. Such arrangement may be implemented on a wafer level to be shipped for further processing . The proposed optoelectronic device arrangement comprises a bonding wafer comprising a plurality of spatially separated anchoring posts . A plurality of optoelectronic devices are arranged on the bonding wafer, each of the plurality of optoelectronic devices2024PF01085

[0015] having a mesa-structured layer stack. The layer stack comprises an active layer arranged between a first doped semiconductor layer and a second doped semiconductor layer, whereas a surface of the second doped semiconductor layer is facing the bonding wafer .

[0016] The anchoring posts may be located between two adj acent layer stacks of the plurality of layer stacks, and particularly in the area between two mesa structured sidewalls of adj acent layer stacks . Each of the plurality of optoelectronic devices further comprises a conductive contact layer being in electrical contact with one of the first and second semiconductor layers of the respective stack. The conductive contact layer extends at least across a portion of a sidewall of the respective mesa structured layer stack and forms a resting region. In accordance with the proposed principle, the resting region is laterally displaced from the portion of the sidewall . Each anchoring post of the plurality of anchoring posts is attached to one of the respective resting regions .

[0017] The anchoring post is adjacent to the device and not below the device itself . It is not in contact with the actual contact area of the device, thereby saving residuals on the actual contact area . One may also reduce the thickness of the device, as the anchoring posts are located in the areas formed by the mesa etching process . In some aspects , the conductive contact layers of two adj acent optoelectronic devices of the optoelectronic devices share a common resting region. Consequently, one can combine two or more devices (up to four devices ) on one shared anchoring post .

[0018] In some aspects , the conductive contact layer forms a metallic bridge between two adj acent devices, wherein the bridge comprises the resting region attached to the anchoring post . In some other aspects , the conductive contact layer forms a metallic bridge between four adj acent devices, wherein the bridge comprises the resting region attached to the anchoring post . In such a case, the conductive contact layer may extend over the respective edges of two adjacent sidewalls of the respective devices .2024PF01085

[0019] Some aspects relate to the shape and the arrangement of the extension of the conductive contact layer . In some aspects , the conductive contact layer extends laterally from the sidewall, thereby forming an extension or bridge comprising the resting region . The bridge or extension is located at a virtual symmetry axis through a centre of the respective optoelectronic device, said virtual axis substantially perpendicular to the sidewall when viewed from the top . The conductive contact layer therefore extends laterally from a sidewall, in particular centrally from a sidewall . In some other aspects, the extension of the conductive contact layer is located at a virtual symmetry axis through a centre of the respective optoelectronic device; said virtual axis substantially going through an edge of two adj acent sidewalls of the device when viewed from the top .

[0020] In some aspects , the anchoring post comprises a diameter smaller than a diameter of the resting region . This is suitable in cases of a slight misalignment during processing of the wafer and the devices . In some other aspects, the resting region is vertically displaced with regard to a surface of the first semiconductor facing away from the bonding wafer . The extension may be located below a level of said surface . In such cases, it may be suitable to arrange material of a sacrificial layer material on a surface of the resting region opposite the anchoring post . The sacrificial layer material may fill the remaining space between two adjacent mesa-structured layer stacks and is optionally flush with the surface of the first semiconductor facing away from a bonding wafer .

[0021] In some aspects , a portion of the sacrificial layer extends laterally from sidewalls onto a part of the resting region. It may form a circular or other shaped opening for the bonding material to adhere to the metal of the conductive contact layer . In some instances , the first and second sacrificial layers are in direct contact, for example, adj acent to the extension of the conductive contact layer and particularly adjacent to the resting region . In some other aspects , the first and sacrificial layer can be of different materials . However, it may be suitable that both sacrificial layers are made of the same material .2024PF01085

[0022] Such material may comprise silicone dioxide or si02 . S102 is easily etched by a fluoride containing gas or liquid.

[0023] In some further aspects , each of the plurality of optoelectronic devices further comprises a passivation layer arranged on the sidewalls of the mesa structured layer stack and the surface of the second doped semiconductor layer facing the bonding wafer and comprising an opening, that is filled by material of the conductive contact layer, thereby contacting the second doped semiconductor layer . The passivation layer may comprise a single structure, but can also comprise a multilayer structure having a plurality of sublayer . In some aspects, the passivation layer comprises a regrowth sublayer of a semiconductor material .

[0024] In some cases of optoelectronic device arrangement, a passivation layer is arranged on the sidewalls of the mesa structured layer stack, electrically isolating the conductive layer from the surface of the second doped semiconductor layer . A via is created through the passivation layer, the second doped semiconductor, and the active region that is filled by material of the conductive contact layer electrically isolated from the second doped semiconductor and the active region and contacting the first doped semiconductor layer . This approach is suitable for horizontal devices, as described above .

[0025] When viewed from top, the optoelectronic devices of the optoelectronic device arrangement in accordance with the proposed principle comprise a rectangular shape, in particular a square . In some aspects, the shape is hexagonal . It is suitable that the edges of such shape follow certain directions of the crystallographic planes , thereby reducing defects and improving the internal quantum efficiency.

[0026] Some aspects concern the material of the conductive contact layer . Material used for the contact layer often comprises a metal, either in its elemental form or as an alloy. The contact layer can comprise a plurality of sublayer . Typical metals include but are not limited to platinum, nickel, titan, gold, silver, tin, indium as well alloys2024PF01085

[0027] thereof . In some aspects, the conductive contact layer comprises a layer stack comprising Pt, Ni and Ti for example, In, Sn and Au.

[0028] In some instances, the optoelectronic device arrangement is further processed to separate the plurality of devices therefrom. An optoelectronic device processed by this approach comprises a mesa-structured layer stack, said layer stack comprising an active layer arranged between a first doped semiconductor layer and a second doped semiconductor layer . A surface of the first doped semiconductor layer is an emission surface . The device further comprises a passivation layer on the sidewalls of the mesa-structured layer stack and a surface of the second doped semiconductor facing away from the emission surface .

[0029] A conductive contact layer is arranged on the passivation layer and is in electrical contact with one of the first and second semiconductor layers . The conductive contact layer extends at least across a portion of a sidewall of the respective mesa structured layer stack and comprises a broken edge or a roughened surface adjacent to said portion of the sidewall .

[0030] The expression "broken edge" resembles an edge or a "surface with rough interface" indicates a material that it has been separated from another material . For example, during the separation process , the material of the conductive layer may be ripped of thereby creating a broken edge . In some other aspects, residuals from the previous material may remain, thereby creating the rough interface . Particularly, a surface of the resting layer facing away from the emission surface may look different than a surface facing the emission surface, as one side has been resting and adhered to the anchoring post .

[0031] In some aspects, the conductive contact layer extends laterally from the sidewall, thereby forming an extension having the broken edge or the roughened surface . Optionally, the extension is substantially parallel to the emission surface . In some other aspects, the extension is located at a virtual symmetry axis through a center of the respective optoelectronic device, said virtual axis substantially perpendicular2024PF01085

[0032] to the sidewall when viewed from the top . The extension can also be located at a virtual symmetry axis through a center of the respective optoelectronic device, whereas said virtual axis is substantially going through an edge of two adj acent sidewalls of the device when viewed from top . Some other aspects concern a method for processing a plurality of optoelectronic devices or an optoelectronic device arrangement . Some other aspects concern a method for processing an optoelectronic arrangement . The method comprises providing a layer stack on a growth substrate . The layer stack comprises a first doped semiconductor, a second doped semiconductor and an active layer in between the two doped semiconductor layers . The semiconductor layer may comprise a plurality of sublayer having different material compositions and / or different doping profiles . In a subsequent step, a plurality of adj acent mesa-structured layer stacks are generated. The mesa structuring process can be varied and designed to the needs and design requirements . In some aspect, the mesa structuring process can be divided into different mesa etching steps interrupted and followed by respective cleaning and processing steps .

[0033] Then a passivation layer is deposited on the surfaces of the adj acent mesa-structured layer stacks . The step of depositing a passivation layer may include further sub-steps . In some instances , the passivation layer may comprise one or more conductive layers . for example the step of depositing a passivation layer may include a regrowth process after a mesa etching step to cover exposed sidewalls of the active layer .

[0034] A conductive contact layer is deposited on the passivation layer and on a portion of a bottom of the mesa-structured recess adjacent to a sidewall of the mesa-structured layer stacks . Material of the conductive contact layer therefore extends adj acent to a sidewall of the mesa structured layer stack, forming an extension, which subsequently acts as resting player for the anchoring post . In some aspects, the extension also forms a bridge between two adj acent layer stacks . The conductive contact layer contacts at least one of the first doped semiconductor and the second doped semiconductor through an opening in the passivation layer . It may contain one or more sublayer,2024PF01085

[0035] wherein at least some of them contain a metal or an ally as described further above .

[0036] A first sacrificial layer is then on the conductive contact layer such that a surface part of the contact layer above the bottom of the mesa-structured recess remains exposed . The exposed surface is then covered by a bonding material that is deposited on the first sacrificial layer and the exposed surface part of the contact layer . The bonding material may be in contact with the exposed surface from an anchoring post for mesa structured layer stack and the optoelectronic device . When the material of the sacrificial layer is removed, the device rests on the post at the resting area formed by the extension of conductive contact layer .

[0037] In some further optional steps , the plurality of adjacent mesa-structured layer stacks may be rebounded to gain access to the growth substrate . The growth substrate is then removed to access a surface of the first semiconductor layer stack . The semiconductor layer stack may be further structured, particularly from the exposed side to expose a surface of the conductive contact layer opposite the bonding material . Then, a second sacrificial layer is deposited on the exposed surface .

[0038] In a further aspect the step of generating a plurality of adj acent mesa-structured layer stacks comprises the step of conducting a mesa etching process , depending on the requirements, the mesa etching process exposes a substantially lateral portion of material of the first semiconductor adjacent to a sidewall . Hence, it leaves material of the first semiconductor layer behind and does not fully etch through . Alternatively, the etching process is conducted as to expose a substantially lateral portion of material of the growth substrate adjacent to a sidewall . In such case material of the first semiconductor adjacent to the sidewalls is fully removed .

[0039] SHORT DESCRIPTION OF THE DRAWINGS

[0040] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments2024PF01085

[0041] and examples described m detail m connection with the accompanying drawings in which

[0042] Figure 1 shows a first embodiment of an optoelectronic device arrangement in accordance with some aspects of the proposed principle;

[0043] Figures 2 illustrates a second embodiment of an optoelectronic device arrangement in accordance with some aspects of the proposed principle;

[0044] Figure 3 shows a third embodiment of an optoelectronic device arrangement in accordance with some aspects of the proposed principle;

[0045] Figure 4 illustrates two top views of optoelectronic devices in accordance with some further aspects of the proposed principle;

[0046] Figure 5 shows a fourth embodiment of an optoelectronic device arrangement in accordance with some aspects of the proposed principle;

[0047] Figure 6 shows a top view of optoelectronic devices in accordance with some further aspects of the proposed principle;

[0048] Figures 7A to 71 illustrate some method steps for processing an optoelectronic device arrangement in accordance with some aspects of the proposed principle .

[0049] DETAILED DESCRIPTION

[0050] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise, different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado, without this contradicting the principle according to the invention . Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without, however, contradicting the inventive idea .2024PF01085

[0051] In addition, the individual figures and aspects are not necessarily shown in the correct size, nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged. However, terms such as "above", "over", "below", "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0052] Figure 1 illustrates a first embodiment of an optoelectronic device arrangement in accordance with some aspects of the proposed principle . The optoelectronic device arrangement comprises a plurality of mesa structured layer stacks 10. Each layer stack comprises a first doped semiconductor region 11 forming the emission surface 100, an active region 12 as well as a second doped semiconductor region 13 stacked on each other . In the present example, the first doped semiconductor region 11 is n-doped, while the second doped semiconductor region is p-doped. The active region in between can comprise a quantum well, a multi-quantum well or a similar structure, optionally including a cladding layer and the like . The two doped layers may comprise a sublayer structure (not shown herein for simplicity) , wherein at least some of the sublayer comprise a different doping concentration or profile as well as a different material composition . To this extent, the proposed principle offers a flexible solution and is not restricted to a specific material system.

[0053] Each layer stack 10 is mesa structured and comprises a plurality of the sidewalls surrounding the respective mesa stack. When viewed from the top the sidewalls may constitute a square or rectangle . In some aspects, based on a specific material system and a crystallographic growth plane, a hexagonal shape may be preferred. In some instances , the shape follows the crystallographic planes .

[0054] The sidewalls are further treated like for instance, by additional doping to provide a quantum well intermixing . As an alternative, they are treated with a regrowth layer ( i . e . in phosphide material systems )2024PF01085

[0055] or other processes to obtain a reduced density of non-ref lective recombination centres and dangling bonds at the sidewall' s surface . These non-ref lective recombination centres are formed by the etching process during the mesa structuring and are usually deteriorating the internal quantum efficiency as they increase non-radiative recombination. All of the processing measures after the mesa etching process are combined in a passivation layer 20 covering the sidewalls and the main surface of the second doped semiconductor layer 13 opposing the top side 100 of the device .

[0056] The passivation layer 20 extends along the sidewalls from the emission surface 100 down to a surface of the second doped semiconductor layer 13 facing away from the emission surface . An central opening 21 is arranged in the passivation layer 20, thereby providing access to the second p-doped semiconductor layer 13 . P-doped semiconductor layer may be covered by a conductive transparent layer (e . g . ITO) for better contact, not shown in the embodiment . Specifically, in nitride-based material systems the doped semiconductor layer 13 may comprise an additional transparent conductive layer of ITO to provide a good adhesive and adhesion for a contact material for respective contact layer 30.

[0057] The openings 21 of each of the passivation layers 20 of the mesa-structured layer stack 10 are filled with a conductive metal of layer 30. The layer 30 extends along the surface of the passivation layer opposite the emission surface and on at least two opposing sidewalls , as shown in this cut view. The conductive layer 30 may comprise a metal or sublayer structure containing a plurality of different metals . Such metals may comprise, for example, Pt, Ni, Ti, Au, Ag, or a combination thereof, as well as a layer stack comprising one or more of such elements . Other possible metals include Sn and In, either alone, as a sublayer structure with one or more of the above metals or as an alloy.

[0058] Conductive contact layer 30 extends along the sidewalls to approximately the upper third of the sidewalls with regard to the emission surface 100. In other words , the metal layer extends along the passivation layer opposite the sidewalls of the second2024PF01085

[0059] semiconductor layer 13, the active layer 12 up to approximately the center of the first semiconductor layer 11. The material of the conductive layer then extends laterally from the sidewalls , forming a material bridge between two adjacent stacks . The metallic bridge between two adj acent mesa structure semiconductor layer stacks forms a resting region 31 for an anchoring post 45 ' made of a bonding material . The bonding material fills the gaps between the layer stacks and forms the post to which the resting area is attached . Anchoring post 45' is part of a bonding layer 40 that also covers the bottom surfaces completely, thereby providing an even surface . The anchoring post 45 ' is arranged to be in direct contact with resting region 31 of the conductive contact layer .

[0060] In accordance with the proposed principle, a material of a sacrificial layer 60 is arranged between the conductive contact layer 30 and the bonding material 40 along the surface opposite the emission surface 100 as well as on the sidewalls . A small portion of the sacrificial layer also extends on the metallic bridge and resting area of the conductive contact layer between two adj acent semiconductor layer stacks and comprises an opening thereon, which is filled by the bonding material, thereby forming anchoring post 45' . Furthermore, a second sacrificial layer material 70 is arranged on the surface of the conductive contact layer bridge 31 facing the emission surface 100. The second sacrificial layer 70 is flush with the emission surface 100.

[0061] Consequently, two sacrificial layers 60 and 70 are arranged, whereas the actual element bridging two adj acent layer stacks is only created by material of the conductive contact layer 30. Resting region 31 is therefore shared by two layer stacks . During the separation process , the sacrificial layer 70 as well as the sacrificial layer 60 are etched away, such that only the posts 45 ' remain and are attached to the resting area 31 of the conductive contact layer 30. These resting areas are holding the respective mesa-structured layer stacks . A stamp or any similar means can be used to lift and break the material of the conductive contact layer 30 in the resting area 31.2024PF01085

[0062] Figure 2 illustrates a similar embodiment, m which the resting area 31 is only connected to a contact conductive layer 30 of one layer stack 10 , but is not shared between two adjacent mesa-structured layer stacks 10 as in Figure 1. The proposed anchoring post 45' is arranged in a similar fashion, essentially on the resting area 31. The sacrificial layer 60 extends along the sidewalls and covers partially the resting area 31 , except for the small opening through which the material of the bonding layer 40 is attached to the resting area 31. The second sacrificial layer 70 is located opposite the resting area 31 towards the main emission surface 100. The material of sacrificial layer 70 is the same as the material of sacrificial layer 60 and may comprise, for example, silicon dioxide SiO2 . The material can be easily removed by using a fluoride containing a gas or liquid, respectively.

[0063] A further embodiment is illustrated in Figure 3 . In contrast to the previous embodiments , the conductive contact layer 30 extends along the sidewalls all the way up to the top, directly adjacent to the emission surface 100. The material of the conductive contact layer 30 extends laterally from the top portion and forms the resting area 31 laterally displaced from the sidewalls . The anchoring post of the bonding material fills the gap formed by the mesa etching process and is attached to the resting area 31 of the metal . Similar to the embodiment in Figure 1 , resting area 31 is used as a common resting area, and the anchoring post is shared among two adjacent semiconductor layer stacks .

[0064] In the present embodiments, particularly in Figure 1 , the common anchoring posts are arranged between two adjacent semiconductor layer stacks . In other words, the semiconductor layer stacks as well as the commonly shared resting areas 31 extend along a plurality of adj acent located and positioned mesa-structured layer stacks . Two resting areas 31 can be aligned to a single mesa stack. This provides additional stability during the transfer process . For example, during a removal of the respective mesa structured layer stacks using a stamp, a more equal force is applied to the emission surface 100 distributed towards the two anchoring posts without the risk of an uneven adhesion .2024PF01085

[0065] However, m some aspects , only a pair of semiconductor layer stacks 10 is combined and attached to a common shared anchoring post 45' . Such embodiment is illustrated in the left drawing of Figure 4 from a top view . A commonly conductive contact layer material 31 is used as a bridge between two adj acent semiconductor layer stacks . The size and diameter of the bridge 31 that is the overall resting area 31 of the conductive contact layer is larger than the respective anchoring post 45 ' . The material bridge and the resting area extend from approximately the centre of the sidewall, as shown, and not from one of the edges .

[0066] During the removal process , the stamp can either pick one of the layer stacks or both layer stacks simultaneously and remove them from the anchoring post .

[0067] The right drawing of Figure 4 illustrates an embodiment, in which the material of the conductive contact layer 30 is not located over the side portion of the sidewall, but actually across an edge of two adjacent sidewalls . Consequently, the resting position is adjacent to an edge of the mesa conductive layer stack when viewed in a top view, as illustrated in Figure 4B . Furthermore, the resting areas 31 are not shared between various and different semiconductor layer stacks, but each resting area attached to a respective anchoring post 45 ' is associated with a single mesa stack.

[0068] In a further embodiment, one can use of the proposed principle to also attach horizontal pLEDs and generally LEDs on such anchoring posts . An optoelectronic device, in which both contact areas are arranged on the same side and the same surface of the respective device, is referred to as a horizontal pLED or more generally, a horizontal LED . In contrast thereto, a vertical LED or vertical optoelectronic device, is a device in which the contacts are arranged on opposing sides . While the embodiments to Figure 1 and Figure 3 represent substantially vertical optoelectronic devices , the embodiment of Figure 5 illustrates a horizontal optoelectronic device .

[0069] The optoelectronic device comprises a mesa-structured semiconductor layer stack having a first doped semiconductor layer 11, a multi-2024PF01085

[0070] quantum well structure 12 , and a second doped semiconductor layer 13. The layer stack is mesa structured and comprises sidewalls , which are subsequently passivated using the passivation layer 20. The passivation layer 20 extends along the sidewalls and on the bottom surface of the second doped semiconductor layer 13 with two openings therein. One opening 21 is connected to the contact material 30 , forming, for example, a p-contact . The material of layer 30 can be the same as described above and includes a metal, for example .

[0071] The second opening comprises an isolated via through the p-doped semiconductor layer 13 , the active region 12 , and into the n-doped semiconductor layer 11. The isolated via is filled with another conductive material 32 ' , which extends along the sidewall 30' towards the resting region 31' laterally displaced from the layer stack. This extension is below the level of emission surface 100. Conductive material 31' also includes metal, like the one described above . Similar to the previous embodiment, the resting area is attached to an anchoring post 45 formed of a material of bonding layer 40. The anchoring post is surrounded by material of a sacrificial layer 60 covering the remaining portions of the resting area and the sidewalls of the conductive contact layer 30' . The resting area 31' is also surrounded by material of the sacrificial layer 60 of the adjacent layer stack . Material of a second sacrificial layer 70 fills the space between the emission surface 100 and the surface of the conductive contact layer and resting area 31' opposing the anchoring post 45' . Material of sacrificial layer 70 and sacrificial layer 60 are the same, similar to the previous embodiments .

[0072] The benefit of this embodiment in comparison to vertically implemented LEDs becomes apparent when reviewing a top view, in accordance with Figure 6. Figure 6 illustrates the top view with the two contact areas , that is, the n-contact and the p-contact . Both contacts 30 and 30' are located on the bottom surface of the optoelectronic devices, with the emission surface being the opposite side . The two contacts are surrounded by the passivation layer 20. The material bridge for the conductive contact layer 30 extends from n-contact area 30' towards the anchoring post 45' .2024PF01085 16

[0073] While it is possible to provide the resting place and the material bridge also from the p-contact 30, it is probably advisable to do that from the n-contact . This is because the material bridge is located close to the n-doped semiconductor, and in case of a short circuit, the current flows into the n-doped semiconductor . The conductive contact layer 30' also extends over an edge of two adj acent sidewalls . Figures 7A to 71 illustrate an embodiment of a method of processing a plurality of optoelectronic devices to provide an optoelectronic device arrangement in accordance with some aspects of the proposed principle .

[0074] A semiconductor layer stack is grown on a growth substrate 80 as shown in Figure 7A. The semiconductor layer stack comprises a first doped semiconductor layer 11 , an active region 12 deposited on the surface of the first doped semiconductor layer 11 and a second doped semiconductor layer 13 on top of the active region . Doping concentrations and doping profiles, as well as the respective material systems of semiconductor layers 11 , 12 and 13 are known in the art . Several different base material systems like nitride, phosphide or arsenide material systems are suitable for this purpose . Semiconductor layer can also comprise a conductive transparent sublayer being its top exposed surface .

[0075] A hard mask layer 81 is deposited on top of the surface of the second doped semiconductor layer 13. The hard mask layer 81 subsequently structured such that certain areas of the top surface of the second doped semiconductor layer 13 are exposed . The hard mask material is resilient against the following etching process, which is performed either in a single step, or in several steps depending on the design limitations and the base material, for example . The various methods and etching components suitable for such mesa etching steps are known to the skilled person . It is appreciated that the skilled person will recognize that the mesa etching steps can be varied and adjusted to the needs and requirements of the design, the base material system, and the other parameters of the devices . For the simplicity of illustration, only a single be the etching step is illustrated .2024PF01085 17

[0076] Figure 7B illustrates the result of the mesa etching process . In this example a mesa etching process exposes the sidewalls of the doped semiconductor layer 13, the active region 12 and further extends into the doped semiconductor layer 11 , but does not reach the surface of the growth substrate 80. In other words, small portion of the semiconductor layer 11 is still present .

[0077] However, particularly this process step can vary, and the mesa etching process is performed until the surface of the growth substrate 80 is reached. In such a case, another subsequent step is applied, in which exposed surfaces of growth substrate 80 are covered by the material of the sacrificial layer 70. However, in other alternatives, as illustrated further below, this last step of depositing the material of sacrificial layer 70 as in the previous embodiments can be performed later .

[0078] In a subsequent step, the mask layer material 81 is removed and a passivation layer 20 is applied on the respective sidewalls and on the surface of the semiconductor layer 13, see Figure 7C . The deposition of the passivation layer is dependent on the material used and the implementation and design approach . An opening 21 is then created on the top surface of the passivation layer 20 , thereby exposing a surface portion of the semiconductor layer 30. Then, the opening as well as the surface of the passivation layer is subsequently covered by material of a conductive contact layer 30. The resulting structure is shown in Figure 7D. The conductive contact layer 30 usually comprises a metal or any other suitable conductive material . Depending on the implementation, a plurality of different metal layers can be used as the conductive contact layer 30.

[0079] Following in a subsequent step, a material of the sacrificial layer 60 is applied on the surface of the conductive contact layer 30 covering the surface over the top portion of semiconductor layer 13 as well as in between the adj acent mesa structured layer stacks . The resulting structure is illustrated in Figure 7E . Then, a small mask material is applied and a portion of the sacrificial layer 60 within the recesses is removed, thereby exposing the surface of the conductive contact2024PF01085 18

[0080] layer 30 again. The resulting structure is illustrated m Figure 7F with its opening 450.

[0081] In this regard, it is possible to first deposit a small mask material within the recess at the area of the resting region 31 of contact layer 30 and then deposited the material of the sacrificial layer 60. In both cases, the surface of conductive contact layer 30 is exposed by opening 450 providing the resting region 31 for the subsequently deposited bonding material as illustrated in Figure 7G. The bonding material 40 fills the opening, wherein the recesses , thereby providing the proposed 45 ' area

[0082] In a subsequent step, a temporary carrier is attached to the bonding layer 40, and the corresponding devices are flipped to provide access to the growth substrate 80. The growth substrate 80 is removed to gain access to the emission surface 100 of the semiconductor layer 100.

[0083] Then, another mask layer material 81' is deposited on the exposed surface of semiconductor layer 11 and subsequently structured to have certain areas exposed above the recesses caused by the mesa structuring process . The results are presented in Figure 7H . The final subsequent step illustrated in Figure 71, and an opening is etched into the semiconductor layer material 11 and through the passivation layer 20 in the area opposite the anchoring post 45. The etching process exposes the surface of the conductive contact layer 30 opposite the anchoring post 45 ' . The recess is then filled in this embodiment by a second sacrificial layer material 70. The optical device arrangement is then finished and prepared for further processing .

[0084] For the placement process of the individual optoelectronic devices of the device arrangement, the sacrificial layers 70 and 30 are removed using a fluoride induced process . This leaves the anchoring posts 45 ' of the bonding layer material unharmed whereas the respective devices , more particularly conductive contact layer 30 with its resting region 31 still being adhered to the anchoring posts 45' . A stamp or any other removing mechanism cannot be used to break the respective devices away from the anchoring posts 45' .2024PF01085 19

[0085] The benefit of resting the conductive contact layer 30 with a laterally displaced resting area 31 on the anchoring posts 45 lies in a separation of the posts away from the semiconductor material of the device itself .

[0086] 5 Consequently, during the separation procedure, only a portion of the conductive contact layer material may break from the device, but the semiconductor material itself or the active region is not damaged thereby. Particularly, mechanical stress is mainly induced in the conductive contact layer material itself and not in the semiconductor .

[0087] 0 The breaking edge is rather small and does not tamper with the functionality of the device .2024PF01085 20

[0088] LIST OF REFERENCES

[0089] 1 device arrangement

[0090] 5 10 layer stack

[0091] 11 , 13 doped semiconductor layers

[0092] 12 active region

[0093] 20 , 20 passivation layer

[0094] 21 opening

[0095] 0 30 , 30' conductive contact layer

[0096] 31 resting area

[0097] 32 conductibe material

[0098] 40 bonding material

[0099] 45 45' anchoring post

[0100] 5 60 , 70 sacrificial layer

[0101] 80 , 81 mask layer

[0102] 100 emission surface

Claims

2024PF01085CLAIMS1. Optoelectronic device arrangement comprising :A bonding wafer comprising a plurality of anchoring posts;A plurality of optoelectronic devices arranged on the bonding wafer, each of the plurality of optoelectronic devices having a mesa structured layer stack, said layer stack comprising an active layer arranged between a first doped semiconductor layer and a second doped semiconductor layer, whereas a surface of the second doped semiconductor layer is facing the bonding wafer;wherein each of the plurality of optoelectronic devices further compriseso a conductive contact layer being in electrical contact with one of the first and second semiconductor layer and extending at least across a portion of a sidewall of the respective mesa structured layer stack;wherein the conductive contact layer forms a resting region, said resting region laterally displaced from the portion of the sidewall ;wherein each anchoring post of the plurality of anchoring posts is attached to the resting region.

2. Optoelectronic device arrangement according to claim 1 , wherein the conductive contact layer of two adj acent optoelectronic devices of the optoelectronic devices share a common resting place .

3. Optoelectronic device arrangement according to any of the preceding claims, wherein the conductive contact layer extends laterally from the sidewall thereby forming an extension comprising the resting region, wherein optionallythe extension is located at a virtual symmetry axis through a center of the respective optoelectronic device said virtual axis substantially perpendicular to the sidewall when viewed from top; orthe extension is located at a virtual symmetry axis through a center of the respective optoelectronic device; said virtual axis2024PF01085substantially going through an edge of two adj acent sidewalls of the device when viewed from top .4 . Optoelectronic device arrangement according to any of the preceding claims, wherein a anchoring post comprises a diameter smaller than a diameter of the resting region.5 . Optoelectronic device arrangement according to any of the preceding claims, wherein the resting region is vertically displaced with regards to a surface of the first semiconductor facing away from the bonding wafer; and in particularly below a level of said surface .

6. Optoelectronic device arrangement according to any of the preceding claims, further comprising a first sacrificial layer material on a surface of the resting region opposite the anchoring post, said sacrificial layer optionally being flush with the surface of the first semiconductor facing away from a bonding wafer .7 . Optoelectronic device arrangement according to any of the preceding claims, further comprising a second sacrificial layer arranged on the conductive contact layer .8 . Optoelectronic device arrangement according to any of the preceding claims, wherein a portion of the second sacrificial layer extends laterally from sidewalls onto a part of the resting region .

9. Optoelectronic device arrangement according to any of the preceding claims, wherein the first and second sacrificial layer comprise the same material, in particularly Si02 .10 . Optoelectronic device arrangement according to any of the preceding claims, wherein each of the plurality of optoelectronic devices further comprises :a passivation layer arranged on the sidewalls of the mesa structured layer stack and the surface of the second doped semiconductor layer facing the bonding wafer and comprising an opening, that is filled by material of the conductive contact2024PF01085layer thereby contacting the second doped semi conductor layer; ora passivation layer arranged on the sidewalls of the mesa structured layer stack electrically isolating the conductive layer from the surface of the second doped semiconductor layer a via through the passivation layer, the second doped semiconductor and the active region that is filled by material of the conductive contact layer electrically isolated from the second doped semiconductor and the active region and contacting the first doped semiconductor layer .11 . Optoelectronic device arrangement according to any of the preceding claims, wherein each of the plurality of optoelectronic devices further comprises the shape of a rectangle, a quadrat, a hexagon or a circle .12 . Optoelectronic device arrangement according to any of the preceding claims, wherein the conductive contact layer comprises at least one from a group consisting of :- Pt;- Ni;- Ti;- An layer stack comprising Pt, Ni and Ti;- Sn;- In;- An alloy or layer stack comprising Sn and Au; and- An alloy or layer stack comprising In, Sn and Au .13 . Optoelectronic device comprising :A mesa structured layer stack, said layer stack comprising an active layer arranged between a first doped semiconductor layer and a second doped semiconductor layer, whereas a surface of the first doped semiconductor layer comprises an emission surface;A passivation layer on the sidewalls of the mesa structured layer stack and a surface of the second doped semiconductor facing away from the emission surface;2024PF01085 24conductive contact layer arranged on the passivation layer and being in electrical contact with one of the first and second semiconductor layerthe conductive contact layer extending at least across a portion of a sidewall of the respective mesa structured layer stack and comprising a broken edge adjacent to said portion of the sidewall .14 . Optoelectronic device according to claim 13, wherein the conductive contact layer extends laterally from the sidewall thereby forming an extension having the broken edge; wherein optionally the extension is substantially parallel to the emission surface .15 . Optoelectronic device according to claim 13 , whereinthe extension is located at a virtual symmetry axis through a center of the respective optoelectronic device, said virtual axis substantially perpendicular to the sidewall when viewed from top; orthe extension is located at a virtual symmetry axis through a center of the respective optoelectronic device; said virtual axis substantially going through an edge of two adj acent sidewalls of the device when viewed from top .

16. Method for processing an optoelectronic arrangement comprising the step of :Providing a layer stack on a growth substrate, the layer stack comprising a first doped semiconductor, a second doped semiconductor and an active layer in betweenGenerating a plurality of adjacent mesa-structured layer stacks ; Depositing a passivation layer on the surfaces of the adj acent mesa-structured layer stacks ;Depositing a conductive contact layer on the passivation layer and on a portion of a bottom of the mesa-structured recess adjacent to a sidewall of the mesa-structured layer stacks , said conductive contact layer contacting at least one of the first doped semiconductor and the second doped semiconductor through an opening in the passivation layer;2024PF01085Depositing a first sacrificial layer on the conductive contact layer such that a surface part of the contact layer above the bottom of the mesa-structured recess remains exposed; Depositing a bonding material on the first sacrificial layer and 5 the exposed surface part of the contact layer .17 . Method according to claim 16, further comprising the steps of : rebonding the plurality of adj acent mesa-structured layer stacks and removing the growth substrate to access a surface of the 0 first semiconductor layer stackstructuring the semiconductor layer stack to expose a surface of the conductive contact layer opposite the bonding material; depositing a second sacrificial layer on the exposed surface .5 18 . Method according to claim 17 , wherein the step of generating a plurality of adj acent mesa-structured layer stacks comprises the step of conducting a mesa etching process , therebyExposing a substantially lateral portion of material of the first semiconductor adjacent to a sidewall; or0 Exposing a substantially lateral portion of material of the growth substrate adjacent to a sidewall .

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