Nonvolatile integrated circuit

Abstract

This invention addresses the problem of providing a new nonvolatile integrated circuit capable of significantly reducing energy overhead.　This problem is solved through a non-volatile integrated circuit in which individual pieces of bit information stored and retained by a plurality of flip-flops during power supply are saved and retained in a non-volatile storage area upon the interruption of power, the non-volatile integrated circuit being characterized by being composed of N bits, and the non-volatile storage area being composed of N+1 magnetic tunnel junction elements.

Description

Non-volatile integrated circuit

[0001] The present invention relates to a non-volatile integrated circuit incorporating a non-volatile memory element inside a chip.

[0002] The power consumption of a semiconductor integrated circuit consists of dynamic power consumption and static power consumption. Dynamic power consumption is the power consumed during circuit operation, i.e., when the transistor circuit is switching, and static power consumption is the power that is continuously consumed by the leakage current of the transistor regardless of whether the circuit is operating or not. With the high integration of circuits, the proportion of static power consumption in the power consumption of semiconductor integrated circuits has been increasing in recent years, and how to reduce static power consumption has become an issue. In particular, in IoT technology, edge devices such as mobile terminals and in-vehicle products continue to be in a standby state for a while after executing processing, so reducing static power consumption is an urgent issue.

[0003] Generally, a method is used that cuts off the power supply during non-operation and transfers the information held in the volatile memory to an external non-volatile memory to avoid generating static power consumption. This method is called power gating technology. FIG. 1 is a graph for explaining the concept of power consumption reduction in power gating technology, where the horizontal axis is the time axis and the vertical axis indicates the power consumption. Of the two graphs shown in FIG. 1, the left graph shows the transition of power consumption of a conventional semiconductor circuit, and the right graph shows the transition of power consumption of a semiconductor integrated circuit using power gating technology.

[0004] The graph on the left shows that the computation execution period, i.e., the period during which dynamic power consumption occurs, is interrupted, while the period during which static power consumption occurs due to transistor leakage current is continuous. On the other hand, the graph on the right shows that, with power gating technology, no static power consumption occurs during the period when the power supply is cut off. However, even when transitioning from the computation execution period to the period when the power supply is cut off, i.e., the power gating period, power consumption occurs due to the backup process that saves information held in volatile memory to external non-volatile memory. Similarly, when transitioning from the power gating period to the computation execution period, power consumption occurs due to the restore process that returns the information saved to external non-volatile memory back to volatile memory. The energy loss associated with these power consumptions and the loss of circuit utilization opportunities, which is the sum of the time required for processing, are called overhead. Overhead reduces the power consumption reduction effect of power gating technology and decreases the period during which computation operations can be performed. According to previous research, the energy consumed when exchanging data with memory such as DRAM is 10 times the energy consumed during computation. 4 It is said that this can double, causing increased overhead. If overhead can be reduced, the power reduction effect of power gating technology can be greatly increased, and the period during which computational operations can be performed can be extended.

[0005] To reduce overhead, instead of saving information held in volatile memory to external non-volatile memory, non-volatile LSIs (Large-Scale Integration) incorporating non-volatile memory elements within the chip have been proposed. Non-volatile LSIs are a fusion of logic-in-memory integrated circuit technology and non-volatile device technology. Logic-in-memory integrated circuit technology significantly reduces global wiring by distributing memory functions within the arithmetic circuit, thereby preventing transfer delays and reducing dynamic power consumption. Non-volatile device technology eliminates the need for data transfer to external memory, enabling rapid power supply cutoff and reducing power consumption. Furthermore, non-volatile device technology significantly reduces circuit size by directly stacking memory devices in CMOS. As a non-volatile device, non-volatile logic circuit technology utilizing magnetic tunnel junction elements (MTJ elements), which are a type of spintronic element, is known.

[0006] Non-volatile power gating using non-volatile logic circuits allows for the non-volatile nature of all modules in an integrated circuit, enabling fine-grained power gating. Therefore, it is expected to significantly reduce wasted power consumption compared to power gating combining volatile logic circuits and external storage circuits. Figure 2 shows schematic diagrams and graphs illustrating the difference in power consumption reduction between power gating using external storage and non-volatile power gating. The upper left diagram shows power gating combining volatile LSIs and external storage circuits, while the lower left diagram shows non-volatile power gating using non-volatile LSIs (NV-LSIs). Corresponding to each schematic diagram, the right side shows graphs where the horizontal axis represents time and the vertical axis represents stored energy.

[0007] Power gating using external storage results in a small drop in stored energy during restore operations, and the overhead is not particularly large. However, during backup operations, the drop in stored energy is large, and the overhead is significant. On the other hand, non-volatile power gating also results in a small drop in stored energy during backup operations, thus reducing overhead. Comparing the graphs above and below, it can be seen that the slope of energy change during the dynamic power consumption period, i.e., the computation execution period, is the same. This indicates that the dynamic power consumption period, i.e., the energy that can be spent on performing calculations and the period during which calculations can be performed, is significantly larger.

[0008] Meanwhile, in IoT technology, energy harvesting, which extracts and utilizes energy from the surrounding light and vibrations, has been attracting attention in recent years. Energy harvesting has the potential to provide virtually unlimited energy and realize battery-less edge devices. However, the energy supplied by energy harvesting is weak and unstable, and in order for edge devices to stably process information, it is necessary to repeatedly store energy and then consume it by executing tasks once a certain amount has been accumulated. This kind of stepwise task execution through power management is called intermittent computing, and the development of this technology is extremely important for using energy harvesting as an energy source.

[0009] Intermittent computing theoretically utilizes the same mechanism as the aforementioned power gating technology that does not rely on energy harvesting. However, while power gating technology that does not rely on energy harvesting saves data just before entering a standby state after a series of processes are completed, intermittent computing, which executes tasks in stages, frequently requires cutting off the power supply midway through processing to save data. Therefore, overhead needs to be minimized as much as possible. To reduce overhead, development needs to be carried out from two perspectives: selecting effective devices as non-volatile memory elements embedded inside the chip, and realizing effective circuit layouts that contribute to low energy consumption.

[0010] Effective non-volatile memory elements require characteristics where the resistance value changes under certain conditions but remains stable in a static state. The inventors have focused their research on MTJ elements (magnetic tunnel junction elements). MTJ elements have advantageous characteristics compared to other non-volatile memory elements in terms of write time, write endurance, and compatibility with CMOS. Figure 3 illustrates the characteristics of a magnetic tunnel junction element (MTJ element). An MTJ element, a type of spintronic element, has a three-layer structure with an insulating layer between two magnetic layers. In the figure, the upper magnetic layer is a free layer in which the sign of the spin current changes depending on the sign of a current of a certain magnitude, while the lower magnetic layer is a fixed layer in which the sign of the spin current does not change regardless of the sign of the current. By applying a rewrite current above the inversion threshold, the MTJ element can take on two states: a parallel state in which the spin currents of the two magnetic layers are in the same direction, and an antiparallel state in which the spin currents of the two magnetic layers are in opposite directions. An MTJ element exhibits low resistance (Rp) in a parallel state and high resistance (Rap) in an antiparallel state. As shown in the resistance-current characteristic of Figure 3, when a current greater than or equal to Iap-p is applied when the resistance is high (Rap), the resistance value changes to low resistance (Rp). However, even if the applied current is removed in this state, the resistance value does not change. However, when a current greater than or equal to Ip-ap is applied in the reverse direction, the resistance value changes to high resistance (Rap). These two resistance values ​​are used as bit information. Thus, an MTJ element can be described as an element that possesses two properties: that of a variable resistor and that of a non-volatile memory.

[0011] To explain effective circuit configurations that contribute to low energy consumption, we will first describe the basic conventional circuit configuration. Figure 4 is a circuit diagram of a non-volatile flip-flop (hereinafter sometimes referred to as "NV-FF") that constitutes a conventional non-volatile register. By arranging NV-FFs for the required number of bits, it will function as a non-volatile register. An NV-FF is a flip-flop equipped with a non-volatile power gating function, and in the example shown here, a master-slave type D flip-flop is given the function of saving data to an MTJ element and the function of restoring data from the MTJ element.

[0012] While power is supplied, data is held by two latches, just like a normal flip-flop. However, just before the power is cut off, a backup circuit applies a rewrite current to the MTJ element, performing a backup process. Then, when power is restored, the slave latch acts as a sense amplifier, reading the resistance difference, and a restore process is performed to return the bit information held by the MTJ element to the D flip-flop.

[0013] Thus, an NV-FF (Non-Variable Flip-Flop) associates two MTJ (Multi-Turn Switch) elements with the complementary outputs of a flip-flop, and holds bit information based on the difference in their resistance states. Therefore, writing is performed to both MTJ elements so that they are in a complementary resistance state of either Rp, Rap or Rap, Rp. However, writing to MTJ elements requires a relatively large current, which leads to a situation where backup processing accounts for the majority of the energy consumption overhead, as shown in the upper graph of Figure 2.

[0014] In addition to the overhead of energy consumption, NV-FFs require large transistors capable of supplying sufficient current to the MTJ elements. The inversion threshold current of the MTJ elements is around 100 μA at room temperature, which cannot be supplied by transistors of normal size. Only by using multiple dedicated backup control transistors with gate widths 4 to 12 times larger can data be written. Thus, in conventional non-volatile registers using NV-FFs (hereinafter sometimes simply referred to as "conventional configurations using NV-FFs"), the writing transistor occupies most of the area, resulting in significant overhead.

[0015] To address the energy consumption overhead and area overhead issues described above, the inventors have developed a non-volatile register based on a shared reference scheme (hereinafter sometimes referred to as "RLSS") that holds one bit of information using a reference resistor used in common by each bit and the resistance value of a single data-holding MTJ element, as shown in Non-Patent Document 1.

[0016] T. Yoshida, M. Natsui, T. Hanyu, "Design of an Energy / Area-Aware MTJ-Based Nonvolatile Register with a Reference-Load Sharing Scheme," 2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS2024), pp.1257-1261, 2024.

[0017] This document explains the advantages of a non-volatile register based on a shared reference scheme (RLSS) (hereinafter referred to as the "RLSS configuration") compared to a conventional configuration using NV-FFs. Figure 5 is an explanatory diagram showing how the conventional NV-FF configuration and the RLSS configuration retain bit information, with the top showing the conventional NV-FF configuration and the bottom showing the RLSS configuration. In the conventional NV-FF configuration, two MTJ elements are used per bit to create and compare the difference in resistance values ​​necessary for the restore process from the MTJ elements, and both MTJ elements are written to so that they are in a complementary resistance state of either Rp, Rap or Rap, Rp.

[0018] On the other hand, in a configuration using RLSS, a reference MTJ element with a resistance value intermediate between high and low resistance is prepared, and bit information is read by comparing the resistance value of this reference MTJ element with the resistance value of the data-holding MTJ element. In a configuration using a shared reference method, the number of MTJ elements that write per bit is reduced from two to one compared to the conventional configuration using NV-FF. This makes it possible to significantly reduce the writing energy to the MTJ elements that rewrite values. As shown in the figure, the reference MTJ element with a resistance value intermediate between high and low resistance employs a structure that obtains an intermediate resistance value by combining four MTJ elements that have the same resistance value as the data-holding MTJ element.

[0019] The RLSS configuration allows for significant reductions in energy consumption and area. However, because the circuit configuration does not allow for simultaneous writing and reading operations on multiple MTJ elements, sharing a reference resistor among many MTJ elements results in longer writing and reading times compared to conventional configurations.

[0020] In view of these problems, the present invention aims to provide a novel non-volatile integrated circuit that can significantly reduce energy overhead.

[0021] To solve these problems, the present invention provides a non-volatile integrated circuit that stores and holds bit information in a plurality of flip-flops when power is supplied, and stores this information in a non-volatile memory area when power is cut off, characterized in that the non-volatile integrated circuit is composed of N bits, and the non-volatile memory area is composed of N+1 magnetic tunnel junction elements.

[0022] This configuration allows for a significant reduction in energy overhead.

[0023] Furthermore, the present invention is characterized in that one magnetic tunnel junction element is associated with the flip-flop constituting the nth bit, and the state of the flip-flop constituting the nth bit (0 or 1) is linked to the agreement or mismatch between the resistance value of the nth magnetic tunnel junction element and the (n+1)th magnetic tunnel junction element.

[0024] This configuration allows for a significant reduction in energy overhead using a method different from RLSS.

[0025] Furthermore, the present invention is characterized in that writing to and reading from the non-volatile memory area is performed in two cycles in which processing of odd-numbered magnetic tunnel junction elements and processing of even-numbered magnetic tunnel junction elements are performed alternately.

[0026] This configuration allows for significant reductions in energy overhead while still enabling backup and restore operations to be performed in the same short time as with conventional NV-FF configurations.

[0027] Furthermore, the present invention is characterized in that writing to the nth magnetic tunnel junction element of the non-volatile memory area is performed based on the output of an exclusive OR circuit, and the output of the (n-1)th exclusive OR circuit (however, a predetermined value when n=1) and the output of the nth flip-flop are connected to the input of the exclusive OR circuit.

[0028] With this configuration, backup operations can be performed with a simple setup.

[0029] Furthermore, the present invention is characterized in that the reading from the non-volatile memory area is performed using a magnetic tunnel junction element identical / unequal state reading circuit that outputs 0 or 1 depending on whether the resistance values ​​of adjacent magnetic tunnel junction elements match or do not match.

[0030] With this configuration, the restore operation can be performed using a method different from RLSS.

[0031] Furthermore, the present invention relates to an N-bit non-volatile integrated circuit that stores and holds bit information in a plurality of flip-flops when power is supplied, and stores this information in a non-volatile memory area when power is cut off, comprising N+1 magnetic tunnel junction elements and a control unit, wherein the control unit performs writing to the nth magnetic tunnel junction element in the non-volatile memory area by connecting the output of the (n-1)th exclusive OR circuit (however, a predetermined value if n=1) and the output of the nth flip-flop to the input of the exclusive OR circuit based on the output of the exclusive OR circuit, and the control unit performs reading by outputting 0 or 1 depending on whether the resistance values ​​of adjacent magnetic tunnel junction elements match or do not match.

[0032] This configuration significantly reduces energy overhead while enabling backup and restore operations to be performed quickly, similar to conventional NV-FF configurations, with a simple circuit design.

[0033] This is a graph illustrating the concept of power consumption reduction in power gating technology. This is a schematic diagram and graph illustrating the difference in power consumption reduction between power gating using external storage and non-volatile power gating. This is a diagram illustrating the characteristics of a magnetic tunnel junction (MTJ) element. This is a circuit diagram of a non-volatile flip-flop that constitutes a non-volatile integrated circuit. This is an explanatory diagram showing how a conventional configuration using NV-FF and a configuration using RLSS hold bit information. This is an explanatory diagram showing how a configuration using DISS holds bit information. This is an explanatory diagram showing the read operation of a configuration using DISS. This is an explanatory diagram comparing the write and read operations of a conventional configuration using NV-FF, and configurations using RLSS and DISS. This is a circuit diagram of a non-volatile integrated circuit according to an embodiment of the present invention. This is a diagram illustrating the backup process of a non-volatile integrated circuit according to an embodiment of the present invention. This is a diagram illustrating the restore process of a non-volatile integrated circuit according to an embodiment of the present invention. This is a diagram illustrating the structure of a read circuit in a configuration using DISS. This is a diagram illustrating the operation of a read circuit in a configuration using DISS. This graph shows the verification results for the conventional configuration using NV-FF, and configurations using RLSS and DISS.

[0034] This invention is based on logic-in-memory integrated circuit technology and non-volatile device technology, enabling high density and overhead reduction. To understand this invention, it is necessary to first understand the differential information storage method, in which a non-volatile memory area composed of N+1 magnetic tunnel junction elements holds bit information in an N-bit integrated circuit. This point will be explained below. The following explanation will use drawings, but these drawings are created for explanatory purposes and may intentionally omit elements that are not necessary for the explanation in order to make them easier to understand. Also, for explanatory purposes, some elements may be intentionally made larger or smaller in the drawings and do not represent the exact scale.

[0035] (Differential Information Storage Method) This invention proposes a new storage method called the differential information storage method (hereinafter sometimes referred to as "DISS (Differential Information Storage Scheme)"), and provides a circuit configuration for which a non-volatile storage area consisting of N+1 magnetic tunnel junction elements (MTJ elements) is provided for an N-bit integrated circuit. Figure 6 is an explanatory diagram showing how a non-volatile register based on the differential information storage method (hereinafter sometimes referred to as "configuration using DISS") holds bit information, and a truth table is shown below. Figure 7 is an explanatory diagram showing the read operation of the configuration using DISS.

[0036] In a configuration using DISS, as shown in Figure 6, one bit of information is held by the difference in the resistance state patterns of two adjacent MTJ elements. Specifically, "0" is assigned when the resistance states match, i.e., when they are Rp, Rp or Rap, Rap, and "1" is assigned when the resistance states do not match, i.e., when they are Rp, Rap or Rap, Rp. In this method, N bits of information are held among N+1 MTJ elements, and if the resistance state of the leading MTJ element is fixed, the number of MTJ elements that need to be rewritten is only N. Therefore, a configuration using DISS, like a configuration using RLSS, can reduce energy consumption and circuit area during data saving.

[0037] In a configuration using DISS, each MTJ element serves both as a data-holding MTJ element and as a resistor used as a reference during reading. As a result, as shown in Figure 7, when reading data held in an even-numbered MTJ, an odd-numbered MTJ element is referenced, and when reading data from an odd-numbered MTJ element, an even-numbered MTJ element is referenced, making it possible to perform simultaneous read operations for both even and odd bits. For example, when reading odd bits such as the 1st and 3rd bits, as shown in the upper part of Figure 7, the resistance values ​​of the 0th and 1st MTJ elements and the 2nd and 3rd MTJ elements can be compared simultaneously. On the other hand, when reading even bits such as the 2nd and 4th bits, as shown in the lower part of Figure 7, the resistance values ​​of the 1st and 2nd MTJ elements and the 3rd and 4th MTJ elements can be compared simultaneously.

[0038] Figure 8 is an explanatory diagram comparing the write and read operations in the conventional configuration using NV-FF and the configurations using RLSS and DISS. The N-bit non-volatile register configured with NV-FF is composed of 2N MTJ elements, and write and read operations are performed in parallel. In the configuration using RLSS, an N-bit register can be configured with N+4 MTJ elements, but in this method, write and read operations must be performed serially, so each backup and restore operation requires N cycles. As the number of bits increases, the number of required cycles increases proportionally. In contrast, the configuration using DISS can configure an N-bit register with N+1 MTJ elements, and in addition, backup and restore operations can be performed in 2 cycles each, regardless of the size of the register. In other words, backup and restore processing can be performed in a constant number of cycles, regardless of the number of bits. Having explained the operating mechanism that forms the basis of the present invention, we will now describe specific embodiments of the present invention.

[0039] <Embodiments of the Invention> (Configuration of Non-Volatile Register) Figure 9 is a circuit diagram of a non-volatile integrated circuit according to an embodiment of the present invention. Here, an example of a non-volatile register is shown. The non-volatile register 100 according to an embodiment of the present invention is an N-bit register, and as can be seen from the read circuit 2 and backup circuit 4 shown in Figure 9, it is composed of 1 / 2N 2-bit sub-register blocks (hereinafter sometimes referred to as "SRBs") arranged in a row. That is, the non-volatile register 100 according to an embodiment of the present invention comprises N flip-flops 1, 1 / 2N read circuits 2, one controller circuit 3, 1 / 2N backup circuits 4, N+1 MTJ elements (MTJ0 to MTJN), and an initialization circuit 5 for MTJ0.

[0040] Furthermore, each SRB has two flip-flops, two XOR gate circuits, two MTJ elements, and one readout circuit 2 and one backup circuit 4. The XOR gate circuits are used to convert the information held by the flip-flops into differential information, and the backup circuit 4 applies a rewrite current to both MTJ elements based on the converted information. In this way, the information held by the nth flip-flop is held between the (n-1)th MTJ element and the nth MTJ element. Therefore, a readout circuit connected to these MTJ elements via a selection NMOS transistor reads the values ​​and returns them to the flip-flops.

[0041] The non-volatile register 100 according to an embodiment of the present invention includes a read-only MTJ element (MTJ0) and its initialization circuit 5, and a controller circuit 3, in which no value is written to the leading MTJ element (MTJ0). The controller circuit 3 receives input of two control signals related to backup and restore from an external source and performs control such as selecting even and odd bits. In the non-volatile register 100 according to an embodiment of the present invention, when power is supplied, only the flip-flop 1 operates, and this operation is the same as that of a general flip-flop. On the other hand, for intermittent computing, the processing operations when transitioning to the power gating period and when returning from the power gating period to the calculation execution period, i.e., backup processing and restore processing, are completely different from conventional configurations using NV-FF or RLSS. This will be explained below.

[0042] (Data Backup Processing) The data backup processing will now be explained. Figure 10 is a diagram illustrating the backup processing of a non-volatile integrated circuit (non-volatile register) according to an embodiment of the present invention. When a power supply voltage monitoring means (not shown) detects that the voltage has fallen below a threshold, power management based on intermittent computing executes a power cutoff process. In the non-volatile register 100 according to an embodiment of the present invention, the backup processing is executed immediately before the power is cut off.

[0043] The data held in flip-flop 1 is encoded into difference information through an XOR gate circuit, as shown in the first callout from the top right of Figure 10. This operation is performed by taking the exclusive OR of the value held by flip-flop 1 with the value from the previous conversion. As a result of this operation, the matching and mismatch of two adjacent bits in the converted data will be the same as "0" and "1" in the original data.

[0044] Backup circuit 4 determines the direction of the current to flow according to the converted information, and writes a value to the MTJ element. That is, as shown in the second balloon from the upper right in FIG. 10, when the converted data is "0", the MTJ element is rewritten to Rp, and when the converted information is "1", the MTJ element is rewritten to Rap. Since this value writing is performed for even bits and odd bits respectively, the writing process will be executed in two cycles.

[0045] (Data restoration process) The data restoration process will be described. FIG. 11 is a diagram for explaining the restoration process of a non-volatile integrated circuit (non-volatile register) according to an embodiment of the present invention. When energy is harvested by energy harvesting and it is detected by voltage monitoring means (not shown) that the voltage has recovered to a certain extent, an on process is executed by power management aiming at intermittent computing. After recovering from the power-off state, the non-volatile register 100 according to the embodiment of the present invention performs a return operation.

[0046] The reading circuit 2, which is specially prepared for the configuration using DSS and will be described later, is connected to two MTJ elements via NMOS transistors. Then, a reading current is passed through the two MTJ elements to determine whether the resistance states match or not. The reading circuit 2 outputs "0" when the resistance states match, and outputs "1" when the resistance states do not match. This means that it is in a state decoded (decrypted) into the original information held by the flip-flop 1. The restoration operation is completed by directly returning this decoded value to the corresponding two flip-flops 1. Also for this operation, since it is performed for even bits and odd bits respectively, it will be executed in two cycles.

[0047] (Readout Circuit) In the conventional configuration using an NV-FF or a configuration using RLSS, information can be read by amplifying the voltage difference generated from the difference in the current amount due to the difference in resistance between two MTJ elements. However, in the configuration using DSS, since it is necessary to discriminate between the match and mismatch of the resistance states, a special circuit is required. FIG. 12 is a diagram for explaining the structure of the readout circuit in the configuration using DSS, and FIG. 13 is a diagram for explaining the operation of the readout circuit in the configuration using DSS.

[0048] For a state where the resistance values match, when using a normal precharge sense amplifier, no voltage difference occurs and correct amplification cannot be achieved. Therefore, the readout circuit 2 in the non-volatile register 100 according to the embodiment of the present invention has a circuit configuration in which latches having two asymmetric characteristics created by appropriately adjusting the size of the transistors are complementarily connected. The possible combinations of the resistance states of the two MTJ elements are four types: (Rp, Rap), (Rp, Rp), (Rap, Rap), and (Rap, Rp). In such a case, the first latch discriminates whether the resistance state is (Rp, Rap) or one of the other three states, and outputs "0" or "1" to B1 to B2. On the other hand, the second latch discriminates whether the resistance state is (Rap, Rp) or one of the other three states, and outputs "0" or "1" to B3 to B4. When these two latches are connected in a dual manner, it becomes possible to detect the cases where the resistance state patterns are Rp, Rap and Rap, Rp.

[0049] By the two latches detecting two patterns of resistance value mismatches, the voltages of the four output terminals become different outputs in each of (1) the case where the resistance values match, (2) the case where MTJ1 has a higher resistance value, and (3) the case where MTJ2 has a higher resistance value. Then, by performing a NAND operation on the outputs of the B1 terminal and the B4 terminal of the two latch outputs, as shown in the truth table of FIG. 13, "0" is output when the resistance states of the MTJ elements match, and "1" is output when the resistance states do not match.

[0050] (Performance Evaluation) Non-volatile registers ranging from 2 bits to 32 bits were designed and verified for each of the following configurations: the conventional NV-FF configuration, the configuration using RLSS, and the configuration using DISS. Specifically, the designs were created using 55nm CMOS / MTJ hybrid process technology, and the evaluation was performed using the circuit simulator "HSPICE". Figure 14 is a graph showing the verification results for the conventional NV-FF configuration, the configuration using RLSS, and the configuration using DISS. Note that the legend for the conventional NV-FF configuration graph is indicated as "Conventional" (Conv.).

[0051] The graph on the left of Figure 14 shows the energy consumption per bit. The majority of the energy consumed during data backup is the energy required to write to the MTJ elements. The number of MTJ elements to be rewritten was 2N in the conventional NV-FF configuration, but has been reduced to N in the RLSS and DISS configurations. This reduces the energy consumption during data backup.

[0052] The middle graph in Figure 14 shows the circuit area. In configurations using RLSS or DISS, as the register size increases, the size of shared reference MTJ elements, controllers, etc., also increases, so the circuit area per bit decreases.

[0053] On the other hand, as shown in the graph on the right of Figure 14, in a configuration using RLSS, the time required for data saving and restoration increases in proportion to the size of the register. In contrast, in a configuration using DISS, data saving and restoration can be performed in a constant time regardless of the size of the register.

[0054] When configuring 32-bit registers, the RLSS-based and DISS-based configurations reduced energy consumption during backup by 49% compared to the conventional configuration, and also reduced circuit area by 34%. On the other hand, while the RLSS-based configuration required time for data standby and recovery processing, the DISS-based configuration was found to have the same processing time as the conventional configuration.

[0055] Although the non-volatile integrated circuit according to embodiments of the present invention has been described in detail above, the specific configuration is not limited to these embodiments, and any design changes, etc., that do not depart from the gist of the present invention are also included. For example, it may be configured as a static random access memory (SRAM) instead of a register, the NMOS described as a transistor switch configuration may be configured as a CMOS, and the flip-flop described as a D flip-flop may be configured as an RS flip-flop or a JK flip-flop. Furthermore, it is possible to make the read-only MTJ element the last MTJ element (MTJN+1) instead of the first MTJ element (MTJ0).

[0056] 1. Flip-flop 2. Read circuit 3. Controller circuit 4. Backup circuit 5. Initialization circuit 100. Non-volatile register

Claims

1. A non-volatile integrated circuit that stores and holds bit information in a plurality of flip-flops when power is supplied, and saves and stores this information in a non-volatile memory area when power is cut off, wherein the non-volatile integrated circuit is composed of N bits, and the non-volatile memory area is composed of N+1 magnetic tunnel junction elements.

2. The non-volatile integrated circuit according to claim 1, characterized in that one magnetic tunnel junction element is associated with the flip-flop constituting the nth bit, and the state of the flip-flop constituting the nth bit (0 or 1) is linked to the agreement or mismatch between the resistance value of the nth magnetic tunnel junction element and the (n+1)th magnetic tunnel junction element.

3. The non-volatile integrated circuit according to claim 2, characterized in that writing to and reading from the non-volatile memory area is performed in two cycles in which processing of odd-numbered magnetic tunnel junction elements and processing of even-numbered magnetic tunnel junction elements are performed alternately.

4. The non-volatile integrated circuit according to claim 3, characterized in that writing to the nth magnetic tunnel junction element of the non-volatile memory area is performed based on the output of an exclusive OR circuit, and the output of the (n-1)th exclusive OR circuit (however, a predetermined value when n=1) and the output of the nth flip-flop are connected to the input of the exclusive OR circuit.

5. The non-volatile integrated circuit according to claim 3, characterized in that the reading from the non-volatile memory area is performed using a magnetic tunnel junction element same-state reading circuit that outputs 0 or 1 depending on whether the resistance values ​​of adjacent magnetic tunnel junction elements match or not.

6. A non-volatile integrated circuit with an N-bit configuration that stores and holds bit information in a plurality of flip-flops when power is supplied, and saves and stores this information in a non-volatile memory area when power is cut off, comprising N+1 magnetic tunnel junction elements and a control unit, wherein the control unit performs writing to the nth magnetic tunnel junction element in the non-volatile memory area by connecting the output of the (n-1)th exclusive OR circuit (however, a predetermined value if n=1) and the output of the nth flip-flop to the input of the exclusive OR circuit based on the output of the exclusive OR circuit, and the control unit performs reading by outputting 0 or 1 depending on whether the resistance values ​​of adjacent magnetic tunnel junction elements match or do not match.

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