Power conversion device

Abstract

The present invention achieves a reduction in size while reducing ripple current. A power conversion device (1) comprises a plurality of positive-side input wiring sections (11), a plurality of first ground wiring sections (12), a plurality of output wiring sections (13), a plurality of second ground wiring sections (14), a plurality of first half-bridge circuits (3), a plurality of second half-bridge circuits (4), a first capacitor (C1), a plurality of second capacitors (C2), a first inductor (L1), and a plurality of second inductors (L2). The first inductor (L1) is provided in a shared ground wiring section (15) between the plurality of second ground wiring sections (14) and one first ground wiring section (12) among the plurality of first ground wiring sections (12). The plurality of second inductors (L2) are connected in series to a fourth switching element (Q4) and the first inductor (L1) in a corresponding second half-bridge circuit (4) among the plurality of second half-bridge circuits (4).

Description

Power conversion device

[0001] The present disclosure relates to a power conversion device, and more particularly to a power conversion device including a plurality of switching elements.

[0002] Patent Document 1 discloses a three-phase inverter circuit including three chopper circuits. In the three-phase inverter circuit disclosed in Patent Document 1, the three chopper circuits include a chopper circuit that outputs a U-phase voltage, a chopper circuit that outputs a V-phase voltage, and a chopper circuit that outputs a W-phase voltage. Each of the three chopper circuits has a power supply side half-bridge circuit, a load side half-bridge circuit, and a reactor. The power supply side half-bridge circuit of each of the three chopper circuits is composed of two switching elements connected in series with each other. Also, the load side half-bridge circuit of each of the three chopper circuits is composed of two switching elements connected in series with each other.

[0003] Further, the three-phase inverter circuit includes a smoothing capacitor (first capacitor) connected between the input ends of the three chopper circuits and a capacitor circuit in which three capacitors are Δ-connected.

[0004] Also, in the three-phase inverter circuit, each switching element is switched by a control circuit.

[0005] Also, the three-phase inverter circuit generates each-phase AC voltage and each-phase AC current having a substantially sinusoidal waveform with a DC voltage superimposed thereon. [[ID=!7]]

[0006] In the three-phase inverter circuit disclosed in Patent Document 1, it is preferable that the inductance of the reactor is larger in order to reduce the ripple of the current flowing through the reactor and the output current respectively. However, in the three-phase inverter circuit, if the inductance of each reactor is increased, the size of each reactor becomes large and the device becomes large-sized.

[0007] Japanese Patent Application Laid-Open No. 2005-295671

[0008] An object of the present disclosure is to provide a power conversion device capable of reducing the ripple current and achieving miniaturization.

[0009] A power converter according to one embodiment of the present disclosure comprises a plurality of positive input wiring sections, a plurality of first ground wiring sections, a plurality of output wiring sections, a plurality of second ground wiring sections, a plurality of first half-bridge circuits, a plurality of second half-bridge circuits, a first capacitor, a plurality of second capacitors, a first inductor, and a plurality of second inductors. The plurality of first half-bridge circuits correspond one-to-one with the plurality of positive input wiring sections and the plurality of first ground wiring sections. Each of the plurality of first half-bridge circuits has a first switching element connected to a corresponding positive input wiring section among the plurality of positive input wiring sections, and a second switching element connected between a corresponding first ground wiring section among the plurality of first ground wiring sections and the first switching element. The plurality of second half-bridge circuits correspond one-to-one with the plurality of output wiring sections and the plurality of second ground wiring sections. Each of the plurality of second half-bridge circuits includes a third switching element connected to a corresponding output wiring section among the plurality of output wiring sections, and a fourth switching element connected between a corresponding second ground wiring section among the plurality of second ground wiring sections and the third switching element. The first capacitor is connected in parallel to the plurality of first half-bridge circuits. The plurality of second capacitors are connected in parallel to each of the plurality of second half-bridge circuits. The first inductor is provided in a common ground wiring section between one of the plurality of first ground wiring sections and the plurality of second ground wiring sections. The plurality of second inductors correspond one-to-one with the plurality of second half-bridge circuits. The plurality of second inductors are connected in series with the fourth switching element and the first inductor in the corresponding second half-bridge circuit among the plurality of second half-bridge circuits.

[0010] A power converter according to one embodiment of the present disclosure comprises three positive input wiring sections, three first ground wiring sections, three output wiring sections, three second ground wiring sections, three first half-bridge circuits, three second half-bridge circuits, a first capacitor, three second capacitors, a first inductor, and three second inductors. The three first half-bridge circuits correspond one-to-one with the three positive input wiring sections and the three first ground wiring sections. Each of the three first half-bridge circuits has a first switching element connected to the corresponding positive input wiring section among the three positive input wiring sections, and a second switching element connected between the corresponding first ground wiring section and the first switching element among the three first ground wiring sections. The three second half-bridge circuits correspond one-to-one with the three output wiring sections and the three second ground wiring sections. Each of the three second half-bridge circuits includes a third switching element connected to a corresponding output wiring section among the three output wiring sections, and a fourth switching element connected between a corresponding second ground wiring section among the three second ground wiring sections and the third switching element. The first capacitor is connected in parallel to the three first half-bridge circuits. The second capacitor is connected in parallel to each of the three second half-bridge circuits. The first inductor is provided in a common ground wiring section between one of the three first ground wiring sections and the three second ground wiring sections. The three second inductors correspond one-to-one with the three first half-bridge circuits. The three second inductors correspond one-to-one with the three second half-bridge circuits. The three second inductors are connected between a first connection point between the first switching element and the second switching element in a corresponding first half-bridge circuit among the three first half-bridge circuits, and a second connection point between the third switching element and the fourth switching element in a corresponding second half-bridge circuit among the three second half-bridge circuits.

[0011] Figure 1 is a schematic circuit diagram of a power converter according to Embodiment 1. Figure 2 is a circuit diagram of the same power converter. Figure 3 is a circuit diagram showing a specific example of the configuration of a control device for the same power converter. Figure 4 is an operating waveform diagram of the same power converter. Figure 5 is an operating waveform diagram of a power converter according to Embodiment 1. Figure 6 is an operating waveform diagram of a power converter according to a comparative example. Figure 7 is an operating waveform diagram of the same power converter. Figure 8 is a circuit diagram of a power converter according to Embodiment 2. Figure 9 is an explanatory diagram of a coupling inductor in the same power converter. Figure 10 is a circuit diagram of a power converter according to Embodiment 3.

[0012] (Embodiment 1) Below, the power conversion device 1 according to Embodiment 1 will be described with reference to Figures 1 to 4.

[0013] (1) Configuration of the power converter The power converter 1 comprises a plurality of (three in Figure 1) positive input wiring sections 11, a plurality of (three in Figure 1) first ground wiring sections 12, a plurality of (three in Figure 1) output wiring sections 13, and a plurality of (three in Figure 1) second ground wiring sections 14. The power converter 1 also comprises a plurality of (three in Figure 1) first half-bridge circuits 3, a plurality of (three in Figure 1) second half-bridge circuits 4, a first capacitor C1, a plurality of (three in Figure 1) second capacitors C2, a first inductor L1, and a plurality of (three in Figure 1) second inductors L2. The plurality of first half-bridge circuits 3 correspond one-to-one with the plurality of positive input wiring sections 11 and the plurality of first ground wiring sections 12. Each of the multiple first half-bridge circuits 3 includes a first switching element Q1 connected to a corresponding positive input wiring section 11 from among the multiple positive input wiring sections 11, and a second switching element Q2 connected between a corresponding first ground wiring section 12 from among the multiple first ground wiring sections 12 and the first switching element Q1. The multiple second half-bridge circuits 4 correspond one-to-one with the multiple output wiring sections 13 and the multiple second ground wiring sections 14. Each of the multiple second half-bridge circuits 4 includes a third switching element Q3 connected to a corresponding output wiring section 13 from among the multiple output wiring sections 13, and a fourth switching element Q4 connected between a corresponding second ground wiring section 14 from among the multiple second ground wiring sections 14 and the third switching element Q3. The first capacitor C1 is connected in parallel to the multiple first half-bridge circuits 3. The multiple second capacitors C2 are connected in parallel to each of the multiple second half-bridge circuits 4. The first inductor L1 is provided in a common ground wiring section 15 between one of the multiple first ground wiring sections 12 and multiple second ground wiring sections 14.

[0014] Furthermore, in the power converter 1, the multiple second inductors L2 correspond one-to-one with the multiple first half-bridge circuits 3 and one-to-one with the multiple second half-bridge circuits 4. The multiple second inductors L2 are connected between the first connection point N1 between the first switching element Q1 and the second switching element Q2 in the corresponding first half-bridge circuit 3, and the second connection point N2 between the third switching element Q3 and the fourth switching element Q4 in the corresponding second half-bridge circuit 4.

[0015] Furthermore, as shown in Figure 2, the power converter 1 further comprises a plurality of (three in the example of Figure 2) first drivers 51, a plurality of (three in the example of Figure 2) second drivers 52, a plurality of (three in the example of Figure 2) third drivers 53, a plurality of (three in the example of Figure 2) fourth drivers 54, a power supply 5, an isolated power supply 6, and a control device 7. The plurality of first drivers 51 correspond to a plurality of first half-bridge circuits 3. Each of the plurality of first drivers 51 drives the first switching element Q1 in the corresponding first half-bridge circuit 3 among the plurality of first half-bridge circuits 3. The plurality of second drivers 52 correspond to a plurality of first half-bridge circuits 3. Each of the plurality of second drivers 52 drives the second switching element Q2 in the corresponding first half-bridge circuit 3 among the plurality of first half-bridge circuits 3. The plurality of third drivers 53 correspond to a plurality of second half-bridge circuits 4. Each of the multiple third drivers 53 drives the third switching element Q3 in the corresponding second half-bridge circuit 4 among the multiple second half-bridge circuits 4. The multiple fourth drivers 54 correspond to the multiple second half-bridge circuits 4. Each of the multiple fourth drivers 54 drives the fourth switching element Q4 in the corresponding second half-bridge circuit 4 among the multiple second half-bridge circuits 4. The power supply 5 is connected to the multiple second drivers 52. The isolated power supply 6 is connected to the multiple fourth drivers 54. The control device 7 outputs multiple first control signals S1 (see Figure 3), multiple second control signals S2 (see Figure 3), multiple third control signals S3 (see Figure 3), and multiple fourth control signals S4 (see Figure 3) to be given to the multiple first drivers 51, multiple second drivers 52, multiple third drivers 53, and multiple fourth drivers 54, respectively.

[0016] Furthermore, the power converter 1 includes a first input terminal T1, a second input terminal T2, and a plurality of (three in Figure 1) output terminals T3. The first input terminal T1 is connected to the positive input wiring section 11. The second input terminal T2 is connected to the first ground wiring section 12. The plurality of output terminals T3 correspond one-to-one with the plurality of output wiring sections 13. The plurality of output terminals T3 are connected to the corresponding output wiring section 13 among the plurality of output wiring sections 13. The first input terminal T1, the second input terminal T2, and the plurality of output terminals T3 do not necessarily have to be physical components (terminals), and may, for example, be part of a conductor included in the circuit board of the power converter 1.

[0017] In the power converter 1, a DC power supply E1 is connected between the first input terminal T1 and the second input terminal T2, and AC loads 10 are connected to multiple output terminals T3. The AC loads 10 are, for example, three-phase servo motors.

[0018] (2) Details of the power converter The power converter 1 is a three-phase inverter that converts DC to three-phase AC.

[0019] The power converter 1 has, for example, the high-potential output terminal (positive terminal) of the DC power supply E1 connected to the first input terminal T1, and the low-potential output terminal (negative terminal) of the DC power supply E1 connected to the second input terminal T2. The output voltage of the DC power supply E1 is, for example, 48V. The output voltage of the DC power supply E1 is not limited to 48V; for example, it may be 12V, 24V, or 141V obtained by inputting an AC voltage of 100V to a diode bridge.

[0020] In the following, with respect to the multiple first half-bridge circuits 3, the first half-bridge circuit 3 corresponding to the U phase will be referred to as the first half-bridge circuit 3u, the first half-bridge circuit 3 corresponding to the V phase will be referred to as the first half-bridge circuit 3v, and the first half-bridge circuit 3 corresponding to the W phase will be referred to as the first half-bridge circuit 3w. Also, in the following, with respect to the multiple second half-bridge circuits 4, the second half-bridge circuit 4 corresponding to the U phase will be referred to as the second half-bridge circuit 4u, the second half-bridge circuit 4 corresponding to the V phase will be referred to as the second half-bridge circuit 4v, and the second half-bridge circuit 4 corresponding to the W phase will be referred to as the second half-bridge circuit 4w. Also, in the following, with respect to the multiple output terminals T3, the output terminal T3 connected to the U phase terminal of the AC load 10 will be referred to as output terminal T3u, the output terminal T3 connected to the V phase terminal of the AC load 10 will be referred to as output terminal T3v, and the output terminal T3 connected to the W phase terminal of the AC load 10 will be referred to as output terminal T3w.

[0021] In this embodiment, the power converter 1 includes a plurality of DC-DC converters 2 (three in the example of Figure 1). The three DC-DC converters 2 include a DC-DC converter 2u corresponding to the U phase, a DC-DC converter 2v corresponding to the V phase, and a DC-DC converter 2w corresponding to the W phase. Each of the plurality of DC-DC converters 2 is a boost-buck converter capable of boosting and bucking. In this embodiment, the first inductor L1 is common to the plurality of DC-DC converters 2 and is shared by the plurality of DC-DC converters 2.

[0022] The DC-DC converter 2u corresponding to the U phase includes a first half-bridge circuit 3u, a second half-bridge circuit 4u, a first inductor L1, and a second inductor L2 connected between the first half-bridge circuit 3u and the second half-bridge circuit 4u.

[0023] The DC-DC converter 2v corresponding to the V phase includes a first half-bridge circuit 3v, a second half-bridge circuit 4v, a first inductor L1, and a second inductor L2 connected between the first half-bridge circuit 3v and the second half-bridge circuit 4v.

[0024] The DC-DC converter 2w corresponding to the W phase includes a first half-bridge circuit 3w, a second half-bridge circuit 4w, a first inductor L1, and a second inductor L2 connected between the first half-bridge circuit 3w and the second half-bridge circuit 4w.

[0025] Each of the three DC-DC converters 2 is capable of a first conversion operation, which converts the first input voltage from the DC power supply E1 to the first half-bridge circuit 3 into a first output voltage, and a second conversion operation, which converts the second input voltage from the AC load 10 (the input voltage to the second half-bridge circuit 4) into a second output voltage. Both the first and second conversion operations are capable of either boost operation (hereinafter also referred to as boost mode operation) or buck operation (hereinafter also referred to as buck mode operation). Furthermore, the power converter 1 is capable of both a power supply operation, which converts the DC power input between the first input terminal T1 and the second input terminal T2 into three-phase AC power and outputs it from the three output terminals T3u, T3v, and T3w, and a power regeneration operation, which converts the three-phase AC power input from the three output terminals T3u, T3v, and T3w into DC power and outputs it between the first input terminal T1 and the second input terminal T2. The power converter 1 performs a power regeneration operation to recover energy from a three-phase servo motor, which is an AC load 10, when the brakes are applied to the three-phase servo motor.

[0026] Each of the multiple first half-bridge circuits 3 has a first switching element Q1 and a second switching element Q2 connected in series between the positive input wiring section 11 and the first ground wiring section 12. Each of the multiple second half-bridge circuits 4 has a third switching element Q3 and a fourth switching element Q4 connected in series between the output wiring section 13 and the second ground wiring section 14. The second inductor L2 is connected between the first connection point N1 between the first switching element Q1 and the second switching element Q2 and the second connection point N2 between the third switching element Q3 and the fourth switching element Q4. The first connection point N1 is not limited to the connection point where the first switching element Q1 and the second switching element Q2 are directly connected, but may be, for example, a node in the wiring section between the first switching element Q1 and the second switching element Q2. The second connection point N2 is not limited to the connection point where the third switching element Q3 and the fourth switching element Q4 are directly connected, but may be, for example, a node in the wiring section between the third switching element Q3 and the fourth switching element Q4.

[0027] Each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 has a control terminal, a first main terminal, and a second main terminal. The multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 are controlled by a control device 7. In this embodiment, each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 is, for example, a normally-off n-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Therefore, the control terminal, first main terminal, and second main terminal of each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 are the gate terminal, drain terminal, and source terminal, respectively.

[0028] In each of the multiple first half-bridge circuits 3, the first main terminal of the first switching element Q1 is connected to the first input terminal T1, the second main terminal of the first switching element Q1 is connected to the first main terminal of the second switching element Q2, and the second main terminal of the second switching element Q2 is connected to the second input terminal T2. In each of the multiple first half-bridge circuits 3, the first switching element Q1 is a high-side switching element (P-side switching element), and the second switching element Q2 is a low-side switching element (N-side switching element).

[0029] Each of the multiple first half-bridge circuits 3 has a first diode D1 and a second diode D2. In each of the multiple first half-bridge circuits 3, the first diode D1 is connected in antiparallel to the first switching element Q1. In each of the multiple first half-bridge circuits 3, the anode of the first diode D1 is connected to the second main terminal (source terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (drain terminal) of the first switching element Q1. In each of the multiple first half-bridge circuits 3, the second diode D2 is connected in antiparallel to the second switching element Q2. In each of the multiple first half-bridge circuits 3, the anode of the second diode D2 is connected to the second main terminal of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal of the second switching element Q2. In each of the multiple first half-bridge circuits 3, the first diode D1 and the second diode D2 are parasitic diodes of the n-channel MOSFETs that constitute the first switching element Q1 and the second switching element Q2, respectively. However, they are not limited to parasitic diodes and may be external diodes.

[0030] In each of the multiple second half-bridge circuits 4, the first main terminal of the third switching element Q3 is connected to the output wiring section 13, the second main terminal of the third switching element Q3 is connected to the first main terminal of the fourth switching element Q4, and the second main terminal of the fourth switching element Q4 is connected to the second ground wiring section 14. In each of the multiple second half-bridge circuits 4, the third switching element Q3 is a high-side switching element, and the fourth switching element Q4 is a low-side switching element.

[0031] Each of the multiple second half-bridge circuits 4 has a third diode D3 and a fourth diode D4. In each of the multiple second half-bridge circuits 4, the third diode D3 is connected in antiparallel to the third switching element Q3. In each of the multiple second half-bridge circuits 4, the anode of the third diode D3 is connected to the second main terminal (source terminal) of the third switching element Q3, and the cathode of the third diode D3 is connected to the first main terminal (drain terminal) of the third switching element Q3. In each of the multiple second half-bridge circuits 4, the fourth diode D4 is connected in antiparallel to the fourth switching element Q4. In each of the multiple second half-bridge circuits 4, the anode of the fourth diode D4 is connected to the second main terminal of the fourth switching element Q4, and the cathode of the fourth diode D4 is connected to the first main terminal of the fourth switching element Q4. In each of the multiple second half-bridge circuits 4, the third diode D3 and the fourth diode D4 are parasitic diodes of the n-channel MOSFETs that constitute the third switching element Q3 and the fourth switching element Q4, respectively. However, they are not limited to parasitic diodes and may be external diodes.

[0032] As shown in Figure 2, the multiple first drivers 51 correspond one-to-one with the multiple first switching elements Q1. Each of the multiple first drivers 51 is a high-side gate driver connected to the control terminal (gate terminal) of the corresponding first switching element Q1 among the multiple first switching elements Q1.

[0033] Each of the multiple second drivers 52 corresponds one-to-one with each of the multiple second switching elements Q2. Each of the multiple second drivers 52 is a low-side gate driver connected to the control terminal (gate terminal) and second main terminal (source terminal) of the corresponding second switching element Q2.

[0034] Each of the multiple third drivers 53 corresponds one-to-one with each of the multiple third switching elements Q3. Each of the multiple third drivers 53 is a high-side gate driver connected to the control terminal (gate terminal) of the corresponding third switching element Q3 among the multiple third switching elements Q3.

[0035] Each of the multiple fourth drivers 54 corresponds one-to-one with each of the multiple fourth switching elements Q4. Each of the multiple fourth drivers 54 is a low-side gate driver connected to the control terminal (gate terminal) and second main terminal (source terminal) of the corresponding fourth switching element Q4 among the multiple fourth switching elements Q4.

[0036] Each of the multiple first drivers 51, multiple second drivers 52, multiple third drivers 53, and multiple fourth drivers 54 includes, for example, a driver IC (Integrated Circuit).

[0037] The control device 7 controls the plurality of first switching elements Q1, plurality of second switching elements Q2, plurality of third switching elements Q3, and plurality of fourth switching elements Q4 via the plurality of first drivers 51, plurality of second drivers 52, plurality of third drivers 53, and plurality of fourth drivers 54, respectively.

[0038] The control device 7 includes a computer system. The computer system mainly consists of a processor and memory as hardware. The processor executes a program recorded in the computer system's memory, thereby realizing the functions of the control device 7 in this disclosure. The processor of the computer system is composed of one or more electronic circuits, including semiconductor integrated circuits (ICs) or large-scale integrated circuits (LSIs). The integrated circuits referred to here, such as ICs or LSIs, are named differently depending on the degree of integration, and include integrated circuits called system LSIs, VLSIs (Very Large Scale Integrations), or ULSIs (Ultra Large Scale Integrations). Furthermore, FPGAs (Field-Programmable Gate Arrays) that are programmed after the LSI is manufactured, or logic devices that allow for the reconfiguration of junction relationships or circuit compartments within the LSI, can also be used as processors. Multiple electronic circuits may be integrated onto a single chip or distributed across multiple chips. Multiple chips may be integrated onto a single device or distributed across multiple devices. The computer system referred to herein includes a microcontroller having one or more processors and one or more memories. Therefore, the microcontroller also consists of one or more electronic circuits, including semiconductor integrated circuits or large-scale integrated circuits.

[0039] As shown in Figure 3, the control device 7 outputs a plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3, and a plurality of fourth control signals S4. Each of the plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3, and a plurality of fourth control signals S4 is, for example, a PWM (Pulse Width Modulation) signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) which is higher than the first potential level. Each of the plurality of switching elements (a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4) is turned on when the corresponding control signal among the plurality of control signals (a plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3, and a plurality of fourth control signals S4) is at a high level, and is turned off when it is at a low level.

[0040] The control device 7 includes a signal generation unit 79. The signal generation unit 79 of the control device 7 generates a plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3, and a plurality of fourth control signals S4 using a triangular wave carrier signal.

[0041] More specifically, the control device 7 generates, for example, a first control signal S1u and a second control signal S2u to be given to the first switching element Q1 and the second switching element Q2 of the first half-bridge circuit 3u, respectively, based on the carrier signal and the U-phase duty cycle command value d1u. The control device 7 also generates, for example, a third control signal S3u and a fourth control signal S4u to be given to the third switching element Q3 and the fourth switching element Q4 of the second half-bridge circuit 4u, respectively, based on the carrier signal and the U-phase duty cycle command value d3u.

[0042] The duty of each of the first control signal S1u and the second control signal S2u generated by the signal generation unit 79 changes based on the duty command value d1u. The signal generation unit 79 compares the duty command value d1u with the carrier signal to generate the first control signal S1u. More specifically, the signal generation unit 79 generates the first control signal S1u that becomes a high level (“1”) during a period when the duty command value d1u is greater than the value of the carrier signal and becomes a low level (“0”) during a period when the duty command value d1u is less than or equal to the value of the carrier signal. Further, the signal generation unit 79 generates the second control signal S2u by inverting the first control signal S1u. Note that the signal generation unit 79 sets a dead time period between the high level period of the first control signal S1u and the high level period of the second control signal S2u so that the on periods of the first switching element Q1 and the second switching element Q2 of the first half-bridge circuit 3u do not overlap.

[0043] The duty of each of the third control signal S3u and the fourth control signal S4u generated by the signal generation unit 79 changes based on the duty command value d3u. The signal generation unit 79 compares the duty command value d3u with the carrier signal to generate the third control signal S3u. Further, the signal generation unit 79 generates the fourth control signal S4u by inverting the third control signal S3u. Note that the signal generation unit 79 sets a dead time period between the high level period of the third control signal S3u and the high level period of the fourth control signal S4u so that the on periods of the third switching element Q3 and the fourth switching element Q4 of the second half-bridge circuit 4u do not overlap.

[0044] Further, the control device 7 generates, for example, the first control signal S1v and the second control signal S2v to be supplied to the first switching element Q1 and the second switching element Q2 of the first half-bridge circuit 3v based on the carrier signal and the duty command value d1v of the V phase. Further, the control device 7 generates, for example, the third control signal S3v and the fourth control signal S4v to be supplied to the third switching element Q3 and the fourth switching element Q4 of the second half-bridge circuit 4v based on the carrier signal and the duty command value d3v of the V phase.

[0045] The duty cycles of the first control signal S1v and the second control signal S2v, generated by the signal generation unit 79, change based on the duty cycle command value d1v. The signal generation unit 79 generates the first control signal S1v by comparing the duty cycle command value d1v with the carrier signal. More specifically, the signal generation unit 79 generates a first control signal S1v that is high level ("1") during periods when the duty cycle command value d1v is greater than the value of the carrier signal, and low level ("0") during periods when the duty cycle command value d1v is less than or equal to the value of the carrier signal. The signal generation unit 79 also generates the second control signal S2v by inverting the first control signal S1v. The signal generation unit 79 sets a dead time period between the high-level period of the first control signal S1v and the high-level period of the second control signal S2v so that the on-period of the first switching element Q1 and the on-period of the second switching element Q2 of the first half-bridge circuit 3v do not overlap.

[0046] The duty cycles of the third control signal S3v and the fourth control signal S4v, generated by the signal generation unit 79, change based on the duty cycle command value d3v. The signal generation unit 79 generates the third control signal S3v by comparing the duty cycle command value d3v with the carrier signal. The signal generation unit 79 also generates the fourth control signal S4v by inverting the third control signal S3v. The signal generation unit 79 sets a dead time period between the high-level period of the third control signal S3v and the high-level period of the fourth control signal S4v so that the on-period of the third switching element Q3 of the second half-bridge circuit 4v and the on-period of the fourth switching element Q4 do not overlap.

[0047] Furthermore, the control device 7 generates, for example, a first control signal S1w and a second control signal S2w to be given to the first switching element Q1 and the second switching element Q2 of the first half-bridge circuit 3w, respectively, based on the carrier signal and the W-phase duty cycle command value d1w. Also, the control device 7 generates, for example, a third control signal S3w and a fourth control signal S4w to be given to the third switching element Q3 and the fourth switching element Q4 of the second half-bridge circuit 4w, respectively, based on the carrier signal and the W-phase duty cycle command value d3w.

[0048] The duty of each of the first control signal S1w and the second control signal S2w generated by the signal generation unit 79 changes based on the duty command value d1w. The signal generation unit 79 compares the duty command value d1w with the carrier signal to generate the first control signal S1w. More specifically, the signal generation unit 79 generates the first control signal S1w that becomes a high level (“1”) during a period when the duty command value d1w is greater than the value of the carrier signal, and becomes a low level (“0”) during a period when the duty command value d1w is less than or equal to the value of the carrier signal. Also, the signal generation unit 79 generates the second control signal S2w by inverting the first control signal S1w. Note that the signal generation unit 79 sets a dead time period between the high level period of the first control signal S1w and the high level period of the second control signal S2w so that the on periods of the first switching element Q1 and the second switching element Q2 of the first half-bridge circuit 3w do not overlap.

[0049] The duty of each of the third control signal S3w and the fourth control signal S4w generated by the signal generation unit 79 changes based on the duty command value d3w. The signal generation unit 79 compares the duty command value d3w with the carrier signal to generate the third control signal S3w. Also, the signal generation unit 79 generates the fourth control signal S4w by inverting the third control signal S3w. Note that the signal generation unit 79 sets a dead time period between the high level period of the third control signal S3w and the high level period of the fourth control signal S4w so that the on periods of the third switching element Q3 and the fourth switching element Q4 of the second half-bridge circuit 4w do not overlap.

[0050] In the present embodiment, the control device 7 performs feedback control based on at least two of the U-phase phase current isa output from the output terminal T3u, the V-phase phase current isb output from the output terminal T3v, and the W-phase phase current isc output from the output terminal T3w.

[0051] The control device 求取 the U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0 based on at least two of the phase currents isa, isb, and isc.

[0052] As shown in Figure 3, the control device 7 obtains the U-phase reference voltage value Va1, the V-phase reference voltage value Vb1, and the W-phase reference voltage value Vc1 by adding the same bias voltage value Vbias to each of the U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0.

[0053] The control device 7 will be described in more detail below.

[0054] The control device 7 includes a first conversion unit 71, a first subtraction unit 72, a second subtraction unit 73, a first PI (Proportional Integral) control unit 74, a second PI control unit 75, a second conversion unit 76, an addition unit 77, a command value generation unit 78, and a signal generation unit 79.

[0055] The first conversion unit 71 acquires a detected value ia from a current sensor 9a (hereinafter also referred to as the U-phase current sensor 9a) that detects the phase current isa. The first conversion unit 71 also acquires a detected value ib from a current sensor 9b (hereinafter also referred to as the V-phase current sensor 9b) that detects the phase current isb. The first conversion unit 71 also acquires a detected value ic from a current sensor 9c (hereinafter also referred to as the W-phase current sensor 9c) that detects the phase current isc. Note that the U-phase current sensor 9a, V-phase current sensor 9b, and W-phase current sensor 9c are not components of the power conversion device 1, but may be components of the power conversion device 1. Each of the three current sensors 9a, 9b, and 9c is a current detection resistor, but it is not limited to a current detection resistor and may be a current transformer.

[0056] The first conversion unit 71 includes, for example, a three-phase to two-phase conversion unit and a dq conversion unit, and converts the detected values ​​ia, ib, and ic of the three-phase phase currents isa, isb, and isc of the abc reference coordinate system, where the U phase is the a phase, the V phase is the b phase, and the W phase is the c phase, into the d-axis current value id and the q-axis current value iq of the dq rotating coordinate system.

[0057] The first subtraction unit 72 calculates the difference between the reference value id1 and the d-axis current value id (hereinafter also referred to as the d-axis current difference) by performing an operation to subtract the d-axis current value id from the reference value id1 of the d-axis current.

[0058] The second subtraction unit 73 calculates the difference between the reference value iq1 and the q-axis current value iq (hereinafter also referred to as the q-axis current difference) by performing an operation to subtract the q-axis current value iq from the reference value iq1 of the q-axis current.

[0059] The reference values ​​id1 for the d-axis current and iq1 for the q-axis current described above are determined in the control device 7 by an external command from a higher-level controller (not shown) to the control device 7. In other words, the control device 7 has the function of generating the reference values ​​id1 for the d-axis current and iq1 for the q-axis current based on an external command from the higher-level controller. Alternatively, the reference values ​​id1 for the d-axis current and iq1 for the q-axis current are stored in the control device 7 in advance by a program. Alternatively, the reference values ​​id1 for the d-axis current and iq1 for the q-axis current may be calculated in the control device 7 based on the angle (position) information of the AC load 10, etc.

[0060] The first PI control unit 74 generates a reference value Vd0 for the d-axis voltage to perform feedback control that brings the d-axis current difference value output from the first subtraction unit 72 closer to zero.

[0061] The second PI control unit 75 generates a reference value Vq0 for the q-axis voltage to perform feedback control that brings the q-axis current difference value output from the second subtraction unit 73 closer to zero.

[0062] The second conversion unit 76 includes, for example, an inverse dq conversion unit and a two-phase to three-phase conversion unit, and converts the reference value Vd0 of the d-axis voltage and the reference value Vq0 of the q-axis voltage into the U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0. The waveforms showing the time change of the U-phase command voltage value Va0, the waveform showing the time change of the V-phase command voltage value Vb0, and the waveform showing the time change of the W-phase command voltage value Vc0 are, for example, sinusoidal waves with a phase difference of 120° from each other. The U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0 are output from the second conversion unit 76. The length of one period of the waveforms showing the time change of the U-phase command voltage value Va0, the waveform showing the time change of the V-phase command voltage value Vb0, and the waveform showing the time change of the W-phase command voltage value Vc0 is the same. Furthermore, the length of one period of the waveforms showing the time variation of the U-phase command voltage value Va0, the waveform showing the time variation of the V-phase command voltage value Vb0, and the waveform showing the time variation of the W-phase command voltage value Vc0 is longer than the length of one period of the carrier signal.

[0063] The adder 77 calculates the U-phase reference voltage value Va1, V-phase reference voltage value Vb1, and W-phase reference voltage value Vc1 by adding the bias voltage value Vbias to the U-phase command voltage value Va0, V-phase command voltage value Vb0, and W-phase command voltage value Vc0, respectively. That is, the adder 77 performs the calculations shown in equations (1), (2), and (3) below. Va1 = Va0 + Vbias Equation (1) Vb1 = Vb0 + Vbias Equation (2) Vc1 = Vc0 + Vbias Equation (3)

[0064] The U-phase reference voltage value Va1, the V-phase reference voltage value Vb1, and the W-phase reference voltage value Vc1 correspond to the target values ​​of the output voltages of the three second half-bridge circuits 4u, 4v, and 4w, respectively. The waveforms showing the time variation of the U-phase reference voltage value Va1, the V-phase reference voltage value Vb1, and the W-phase reference voltage value Vc1 are sinusoidal waves with a phase difference of 120° from each other and biased to the positive side by a bias voltage value Vbias.

[0065] The command value generation unit 78 sets the duty cycle command value d3u to 1 when the DC-DC converter 2u is operating in step-down mode. The command value generation unit 78 also sets the duty cycle command value d3v to 1 when the DC-DC converter 2v is operating in step-down mode. Furthermore, the command value generation unit 78 sets the duty cycle command value d3w to 1 when the DC-DC converter 2w is operating in step-down mode. The command value generation unit 78 calculates the duty cycle command value d1u using the following equation (4) with respect to the DC voltage value Vdc input between the first input terminal T1 and the second input terminal T2, and the U-phase reference voltage value Va1. Also, the command value generation unit 78 calculates the duty cycle command value d1v using the DC voltage value Vdc and the V-phase reference voltage value Vb1 using the following equation (5). The command value generation unit 78 calculates the duty cycle command value d1w using the DC voltage value Vdc and the W-phase reference voltage value Vc1 according to the following equation (6): d1u = Va1 ÷ Vdc Equation (4) d1v = Vb1 ÷ Vdc Equation (5) d1w = Vc1 ÷ Vdc Equation (6)

[0066] Furthermore, the command value generation unit 78 sets the duty cycle command value d1u to 1 when the DC-DC converter 2u is operating in boost mode. Also, the command value generation unit 78 sets the duty cycle command value d1v to 1 when the DC-DC converter 2v is operating in boost mode. Also, the command value generation unit 78 sets the duty cycle command value d1w to 1 when the DC-DC converter 2w is operating in boost mode. The duty cycle command value d3u is calculated using the DC voltage value Vdc and the U-phase reference voltage value Va1 according to the following equation (7). Also, the command value generation unit 78 calculates the duty cycle command value d3v using the DC voltage value Vdc and the V-phase reference voltage value Vb1 according to the following equation (8). Also, the command value generation unit 78 calculates the duty cycle command value d3w using the DC voltage value Vdc and the W-phase reference voltage value Vc1 according to the following equation (9). d3u=Vdc÷Va1 Formula (7) d3v=Vdc÷Vb1 Formula (8) d3w=Vdc÷Vc1 Formula (9)

[0067] Although the operation of each of the three DC-DC converters 2u, 2v, and 2w has been described for both the step-down mode and the step-up mode, the command value generation unit 78 also calculates the duty cycle command values ​​d1u, d3u, d1v, d3v, d1w, and d3w when each of the three DC-DC converters 2u, 2v, and 2w is operating in step-up / step-down mode. Furthermore, the control device 7 may use a value stored in advance as the voltage value Vdc, or it may use a value detected by a voltage detection circuit or voltage sensor that detects the voltage value Vdc.

[0068] In this embodiment, the control device 7 sets the maximum value of the carrier signal to 1 and the minimum value to 0. Furthermore, the control device 7 sets the maximum value of each of the duty cycle command values ​​d1u, d1v, d1w, d3u, d3v, and d3w to 1 and the minimum value to 0.

[0069] As shown in Figure 2, the power supply 5 is connected between the power supply terminals of the multiple second drivers 52 and the ground terminals of the multiple second drivers 52. The power supply 5 is a voltage regulator, but is not limited to a voltage regulator; for example, it may be an LDO (Low Dropout) regulator, an isolated DC-DC converter, etc. An isolated DC-DC converter is, for example, a flyback converter. The output voltage of the power supply 5 is, for example, 12V.

[0070] The isolated power supply 6 is connected between the power terminals of the multiple fourth drivers 54 and the ground terminals of the multiple fourth drivers 54. The isolated power supply 6 includes an isolated DC-DC converter. The isolated DC-DC converter is, for example, a flyback converter. The output voltage of the isolated power supply 6 is, for example, 12V.

[0071] Although not shown in Figure 2, the power converter 1 includes, for example, a plurality (three) of first bootstrap circuits connected to the power supply 5, and can supply power voltage from the plurality (three) of first bootstrap circuits to a plurality (three) of first drivers 51. Furthermore, the power converter 1 includes, for example, a plurality (three) of second bootstrap circuits connected to the isolated power supply 6, and can supply power voltage from the plurality (three) of second bootstrap circuits to a plurality (three) of third drivers 53.

[0072] In this embodiment, each of the multiple (three in Figure 1) second inductors L2 is connected between the first connection point N1 of the corresponding first half-bridge circuit 3 among the multiple first half-bridge circuits 3 and the second connection point N2 of the corresponding second half-bridge circuit 4 among the multiple second half-bridge circuits 4. Therefore, each of the multiple second inductors L2 is connected in series with the fourth switching element Q4 and the first inductor L1 in the corresponding second half-bridge circuit 4 among the multiple second half-bridge circuits 4. In other words, each of the multiple second inductors L2 is connected to the first inductor L1 via the fourth switching element Q4 in the corresponding second half-bridge circuit 4 among the multiple second half-bridge circuits 4.

[0073] The inductances of the multiple (three in Figure 1) second inductors L2 are the same. That is, the inductances of the three second inductors L2 are the same. "The inductances of the three second inductors L2 are the same" does not only mean that the inductance of two of the three second inductors L2 is 100% of the inductance of the remaining second inductor L2, but also that the inductance of the two second inductors L2 is within the range of 80% to 120% of the inductance of the remaining second inductor L2.

[0074] The inductance of the first inductor L1 is 20% or more of the average value of the inductances of the multiple second inductors L2. The inductance of the first inductor L1 is greater than the parasitic inductance of the common ground wiring section 15. For example, if the average value of the inductances of the multiple second inductors L2 is 10 μH, the inductance of the first inductor L1 is 2 μH or more. The inductance of a wiring approximately 2 m long is about 2 μH, and the parasitic inductance of the common ground wiring section 15 will not unintentionally become 2 μH.

[0075] The first capacitor C1 is connected in parallel to a plurality of first half-bridge circuits 3. The first capacitor C1 is connected between the first input terminal T1 and the second input terminal T2. Therefore, in this embodiment, the first capacitor C1 is connected between a plurality of positive input wiring sections 11 and a plurality of first ground wiring sections 12. The first capacitor C1 is, for example, an electrolytic capacitor, but is not limited to an electrolytic capacitor; for example, it may be configured by connecting a plurality of multilayer ceramic capacitors in series and parallel.

[0076] Each of the multiple second capacitors C2 includes, for example, multiple (e.g., four) multilayer ceramic capacitors. The second capacitor C2 is constructed by connecting multiple multilayer ceramic capacitors in series and parallel. The second capacitor C2 is not limited to a configuration that includes multiple multilayer ceramic capacitors; it may include at least one multilayer ceramic capacitor. The second capacitor C2 may also be an electrolytic capacitor.

[0077] The capacitances of the multiple (three in Figure 1) second capacitors C2 are the same. That is, the capacitances of the three second capacitors C2 are the same. "The capacitances of the three second capacitors C2 are the same" means not only that the capacitance of two of the three second capacitors C2 is 100% of the capacitance of the remaining second capacitor C2, but also that the capacitance of the two second capacitors C2 is within the range of 80% to 120% of the capacitance of the remaining second capacitor C2.

[0078] (3) Operation of the power converter In the power converter 1, the control device 7 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4, thereby outputting sinusoidal DC voltages with a phase difference of 120° from each other from a plurality of output terminals T3. In other words, in the power converter 1, the control device 7 controls three DC-DC converters 2, thereby outputting sinusoidal DC voltages with a phase difference of 120° from each other from the three DC-DC converters 2. At this time, the output currents of the three DC-DC converters 2 are sinusoidal AC currents with a phase difference of 120° from each other. Also, in the power converter 1, the current i2 flowing through the three second inductors L2 is a sinusoidal AC current with a phase difference of 120° from each other.

[0079] The control device 7 operates each of the multiple DC-DC converters 2 in step-down mode when the output voltage of each of the multiple DC-DC converters 2 is less than the output voltage of the DC power supply E1 (for example, 48V), and operates each of the multiple DC-DC converters 2 in step-up mode when the output voltage of each of the multiple DC-DC converters 2 is equal to or greater than the output voltage of the DC power supply E1. In the power conversion device 1, the control device 7 changes the output voltage of each of the multiple DC-DC converters 2 within a predetermined voltage range (for example, a range of 0V to 100V).

[0080] When the control device 7 operates each of the multiple DC-DC converters 2 in step-down mode, it controls the third switching element Q3 of each of the multiple second half-bridge circuits 4 to be constantly ON, and controls the fourth switching element Q4 to be constantly OFF.

[0081] When the control device 7 operates each of the multiple DC-DC converters 2 in boost mode, it controls the first switching element Q1 of each of the multiple first half-bridge circuits 3 to be constantly ON, and controls the second switching element Q2 to be constantly OFF.

[0082] The control device 7 is not limited to a step-down mode operation in which the third switching element Q3 is always controlled to be ON, or a step-up mode operation in which the control device 7 is always controlled to be ON, but may also perform a step-up / step-down mode operation in which the first to fourth switching elements Q1 to Q4 are always switched.

[0083] When the three DC-DC converters 2 are operating in step-down mode, the duty cycle command values ​​d3u, d3v, and d3w generated by the command value generation unit 78 shown in Figure 3 are constant (maximum value), while the duty cycle command values ​​d1u, d1v, and d1w each change over time. The waveforms showing the time change of duty cycle command value d1u, d1v, and d1w are waveforms with a phase difference of 120° from each other. In Figure 4, only the duty cycle command value d1u is shown among the duty cycle command values ​​d1u, d1v, and d1w, and only the duty cycle command value d3u is shown among the duty cycle command values ​​d3u, d3v, and d3w.

[0084] When the three DC-DC converters 2 are operating in step-down mode, the phase voltages Va of the U-phase, Vb of the V-phase, and Vc of the W-phase are sinusoidal voltages as shown in Figure 4. However, the phase voltages Va, Vb, and Vc are DC voltages. Furthermore, the line voltages Va-Vb between the U-phase and V-phase, Vb-Vc between the V-phase and W-phase, and Vc-Va between the W-phase and U-phase are sinusoidal AC voltages with a phase difference of 120° from each other, as shown in Figure 4. Also, the phase currents isa of the U-phase, isb of the V-phase, and isc of the W-phase are sinusoidal AC currents with a phase difference of 120° from each other, as shown in Figure 4.

[0085] When the three DC-DC converters 2 are operating in boost mode, the duty cycle command values ​​d1u, d1v, and d1w generated by the command value generation unit 78 shown in Figure 3 are constant (maximum value), while the duty cycle command values ​​d3u, d3v, and d3w each change over time. The waveforms showing the time change of duty cycle command value d3u, the time change of duty cycle command value d3v, and the time change of duty cycle command value d3w are waveforms with a phase difference of 120° from each other.

[0086] In both the boost mode and buck-boost mode of the three DC-DC converters 2, the phase voltage Va of the U-phase, the phase voltage Vb of the V-phase, and the phase voltage Vc of the W-phase are sinusoidal voltages. However, the phase voltages Va, Vb, and Vc are DC voltages. Also, in both the boost mode and buck-boost mode of the three DC-DC converters 2, the line voltages Va-Vb between the U-phase and V-phase, Vb-Vc between the V-phase and W-phase, and Vc-Va between the W-phase and U-phase are sinusoidal AC voltages with a phase difference of 120° from each other. Also, in both the boost mode and buck-boost mode of the three DC-DC converters 2, the phase currents isa of the U-phase, isb of the V-phase, and isc of the W-phase are sinusoidal AC currents with a phase difference of 120° from each other.

[0087] (4) Characteristic diagrams 4 and 5 show the operating waveforms of the power converter 1 (see Figures 1 to 3) when, as an example, the carrier signal frequency is 100 kHz, the dead time period length is 0.4 μs, the inductance of the first inductor L1 is 10 μH, the inductance of each of the three second inductors L2 is 8.2 μH, the DC voltage value Vdc is 48 V, the capacitance of each of the three second capacitors C2 is 5 μF, the inductance and resistance of the AC load 10 are 340 μH and 1 Ω, respectively, the number of poles of the three-phase servo motor which is the AC load 10 is 10, the rotation speed of the three-phase servo motor is 3000 rpm, and the frequencies of the U-phase phase current isa, the V-phase phase current isb, and the W-phase phase current isc are all 250 Hz. In Figure 5, the inductor current is i2, the current flowing through the second inductor L2 of the U phase, and is a sinusoidal alternating current. Also in Figure 5, the phase voltage is the phase voltage Va of the U phase. Also in Figure 5, the ground current is i1, the current flowing through the common ground wiring section 15 (i.e., the current flowing through the first inductor L1).

[0088] Figures 6 and 7 are waveform diagrams of the operation of a power converter according to a comparative example. The power converter of the comparative example differs from the power converter 1 of Embodiment 1 in that it does not have the first inductor L1 and the common ground wiring section 15 of the power converter 1 of Embodiment 1. In the power converter of the comparative example, in each of the three DC-DC converters, the second main terminal of the second switching element of the first half-bridge circuit and the second main terminal of the fourth switching element of the second half-bridge circuit are connected via the ground wiring section. Also, the power converter of the comparative example has an inductor connected between the first connection point in the first half-bridge circuit and the second connection point in the second half-bridge circuit, instead of the second inductor L2 of Embodiment 1. Figures 6 and 7 are waveforms of the operation of the power converter of the comparative example when the inductance of the inductor in each of the three DC-DC converters is 15 μH. In Figure 7, the inductor current is the current flowing through the U-phase inductor and is a sinusoidal alternating current. Also in Figure 7, the phase voltage is the U-phase phase voltage Va. Furthermore, in Figure 7, the ground current is the current flowing through the ground wiring section.

[0089] Figures 4 and 6 show that the power converter 1 of Embodiment 1 can reduce the ripple voltages of phase voltages Va, Vb, and Vc compared to the power converter of the comparative example.

[0090] Furthermore, as can be seen from Figures 5 and 7, the power converter 1 of Embodiment 1 can reduce the ripple current of the inductor current compared to the power converter of the comparative example.

[0091] In the comparative example power converter, the total volume of the three inductors, each having an inductance of 15 μH, is, for example, 10.4 cc. In the power converter 1 of Embodiment 1, for example, if an inductor component with the same current capacity as the inductor of the comparative example power converter is selected as the second inductor L2, the total volume of the first inductor L1 having an inductance of 10 μH and the three second inductors L2, each having an inductance of 8.2 μH, is, for example, 4.0 cc. The reason why the total volume can be reduced in this way is that the inductance required for the inductor in the path through which a large current (sine wave current and a relatively large ripple current) flows is reduced (15 μH in the comparative example, reduced to 8.2 μH in Embodiment 1), and a component with a small current capacity can be selected as the first inductor L1 through which only a relatively small ripple current flows. Furthermore, in the power converter 1 of Embodiment 1, the total mounting area of ​​the first inductor L1 and the three second inductors L2 on the printed circuit board of the power converter 1 can be made smaller than the total mounting area of ​​the three inductors on the printed circuit board of the power converter of the comparative example.

[0092] (5) Advantages The power converter 1 according to Embodiment 1 comprises a plurality of positive input wiring sections 11, a plurality of first ground wiring sections 12, a plurality of output wiring sections 13, a plurality of second ground wiring sections 14, a plurality of first half-bridge circuits 3, a plurality of second half-bridge circuits 4, a first capacitor C1, a plurality of second capacitors C2, a first inductor L1, and a plurality of second inductors L2. The plurality of first half-bridge circuits 3 correspond one-to-one with the plurality of positive input wiring sections 11 and the plurality of first ground wiring sections 12. Each of the plurality of first half-bridge circuits 3 has a first switching element Q1 connected to the corresponding positive input wiring section 11 among the plurality of positive input wiring sections 11, and a second switching element Q2 connected between the corresponding first ground wiring section 12 and the first switching element Q1 among the plurality of first ground wiring sections 12. The plurality of second half-bridge circuits 4 correspond one-to-one with the plurality of output wiring sections 13 and the plurality of second ground wiring sections 14. Each of the multiple second half-bridge circuits 4 includes a third switching element Q3 connected to a corresponding output wiring section 13 among the multiple output wiring sections 13, and a fourth switching element Q4 connected between a corresponding second ground wiring section 14 and the third switching element Q3 among the multiple second ground wiring sections 14. The first capacitor C1 is connected in parallel to the multiple first half-bridge circuits 3. The multiple second capacitors C2 are connected in parallel to each of the multiple second half-bridge circuits 4. The first inductor L1 is provided in a common ground wiring section 15 between one of the multiple first ground wiring sections 12 and the multiple second ground wiring sections 14. The multiple second inductors L2 correspond one-to-one with the multiple second half-bridge circuits 4. Each of the multiple second inductors L2 is connected in series to the fourth switching element Q4 and the first inductor L1 in the corresponding second half-bridge circuit 4 among the multiple second half-bridge circuits 4.

[0093] According to the above configuration, it is possible to reduce the ripple current while miniaturizing the power converter 1. More specifically, the power converter 1 according to Embodiment 1 can reduce both the ripple current of the sinusoidal current flowing through the second inductor L2 and the ripple current of the ground current compared to the case where the first inductor L1 is not provided. Therefore, the inductance of the second inductor L2 through which the sinusoidal current flows can be reduced, making it possible to miniaturize the second inductor L2. Furthermore, since no sinusoidal current flows through the first inductor L1, an inductor component with a smaller current rating than the second inductor L2 can be used, thus making it possible to miniaturize the power converter 1.

[0094] Furthermore, in the power conversion device 1 according to Embodiment 1, the plurality of second inductors L2 correspond one-to-one with the plurality of first half-bridge circuits 3. Each of the plurality of second inductors L2 is connected between the first connection point N1 between the first switching element Q1 and the second switching element Q2 in the corresponding first half-bridge circuit 3 among the plurality of first half-bridge circuits 3, and the second connection point N2 between the third switching element Q3 and the fourth switching element Q4 in the corresponding second half-bridge circuit 4 among the plurality of second half-bridge circuits 4. The power conversion device 1 also further comprises a plurality of first drivers 51, a plurality of second drivers 52, a plurality of third drivers 53, a plurality of fourth drivers 54, an isolated power supply 6, and a control device 7. Each of the plurality of first drivers 51 drives the first switching element Q1 in the corresponding first half-bridge circuit 3 among the plurality of first half-bridge circuits 3. Each of the multiple second drivers 52 drives the second switching element Q2 in the corresponding first half-bridge circuit 3 among the multiple first half-bridge circuits 3. Each of the multiple third drivers 53 drives the third switching element Q3 in the corresponding second half-bridge circuit 4 among the multiple second half-bridge circuits 4. Each of the multiple fourth drivers 54 drives the fourth switching element Q4 in the corresponding second half-bridge circuit 4 among the multiple second half-bridge circuits 4. The isolated power supply 6 is connected to the multiple fourth drivers 54. The control device 7 outputs multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4 to be given to the multiple first drivers 51, multiple second drivers 52, multiple third drivers 53, and multiple fourth drivers 54, respectively.

[0095] With the above configuration, the power supplies for driving multiple second half-bridge circuits 4 can be reduced to a single isolated power supply 6, making it possible to miniaturize the device.

[0096] (Embodiment 2) The power converter 1A according to Embodiment 2 will be described with reference to Figures 8 and 9. With respect to the power converter 1A according to Embodiment 2, components that are the same as those in the power converter 1 according to Embodiment 1 (see Figures 1 to 3) are denoted by the same reference numerals and their description is omitted.

[0097] (1) The power converter 1A according to Embodiment 2 differs from the power converter 1 according to Embodiment 1 in that the three second inductors L2 are coupled inductors. In other words, the power converter 1A according to Embodiment 2 differs from the power converter 1 according to Embodiment 1 in that the three second inductors L2 are included in a single magnetic component (coupled inductor) so as to be magnetically coupled.

[0098] In this embodiment, as shown in Figure 9, the coupled inductor has a common core 81 for the three second inductors L2, and each of the windings 82 for the three second inductors L2 is wound around the core 81. In this embodiment, the core 81 is ring-shaped.

[0099] In this embodiment, the magnetic flux generated by the current i2 (see Figure 8) flowing through each of the three second inductors L2 is magnetically coupled in such a way that it cancels out. In other words, in this embodiment, the three second inductors L2 are in phase coupled.

[0100] In the U-phase second inductor L2, a magnetic flux proportional to the phase current isa (see Figure 8) is generated; in the V-phase second inductor L2, a magnetic flux proportional to the phase current isb (see Figure 8) is generated; and in the W-phase second inductor L2, a magnetic flux proportional to the phase current isc (see Figure 8) is generated. In a coupled inductor, three windings 82 are wound around the core 81 such that the magnetic flux generated in the U-phase second inductor L2, the magnetic flux generated in the V-phase second inductor L2, and the magnetic flux generated in the W-phase second inductor L2 are added together. Since the combined current of the three phase currents isa, isb, and isc is zero, in a coupled inductor, the magnetic flux generated in the U-phase second inductor L2, the magnetic flux generated in the V-phase second inductor L2, and the magnetic flux generated in the W-phase second inductor L2 can be canceled out by adding them together.

[0101] (2) Advantages The power converter 1A according to Embodiment 2 is equipped with a first inductor L1 and a plurality of second inductors L2, similar to the power converter 1 according to Embodiment 1, so it is possible to reduce the size while suppressing current ripple.

[0102] Furthermore, in the power conversion device 1A according to Embodiment 2, since the three second inductors L2 are coupled inductors, it is possible to achieve miniaturization and reduction of losses.

[0103] (Embodiment 3) The power converter 1B according to Embodiment 3 will be described with reference to Figure 10. With respect to the power converter 1B according to Embodiment 3, components that are the same as those in the power converter 1 according to Embodiment 1 (see Figures 1 to 3) are denoted by the same reference numerals and their description is omitted.

[0104] (1) The power converter 1B according to the configuration embodiment 3 differs from the power converter 1 according to embodiment 1 in that each of the plurality of second inductors L2 is connected between the second main terminal of the fourth switching element Q4 in the corresponding second half-bridge circuit 4 among the plurality of second half-bridge circuits 4 and the first inductor L1.

[0105] In this embodiment, each of the multiple second inductors L2 is connected in series with a common first inductor L1. Each of the multiple second inductors L2 is connected in series with the fourth switching element Q4 and the first inductor L1 in the corresponding second half-bridge circuit 4 among the multiple second half-bridge circuits 4. The U-phase second inductor L2 is connected between the second main terminal of the fourth switching element Q4 and the first inductor L1 in the U-phase second half-bridge circuit 4u. The V-phase second inductor L2 is connected between the second main terminal of the fourth switching element Q4 and the first inductor L1 in the V-phase second half-bridge circuit 4v. The W-phase second inductor L2 is connected between the second main terminal of the fourth switching element Q4 and the first inductor L1 in the W-phase second half-bridge circuit 4w.

[0106] The power converter 1B of this embodiment, like the power converter 1 of Embodiment 1 (see Figures 1 to 3), is equipped with multiple (three) fourth drivers 54 (see Figure 2) that correspond one-to-one with multiple (three) fourth switching elements Q4. In this embodiment, multiple (three) isolated power supplies 6 (see Figure 2) of Embodiment 1 are provided, and the multiple isolated power supplies 6 correspond one-to-one with the multiple fourth drivers 54.

[0107] (2) Advantages The power converter 1B according to Embodiment 3 is equipped with a first inductor L1 and a plurality of second inductors L2, similar to the power converter 1 according to Embodiment 1, so it is possible to reduce the size while suppressing current ripple.

[0108] (Other Modifications) Embodiments 1 to 3 described above are merely one of many embodiments of this disclosure. Embodiments 1 to 3 described above can be modified in various ways depending on the design, etc., as long as the objectives of this disclosure are achieved.

[0109] For example, each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 is not limited to n-channel MOSFETs, but may also be p-channel MOSFETs. Also, each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 is a Si-based MOSFET, but is not limited to Si-based MOSFETs, but may also be, for example, a SiC-based MOSFET. Furthermore, each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 is not limited to MOSFETs, but may also be, for example, a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor), or a GaN-based GIT (Gate Injection Transistor).

[0110] Furthermore, in power conversion devices 1 and 1B, the number of DC-DC converters 2, which include the first half-bridge circuit 3, the second half-bridge circuit 4, and the second inductor L2, is not limited to three, but may be four or more, for example.

[0111] Furthermore, the control device 7 may, instead of the first PI control unit 74 that performs PI (Proportional Integral) control, be equipped with, for example, a P control unit that performs P (Proportional) control or a PID control unit that performs PID (Proportional Integral Differential) control as the first feedback control unit that performs feedback control.

[0112] Furthermore, the control device 7 may, instead of the second PI control unit 75 that performs PI control, include, for example, a P control unit that performs P control or a PID control unit that performs PID control, as a second feedback control unit that performs feedback control.

[0113] (Aspects) The following aspects are disclosed in this specification.

[0114] The power converter according to the first embodiment (1; 1A; 1B) comprises a plurality of positive input wiring sections (11), a plurality of first ground wiring sections (12), a plurality of output wiring sections (13), a plurality of second ground wiring sections (14), a plurality of first half-bridge circuits (3), a plurality of second half-bridge circuits (4), a first capacitor (C1), a plurality of second capacitors (C2), a first inductor (L1), and a plurality of second inductors (L2). The plurality of first half-bridge circuits (3) correspond one-to-one with the plurality of positive input wiring sections (11) and the plurality of first ground wiring sections (12). Each of the multiple first half-bridge circuits (3) includes a first switching element (Q1) connected to a corresponding positive input wiring section (11) among the multiple positive input wiring sections (11), and a second switching element (Q2) connected between a corresponding first ground wiring section (12) among the multiple first ground wiring sections (12) and the first switching element (Q1). The multiple second half-bridge circuits (4) correspond one-to-one to the multiple output wiring sections (13) and the multiple second ground wiring sections (14). Each of the multiple second half-bridge circuits (4) includes a third switching element (Q3) connected to a corresponding output wiring section (13) among the multiple output wiring sections (13), and a fourth switching element (Q4) connected between a corresponding second ground wiring section (14) among the multiple second ground wiring sections (14) and the third switching element (Q3). The first capacitor (C1) is connected in parallel to the multiple first half-bridge circuits (3). Multiple second capacitors (C2) are connected in parallel to each of the multiple second half-bridge circuits (4). A first inductor (L1) is provided in a common ground wiring section (15) between one of the multiple first ground wiring sections (12) and multiple second ground wiring sections (14). Multiple second inductors (L2) correspond one-to-one to the multiple second half-bridge circuits (4). Multiple second inductors (L2) are connected in series to the fourth switching element (Q4) and the first inductor (L1) in the corresponding second half-bridge circuit (4) among the multiple second half-bridge circuits (4).

[0115] This embodiment makes it possible to reduce ripple current while miniaturizing the device.

[0116] In the power converter (1; 1A) according to the second embodiment, in the first embodiment, the plurality of second inductors (L2) correspond one-to-one with the plurality of first half-bridge circuits (3). The plurality of second inductors (L2) are connected between the first connection point (N1) between the first switching element (Q1) and the second switching element (Q2) in the corresponding first half-bridge circuit (3) among the plurality of first half-bridge circuits (3), and the second connection point (N2) between the third switching element (Q3) and the fourth switching element (Q4) in the corresponding second half-bridge circuit (4) among the plurality of second half-bridge circuits (4).

[0117] The power converter (1; 1A) according to the third embodiment further comprises, in the second embodiment, a plurality of first drivers (51), a plurality of second drivers (52), a plurality of third drivers (53), a plurality of fourth drivers (54), an isolated power supply (6), and a control device (7). The first drivers (51) correspond to a plurality of first half-bridge circuits (3). Each of the plurality of first drivers (51) drives a first switching element (Q1) in the corresponding first half-bridge circuit (3) among the plurality of first half-bridge circuits (3). The plurality of second drivers (52) correspond to a plurality of first half-bridge circuits (3). The plurality of second drivers (52) drive a second switching element (Q2) in the corresponding first half-bridge circuit (3) among the plurality of first half-bridge circuits (3). The plurality of third drivers (53) correspond to a plurality of second half-bridge circuits (4). Multiple third drivers (53) drive the third switching element (Q3) in the corresponding second half-bridge circuit (4) among the multiple second half-bridge circuits (4). Multiple fourth drivers (54) correspond to multiple second half-bridge circuits (4). Multiple fourth drivers (54) drive the fourth switching element (Q4) in the corresponding second half-bridge circuit (4) among the multiple second half-bridge circuits (4). An isolated power supply (6) is connected to the multiple fourth drivers (54). The control device (7) outputs multiple first control signals (S1), multiple second control signals (S2), multiple third control signals (S3), and multiple fourth control signals (S4) to be given to the multiple first drivers (51), multiple second drivers (52), multiple third drivers (53), and multiple fourth drivers (54), respectively.

[0118] According to this embodiment, the power supply for driving multiple second half-bridge circuits (4) can be a single isolated power supply (6), making it possible to miniaturize the device.

[0119] In the power converter (1A) according to the fourth embodiment, in the second or third embodiment, the plurality of first half-bridge circuits (3) are three first half-bridge circuits (3). The plurality of second half-bridge circuits (4) are three second half-bridge circuits (4). The plurality of second inductors (L2) are three second inductors (L2). The three second inductors (L2) are coupled inductors.

[0120] This embodiment makes it possible to further miniaturize the product.

[0121] The power converter (1) according to the fifth embodiment comprises three positive input wiring sections (11), three first ground wiring sections (12), three output wiring sections (13), three second ground wiring sections (14), three first half-bridge circuits (3), three second half-bridge circuits (4), a first capacitor (C1), three second capacitors (C2), a first inductor (L1), and three second inductors (L2). The three first half-bridge circuits (3) correspond one-to-one with the three positive input wiring sections (11). The three first half-bridge circuits (3) correspond one-to-one with the three first ground wiring sections (12). Each of the three first half-bridge circuits (3) includes a first switching element (Q1) connected to the corresponding positive input wiring section (11) among the three positive input wiring sections (11), and a second switching element (Q2) connected between the corresponding first ground wiring section (12) among the three first ground wiring sections (12) and the first switching element (Q1). The three second half-bridge circuits (4) correspond one-to-one to the three output wiring sections (13) and the three second ground wiring sections (14). Each of the three second half-bridge circuits (4) includes a third switching element (Q3) connected to the corresponding output wiring section (13) among the three output wiring sections (13), and a fourth switching element (Q4) connected between the corresponding second ground wiring section (14) among the three second ground wiring sections (14) and the third switching element (Q3). The first capacitor (C1) is connected in parallel to the three first half-bridge circuits (3). The second capacitor (C2) is connected in parallel to each of the three second half-bridge circuits (4). The first inductor (L1) is provided in the common ground wiring section (15) between one of the three first ground wiring sections (12) and the three second ground wiring sections (14). The three second inductors (L2) correspond one-to-one to the three first half-bridge circuits (3). The three second inductors (L2) correspond one-to-one to the three second half-bridge circuits (4).The three second inductors (L2) are connected between the first connection point (N1) between the first switching element (Q1) and the second switching element (Q2) in the corresponding first half-bridge circuit (3) among the three first half-bridge circuits (3), and the second connection point (N2) between the third switching element (Q3) and the fourth switching element (Q4) in the corresponding second half-bridge circuit (4) among the three second half-bridge circuits (4).

[0122] This embodiment makes it possible to reduce ripple current while miniaturizing the device.

[0123] 1, 1A, 1B Power converter 3 First half-bridge circuit 4 Second half-bridge circuit 5 Power supply 6 Isolated power supply 7 Control device 11 Positive input wiring section 12 First ground wiring section 13 Output wiring section 14 Second ground wiring section 15 Common ground wiring section 51 First driver 52 Second driver 53 Third driver 54 Fourth driver 81 Core 82 Winding C1 First capacitor C2 Second capacitor L1 First inductor L2 Second inductor N1 First connection point N2 Second connection point Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element S1 First control signal S2 Second control signal S3 Third control signal S4 Fourth control signal T3 Output terminal

Claims

1. A plurality of first half-bridge circuits having a plurality of positive input wiring sections, a plurality of first ground wiring sections, a plurality of output wiring sections, a plurality of second ground wiring sections, a plurality of first half-bridge circuits having a first switching element that corresponds one-to-one with the plurality of positive input wiring sections and the plurality of first ground wiring sections, and each of these elements being connected to the corresponding positive input wiring section among the plurality of positive input wiring sections, and a second switching element that is connected between the corresponding first ground wiring section among the plurality of first ground wiring sections and the first switching element, a plurality of second half-bridge circuits having a third switching element that corresponds one-to-one with the plurality of output wiring sections and the plurality of second ground wiring sections, and a fourth switching element that is connected between the corresponding second ground wiring section among the plurality of second ground wiring sections and the third switching element, a first capacitor connected in parallel to the plurality of first half-bridge circuits, a plurality of second capacitors connected in parallel to each of the plurality of second half-bridge circuits, A power conversion device comprising: a first inductor provided in a common ground wiring section between one of the plurality of first ground wiring sections and the plurality of second ground wiring sections; and a plurality of second inductors that correspond one-to-one with the plurality of second half-bridge circuits and are connected in series with the fourth switching element and the first inductor in the corresponding second half-bridge circuit among the plurality of second half-bridge circuits.

2. The power conversion device according to claim 1, wherein the plurality of second inductors correspond one-to-one with the plurality of first half-bridge circuits and are connected between a first connection point between the first switching element and the second switching element in a corresponding first half-bridge circuit among the plurality of first half-bridge circuits and a second connection point between the third switching element and the fourth switching element in a corresponding second half-bridge circuit among the plurality of second half-bridge circuits.

3. The power conversion device according to claim 2, further comprising: a plurality of first drivers corresponding to the plurality of first half-bridge circuits and driving the first switching elements in the corresponding first half-bridge circuits among the plurality of first half-bridge circuits; a plurality of second drivers corresponding to the plurality of first half-bridge circuits and driving the second switching elements in the corresponding first half-bridge circuits among the plurality of first half-bridge circuits; a plurality of third drivers corresponding to the plurality of second half-bridge circuits and driving the third switching elements in the corresponding second half-bridge circuits among the plurality of second half-bridge circuits; a plurality of fourth drivers corresponding to the plurality of second half-bridge circuits and driving the fourth switching elements in the corresponding second half-bridge circuits among the plurality of second half-bridge circuits; an isolated power supply connected to the plurality of fourth drivers; and a control device that outputs a plurality of first control signals, a plurality of second control signals, a plurality of third control signals, and a plurality of fourth control signals to each of the plurality of first drivers, the plurality of second drivers, the plurality of third drivers, and the plurality of fourth drivers, respectively.

4. The power conversion device according to claim 2 or 3, wherein the plurality of first half-bridge circuits are three first half-bridge circuits, the plurality of second half-bridge circuits are three second half-bridge circuits, the plurality of second inductors are three second inductors, and the three second inductors are coupled inductors.

5. Three first half-bridge circuits having three positive input wiring sections, three first ground wiring sections, three output wiring sections, three second ground wiring sections, three first half-bridge circuits having a first switching element that corresponds one-to-one with the three positive input wiring sections and the three first ground wiring sections, and each having a first switching element connected to the corresponding positive input wiring section among the three positive input wiring sections, and a second switching element connected between the corresponding first ground wiring section among the three first ground wiring sections and the first switching element, three second half-bridge circuits having a third switching element that corresponds one-to-one with the three output wiring sections and the three second ground wiring sections, and each having a fourth switching element connected between the corresponding second ground wiring section among the three second ground wiring sections and the third switching element, a first capacitor connected in parallel to the three first half-bridge circuits, and three second capacitors connected in parallel to each of the three second half-bridge circuits. A power converter comprising: a first inductor provided in a common ground wiring section between one of the three first ground wiring sections and the three second ground wiring sections; and three second inductors, each corresponding one-to-one to the three first half-bridge circuits and each corresponding one-to-one to the three second half-bridge circuits, and connected between a first connection point between the first switching element and the second switching element in the corresponding first half-bridge circuit and a second connection point between the third switching element and the fourth switching element in the corresponding second half-bridge circuit.

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