Photoelectric converter, photoelectric converter system, mobile device, equipment and drive method
By controlling the buffer circuit to maintain a stable output node potential during reduced power states, the device addresses image quality issues in photoelectric conversion devices, ensuring accurate image processing.
JP7877380B2Active Publication Date: 2026-06-22CANON KK
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- CANON KK
- Filing Date
- 2024-04-11
- Publication Date
- 2026-06-22
AI Technical Summary
Technical Problem
The photoelectric conversion device described in Patent Document 1 does not adequately address the issue of image quality deterioration due to fluctuations in the potential of a floating output node when parts of the buffer circuit are powered off.
Method used
The device controls the buffer circuit to operate in a first state with normal power consumption and a second state with reduced power consumption, maintaining the potential of the output node to a predetermined value during the second state, thereby preventing fluctuations.
Benefits of technology
This approach reduces image quality degradation by stabilizing the output node potential, ensuring accurate and high-quality image processing even when some column circuits are powered off.
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Smart Images
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Abstract
To provide a technique that can reduce a deterioration in image quality due to variations of an output node in a floating state.SOLUTION: A photoelectric conversion device of the present invention comprises a plurality of pixels arranged over a plurality of rows and a plurality of columns, a plurality of column circuits corresponding respectively to the plurality of columns; and a control unit. The column circuit has a comparison circuit that has a first input node to which pixel signals from the plurality of pixels on a corresponding column are input and a second input node to which a reference signal is input, and a buffer circuit that has an output node outputting the reference signal to the comparison circuit on the corresponding column. The control unit can control the potentials of the output nodes in the plurality of buffer circuits to be a predetermined potential.SELECTED DRAWING: Figure 3
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