Ad conversion circuit and communication device

Abstract

The present invention inhibits interference of time-interleaved AD converters.　An AD conversion circuit (TD1) is provided with a plurality of time-interleaved AD converters (AD1 to AD4) and a plurality of sample-and-hold circuits (SH1 to SH4; SW1, SC1, GW1, . . . , SW4, SC4, and GW4) that sample and hold an analog input (AI) and a reference potential (VS) of each of the plurality of AD converters (AD1 to AD4).

Description

AD Conversion Circuit and Communication Device

[0001] This technology relates to an AD conversion circuit, an imaging device, and an electronic circuit. Specifically, this technology relates to an AD conversion circuit and a communication device capable of time interleaving.

[0002] To speed up AD conversion, there is a time interleaving technology in which a plurality of AD converters are paralleled. For example, in a time interleaved AD converter, a technology for correcting timing errors based on sampling of the analog output of an input buffer has been proposed (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2016-213827

[0004] However, in the above-mentioned conventional technology, if the ground for setting the reference potential of the input buffer and the AD converter is directly connected, there is a risk of deterioration in the performance of AD conversion due to interference.

[0005] This technology has been created in view of such a situation, and an object thereof is to suppress interference of a time interleaved AD converter.

[0006] This technology has been made to solve the above-mentioned problems, and a first aspect thereof is an AD conversion circuit including a plurality of AD converters to be time interleaved and a plurality of sample and hold circuits for sample and hold of analog inputs and reference potentials of the plurality of AD converters. Thereby, while enabling sample and hold of an analog input based on a reference potential, an effect is brought about that interference of an AD converter caused by fluctuations in the reference potential is suppressed.

[0007] Also, in the first aspect, the sample and hold of the analog input and the reference potential may be synchronized for each of the AD converters. Thereby, while enabling sample and hold of an analog input based on a reference potential, an effect is brought about that fluctuations in the reference potential between AD converters are blocked.

[0008] Furthermore, in the first aspect, the sample-and-hold circuit may include a sample-and-hold capacitor that holds a voltage corresponding to the analog input, an input switch that switches the analog input input to one end of the sample-and-hold capacitor, and a reference switch that switches the reference potential input to the other end of the sample-and-hold capacitor. This allows the analog input and the reference potential to be applied to the sample-and-hold capacitor while blocking fluctuations in the reference potential between the AD converters.

[0009] Furthermore, in the first aspect, one end of the reference switch may be connected to the reference potential. This results in the effect of setting one end of the sample-hold capacitor to the reference potential or disconnecting it from the reference potential via the reference switch.

[0010] Furthermore, in the first aspect, the input switch and the reference switch may be turned on and off simultaneously at different times between the AD converters. This results in the analog input and reference potential being applied to the sample-and-hold capacitor while blocking fluctuations in the reference potential between the AD converters.

[0011] Furthermore, in the first aspect, the ON period of the input switch may include an overlapping period that overlaps with the ON period of the reference switch and a non-overlapping period that does not overlap with the ON period of the reference switch. This ensures that the analog input and reference potential are applied to the sample-and-hold capacitor even when there is a difference between the ON period of the input switch and the ON period of the reference switch.

[0012] Furthermore, in the first aspect, the ON period of the reference switch may include an overlapping period that overlaps with the ON period of the input switch and a non-overlapping period that does not overlap with the ON period of the input switch. This prevents charge injection and feedthrough of the input switch while ensuring that the analog input and reference potential are applied to the sample-hold capacitance.

[0013] Furthermore, in the first aspect, the system may include a switch control unit that controls the on / off state of the input switch and the reference switch. This provides the effect of controlling the application of the analog input and reference potential to the sample-hold capacitor while blocking fluctuations in the reference potential between the AD converters.

[0014] Furthermore, in the first aspect, a delay circuit may be provided to delay the sampling timing of the analog input. This prevents charge injection and feedthrough of the input switch when the analog input and reference potential are applied to the sample-hold capacitor, while suppressing an increase in circuit size.

[0015] Furthermore, in the first aspect, the AD converter may include a successive approximation type AD converter with an input capacitor driven based on the analog input, and the sample-and-hold capacitor may be shared with the input capacitor. This allows for sample-and-hold of the analog input based on a reference potential while suppressing an increase in circuit size, and also suppresses interference of the AD converter caused by fluctuations in the reference potential.

[0016] Furthermore, in the first aspect, a buffer may be provided to propagate the analog input and the reference potential to the sample-and-hold circuit. This has the effect of increasing the driving force of the sample-and-hold circuit.

[0017] The second aspect is a communication device comprising multiple A / D converters that time-interleave the received signal as an analog input, multiple sample-and-hold circuits that sample and hold the analog inputs and reference potentials of each of the multiple A / D converters, and a logic circuit that serializes the outputs of the multiple A / D converters. This enables sample-and-hold of the received signal based on the reference potential, while suppressing interference from the A / D converters caused by fluctuations in the reference potential.

[0018] This is a block diagram showing an example of the configuration of an AD conversion circuit according to the first embodiment. This is a timing chart showing an example of the on / off timing of the input switch and reference switch according to the first embodiment. This is a timing chart showing another example of the on / off timing of the input switch and reference switch according to the first embodiment. This is a timing chart showing yet another example of the on / off timing of the input switch and reference switch according to the first embodiment. This is a block diagram showing an example of the configuration of an AD conversion circuit according to the second embodiment. This is a block diagram showing an example of the configuration of an AD conversion circuit according to the third embodiment. This is a timing chart showing the on / off timing of the input switch SW1 and reference switch GW1 according to the third embodiment. This is a block diagram showing an example of the configuration of an AD converter according to the fourth embodiment. This is a block diagram showing another example of the configuration of an AD converter according to the fourth embodiment. This is a block diagram showing an example of the configuration of a communication device according to the fifth embodiment. This is a diagram showing the eye pattern of the signal during sampling according to the fifth embodiment.

[0019] The following describes the embodiments for implementing this technology (hereinafter referred to as embodiments). The description will be in the following order: 1. First embodiment (an example in which the analog inputs and reference potentials of each of the multiple time-interleaved AD converters are sampled and held) 2. Second embodiment (an example in which the analog inputs of each of the multiple time-interleaved AD converters are sampled and held via input switches, and the reference potential is sampled and held via a reference switch, and the input switches and reference switches are each composed of MOS (Metal Oxide Semiconductor) transistors) 3. Third embodiment (an example in which the analog inputs of each of the multiple time-interleaved AD converters are sampled and held via input switches, and the reference potential is sampled and held via a reference switch, and a delay circuit is provided to delay the sampling timing of the analog input) 4. Fourth embodiment (an example in which the analog inputs and reference potentials of each of the multiple time-interleaved AD converters are sampled and held, and a successive approximation type AD converter with an input capacitance driven based on the analog input is used as the AD converter) 5. Fifth Embodiment (An example in which a Time Interleaved Analog to Digital Converter (TIADC) that samples and holds the analog inputs and reference potentials of multiple time-interleaved A / D converters is applied to a receiver)

[0020] <1. First Embodiment> Figure 1 is a block diagram showing an example of the configuration of an AD conversion circuit according to the first embodiment. In this figure, an example is shown in which four AD converters AD1 to AD4 are time-interleaved, but a TIAD converter that time-interleaves two or more AD converters may also be used.

[0021] In the figure, the TIAD converter TD1 performs AD conversion based on time interleaving operation. A buffer BA is connected before the TIAD converter TD1, and a logic circuit LG is connected after the TIAD converter TD1. The TIAD converter TD1 comprises multiple AD converters AD1 to AD4.

[0022] Each AD converter AD1 to AD4 is time-interleaved. In this case, each AD converter AD1 to AD4 samples and holds the analog input AI and the reference potential VS in synchronous manner, and performs AD conversion based on the sampled and held analog input AI. The reference potential VS may be the ground potential GND. In this case, the ground potential GND may be supplied to each AD converter AD1 to AD4 as the reference potential VS via a wire PW connecting the TIAD converter TD1 to the substrate. Here, the sampling timing of the analog input AI and the reference potential VS can be synchronized with each AD converter AD1 to AD4, but can be made to differ from each other. As a result, in each AD converter AD1 to AD4, the reference potential VS can be blocked except during the sampling period of the analog input AI. Each AD converter AD1 to AD4 is equipped with a sample-and-hold circuit SH1 to SH4 and an AD conversion unit AK1 to AK4, respectively.

[0023] Each sample-and-hold circuit SH1 to SH4 samples and holds the analog input AI and reference potential VS of the respective A / D converters AD1 to AD4. Each sample-and-hold circuit SH1 to SH4 is equipped with input switches SW1 to SW4, reference switches GW1 to GW4, and sample-and-hold capacitors SC1 to SC4, respectively.

[0024] Each input switch SW1 to SW4 switches the analog input AI that is input to one end of each sample-and-hold capacitor SC1 to SC4. Each input switch SW1 to SW4 is connected between one end of each sample-and-hold capacitor SC1 to SC4 and the output of buffer BA, respectively.

[0025] Each reference switch GW1 to GW4 switches the reference potential VS input to the other end of each sample-hold capacitor SC1 to SC4. Each reference switch GW1 to GW4 is connected between the other end of each sample-hold capacitor SC1 to SC4 and the reference potential VS. Each input switch SW1 to SW4 and each reference switch GW1 to GW4 can be switched on and off synchronously in each AD converter AK1 to AK4. In this case, each input switch SW1 to SW4 and each reference switch GW1 to GW4 may be switched on and off simultaneously at different times in each AD converter AK1 to AK4, or there may be a difference in the on or off times of each input switch SW1 to SW4 and each reference switch GW1 to GW4.

[0026] Each sample-and-hold capacitor SC1 to SC4 holds a voltage corresponding to the analog input AI, with reference potential VS as the reference, based on the on / off state of each input switch SW1 to SW4 and each reference switch GW1 to GW4. One end of each sample-and-hold capacitor SC1 to SC4 is connected between each input switch SW1 to SW4 and each AD converter AK1 to AK4, respectively. The other end of each sample-and-hold capacitor SC1 to SC4 is connected to each reference switch GW1 to GW4, respectively.

[0027] If the other ends of each sample-and-hold capacitor SC1 to SC4 are directly connected to the reference potential VS, fluctuations in the reference potential VS during the AD conversion operation of each A / D converter AD1 to AD4 will propagate between A / D converters AD1 to AD4. Furthermore, fluctuations in the reference potential VS during the operation of each A / D converter AD1 to AD4 will cause fluctuations in the ground potential of buffer BA. This will cause fluctuations in the analog input AI output from buffer BA, reducing the AD conversion accuracy of each A / D converter AD1 to AD4.

[0028] In this configuration, the other ends of each sample-and-hold capacitor SC1 to SC4 are directly connected to the reference potential VS via each reference switch GW1 to GW4. This allows the reference potential VS to be blocked except during the sampling period of the analog input AI of each AD converter AD1 to AD4, thereby suppressing a decrease in the AD conversion accuracy of each AD converter AD1 to AD4.

[0029] Each AD conversion unit AK1 to AK4 converts the analog input AI, sampled and held by each sample-and-hold circuit SH1 to SH4, into digital values ​​D1 to D4, respectively. The digital values ​​D1 to D4 converted by each AD conversion unit AK1 to AK4 are output in parallel to the logic circuit LG.

[0030] Buffer BA drives the load capacitance of the TIAD converter TD1. In this case, the load capacitance of the TIAD converter TD1 includes sample-and-hold capacitances SC1 to SC4. The power supply for buffer BA is connected between the power supply potential VDD and the reference potential VS. The reference potential VS is connected to one end of the reference switches GW1 to GW4.

[0031] The logic circuit LG serializes the outputs of AD4 from multiple AD converters AD1. At this time, the outputs of AD4 from multiple AD converters AD1 are input to the logic circuit LG in parallel.

[0032] Figure 2 is a timing chart showing an example of the on / off timing of the input switch and reference switch according to the first embodiment.

[0033] In the figure, each input switch SW1 to SW4 and each reference switch GW1 to GW4 are simultaneously turned on and off at different times between each AD converter AK1 to AK4. At this time, the analog input AI and the reference potential VS can be sampled during the fall of each input switch SW1 to SW4 and each reference switch GW1 to GW4. The fall timing of each input switch SW1 to SW4 and each reference switch GW1 to GW4 can be set to the time when the fluctuation of the reference potential VS during switching of each input switch SW1 to SW4 and each reference switch GW1 to GW4 settles down. Here, the fall timing of each input switch SW1 to SW4 and each reference switch GW1 to GW4 is synchronized for each AD converter AD1 to AD4.

[0034] Figure 3 is a timing chart showing other examples of the on / off timing of the input switches and reference switches according to the first embodiment. Although the figure shows the on / off timing of input switch SW1 and reference switch GW1, the on / off timing of input switches SW2 to SW4 and reference switches GW2 to GW4 can be set in the same way.

[0035] In the figure, the ON period of the reference switch GW1 includes an overlapping period KJ that overlaps with the ON period of the input switch SW1, and non-overlapping periods NJ1 and NJ2 that do not overlap with the ON period of the input switch SW1. In this case, the ON period of the reference switch GW1 can be made longer than the ON period of the input switch SW1. In the figure, an example is shown in which the non-overlapping periods NJ1 and NJ2 are provided on both the rise side and the fall side of the input switch SW1, but they may be provided on either the rise side or the fall side of the input switch SW1. Also, the lengths of the non-overlapping periods NJ1 and NJ2 may be different from each other.

[0036] Figure 4 is a timing chart showing yet another example of the on / off timing of the input switches and reference switches according to the first embodiment. Although the figure shows the on / off timing of input switch SW1 and reference switch GW1, the on / off timing of input switches SW2 to SW4 and reference switches GW2 to GW4 can be set in the same way.

[0037] In the figure, the ON period of input switch SW1 includes an overlapping period KJ that overlaps with the ON period of reference switch GW1, and non-overlapping periods NJ1 and NJ2 that do not overlap with the ON period of reference switch GW1. In this case, the ON period of reference switch GW1 can be shorter than the ON period of input switch SW1. In the figure, an example is shown in which the non-overlapping periods NJ1 and NJ2 are provided on both the rise side and the fall side of reference switch GW1, but they may be provided on either the rise side or the fall side of reference switch GW1.

[0038] Here, by providing an overlapping period KJ and non-overlapping periods NJ1 and NJ2 during the ON period of input switch SW1, it is possible to simultaneously apply the analog input AI and the reference potential VS to the sample-and-hold capacitor SH1 while preventing charge injection and feedthrough of input switch SW1.

[0039] As described above, in the first embodiment, the analog input AI and reference potential VS of each of the multiple time-interleaved AD converters AD1 to AD4 are sampled and held. This allows the multiple AD converters AD1 to AD4 to operate in time-interleaved mode while suppressing interference between them caused by fluctuations in the reference potential VS. Therefore, it is possible to speed up AD conversion while suppressing a decrease in the AD conversion accuracy of the TIAD converter TD1.

[0040] <2. Second Embodiment>In the above-described first embodiment, the analog inputs AI and the reference potential VS of the plurality of AD converters AD1 to AD4 that are time-interleaved are sample-held. In this second embodiment, the analog inputs AI of the plurality of AD converters AD1 to AD4 that are time-interleaved are sample-held via input switches SW1 to SW4, and the reference potential VS is sample-held via reference switches GW1 to GW4. The input switches SW1 to SW4 and the reference switches GW1 to GW4 are each constituted by MOS transistors.

[0041] FIG. 5 is a block diagram showing a configuration example of an AD conversion circuit according to the second embodiment.

[0042] In this figure, this AD conversion circuit includes a TIAD converter TD2 instead of the TIAD converter TD1 of the first embodiment described above. Also, a switch control unit SB is added to the AD conversion circuit of the first embodiment described above. The other configuration of the AD conversion circuit of the second embodiment is the same as the configuration of the AD conversion circuit of the first embodiment described above.

[0043] The TIAD converter TD2 includes AD converters AD21 to AD24 instead of the AD converters AD1 to AD4 of the first embodiment described above. The other configuration of the TIAD converter TD2 of the second embodiment is the same as the configuration of the TIAD converter TD2 of the first embodiment described above.

[0044] Each of the AD converters AD21 to AD24 includes sample-hold circuits SH21 to SH24 instead of the sample-hold circuits SH1 to SH4 of the first embodiment described above. The other configuration of each of the AD converters AD21 to AD24 of the second embodiment is the same as the configuration of each of the AD converters AD1 to AD4 of the first embodiment described above.

[0045] Each of the sample hold circuits SH21 to SH24 includes MOS transistors SM1 to SM4 as the input switches SW1 to SW4. Also, each of the sample hold circuits SH21 to SH24 includes MOS transistors GM1 to GM4 as the reference switches GW1 to GW4. The other configurations of the sample hold circuits SH21 to SH24 in the second embodiment are the same as those of the sample hold circuits SH1 to SH4 in the first embodiment described above.

[0046] Each of the MOS transistors SM1 to SM4 is turned on and off based on the control of the switch control unit SB. Each of the MOS transistors SM1 to SM4 is connected between one end of each of the sample hold capacitors SC1 to SC4 and the output of the buffer BA. The gates of each of the MOS transistors SM1 to SM4 are connected to the switch control unit SB.

[0047] Each of the MOS transistors GM1 to GM4 is turned on and off based on the control of the switch control unit SB. Each of the MOS transistors GM1 to GM4 is connected between the other end of each of the sample hold capacitors SC1 to SC4 and the reference potential VS. The gates of each of the MOS transistors GM1 to GM4 are connected to the switch control unit SB.

[0048] The switch control unit SB can turn on and off each of the MOS transistors SM1 to SM4 and GM1 to GM4 in synchronization for each of the AD converters AD21 to AD24. The control output of the switch control unit SB can be provided for each of the AD converters AD21 to AD24. At this time, the switch control unit SB may turn on and off each of the MOS transistors SM1 to SM4 and GM1 to GM4 simultaneously at different times among the AD converters AD21 to AD24, or there may be a deviation in the on-time or off-time of each of the MOS transistors SM1 to SM4 and GM1 to GM4.

[0049] As described above, in the second embodiment, the input switches SW1 to SW4 and the reference switches GW1 to GW4 of each sample-and-hold circuit SH1 to SH4 are each made of MOS transistors. This allows for the sample-and-hold operation of the analog input AI and reference potential VS of each of the multiple AD converters AD21 to AD24 while suppressing an increase in the circuit size of the input switches SW1 to SW4 and the reference switches GW1 to GW4.

[0050] In the second embodiment described above, an example was shown in which each input switch SW1 to SW4 and each reference switch GW1 to GW4 are each composed of NMOS transistors. However, they may also be composed of PNMOS transistors, CMOS transistors, or bootstrap switches. Furthermore, in the second embodiment described above, an example was shown in which each input switch SW1 to SW4 and each reference switch GW1 to GW4 are controlled via the same control line. However, each input switch SW1 to SW4 and each reference switch GW1 to GW4 may be controlled via separate control lines. In this case, the separate control lines that control each input switch SW1 to SW4 and each reference switch GW1 to GW4 are synchronized.

[0051] <3. Third Embodiment> In the first embodiment described above, the analog inputs AI and reference potential VS of each of the multiple time-interleaved AD converters AD1 to AD4 were sampled and held. In this third embodiment, the analog inputs of each of the multiple time-interleaved AD converters are sampled and held via input switches, and the reference potential is sampled and held via a reference switch, and a delay circuit is provided to delay the sampling timing of the analog inputs.

[0052] Figure 6 is a block diagram showing an example configuration of an AD conversion circuit according to the third embodiment.

[0053] In the figure, this AD conversion circuit includes a TIAD converter TD3 instead of the TIAD converter TD2 of the second embodiment described above. The other configurations of the AD conversion circuit of the third embodiment are the same as those of the AD conversion circuit of the second embodiment described above.

[0054] The TIAD converter TD3 includes AD converters AD31 to AD34 instead of AD converters AD21 to AD24 in the second embodiment described above. The other configurations of the TIAD converter TD3 in the third embodiment are the same as those of the TIAD converter TD2 in the second embodiment described above.

[0055] Each of the AD converters AD31 to AD34 has delay circuits BA1 to BA4 added to the AD converters AD21 to AD24 of the second embodiment described above. The other configurations of each of the AD converters AD31 to AD34 of the third embodiment are the same as the configurations of each of the AD converters AD21 to AD24 of the second embodiment described above.

[0056] Each delay circuit BA1 to BA4 delays the sampling timing of the analog input AI. The control output of each delay circuit BA1 to BA4 in the switch control unit SB is connected to the gates of each MOS transistor SM1 to SM4, respectively. Each delay circuit BA1 to BA4 may be a buffer or an even-numbered series of inverters.

[0057] Figure 7 is a timing chart showing the on / off timing of input switch SW1 and reference switch GW1 according to the third embodiment. Although the figure shows the on / off timing of input switch SW1 and reference switch GW1, the on / off timing of input switches SW2 to SW4 and reference switches GW2 to GW4 can be set in the same way.

[0058] In the figure, the ON period of input switch SW1 is delayed relative to the ON period of reference switch GW1. At this time, a discrepancy MS occurs between the ON period of input switch SW1 and the ON period of reference switch GW1.

[0059] Thus, in the third embodiment described above, delay circuits BA1 to BA4 are provided to sample and hold the analog input AI and reference potential VS of each of the multiple time-interleaved AD converters AD1 to AD4, and to delay the sampling timing of the analog input AI. This makes it possible to control the application timing of the analog input AI and reference potential VS to each sample-and-hold capacitor SC1 to SC4 while blocking fluctuations in the reference potential VS between the AD converters AD1 to AD4.

[0060] <4. Fourth Embodiment> In the first embodiment described above, the analog inputs AI and reference potential VS of each of the multiple time-interleaved AD converters AD1 to AD4 were sampled and held. In this fourth embodiment, a successive approximation AD converter with an input capacitance driven based on the analog input is used as the AD converter, and the sample-and-hold capacitance is used in conjunction with the input capacitance of the successive approximation AD converter.

[0061] Figure 8 is a block diagram showing an example configuration of an AD converter according to the fourth embodiment.

[0062] In the figure, the AD converter AD41 operates as a successive approximation type AD converter equipped with input capacitors PC1 to PC4 that are driven based on the analog input AI. The AD converter AD41 includes an input switch SW1, reference switches KW1 to KW4, high-side switches HW1 to HW4, low-side switches LW1 to LW4, input capacitors PC1 to PC4, a comparator CNP, and a control unit CNT.

[0063] Each high-side switch HW1 to HW4 samples the analog input AI with respect to a reference voltage VH, based on the control of the control unit CNT. Each low-side switch LW1 to LW4 samples the analog input AI with respect to a reference voltage VL, based on the control of the control unit CNT. The reference voltage VH can be set to a voltage higher than the reference voltage VL.

[0064] The input capacitors PC1 to PC4 have their capacitance values ​​set sequentially in a binary (power of 2) ratio. One end of each input capacitor PC1 to PC4 is connected to the input of comparator CNP. The other end of each input capacitor PC1 to PC4 is connected to a reference voltage VH via high-side switches HW1 to HW4, respectively. The other end of each input capacitor PC1 to PC4 is connected to a reference voltage VL via low-side switches LW1 to LW4, respectively.

[0065] Each input capacitor PC1 to PC4 can also be used as a sample-and-hold capacitor SC1. One end of each input capacitor PC1 to PC4 is connected between the input switch SW1 and the input of the comparator CNP, respectively. The other end of each input capacitor PC1 to PC4 is connected to the reference potential VS via the reference switches GW1 to GW4, respectively. Each input capacitor PC1 to PC4 can hold a voltage corresponding to the analog input AI based on the on / off status of the input switch SW1 and each reference switch KW1 to KW4. The on / off timing of the input switch SW1 and each reference switch KW1 to KW4 may be the on / off timing of either the input switch SW1 or the reference switch GW1 as shown in Figures 2 to 4 and Figure 7.

[0066] Input switch SW1 switches the analog input AI that is input from each input capacitor PC1 to one end of PC4. Input switch SW1 is connected between each input capacitor PC1 to one end of PC4 and the output of buffer BA.

[0067] Each reference switch KW1 to KW4 switches the reference potential VS input to the other end of each input capacitor PC1 to PC4. Each reference switch GW1 to GW4 is connected between the other end of each input capacitor PC1 to PC4 and the reference potential VS.

[0068] Comparator CNP compares two comparator inputs. In this case, one comparator input can be set to the potential held by each input capacitor PC1 to PC4, and the other comparator input can be set to ground potential.

[0069] The control unit CNT controls the high-side switches HW1 to HW4 and the low-side switches LW1 to LW4 on and off based on the output of the comparator CNP, and generates the comparison voltage for the next bit.

[0070] The control unit CNT then turns on and then off the high-side switches HW1 to HW4 and the low-side switches LW1 to LW4. At this time, the intermediate value of the reference voltage is given as an initial value to each input capacitor PC1 to PC4. Then, the voltage (VH - VL) / 2 is compared by the comparator CNP, and the comparison result is input to the control unit CNT. Subsequently, based on the comparison result of the comparator CNP, the control unit CNT switches the high-side switches HW1 to HW4 and the low-side switches LW1 to LW4 using binary search, and performs a comparison operation between the reference voltages VH and VL and the analog input AI from the most significant bit (MSB) to the least significant bit (LSB).

[0071] Figure 9 is a block diagram showing other configuration examples of the AD converter according to the fourth embodiment.

[0072] In the same figure, the AD converter AD42 is equipped with a reference switch GW1 instead of the reference switches KW1 to KW4 in Figure 8. The other configurations of the AD converter AD42 are the same as those of the AD converter AD41 in Figure 8.

[0073] The reference switch GW1 is connected between the other end of each input capacitor PC1 to PC4 and the reference potential VS. The on / off timing of the input switch SW1 and reference switch GW1 of the AD converter AD42 may be any on / off timing of the input switch SW1 and reference switch GW1 shown in Figures 2 to 4 and Figure 7.

[0074] Thus, in the fourth embodiment described above, successive approximation AD converters AD41 and AD42 are used, each equipped with input capacitors PC1 to PC4 driven based on the analog input AI, and the sample-and-hold capacitor that holds the voltage corresponding to the analog input AI is shared with the input capacitors PC1 to PC4 of the successive approximation AD converter. This makes it possible to sample and hold the analog input AI with respect to the reference potential VS while suppressing an increase in the circuit size of each AD converter AD41 and AD42, and also suppresses interference between each AD converter AD41 and AD42 caused by fluctuations in the reference potential VS.

[0075] <5. Fifth Embodiment> In the first embodiment described above, the analog input AI and reference potential VS of each of the multiple time-interleaved AD converters AD1 to AD4 were sampled and held. In this fifth embodiment, a TIAD converter TD1 that samples and holds the analog input AI and reference potential VS of each of the multiple time-interleaved AD converters AD1 to AD4 is applied to the receiver.

[0076] Figure 10 is a block diagram showing an example configuration of a communication device according to the fifth embodiment.

[0077] In the figure, the receiver RB comprises the buffer BA, TIAD converter TD1, and logic circuit LG of the first embodiment described above. The receiver RB receives the transmission signal TS transmitted from the transmitter TB as a received signal and can use it as an analog input AI. At this time, the TIAD converter TD1 converts the received signal received from the transmitter TB from digital value D1 to D4 based on time-interleaved AD conversion and outputs it in parallel to the logic circuit LG. Then, the digital values ​​D1 to D4 are serialized and output via the logic circuit LG. The receiver RB may be an NRZ type, a PAM4 type, or any other type.

[0078] Figure 11 shows the eye pattern of the signal during sampling according to the fifth embodiment. In the figure, a shows an example in which the TIAD converter TD12 of the first embodiment described above is applied to NRZ (Non Return to Zero) reception, and b shows an example in which the TIAD converter TD12 of the first embodiment described above is applied to PAM4 (Pulse Amplitude Modulation 4) reception.

[0079] In the figure, at point a, during NRZ reception, the eye pattern is open and binary data V is obtained. １ , V ２ This allows sampling to be performed. This enables receiver RB to improve reception accuracy in NRZ reception.

[0080] In the figure, at point b, when PAM4 is received, the eye pattern is open and quadrant data V is received. １ From V ４ This allows for sampling. As a result, receiver RB can improve the reception accuracy in PAM4 reception.

[0081] In the receiver RB of the fifth embodiment described above, an example was shown in which the TIAD converter TD12 of the first embodiment described above was applied, but any of the TIAD converters from the second to fourth embodiments described above may be applied.

[0082] Thus, in the fifth embodiment described above, a TIAD converter TD1 that samples and holds the analog inputs AI and reference potentials VS of each of the multiple time-interleaved AD converters AD1 to AD4 is applied to the receiver RB. This makes it possible to sample and hold the received signal TS based on the reference potentials VS while suppressing interference between each AD converter AD1 to AD4 caused by fluctuations in the reference potentials VS.

[0083] The embodiments described above are merely examples for realizing the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. Furthermore, the effects described herein are merely examples and are not limiting, and other effects may also exist.

[0084] Furthermore, this technology can also take the following configurations: (1) An AD conversion circuit comprising a plurality of time-interleaved AD converters and a plurality of sample-and-hold circuits for sampling and holding the analog inputs and reference potentials of each of the plurality of AD converters. (2) The AD conversion circuit according to (1) wherein the sampling and holding of the analog inputs and the reference potentials is synchronized for each of the AD converters. (3) The AD conversion circuit according to (1) or (2) wherein the sample-and-hold circuit comprises a sample-and-hold capacitor that holds a voltage corresponding to the analog input, an input switch that switches the analog input input to one end of the sample-and-hold capacitor, and a reference switch that switches the reference potential input to the other end of the sample-and-hold capacitor. (4) The AD conversion circuit according to (3) wherein one end of the reference switch is connected to the reference potential. (5) The AD conversion circuit according to (3) or (4) wherein the input switch and the reference switch are simultaneously turned on and off at different times between the AD converters. (6) The AD conversion circuit according to (3) or (4), wherein the ON period of the input switch comprises an overlapping period that overlaps with the ON period of the reference switch and a non-overlapping period that does not overlap with the ON period of the reference switch. (7) The AD conversion circuit according to (3) or (4), wherein the ON period of the reference switch comprises an overlapping period that overlaps with the ON period of the input switch and a non-overlapping period that does not overlap with the ON period of the input switch. (8) The AD conversion circuit according to any one of (3) to (7), comprising a switch control unit that controls the ON / OFF status of the input switch and the reference switch. (9) The AD conversion circuit according to any one of (3) to (8), comprising a delay circuit that delays the sampling timing of the analog input. (10) The AD converter comprises a successive approximation type AD converter provided with an input capacitor driven based on the analog input, wherein the sample-hold capacitor is shared with the input capacitor. (11) The AD conversion circuit according to any one of (1) to (10), comprising a buffer for propagating the analog input and the reference potential to the sample-and-hold circuit.(12) A communication device comprising: a plurality of A / D converters that time-interleave the received signals as analog inputs; a plurality of sample-and-hold circuits that sample and hold the analog inputs and reference potentials of each of the plurality of A / D converters; and a logic circuit that serializes the outputs of the plurality of A / D converters.

[0085] TD1 TIAD converter BA Buffer LG Logic circuit AD1 to AD4 AD converter SH1 to SH4 Sample-and-hold circuit AK1 to AK4 AD converter SW1 to SW4 Input switch GW1 to GW4 Reference switch SC1 to SC4 Sample-and-hold capacitor

Claims

1. An AD conversion circuit comprising multiple time-interleaved AD converters and multiple sample-and-hold circuits for sampling and holding the analog inputs and reference potentials of each of the multiple AD converters.

2. The AD conversion circuit according to claim 1, wherein the sample-and-hold of the analog input and the reference potential is synchronized for each AD converter.

3. The AD conversion circuit according to claim 1, comprising: a sample-and-hold capacitor that holds a voltage corresponding to the analog input; an input switch that switches the analog input input to one end of the sample-and-hold capacitor; and a reference switch that switches the reference potential input to the other end of the sample-and-hold capacitor.

4. The AD conversion circuit according to claim 3, wherein one end of the reference switch is connected to the reference potential.

5. The AD conversion circuit according to claim 3, wherein the input switch and the reference switch are simultaneously turned on and off at different times between the AD converters.

6. The AD conversion circuit according to claim 3, wherein the ON period of the input switch includes an overlapping period that overlaps with the ON period of the reference switch and a non-overlapping period that does not overlap with the ON period of the reference switch.

7. The AD conversion circuit according to claim 3, wherein the ON period of the reference switch includes an overlapping period that overlaps with the ON period of the input switch and a non-overlapping period that does not overlap with the ON period of the input switch.

8. The AD conversion circuit according to claim 3, further comprising a switch control unit for controlling the on / off state of the input switch and the reference switch.

9. The AD conversion circuit according to claim 1, further comprising a delay circuit for delaying the sampling timing of the analog input.

10. The AD converter according to claim 1, wherein the AD converter comprises a successive approximation type AD converter provided with an input capacitance driven based on an analog input, and the sample-and-hold capacitance is shared with the input capacitance.

11. The AD conversion circuit according to claim 1, further comprising a buffer for propagating the analog input and the reference potential to the sample-and-hold circuit.

12. A communication device comprising: a plurality of A / D converters that time-interleave the received signal as an analog input; a plurality of sample-and-hold circuits that sample and hold the analog input and reference potential of each of the plurality of A / D converters; and a logic circuit that serializes the outputs of the plurality of A / D converters.

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