Abnormality monitoring system and abnormality monitoring method

Abstract

Provided is a technology that enables control for minimizing power required for analysis.　This abnormality monitoring system comprises: an A / D converter that samples, at a sampling frequency corresponding to a prescribed operation mode, an output signal from a sensor for outputting a measurement result on a given physical quantity as an analog electric signal, and digitizes the sampled signal; a processor that performs proscribed processing, at a processing clock corresponding to the prescribed operation mode, on a digital signal that is outputted from the A / D converter; and an abnormal signal detection unit that monitors the output signal from the sensor and sets one of operation modes depending on the output cycle of an abnormal value of the output signal.

Description

Anomaly monitoring system and anomaly monitoring method

[0001] This invention relates to an anomaly monitoring system and an anomaly monitoring method. This invention claims priority to Japanese Patent Application No. 2024-228762, filed on December 25, 2024, and in designated countries where incorporation by reference is permitted, the contents described in that application are incorporated into this application by reference.

[0002] In recent years, there has been a growing need for real-time condition monitoring of industrial equipment and other devices, with the aim of ensuring the long-term stable operation of high-performance, highly reliable electronic equipment and industrial machinery. In particular, with the development of digital and IoT (Internet of Things) technologies, there is an increasing trend to implement high-performance sensors, analog-to-digital converters (ADCs), and high-speed signal processing function blocks on circuit boards and devices to acquire and analyze real-time monitoring data from electronic equipment and industrial machinery to understand their operating status and utilize it for maintenance and fault monitoring.

[0003] Furthermore, to ensure the reliability of systems that monitor the operating status of electronic equipment, there is an increasing need for systems capable of accurately monitoring various abnormal signals. To handle a wide bandwidth from low-frequency to high-frequency signals, there is a growing trend towards using high-speed ADCs and digital signal processing blocks (FPGAs, microcontrollers, CPUs (Central Processing Units), and other DSPs (Digital Signal Processors)). Consequently, the power consumption of abnormality monitoring systems increases. On the other hand, there is also an increasing demand for low power consumption in electronic equipment and devices to reduce environmental impact.

[0004] Patent Document 1 discloses a vibration monitoring system comprising: a circuit that transmits only specific frequency components of an input signal from a vibration detection sensor using an analog signal processing method; a circuit that detects the signal; a circuit that outputs a value proportional to the root mean square of the vibration acceleration at a specific frequency using a low-pass filter; a controller that changes and controls the center frequency of the circuit that transmits only specific frequency components; and means for converting the value proportional to the root mean square of the vibration acceleration at a specific frequency into a digital signal.

[0005] Japanese Patent Application Laid-Open No. 2019-35666

[0006] In the technology described in Patent Document 1, it is possible to obtain vibration data analyzed by battery drive at a small size and low cost. However, when performing frequency analysis, it is not possible to control appropriate power consumption according to the analysis target. For example, when analyzing vibration detected by a sensor, the sampling frequency of A / D (analog / digital) conversion for minimizing the power related to the analysis and the processing clock of the analysis process in the DSP are different between the case where the frequency of the vibration is high and the case where it is low, but the technology described in Patent Document 1 does not disclose consideration for such points. An object of the present invention is to enable control to minimize the power required for analysis.

[0007] This application includes a plurality of means for solving at least a part of the above problems, and examples thereof are as follows. An abnormality monitoring system according to one aspect of the present invention for solving the above problems samples and digitizes an output signal from a sensor that outputs the result of measuring a predetermined physical quantity as an analog electrical signal at a predetermined sampling frequency according to an operation mode, and performs a predetermined process on the digital signal output by the A / D converter with a processing clock according to the predetermined operation mode, and a processor, and an abnormality signal detection unit that monitors the output signal from the sensor and sets any one of the operation modes according to the output period of an abnormal value of the output signal.

[0008] According to the present invention, it is possible to reduce the power consumption of the entire system by avoiding high-speed operations for unnecessary abnormality monitoring. Problems, configurations, and effects other than those described above will be clarified by the description of the embodiments for carrying out the following invention.

[0009] This figure shows an example of the configuration of an abnormality monitoring system. This figure shows an example of the configuration of the signal change period detection unit. This figure shows an example of the operating mode setting. This figure shows an example of a low-period monitored signal. This figure shows an example of a high-period monitored signal. This figure shows an example of how to handle low-period abnormal fluctuations. This figure shows an example of how to handle high-period abnormal fluctuations. This figure shows a modified version of the abnormality monitoring system. This figure shows another modified version of the abnormality monitoring system. This figure shows another example of the configuration of the abnormality monitoring system.

[0010] Embodiments of the present invention will be described below with reference to the drawings. The embodiments are illustrative examples for explaining the present invention, and have been omitted and simplified as appropriate for clarity of explanation. The present invention can also be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0011] The positions, sizes, shapes, and ranges of the components shown in the drawings may not represent their actual positions, sizes, shapes, and ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in the drawings.

[0012] Examples of various types of information may be described using expressions such as "table," "list," and "queue," but these types of information may also be represented by data structures other than these. For example, various types of information such as "XX table," "XX list," and "XX queue" may be referred to as "XX information." When describing identification information, expressions such as "identification information," "identifier," "name," "ID," and "number" are used, but these are interchangeable. Furthermore, the identification information described using these expressions may be represented using symbols, numbers, natural language, or combinations thereof in the embodiment, but the identification information may also be in other formats.

[0013] When there are multiple components with the same or similar function, they may be described using the same symbol but with different subscripts. Furthermore, when it is not necessary to distinguish between these multiple components, the subscripts may be omitted in the description.

[0014] In embodiments, processing performed by executing a program may be described. Here, the computer executes the program using a processor (e.g., CPU, GPU) and performs processing defined by the program using memory resources (e.g., memory) and interface devices (e.g., communication ports). Therefore, the main entity performing the processing by executing the program may be the processor. Similarly, the main entity performing the processing by executing the program may be a controller, device, system, computer, or node having a processor. The main entity performing the processing by executing the program may be an arithmetic unit, and may include a dedicated circuit that performs a specific processing. Here, a dedicated circuit is, for example, an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a CPLD (Complex Programmable Logic Device).

[0015] The program may be installed on the computer from the program source. The program source may be, for example, a program distribution server or a storage medium readable by the computer. If the program source is a program distribution server, the program distribution server includes a processor and storage resources for storing the program to be distributed, and the processor of the program distribution server may distribute the program to other computers. In addition, in some embodiments, two or more programs may be implemented as a single program, or one program may be implemented as two or more programs.

[0016] In this embodiment, the abnormality monitoring system 1 contributes to power saving by setting the operating mode of the DSP 400, which performs abnormality monitoring, and the ADC (A / D converter) 300, which supplies a digital signal obtained by digitizing the sensor output to the DSP 400, to a dormant state when normal. On the other hand, the abnormality monitoring system 1 ensures the accuracy of abnormality monitoring by quickly setting the operating mode of the DSP 400 and ADC 300 to low frequency (low speed) or high frequency (high speed) by detecting the initial reaction observed when monitoring is required using the abnormality signal detection unit 100.

[0017] The distinction between low-speed and high-speed operating modes, and their further subdivisions, are not limited here, as there are various implementations depending on the industrial equipment or IoT device being implemented. Therefore, in the following embodiments, for convenience, the operating modes of the ADC300 and DSP400 will be described as a sleep mode, a low-frequency mode, and a high-frequency mode that operates at a higher frequency than the low-frequency mode, but they are not limited to these, and it is sufficient if they are divided into multiple stages in advance, including a sleep mode that pauses operation.

[0018] Furthermore, the ADC300's operating mode can be set externally using an operating mode setting signal. For example, in this embodiment, when the low-frequency mode is selected, the sampling frequency is set low (for example, a period longer than several tens of Hz, less than 1 Hz for detecting temperature, vibration, etc., and once every few weeks to several months for time-dependent changes such as drift). When the high-frequency mode is selected, the sampling frequency is set high (for example, a period shorter than several tens of kHz to several hundred kHz for disturbance noise). The ADC300 with a high sampling frequency samples the input analog waveform at a high frequency, enabling it to detect finer changes than the ADC300 with a low sampling frequency. Also, the power consumption of the ADC300 increases in the order of idle mode, low-frequency mode, and high-frequency mode.

[0019] Similarly, the DSP400's operating mode can be set externally using an operating mode setting signal. For example, when set to low-frequency mode, the processing clock frequency is set lower according to the mode, and when set to high-frequency mode, the clock frequency is set higher according to the mode. A DSP400 with a high clock frequency digitally processes the input digital waveform at a high clock speed, enabling it to detect finer changes than a DSP400 with a low clock frequency. In addition, the power consumption of the DSP400 increases in the order of sleep mode, low-frequency mode, and high-frequency mode.

[0020] The ADC300 and DSP400 may also be configured to allow for more precise setting of the sampling frequency and clock frequency, respectively, via external setting signals.

[0021] Figure 1 shows an example of the configuration of an anomaly monitoring system. The anomaly monitoring system 1 is implemented as an analog circuit system or module provided for internal monitoring for each piece of equipment to be monitored for anomalies, or for each unit of multiple pieces of equipment to be monitored for anomalies. The anomaly monitoring system 1 includes an anomaly signal detection unit 100, a sensor 200, an ADC 300, and a DSP 400.

[0022] Sensor 200 is one of several sensors that measure and detect various physical quantities, such as a voltage sensor, current sensor, temperature sensor, rotation sensor, or vibration sensor. Sensor 200 outputs the detected physical quantity as an analog electrical signal (monitored signal 210), such as a predetermined voltage or current. In this embodiment, sensor 200 outputs the monitored signal 210 as an output signal to the abnormal signal detection unit 100.

[0023] The abnormal signal detection unit 100 receives the monitored signal 210 output from the sensor 200 as input, passes the monitored signal 210 to the ADC 300, and outputs an operation mode setting signal 150 to the ADC 300 and an operation mode setting signal 160 to the DSP 400. The abnormal signal detection unit 100 includes a signal change period detection unit 110 that analyzes and detects the signal change period (output period) of abnormal values ​​in the input monitored signal 210, and an operation mode setting unit 120 that receives a flag signal output from the signal change period detection unit 110.

[0024] Figure 2 shows an example of the configuration of the signal change period detection unit. The signal change period detection unit 110 detects the presence or absence of abnormal values ​​in the input monitored signal 210 and inputs the output value of the integration circuit 111 for detecting low-frequency (long-period abnormal waves) abnormal values ​​to the comparator 112. If the value is below a predetermined low-period threshold, it outputs a low-period signal flag 113. The signal change period detection unit 110 also inputs the output value of the differentiation circuit 116 for detecting high-frequency (short-period abnormal waves) abnormal values ​​in the input monitored signal 210 to the comparator 117. If the value exceeds a predetermined high-period threshold, it outputs a high-period signal flag 118.

[0025] The operation mode setting unit 120 outputs an operation mode setting signal 150 to specify the sampling frequency to the ADC 300 and an operation mode setting signal 160 to specify the clock frequency to the DSP 400, in accordance with the flag signal. The operation mode setting unit 120 may be an analog or digital logic circuit, and may be implemented, for example, by an FPGA.

[0026] Figure 3 shows an example of an operating mode setting. The operating mode setting 121 is a table that determines the operating mode of the ADC 300 and DSP 400 according to the combination of the low-period signal flag 113 and the high-period signal flag 118 output by the signal change period detection unit 110. Although it is described as a table for convenience, the operating mode setting 121 may be implemented as an analog circuit to obtain the same result, or as a digital circuit to obtain the same result.

[0027] For example, in the operation mode setting 121, when neither the low-period signal flag 113 nor the high-period signal flag 118 is output (in the case of "0"), the operation mode is defined to be "Hibernation Mode". Also, in the operation mode setting 121, when both the low-period signal flag 113 and the high-period signal flag 118 are output (in the case of "1"), the operation mode is defined to be "High-Frequency (High-Resolution) Mode".

[0028] Furthermore, in the operation mode setting 121, when the low-period signal flag 113 is output and the high-period signal flag 118 is not output (when they are "1" and "0" respectively), the operation mode is defined to be "low-frequency mode". Also, in the operation mode setting 121, when the low-period signal flag 113 is not output and the high-period signal flag 118 is output (when they are "0" and "1" respectively), the operation mode is defined to be "high-frequency mode".

[0029] Figure 4 shows an example of a low-period monitored signal. The low-period monitored signal 211 is a signal that occurs when low-period waveform abnormalities are observed due to the generation of low-period noise components (for example, with a frequency of 100 Hz or less) such as drift, temperature fluctuations, and mechanical vibrations, relative to a normal signal without abnormal fluctuations. In the abnormal signal detection unit 100 according to this embodiment, such a signal is detected by the integrating circuit 111 and a low-period signal flag 113 is generated.

[0030] Figure 5 shows an example of a high-frequency monitored signal. The high-frequency monitored signal 212 is a signal that occurs when a high-frequency waveform abnormality is observed due to the generation of high-frequency noise components (for example, with a frequency of 10 kHz or higher) such as electrical noise or electromagnetic interference noise, relative to a normal signal without abnormal fluctuations. In the abnormal signal detection unit 100 according to this embodiment, such a signal is detected by the differentiating circuit 116 and a high-frequency signal flag 118 is generated.

[0031] Figure 6 shows an example of how to respond to low-period abnormal fluctuations. To respond to low-period abnormal fluctuations, when a low-period abnormal fluctuation is detected by the signal change period detection unit 110 of the abnormal signal detection unit 100, the operation mode setting unit 120 outputs an "low-frequency mode" operation mode setting signal 150 to the ADC 300, specifying a low-period sampling frequency, and an "low-frequency mode" operation mode setting signal 160 to the DSP 400, specifying a low-period clock frequency, if no high-period abnormal fluctuations are detected.

[0032] When the ADC300 receives the "low frequency mode" setting signal 150, it starts sampling at a low speed (sampling at a low sampling frequency). Similarly, when the DSP400 receives the "low frequency mode" setting signal 160, it starts operating with a low-speed clock.

[0033] Figure 7 shows an example of how to respond to high-period abnormal fluctuations. To respond to high-period abnormal fluctuations, when a high-period abnormal fluctuation is detected by the signal change period detection unit 110 of the abnormal signal detection unit 100, the operation mode setting unit 120 outputs an "high-frequency mode" operation mode setting signal 150 to specify a high-period sampling frequency to the ADC 300, and an "high-frequency mode" operation mode setting signal 160 to specify a high-period clock frequency to the DSP 400.

[0034] When the ADC300 receives the "high frequency mode" setting signal 150, it starts high-speed sampling (sampling at a high sampling frequency). Similarly, when the DSP400 receives the "high frequency mode" setting signal 160, it starts operating at a high-speed clock.

[0035] As described above, the abnormal signal detection unit 100 according to this embodiment can specify the operating mode stages of the ADC 300 and DSP 400 to be synchronized with the high and low periods of the abnormal waveform. Therefore, it is possible to maintain the accuracy of abnormality detection while suspending the ADC 300 and DSP 400 during normal operation, and when an abnormality is detected, it is possible to control the power required for analysis to be minimized according to the abnormal waveform.

[0036] The above is an example of an anomaly monitoring system according to the first embodiment. According to the anomaly monitoring system 1 of the first embodiment, it is possible to reduce the overall power consumption of the system by avoiding high-speed operation for anomaly monitoring that is not necessary.

[0037] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail for the purpose of clearly illustrating the present invention, and are not necessarily limited to those having all the configurations described.

[0038] For example, in the abnormal signal detection unit 100, the monitored signal 210 is passed to the ADC 300, but the timing of this transmission may be varied.

[0039] Figure 8 shows a modified example of the abnormality monitoring system. In the abnormality monitoring system 1', the abnormality signal detection unit 100' is configured to receive the monitored signal 210 by passing it through a delay circuit 130. The delay circuit 130 is composed of, for example, an analog delay circuit or a filter circuit, and delays the monitored signal 210 to synchronize with the processing delay of the signal change period detection unit 110 and the operation mode setting unit 120. The presence of this delay circuit 130 makes it possible to synchronize with the processing delay of the signal change period detection unit 110 and the operation mode setting unit 120.

[0040] Figure 9 shows another modified example of the abnormality monitoring system. As shown in Figure 9, in another modified example 1'' of the abnormality monitoring system, a preamplifier 220 may be provided before the abnormality signal detection unit 100 or the abnormality signal detection unit 100'' to amplify the monitored signal 210 with an amplification circuit. In this way, even if the change in the detected amount output from the sensor 200 is minute, it becomes possible to detect it with high accuracy.

[0041] Figure 10 shows another example configuration of the abnormality monitoring system. In another example configuration of the abnormality monitoring system, the abnormality signal detection unit 500 is provided instead of the abnormality signal detection unit 100 or the abnormality signal detection unit 100'. The abnormality signal detection unit 500 includes a plurality of filter circuits (LPF 510 (Low Pass Filter), BPF-A 511 (Band Pass Filter-A), BPF-B 512 (Band Pass Filter-B), HPF 513 (High Pass Filter)) that extract signals of different bandwidths in parallel from the input monitored signal 210. The abnormality signal detection unit 500 also includes a decoder 520 that receives the signals that have passed through each filter circuit, and an operating mode setting unit 530.

[0042] Decoder 520 receives the signal that has passed through the filter circuit, accepts a signal from the outside indicating whether to transfer the signal to ADC 300 for each predetermined band, and transfers the signal to ADC 300 according to the signal. The operation mode setting unit 530 detects the band in which an abnormal waveform has been detected in the filter circuit, and sends a signal to the decoder 520 to transfer the signal of the band in which the abnormal waveform has been detected (a signal that has passed through any one of LPF 510, BPF-A 511, BPF-B 512, and HPF 513) to ADC 300. Further, the operation mode setting unit 530 outputs an operation mode setting signal 150 that specifies a sampling frequency corresponding to the operation mode to ADC 300 and an operation mode setting signal 160 that specifies a clock frequency corresponding to the operation mode to DSP 400 according to the band in which the abnormal waveform has been detected.

[0043] For example, if the combination of the bands in which the abnormal waveform has been detected is a signal in the band that has passed through LPF 510, the operation mode setting unit 530 outputs an operation mode setting signal 150 of "low frequency mode" that specifies a low-period sampling frequency to ADC 300, outputs an operation mode setting signal 160 of "low frequency mode" that specifies a low-period clock frequency to DSP 400, and sends a signal to the decoder 520 to transfer the signal in the band that has passed through LPF 510 to ADC 300.

[0044] For another example, if the combination of the bands in which the abnormal waveform has been detected is a signal in the band that has passed through BPF-B 512 and HPF 513, the operation mode setting unit 530 outputs an operation mode setting signal 150 of "high frequency mode" that specifies a high-period sampling frequency to ADC 300, outputs an operation mode setting signal 160 of "high frequency mode" that specifies a high-period clock frequency to DSP 400, and sends a signal to the decoder 520 to transfer the signal in the band that has passed through BPF-B 512 and HPF 513 to ADC 300.

[0045] The above is another configuration example of the abnormality monitoring system. According to another configuration example of the abnormality monitoring system, detection is performed for a plurality of bands, and the signal can be sent to the processing stages of the ACD and DSP only for the bands with abnormal waveforms, so that power consumption can be further suppressed.

[0046] Also, in another configuration example 2 of the abnormality monitoring system, a delay circuit may be provided at the output stage of the filter circuit of the abnormality signal detection unit 500. Due to the existence of this delay circuit, it becomes possible to match the processing delay of the operation mode setting unit 530. <�

[0047] Note that a part of the configuration of the above-described embodiment can be replaced with other configurations, and the configuration of other embodiments can also be added to the configuration of the embodiment. Also, a part of the configuration of the embodiment can be deleted.

[0048] Each of the above-described units, configurations, functions, processing units, etc. may be realized in hardware by designing a part or all of them, for example, by an integrated circuit. Also, each of the above-described units, configurations, functions, etc. may be configured as a chiplet that forms a single chip including the abnormality signal detection unit 100 from the sensor 200, or may be configured as a chiplet that forms a single chip including up to the abnormality signal detection unit 100 and the ADC 300 from the sensor 200.

[0049] Note that the control lines and information lines according to the above-described embodiment show those considered necessary for explanation, and not necessarily all the control lines and information lines are shown in the product. In reality, it may be considered that almost all the configurations are interconnected. The above is an explanation of the present invention centered on the embodiment.

[0050] 1: Abnormality monitoring system, 100: Abnormality signal detection unit, 110: Signal change period detection unit, 120: Operation mode setting unit, 150, 160: Operation mode setting signal, 200: Sensor, 210: Monitoring target signal, 300: ADC, 400: DSP.

Claims

1. An abnormality monitoring system comprising: an A / D converter that samples and digitizes an output signal from a sensor that outputs the result of measuring a predetermined physical quantity as an analog electrical signal at a sampling frequency corresponding to a predetermined operating mode; a processor that performs predetermined processing on the digital signal output by the A / D converter at a processing clock corresponding to the predetermined operating mode; and an abnormal signal detection unit that monitors the output signal from the sensor and sets one of the operating modes according to the output period of an abnormal value in the output signal.

2. An anomaly monitoring system according to claim 1, wherein the operating mode is divided in advance into a plurality of stages, including a pause mode in which the operation is suspended, and the anomaly signal detection unit sets one of the operating modes.

3. An anomaly monitoring system according to claim 1, wherein the operating mode is divided in advance into a plurality of stages, including a pause mode in which the operation is suspended, and the anomaly signal detection unit analyzes the output period of the anomaly value of the output signal, identifies a combination of the presence or absence of a low-frequency anomaly value and the presence or absence of a high-frequency anomaly value with a frequency higher than the low-frequency anomaly, and sets one of the operating modes according to the combination.

4. An anomaly monitoring system according to claim 1, wherein the operating mode is divided in advance into a plurality of stages, including a pause mode in which the operation is suspended; the anomaly signal detection unit analyzes the output period of the abnormal value of the output signal, identifies a combination of the presence or absence of a low-frequency abnormal value and the presence or absence of a high-frequency abnormal value with a frequency higher than the low-frequency abnormal value, and sets one of the operating modes according to the combination; and if neither the low-frequency abnormal value nor the high-frequency abnormal value is detected, the pause mode is set.

5. An anomaly monitoring system according to claim 1, wherein the operating mode is divided in advance into a plurality of stages, including a pause mode for pausing operation, a low-frequency mode, and a high-frequency mode for operating at a frequency higher than the low-frequency mode; the anomaly signal detection unit analyzes the output period of the abnormal value of the output signal, identifies a combination of the presence or absence of a low-frequency abnormal value and the presence or absence of a high-frequency abnormal value with a frequency higher than the low-frequency, and sets one of the operating modes according to the combination; and if the low-frequency abnormal value is detected and the high-frequency abnormal value is not detected, the low-frequency mode is set.

6. An anomaly monitoring system according to claim 1, wherein the operating mode is divided in advance into a plurality of stages, including a pause mode in which the operation is suspended, a low-frequency mode, and a high-frequency mode in which the operation is performed at a higher frequency than the low-frequency mode; the anomaly signal detection unit analyzes the output period of the abnormal value of the output signal, identifies a combination of the presence or absence of a low-frequency abnormal value and the presence or absence of a high-frequency abnormal value with a frequency higher than the low-frequency, and sets one of the operating modes according to the combination; and if the low-frequency abnormal value is not detected and the high-frequency abnormal value is detected, the high-frequency mode is set.

7. An anomaly monitoring system according to claim 1, wherein the operating mode is divided in advance into a plurality of stages, including a pause mode in which the operation is suspended, a low-frequency mode, and a high-frequency mode in which the operation is performed at a higher frequency than the low-frequency mode; the anomaly signal detection unit analyzes the output period of the abnormal value of the output signal, identifies a combination of the presence or absence of a low-frequency abnormal value and the presence or absence of a high-frequency abnormal value with a frequency higher than the low-frequency, and sets one of the operating modes according to the combination; and if both the low-frequency abnormal value and the high-frequency abnormal value are detected, the stage is set to the high-frequency mode.

8. An anomaly monitoring system according to claim 1, characterized in that it comprises a delay circuit that adds a delay to the output signal passed from the sensor to the A / D converter.

9. An anomaly monitoring system according to claim 1, characterized in that it comprises an amplification circuit for amplifying the output signal passed from the sensor to the A / D converter.

10. An anomaly monitoring system according to claim 1, wherein the anomaly signal detection unit monitors the output signal in parallel using a plurality of filters that extract components of different frequency bands, and sets one of the operating modes according to the output period of the anomaly value of the output signal.

11. An abnormality monitoring system comprising: an A / D converter that samples and digitizes an output signal from a sensor that outputs the result of measuring a predetermined physical quantity as an analog electrical signal at a sampling frequency corresponding to a predetermined operating mode; and a processor that performs predetermined processing on the digital signal output by the A / D converter at a processing clock corresponding to the predetermined operating mode, wherein the abnormality monitoring method includes: an abnormality signal detection step in which an abnormality signal detection unit detects an abnormal value in the output signal from the sensor; and an operating mode setting step in which one of the operating modes is set according to the output period of the abnormal value in the output signal.

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