Imaging element, manufacturing method, and electronic device

Abstract

The present disclosure relates to an imaging element, a manufacturing method, and an electronic device that make it possible to capture higher-quality images. The imaging element is configured by: bonding a logic chip to a sensor chip via a wiring layer laminated on a semiconductor substrate provided with a photoelectric conversion unit for each pixel; and then forming, on a side surface of a trench used as an element isolation section for isolating the photoelectric conversion units from those of adjacent pixels, a single-crystal silicon germanium layer doped with boron at a prescribed concentration. The present technology is applicable to, for example, a CMOS image sensor having a laminated structure.

Description

Image pickup device, manufacturing method, and electronic device

[0001] The present disclosure relates to an image pickup device, a manufacturing method, and an electronic device, and more particularly to an image pickup device, a manufacturing method, and an electronic device that can capture higher-quality images.

[0002] Conventionally, in an image pickup device such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor, it is required to perform pinning by doping the side surface of a trench that separates pixels with P-type to provide a P-type layer, and suppress the generation of dark current by suppressing the emission of electrons due to interface levels.

[0003] Patent Document 1 discloses a solid-state imaging device configured to prevent the diffusion of boron by embedding the inside of an element isolation groove with a P-type embedded region doped with boron through a second silicon carbide layer formed of an epitaxial growth layer on the inner surface of the element isolation groove formed in a semiconductor substrate.

[0004] Japanese Patent Application Laid-Open No. 2011-077498

[0005] However, when P-type doping is performed after forming a transistor, for example, since the temperature is restricted by metal wirings and connection pads already formed in a wiring layer, it becomes difficult to sufficiently activate boron. When the P-type layer is not activated and pinning is insufficient in this way, there is a concern that the dark-time characteristics may deteriorate due to an increase in dark current, and the image quality may decrease.

[0006] The present disclosure has been made in view of such a situation, and enables capturing higher-quality images.

[0007] An image pickup device according to one aspect of the present disclosure includes a sensor chip bonded to a logic chip through a wiring layer laminated on a semiconductor substrate provided with a photoelectric conversion unit for each pixel, and a trench used as an element isolation unit that separates the photoelectric conversion units between adjacent pixels of the semiconductor substrate, and a single-crystalline silicon germanium layer provided at least on the side surface of the trench and doped with boron at a predetermined concentration.

[0008] One aspect of the manufacturing method of this disclosure includes, after bonding a logic chip to a sensor chip via a wiring layer stacked on a semiconductor substrate on which a photoelectric conversion unit is provided for each pixel, forming trenches in the semiconductor substrate that are used as element isolation units to separate the photoelectric conversion units from adjacent pixels, and forming a single-crystal silicon germanium layer doped with boron at a predetermined concentration on at least the side surface of the trench.

[0009] One aspect of the present disclosure is an electronic device comprising an image sensor having a sensor chip bonded to a logic chip via a wiring layer stacked on a semiconductor substrate on which a photoelectric conversion unit is provided for each pixel; a trench used as an element isolation unit to separate the photoelectric conversion units from each other between adjacent pixels on the semiconductor substrate; and a single-crystal silicon germanium layer provided on at least the side surface of the trench and doped with boron at a predetermined concentration.

[0010] In one aspect of this disclosure, after a logic chip is bonded to a sensor chip via a wiring layer stacked on a semiconductor substrate on which a photoelectric conversion unit is provided for each pixel, trenches are formed in the semiconductor substrate to be used as element isolation units to separate the photoelectric conversion units from adjacent pixels, and a single-crystal silicon germanium layer doped with boron at a predetermined concentration is formed on at least the side surface of the trench.

[0011] This figure shows an example configuration of a first embodiment of an image sensor to which this technology is applied. This figure illustrates the manufacturing method of the image sensor in Figure 1. This figure illustrates the manufacturing method of the image sensor in Figure 1. This figure shows an example configuration of a second embodiment of an image sensor to which this technology is applied. This figure illustrates the manufacturing method of the image sensor in Figure 4. This figure illustrates the manufacturing method of the image sensor in Figure 4. This figure illustrates the manufacturing method of the image sensor in Figure 4. This figure shows an example configuration of a third embodiment of an image sensor to which this technology is applied. This figure shows an example configuration of a fourth embodiment of an image sensor to which this technology is applied. This figure shows an example configuration of a fifth embodiment of an image sensor to which this technology is applied. This figure shows an example configuration of a sixth embodiment of an image sensor to which this technology is applied. This figure shows an example configuration of a seventh embodiment of an image sensor to which this technology is applied. This is a block diagram showing an example configuration of an imaging device. This figure shows an example of use using an image sensor.

[0012] The following describes in detail a specific embodiment of this technology, with reference to the drawings.

[0013] <First Configuration Example of Image Sensor> Referring to Figures 1 to 3, a configuration example of a first embodiment of an image sensor to which this technology is applied will be described.

[0014] Figure 1A shows an example of a cross-sectional configuration of a pixel 12 provided on an image sensor 11, and Figure 1B shows a planar cross-sectional configuration along the dashed line shown in Figure 1A.

[0015] As shown in Figure 1A, the image sensor 11 is composed of a stacked structure in which a sensor chip 21 in which a plurality of pixels 12 are arranged in an array and a logic chip 22 that performs signal processing on the pixel signals output from those pixels 12 are stacked.

[0016] The sensor chip 21 is constructed by sequentially stacking a silicon germanium layer 32, an insulating layer 33, a filter layer 34, and an on-chip lens layer 35 on the back surface (the side facing upward in Figure 1) of the semiconductor substrate 31, and stacking a wiring layer 36 on the front surface of the semiconductor substrate 31.

[0017] The semiconductor substrate 31 is configured such that each pixel 12 has a photoelectric conversion section made up of a PN junction of an N-type layer and a P-type layer, with the dashed line region shown in the figure representing the N-type layer. Furthermore, the semiconductor substrate 31 has trenches of a predetermined depth formed on the back side as element isolation sections to separate the photoelectric conversion sections from adjacent pixels 12.

[0018] The silicon germanium layer 32 is laminated on the back surface of the semiconductor substrate 31, and also along the sides and bottom surfaces of trenches formed in the semiconductor substrate 31. For example, in the silicon germanium layer 32, boron is present in a concentration of 1e17 to 1e20 cm³. -3 The material is doped at a certain concentration, and the germanium concentration is adjusted within the range of 10-60% to achieve a higher boron activation rate than silicon. The silicon germanium layer 32 is formed as a single crystal by epitaxial growth to a thickness of approximately 1-20 nm.

[0019] The insulating layer 33 is laminated on the back surface of the semiconductor substrate 31 via a silicon germanium layer 32, and is also embedded inside trenches formed in the semiconductor substrate 31 via the silicon germanium layer 32. For example, insulating materials such as silicon oxide films or silicon nitride films are used for the insulating layer 33.

[0020] The filter layer 34 is configured such that each pixel 12 has a color filter 41 that transmits light of the color received by that pixel 12, and a light-shielding film 42 is provided between adjacent color filters 41.

[0021] The on-chip lens layer 35 is configured such that a microlens 43 for focusing light is provided for each pixel 12 (either on a per-pixel basis or on a per-pixel basis for multiple pixels shared by a single pixel).

[0022] The wiring layer 36 is constructed by providing metal wiring and through electrodes, which electrically connect the pixel 12 and the logic chip 22, inside the interlayer insulating film. Furthermore, by joining the connection pads 44 provided on the surface of the wiring layer 36 and the connection pads 45 provided on the logic chip 22 to each other, the sensor chip 21 and the logic chip 22 can be electrically and mechanically bonded together.

[0023] The image sensor 11 is configured in this way, and the single-crystal silicon-germanium layer 32 provided on the side surface of the trench in the semiconductor substrate 31 can suppress the generation of dark current in the photoelectric conversion section of the semiconductor substrate 31. For example, because the silicon-germanium layer 32 has a high activation rate of boron with respect to silicon, it becomes easier to pin the side surface of the trench, and better interface characteristics can be obtained. Therefore, the image sensor 11 can suppress the adverse effects of dark current and capture higher-quality images.

[0024] A method for manufacturing the image sensor 11 will be described with reference to Figures 2 and 3.

[0025] In the first step, as shown in the first step of Figure 2, the logic chip 22 is bonded to the wiring layer 36 stacked on the semiconductor substrate 31.

[0026] In the second step, as shown in the second step of Figure 2, trenches 51 are formed by excavating the semiconductor substrate 31 from the back side to separate the N-type layers of each pixel 12.

[0027] In the third step, as shown in the first step of Figure 3, a single-crystal silicon-germanium layer 32 is laminated by epitaxial growth on the back surface of the semiconductor substrate 31, and on the side and bottom surfaces of the trench 51 formed in the semiconductor substrate 31. At this time, because there is metal wiring (for example, Cu) inside the wiring layer 36, it is necessary to epitaxially grow the silicon-germanium layer 32 under temperature-constrained conditions.

[0028] In the fourth step, as shown in the second step of Figure 3, an insulating layer 33 is formed by embedding it inside the trench 51 formed in the semiconductor substrate 31 via a silicon germanium layer 32, and by laminating it on the back surface of the semiconductor substrate 31 via the silicon germanium layer 32.

[0029] Subsequently, the image sensor 11 shown in Figure 1 is manufactured by sequentially stacking the filter layer 34 and the on-chip lens layer 35 on the insulating layer 33.

[0030] By the manufacturing method described above, an image sensor 11 can be manufactured in which a single-crystal silicon-germanium layer 32 is provided on the side surface of a trench 51 formed in a semiconductor substrate 31.

[0031] <Second Configuration Example of Image Sensor> Referring to Figures 4 to 7, a configuration example of a second embodiment of an image sensor to which this technology is applied will be described. In the image sensor 11A shown in Figure 4, components common to the image sensor 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0032] Figure 4A shows an example of a cross-sectional configuration of a pixel 12 provided on the image sensor 11A, and Figure 4B shows a planar cross-sectional configuration along the dashed line shown in Figure 4A.

[0033] As shown in Figure 4, the image sensor 11A is composed of a stacked structure in which a sensor chip 21A and a logic chip 22 are stacked, and the logic chip 22 is configured in the same way as in Figure 1. The sensor chip 21A is composed of a silicon germanium layer 32A, an insulating layer 33, a filter layer 34, and an on-chip lens layer 35 stacked in order on the back surface (the surface facing upward in Figure 4) of the semiconductor substrate 31A, and a wiring layer 36 stacked on the front surface of the semiconductor substrate 31A. The insulating layer 33, filter layer 34, on-chip lens layer 35, and wiring layer 36 are configured in the same way as in Figure 1.

[0034] The semiconductor substrate 31A differs from the semiconductor substrate 31 in Figure 1 in that it has trenches formed from the front surface to the back surface as element isolation sections that separate adjacent pixels 12, and an insulator 61 is embedded from the front surface of the trenches to a predetermined depth. In other words, while the semiconductor substrate 31 in Figure 1 has a structure in which the photoelectric conversion sections are not completely separated by trenches, the semiconductor substrate 31A has a structure in which the photoelectric conversion sections are completely separated by trenches.

[0035] The silicon germanium layer 32A differs from the silicon germanium layer 32 in Figure 1 in that it is laminated on the back surface of the semiconductor substrate 31A and on the side surfaces of the trenches formed in the semiconductor substrate 31A, but is not laminated on the insulator 61 which forms the bottom surface of the trenches formed in the semiconductor substrate 31A.

[0036] The image sensor 11A is configured in this way, and, similar to the image sensor 11 in Figure 1, by providing a single-crystal silicon-germanium layer 32A on the side surface of the trench in the semiconductor substrate 31A, the generation of dark current can be suppressed, and higher quality images can be captured.

[0037] The manufacturing method of the image sensor 11A will be described with reference to Figures 5 to 7.

[0038] In the 11th step, as shown in the first step of Figure 5, trenches 51A are formed by excavating the semiconductor substrate 31A from the surface side to separate the N-type layers of individual pixels 12. Furthermore, the trenches 51A are formed such that a stepped portion is provided at a predetermined depth from the surface side of the semiconductor substrate 31A.

[0039] For example, using a mask 71 that opens wider than the width corresponding to the portion where the silicon germanium layer 32A and the insulating layer 33 are to be embedded, a shallow trench is formed from the surface side of the semiconductor substrate 31A to a predetermined depth (the depth where the insulator 61 is to be embedded), and an insulator 72 is embedded in the shallow trench. Further, using a mask that opens with a width corresponding to the portion where the silicon germanium layer 32A and the insulating layer 33 are to be embedded, the insulator 72 and the semiconductor substrate 31A are dug. Thereby, a trench 51A provided with a step portion at a predetermined depth from the surface side of the semiconductor substrate 31A can be formed.

[0040] In the 12th step, the mask 71 and the insulator 72 are removed. Then, as shown in the second stage of FIG. 5, after forming a sacrificial film 73 by embedding silicon oxide or the like in the narrow-width portion up to the depth of the step portion in the trench 51A, the insulator 61 is embedded in the wide-width portion of the trench 51A, and the insulator 61 is laminated on the surface of the semiconductor substrate 31A.

[0041] In the 13th step, after removing the insulator 61 laminated on the surface of the semiconductor substrate 31A, as shown in the third stage of FIG. 5, a wiring layer 36 is laminated on the surface of the semiconductor substrate 31A, and the logic chip 22 is bonded to the wiring layer 36.

[0042] In the 14th step, as shown in the first stage of FIG. 6, after inverting the semiconductor substrate 31A and the wiring layer 36, the semiconductor substrate 31A is thinned from the back side by, for example, CMP (Chemical Mechanical Polishing).

[0043] In the 15th step, by removing the sacrificial film 73 in the trench 51A of the semiconductor substrate 31A by etching or the like, the narrow-width portion of the trench 51A is opened as shown in the second stage of FIG. 6.

[0044] In the 16th step, as shown in the first stage of FIG. 7, a single-crystalline silicon germanium layer 32A is laminated on the back surface of the semiconductor substrate 31A and the side surface of the trench 51A formed in the semiconductor substrate 31A by epitaxial growth. <00​In the 17th step, as shown in the second row of FIG. 7, the silicon germanium layer 32A is embedded inside the trench 51A formed in the semiconductor substrate 31A through the silicon germanium layer 32A, and the insulating layer 33 is formed so as to be laminated on the back surface of the semiconductor substrate 31A through the silicon germanium layer 32A.

[0046] After that, by sequentially laminating the filter layer 34 and the on-chip lens layer 35 on the insulating layer 33, the image sensor 11A shown in FIG. 4 is manufactured.

[0047] By the manufacturing method as described above, an image sensor 11A provided with a single crystal silicon germanium layer 32A on the side surface of the trench 51A formed in the semiconductor substrate 31A can be manufactured.

[0048] <Example of the Third Configuration of the Image Sensor> Referring to FIG. 8, a configuration example of the third embodiment of the image sensor to which the present technology is applied will be described. In the image sensor 11B shown in FIG. 8, the same reference numerals are given to the configurations common to the image sensor 11 shown in FIG. 1, and the detailed description thereof is omitted.

[0049] In FIG. 8A, a cross-sectional configuration example of the pixel 12 provided in the image sensor 11B is shown, and in FIG. 8B, a planar cross-sectional configuration along the dashed-dotted line shown in FIG. 8A is shown.

[0050] As shown in FIG. 8, the image sensor 11B has a stacked structure in which the sensor chip 21B and the logic chip 22 are stacked, and the logic chip 22 is configured in the same manner as in FIG. 1. The sensor chip 21B has a silicon germanium layer 32, an insulating layer 33B, a filter layer 34, and an on-chip lens layer 35 sequentially laminated on the back surface of the semiconductor substrate 31 (the surface facing upward in FIG. 8), and a wiring layer 36 is laminated on the surface of the semiconductor substrate 31. The silicon germanium layer 32, the filter layer 34, the on-chip lens layer 35, and the wiring layer 36 are configured in the same manner as in FIG. 1.

[0051] The insulating layer 33B differs from the insulating layer 33 in Figure 1 in that a thin-film metal electrode 62 is provided inside it. As shown in the figure, the thin-film metal electrode 62 is provided inside the insulating layer 33B along the back surface of the semiconductor substrate 31 and along the shape of a trench formed in the semiconductor substrate 31. For example, in the fourth step described above (see Figure 3), the thin-film metal electrode 62 can be embedded inside the insulating layer 33B when forming the insulating layer 33B. The thin-film metal electrode 62 is made of, for example, titanium nitride (TiN) and is used to apply a negative bias to the photoelectric conversion section of the pixel 12.

[0052] The image sensor 11B is configured in this way, and, similar to the image sensor 11 in Figure 1, a single-crystal silicon-germanium layer 32 is provided on the side surface of the trench in the semiconductor substrate 31, and by applying a negative bias using a thin-film metal electrode 62, the effect of suppressing the generation of dark current can be enhanced, and even higher quality images can be captured.

[0053] <Fourth Configuration Example of Image Sensor> Referring to Figure 9, a configuration example of a fourth embodiment of an image sensor to which this technology is applied will be described. In the image sensor 11C shown in Figure 9, components common to the image sensor 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0054] Figure 9A shows an example of the cross-sectional configuration of a pixel 12 provided on the image sensor 11C, and Figure 9B shows a planar cross-sectional configuration along the dashed line shown in Figure 9A.

[0055] As shown in Figure 9, the image sensor 11C is composed of a stacked structure in which a sensor chip 21C and a logic chip 22 are stacked, and the logic chip 22 is configured in the same way as in Figure 1. The sensor chip 21C is composed of a silicon germanium layer 32, an insulating layer 33C, a filter layer 34, and an on-chip lens layer 35 stacked in order on the back surface of the semiconductor substrate 31 (the surface facing upward in Figure 9), and a wiring layer 36 stacked on the front surface of the semiconductor substrate 31. The silicon germanium layer 32, filter layer 34, on-chip lens layer 35, and wiring layer 36 are configured in the same way as in Figure 1.

[0056] The insulating layer 33C differs from the insulating layer 33 in Figure 1 in that a transparent conductive film electrode 63 is provided inside it. As shown in the figure, the transparent conductive film electrode 63 is provided inside the insulating layer 33C along the back surface of the semiconductor substrate 31 and is also provided so as to be embedded in a trench formed in the semiconductor substrate 31. For example, in the fourth step described above (see Figure 3), when forming the insulating layer 33C, the transparent conductive film electrode 63 can be embedded inside the insulating layer 33C. The transparent conductive film electrode 63 is made of, for example, indium oxide (InO) or indium tin oxide (ITO), and is used to apply a negative bias to the photoelectric conversion section of the pixel 12.

[0057] The image sensor 11C is configured in this way, and, similar to the image sensor 11 in Figure 1, a single-crystal silicon-germanium layer 32 is provided on the side surface of the trench in the semiconductor substrate 31, and by applying a negative bias using the transparent conductive film electrode 63, the effect of suppressing the generation of dark current can be enhanced, and even higher quality images can be captured.

[0058] <Fifth Configuration Example of Image Sensor> Referring to Figure 10, a fifth embodiment of the configuration example of an image sensor to which this technology is applied will be described. In the image sensor 11D shown in Figure 10, components common to the image sensor 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0059] Figure 10A shows an example of a cross-sectional configuration of a pixel 12 provided on the image sensor 11D, and Figure 10B shows a planar cross-sectional configuration along the dashed line shown in Figure 10A.

[0060] As shown in Figure 10, the image sensor 11D is composed of a stacked structure in which a sensor chip 21D and a logic chip 22 are stacked, and the logic chip 22 is configured in the same way as in Figure 1. The sensor chip 21D is composed of a silicon germanium layer 32D, an insulating layer 33, a filter layer 34, and an on-chip lens layer 35 stacked in order on the back surface (the surface facing upward in Figure 10) of the semiconductor substrate 31, and a wiring layer 36 stacked on the front surface of the semiconductor substrate 31. The insulating layer 33, filter layer 34, on-chip lens layer 35, and wiring layer 36 are configured in the same way as in Figure 1.

[0061] The silicon germanium layer 32D differs from the silicon germanium layer 32 in Figure 1, as shown in an enlarged view to the right of B in Figure 10, in that it has a concentration gradient such that the germanium concentration on the semiconductor substrate 31 side is low and the germanium concentration on the insulating layer 33 side becomes high. For example, in the third step described above (see Figure 3), when epitaxially growing the silicon germanium layer 32D, it is possible to form it with a concentration gradient by gradually increasing the germanium concentration. This prevents abrupt changes in the lattice constant of the silicon germanium layer 32D and suppresses the occurrence of crystal defects in the silicon germanium layer 32D.

[0062] The image sensor 11D is configured in this way, and, similar to the image sensor 11 in Figure 1, by providing a single-crystal silicon-germanium layer 32D on the side surface of the trench in the semiconductor substrate 31, the generation of dark current can be suppressed, and higher quality images can be captured. Furthermore, the image sensor 11D can further improve quality by suppressing the occurrence of crystal defects in the silicon-germanium layer 32D.

[0063] <Sixth Configuration Example of Image Sensor> Referring to Figure 11, a sixth embodiment of the configuration example of an image sensor to which this technology is applied will be described. In the image sensor 11E shown in Figure 11, components common to the image sensor 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0064] Figure 11A shows an example of a cross-sectional configuration of a pixel 12 provided on the image sensor 11E, and Figure 11B shows a planar cross-sectional configuration along the dashed line shown in Figure 11A.

[0065] As shown in Figure 11, the image sensor 11E is composed of a stacked structure in which a sensor chip 21E and a logic chip 22 are stacked, and the logic chip 22 is configured in the same way as in Figure 1. The sensor chip 21E is composed of a silicon germanium layer 32, a silicon layer 37, an insulating layer 33, a filter layer 34, and an on-chip lens layer 35 stacked in order on the back surface of the semiconductor substrate 31 (the surface facing upward in Figure 11), and a wiring layer 36 stacked on the front surface of the semiconductor substrate 31. The silicon germanium layer 32, insulating layer 33, filter layer 34, on-chip lens layer 35, and wiring layer 36 are configured in the same way as in Figure 1.

[0066] In other words, the image sensor 11E has a different configuration from the image sensor 11 in Figure 1, in that the silicon layer 37 is laminated between the silicon-germanium layer 32 and the insulating layer 33. Furthermore, within the trench of the semiconductor substrate 31, the insulating layer 33 is embedded via the silicon-germanium layer 32 and the silicon layer 37. For example, the silicon layer 37 can be formed in the third step described above (see Figure 3) by epitaxial growth of the silicon-germanium layer 32, and then by performing epitaxial growth with a germanium concentration of 0%, thereby creating a multilayer structure of epitaxial growth. Also, the silicon layer 37 is doped with boron, similar to the silicon-germanium layer 32.

[0067] The image sensor 11E is configured in this way, and similar to the image sensor 11 in Figure 1, the generation of dark current can be suppressed by providing a single-crystal silicon-germanium layer 32 on the side surface of the trenches in the semiconductor substrate 31, thereby enabling the capture of higher-quality images. Furthermore, the image sensor 11E is configured such that an insulating layer 33 is provided with respect to the silicon-germanium layer 32 via a silicon layer 37, thereby reducing the energy levels at the interface with the insulating layer 33 by converting the trenches formed in the semiconductor substrate 31 into silicon-germanium. Even with this configuration, pinning is possible because carriers spread from the silicon-germanium layer 32.

[0068] <Seventh Configuration Example of Image Sensor> Referring to Figure 12, a configuration example of a seventh embodiment of an image sensor to which this technology is applied will be described. In the image sensor 11F shown in Figure 12, components common to the image sensor 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0069] Figure 12A shows an example of the cross-sectional configuration of a pixel 12 provided on the image sensor 11F, and Figure 12B shows a planar cross-sectional configuration along the dashed line shown in Figure 12A.

[0070] As shown in Figure 12, the image sensor 11F is composed of a stacked structure in which a sensor chip 21F and a logic chip 22 are stacked, and the logic chip 22 is configured in the same way as in Figure 1. The sensor chip 21F is composed of an insulating layer 33, a filter layer 34, and an on-chip lens layer 35 stacked in order on the back surface of the semiconductor substrate 31 (the surface facing upward in Figure 12), and a wiring layer 36 stacked on the front surface of the semiconductor substrate 31. The insulating layer 33, filter layer 34, on-chip lens layer 35, and wiring layer 36 are configured in the same way as in Figure 1.

[0071] Furthermore, the image sensor 11F differs from the image sensor 11 in that a silicon germanium layer 32F is laminated on the side surface of the trench formed in the semiconductor substrate 31, and no silicon germanium layer 32F is laminated on the back surface of the semiconductor substrate 31. For example, after epitaxial growth of the silicon germanium layer 32F in the third step described above (see Figure 3), the silicon germanium layer 32F as shown can be formed by removing the portion formed on the back surface of the semiconductor substrate 31. Note that the image sensor 11F only needs to be configured such that at least a silicon germanium layer 32F is provided on the side surface of the trench with weak pinning.

[0072] The image sensor 11F is configured in this way, and, similar to the image sensor 11 in Figure 1, by providing a single-crystal silicon-germanium layer 32F on the side surface of the trench in the semiconductor substrate 31, the generation of dark current can be suppressed, and higher quality images can be captured. Furthermore, since the image sensor 11F does not have a silicon-germanium layer 32F on the light-receiving surface, which is the back surface of the semiconductor substrate 31, it is possible to avoid the silicon-germanium layer 32F absorbing visible light on the light-receiving surface, thereby improving the quantum efficiency in the photoelectric conversion unit.

[0073] <Example of Electronic Device Configuration> The image sensor 11 described above can be applied to various electronic devices such as imaging systems like digital still cameras and digital video cameras, mobile phones equipped with imaging functions, or other devices equipped with imaging functions.

[0074] Figure 13 is a block diagram showing an example configuration of an imaging device mounted on an electronic device.

[0075] As shown in Figure 13, the imaging device 101 is configured to include an optical system 102, an image sensor 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still images and moving images.

[0076] The optical system 102 is composed of one or more lenses and guides the image light (incident light) from the subject to the image sensor 103, forming an image on the light-receiving surface (sensor part) of the image sensor 103.

[0077] The image sensor 103 is the same as the image sensor 11 described above. Electrons are accumulated in the image sensor 103 for a certain period of time, depending on the image formed on the light-receiving surface via the optical system 102. Then, a signal corresponding to the electrons accumulated in the image sensor 103 is supplied to the signal processing circuit 104.

[0078] The signal processing circuit 104 performs various signal processing operations on the pixel signals output from the image sensor 103. The image (image data) obtained by the signal processing circuit 104 is supplied to the monitor 105 for display or supplied to the memory 106 for storage (recording).

[0079] In the imaging device 101 configured in this way, by applying the image sensor 11 described above, for example, it is possible to improve the image quality.

[0080] <Examples of Image Sensor Usage> Figure 14 shows an example of using the image sensor (imaging element) described above.

[0081] The image sensor described above can be used in various cases to sense light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0082] - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0083] <Examples of Configuration Combinations> The technology can also take the following configurations: (1) An image sensor comprising: a sensor chip bonded to a logic chip via a wiring layer stacked on a semiconductor substrate on which a photoelectric conversion unit is provided for each pixel; a trench used as an element isolation unit to separate the photoelectric conversion units between adjacent pixels on the semiconductor substrate; and a single-crystal silicon-germanium layer doped with boron at a predetermined concentration, provided at least on the side surface of the trench. (2) The image sensor according to (1) above, wherein the trench is formed to a predetermined depth from the back side of the semiconductor substrate, and the silicon-germanium layer formed by epitaxial growth is provided on the back surface of the semiconductor substrate, and on the side surface and bottom surface of the trench. (3) The image sensor according to (1) above, wherein the trench is formed to penetrate the semiconductor substrate from the front side, an insulator is embedded to a predetermined depth from the front side of the trench, and the silicon-germanium layer formed by epitaxial growth is provided on the back surface of the semiconductor substrate and on the side surface of the trench. (4) An image sensor according to any one of (1) to (3) above, wherein at least an insulating layer is embedded in the trench via the silicon germanium layer, and an electrode used for applying a negative bias to the photoelectric conversion unit is provided inside the insulating layer. (5) An image sensor according to (4) above, wherein the electrode is a thin-film metal electrode or a transparent conductive film electrode. (6) An image sensor according to any one of (1) to (5) above, wherein the silicon germanium layer has a concentration gradient such that the germanium concentration changes from low to high as it moves away from the semiconductor substrate. (7) An image sensor according to any one of (1) to (6) above, further comprising a silicon layer laminated on the silicon germanium layer, and at least an insulating layer embedded in the trench via the silicon germanium layer and the silicon layer. (8) An image sensor according to any one of (1) to (7) above, wherein the silicon germanium layer is removed from the light-receiving surface of the semiconductor substrate and is provided only inside the trench of the semiconductor substrate.(9) The image sensor according to any one of (1) to (8) above, wherein the silicon germanium layer has a film thickness of 1 to 20 nm and is formed with a germanium concentration of 10 to 60%. (10) A method for manufacturing an image sensor, comprising: bonding a logic chip to a sensor chip via a wiring layer stacked on a semiconductor substrate on which a photoelectric conversion unit is provided for each pixel; forming a trench in the semiconductor substrate used as an element isolation section to separate the photoelectric conversion units from adjacent pixels; and forming a single-crystal silicon germanium layer doped with boron at a predetermined concentration on at least the side surface of the trench. (11) An electronic device comprising an image sensor having a sensor chip bonded to a logic chip via a wiring layer stacked on a semiconductor substrate on which a photoelectric conversion unit is provided for each pixel; a trench used as an element isolation section to separate the photoelectric conversion units from adjacent pixels on the semiconductor substrate; and a single-crystal silicon germanium layer doped with boron at a predetermined concentration, provided on at least the side surface of the trench.

[0084] It should be noted that this embodiment is not limited to the embodiment described above, and various modifications are possible without departing from the spirit of this disclosure. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist.

[0085] 11 Image sensor, 12 Pixel, 21 Sensor chip, 22 Logic chip, 31 Semiconductor substrate, 32 Silicon germanium layer, 33 Insulating layer, 34 Filter layer, 35 On-chip lens layer, 36 Wiring layer, 37 Silicon layer, 41 Color filter, 42 Light-shielding film, 61 Insulator, 62 Thin-film metal electrode, 63 Transparent conductive film electrode

Claims

1. An image sensor comprising: a sensor chip bonded to a logic chip via a wiring layer stacked on a semiconductor substrate, each of which is provided with a photoelectric conversion unit; a trench used as an element isolation unit to separate the photoelectric conversion units from each other between adjacent pixels on the semiconductor substrate; and a single-crystal silicon germanium layer provided on at least the side surface of the trench and doped with boron at a predetermined concentration.

2. The image sensor according to claim 1, wherein the trench is formed to a predetermined depth from the back side of the semiconductor substrate, and the silicon germanium layer formed by epitaxial growth is provided on the back side of the semiconductor substrate and on the side and bottom surfaces of the trench.

3. The image sensor according to claim 1, wherein a trench is formed from the surface side of the semiconductor substrate so as to penetrate the semiconductor substrate, an insulator is embedded from the surface side of the trench to a predetermined depth, and the silicon germanium layer formed by epitaxial growth is provided on the back surface of the semiconductor substrate and the side surface of the trench.

4. The image sensor according to claim 1, wherein at least an insulating layer is embedded in the trench via the silicon germanium layer, and an electrode used for applying a negative bias to the photoelectric conversion unit is provided inside the insulating layer.

5. The image sensor according to claim 4, wherein the electrode is a thin-film metal electrode or a transparent conductive film electrode.

6. The image sensor according to claim 1, wherein the silicon germanium layer has a concentration gradient such that the concentration of germanium changes from low to high as it moves away from the semiconductor substrate.

7. The image sensor according to claim 1, further comprising a silicon layer laminated on the silicon germanium layer, and an insulating layer embedded in at least the trench via the silicon germanium layer and the silicon layer.

8. The image sensor according to claim 1, wherein the silicon germanium layer is removed from the light-receiving surface of the semiconductor substrate and is provided only inside the trench of the semiconductor substrate.

9. The image sensor according to claim 1, wherein the silicon germanium layer is formed with a thickness of 1 to 20 nm and a germanium concentration of 10 to 60%.

10. A method for manufacturing an image sensor, comprising: bonding a logic chip to a sensor chip via a wiring layer stacked on a semiconductor substrate on which a photoelectric conversion unit is provided for each pixel; forming trenches in the semiconductor substrate to be used as element isolation units to separate the photoelectric conversion units from adjacent pixels; and forming a single-crystal silicon germanium layer doped with boron at a predetermined concentration on at least the side surface of the trenches.

11. An electronic device comprising an image sensor having a sensor chip bonded to a logic chip via a wiring layer stacked on a semiconductor substrate, each of which is provided with a photoelectric conversion unit; a trench used as an element isolation unit to separate the photoelectric conversion units from each other between adjacent pixels on the semiconductor substrate; and a single-crystal silicon germanium layer provided on at least the side surface of the trench and doped with boron at a predetermined concentration.

Images