Semiconductor device, method for generating logic circuit construction data, program, and compiler

Abstract

[Problem] To provide a semiconductor device capable of improving operation speed and reducing power consumption by optimizing wiring efficiency in a silicon chip, and to provide: a method for generating logic circuit construction data for simplifying a process related to a design for constructing a logic circuit of the semiconductor device; a program; and a compiler that facilitates integration into a system-on-chip (SoC). [Solution] The present invention comprises: a plurality of logic memory blocks having a plurality of SRAMs for realizing a logic function by storing a prescribed output value corresponding to an arbitrary input value; signal wiring disposed in a grid pattern for arranging the logic memory blocks in a two-dimensional array pattern and connecting the logic memory blocks to each other; and cut-off switch blocks disposed at intersections of the signal wiring.

Description

Semiconductor Device, Method for Generating Logic Circuit Construction Data, Program, and Compiler

[0001] The present invention relates to a semiconductor device, a method for generating logic circuit construction data, a program, and a compiler that enable an arbitrary logic configuration to be realized by software writing after manufacturing.

[0002] Conventionally, there is a semiconductor device called a field programmable gate array (hereinafter referred to as FPGA) that realizes an arbitrary logic function by programming with software after manufacturing.

[0003] An FPGA mainly has a configuration in which programmable logic blocks are arranged in a two-dimensional array, a plurality of signal lines are provided in the vertical and horizontal directions between the logic blocks, and a switch matrix is arranged at the intersection of the signal lines.

[0004] A logic block has a configuration called a look-up table (hereinafter referred to as LUT). This LUT is composed of a tournament-form circuit including a SRAM that stores a truth table corresponding to a desired function and a plurality of selectors connected to the SRAM.

[0005] The LUT outputs a desired truth value by activating a selector circuit using the address input value corresponding to the input signal from the truth table stored in the SRAM as the input value of the logical operation as it is.

[0006] Also, an FPGA is provided with a switch matrix for switching the signal path on signal lines arranged in a vertical and horizontal grid pattern prepared in advance.

[0007] The switch matrix consists of a plurality of transistor switch groups each regarded as one set of six transistor switches. This transistor switch group is arranged at the intersection of the signal lines, and forms a path for flowing a signal by switching on / off each transistor switch.

[0008] In other words, FPGAs enable the creation and rewriting of logic circuits after manufacturing by rewriting the truth table held by the LUT and switching the transistor switches that make up the switch matrix. That is, FPGAs can implement arbitrary logic functions after manufacturing.

[0009] Conventional FPGAs calculate the address input value for logical operations from the input values ​​based on the truth table within the LUT, and then activate the selector circuit using that address input value. Therefore, the physical operation of the selector circuit is always required, which could cause operational delays. In addition, this slower operation resulted in increased power consumption.

[0010] Furthermore, the switch matrix required to realize the desired signal routing consisted of multiple transistor switch groups, making it difficult to miniaturize. In addition, a large number of these switches needed to be installed inside the FPGA to enable all conceivable signal paths.

[0011] Therefore, FPGAs occupy the majority of the silicon chip area with signal lines and switch matrices, making it difficult to incorporate many logic functions into a single semiconductor device.

[0012] Therefore, as a method to solve the problems of reduced operating speed and increased power consumption caused by LUTs, a semiconductor device that realizes logic functions by storing truth values ​​to be output in response to a predetermined input signal is disclosed in Patent Document 1.

[0013] In other words, the semiconductor device described in Patent Document 1 stores a truth table in its memory to realize a desired logic function, and outputs the corresponding truth value from the truth table in response to a predetermined input value. This eliminates the selector circuit that was previously configured in the LUT of a conventional FPGA, thereby improving operating speed and reducing power consumption.

[0014] WO2007 / 060738 publication

[0015] However, the semiconductor device disclosed in Patent Document 1 does not disclose the wiring efficiency of signal lines and therefore does not solve the problem of the area occupied by signal lines and switches on the chip. This allows for complex and long signal line wiring, which can lead to a decrease in operating speed and an increase in power consumption.

[0016] Furthermore, while writing truth tables to memory and performing output based on them contributes to increased operating speed and reduced power consumption compared to LUT selector circuits, there was still room to further improve operating speed and reduce power consumption by selecting the appropriate memory.

[0017] Therefore, the present invention aims to provide a semiconductor device that optimizes wiring efficiency in a silicon chip to improve operating speed and reduce power consumption. It also aims to provide a method for generating logic circuit construction data for constructing arbitrary logic circuits, a program, and a compiler that enables integration into a system-on-a-chip (hereinafter referred to as SoC).

[0018] To solve the above problems, the semiconductor device, method for generating logic circuit construction data, program, and compiler of the present invention have the following features: [1] A semiconductor device having a plurality of logic memory blocks each having an SRAM that realizes a logic function by storing a predetermined output value corresponding to an arbitrary input value, signal lines arranged in a grid pattern to connect the logic memory blocks to each other in a two-dimensional array, and a disconnection switch block disposed at the intersection of the signal lines. [2] The semiconductor device according to [1], wherein the disconnection switch block has at least three switch mechanisms: a vertical disconnection switch provided on a vertical signal line arranged vertically among the signal lines, a horizontal disconnection switch provided on a horizontal signal line arranged horizontally, and a bridge disconnection switch installed across the vertical signal line and the horizontal signal line. [3] The semiconductor device according to [1] or [2], wherein the SRAM is clock asynchronous. [4] The semiconductor device according to [1] or [2], wherein the SRAM is clock synchronous. [5] The semiconductor device according to [1] or [2], wherein the SRAM is a mixture of clock-synchronous and clock-asynchronous types. [6] The semiconductor device according to any one of [1] to [5], wherein the logic memory block has four of the SRAMs. [7] The semiconductor device according to any one of [1] to [6], comprising a junction switch that connects two parallel signal lines, and capable of constructing any logic circuit by switching the junction switch on or off.[8] A method for generating logic circuit construction data for constructing an arbitrary logic circuit in a semiconductor device having a plurality of logic memory blocks, comprising: a function design description step for designing a predetermined logic function for the semiconductor device; a diagram generation step for generating a diagram showing the grouping of the logic memory blocks for executing the logic function; a terminal number comparison step for comparing the number of input terminals required for each group with the number of input terminals that the actual logic memory block has; a logic function assignment step for determining how to assign the groups to the plurality of actual logic memory blocks; a logic description step for generating logic description statements to be written to the logic memory blocks in order to realize the logic function; a verification data generation step for generating verification data for functional verification of the circuit data of the semiconductor device; a function verification step for performing functional verification based on the verification data; a truth value calculation step for calculating the truth value of each logic operation from the logic description statements; and a programming data generation step for generating programming data to be implemented in the semiconductor device in order to realize the logic function based on the truth value and the circuit data.[9] A method for generating logic circuit construction data for a semiconductor device having a plurality of logic memory blocks, comprising: a logic function assignment step of determining how to assign predetermined logic functions to the actual devices of the plurality of logic memory blocks; an external assignment setting step of determining which terminals to assign external devices to be externally connected to the semiconductor device to; an internal assignment setting step of setting the assignment of terminals used for connecting the plurality of logic memory blocks to each other; an entity generation step of generating framework data relating to logic description statements to be written to each of the logic memory blocks in order to realize the logic functions; a logic memory block design step of writing the logic description statements according to the framework data; a verification data generation step of generating verification data for functional verification of the circuit data of the semiconductor device; a functional verification step of performing functional verification based on the verification data; a truth value calculation step of calculating the truth value of each logic operation from the logic description statements; and a programming data generation step of generating programming data to be implemented in the semiconductor device in order to realize the logic functions based on the truth value and the circuit data.

[10] A program that causes a computer to execute the following steps: a function design description step for designing a predetermined logic function for a semiconductor device; a diagram generation step for generating a diagram showing the grouping of logic memory blocks for executing the logic function; a terminal number comparison step for comparing the number of input terminals required for each group with the number of input terminals on the actual logic memory block; a logic function assignment step for determining how to assign the groups to a plurality of actual logic memory blocks; a logic description step for generating logic description statements to be written to the logic memory blocks in order to realize the logic function; a verification data generation step for generating verification data for functional verification of the circuit data of the semiconductor device; a function verification step for performing functional verification based on the verification data; a truth value calculation step for calculating the truth value of each logic operation from the logic description statements; and a programming data generation step for generating programming data to be implemented on the semiconductor device in order to realize the logic function based on the truth value and the circuit data.

[11] A program that causes a computer to execute the following steps: a logic function assignment step of determining how to assign predetermined logic functions to multiple logic memory blocks; an external assignment setting step of determining which terminals to assign external devices to be externally connected to the semiconductor device; an internal assignment setting step of setting the assignment of terminals used for connecting multiple logic memory blocks to each other; an entity generation step of generating framework data relating to logic description statements to be written to each of the logic memory blocks in order to realize the logic functions; a logic memory block design step of writing the logic description statements according to the framework data; a verification data generation step of generating verification data for functional verification of the circuit data of the semiconductor device; a functional verification step of performing functional verification based on the verification data; a truth value calculation step of calculating the truth value of each logic operation from the logic description statements; and a programming data generation step of generating programming data to be implemented in the semiconductor device in order to realize the logic functions based on the truth value and the circuit data.

[12] A compiler capable of generating layout data for incorporating a semiconductor device having multiple logic memory blocks consisting of multiple SRAMs into an SoC, the compiler which automatically compiles based on predetermined input information and outputs layout data including design information of the logic memory blocks and design information of the semiconductor device.

[0019] The semiconductor device of the present invention uses SRAM in the logic memory block and further optimizes the signal wiring path with a disconnection switch block, thereby improving operating speed and reducing power consumption. Furthermore, the disconnection switch block can be made smaller than the switch matrix used in FPGAs, allowing sufficient space for the logic memory block on the silicon chip. In addition, by incorporating clock-asynchronous SRAM, signals can be read and written without being affected by the clock period, contributing to further improvements in operating speed and reductions in power consumption.

[0020] Furthermore, the method and program for generating logic circuit construction data of the present invention can eliminate the enormous amount of time and effort required for tasks such as timing verification in FPGA development, thereby enabling the rapid development of semiconductor devices.

[0021] Furthermore, the compiler of the present invention can generate layout data for integration into an SoC by inputting predetermined information, thereby enabling the integration of the semiconductor device of the present invention into an SoC. In other words, it makes it possible to integrate a logic-programmable semiconductor device, which can replace FPGAs that were previously difficult to integrate into SoCs, into an SoC. Moreover, since it compiles and generates layout data by inputting predetermined information, it can contribute to the eco-friendliness of SoC design.

[0022] This is a schematic diagram showing the overall configuration of a semiconductor device according to one embodiment of the present invention. This is a schematic diagram showing the configuration of a logic memory block according to one embodiment of the present invention. This is a schematic diagram showing the configuration and usage state of a disconnection switch block according to one embodiment of the present invention. This is a schematic diagram showing the arrangement state of a junction switch according to one embodiment of the present invention. This is a flowchart showing the process of generating logic circuit construction data when constructing a new logic circuit according to one embodiment of the present invention. This is a flowchart showing the process of generating logic circuit construction data when constructing a logic circuit based on existing design data according to one embodiment of the present invention. This is an explanatory diagram showing an overview of a compiler according to one embodiment of the present invention. This is an explanatory diagram showing the compilation flow in a compiler according to one embodiment of the present invention.

[0023] [1. About the Semiconductor Device] The configuration of the semiconductor device SE according to one embodiment of the present invention will be described below based on the drawings. Figure 1 schematically shows the overall configuration of the semiconductor device SE. Therefore, although the actual signal lines 3 consist of multiple lines arranged in parallel both vertically and horizontally, they are shown as one line each for the sake of simplicity in the diagram. Figure 2 is a diagram showing the configuration of the logic memory block 2, and each arrow schematically indicates the input and output of a signal. Figure 3 schematically shows the configuration of the disconnection switch block 4, and (b) and (c) show the electrical disconnection state of the signal line 3 due to the switch function being turned off in order to realize the desired wiring path. In addition, the numbers 0 and 1 shown near the switch function in Figure 3 represent the off state of the switch mechanism and the on state of the switch mechanism, respectively, with 0 representing the off state and 1 representing the on state of the switch mechanism. Figure 4 schematically shows the state in which the junction switch 6 is installed, illustrating a partially enlarged view of the semiconductor device SE.

[0024] As shown in Figure 1, the semiconductor device SE includes a base silicon chip 1, a plurality of logic memory blocks 2 arranged in a two-dimensional array on the silicon chip 1, signal lines 3 arranged in a grid pattern to connect the logic memory blocks 2, and disconnection switch blocks 4 arranged at the intersections of the signal lines 3.

[0025] As shown in Figure 2, the logical memory block 2 consists of four SRAMs 21 and internal wiring 22 connecting each SRAM 21 to each other.

[0026] The SRAM 21 stores predetermined output values ​​(truth values) corresponding to arbitrary input values ​​in order to realize the desired logic functions during the logic design phase. For example, if the input value to the SRAM is 0, it stores the corresponding truth value of 0 or 1 in advance and outputs that value.

[0027] This eliminates the need for the selector circuit within the LUT in conventional FPGAs, thereby enabling the desired logic functionality. This eliminates the physical operating speed required by the selector circuit, resulting in improved operating speed. Furthermore, since the selector circuit is no longer needed, it eliminates the power consumption associated with its operation.

[0028] Furthermore, by configuring the logical memory block 2 with SRAM 21, there is an advantage in that the operating speed is faster compared to when other storage devices are used.

[0029] Incidentally, while SRAM always operates in sync with the clock when writing information, it can read information independently of the clock period.

[0030] Therefore, at least one of the four SRAMs 21 constituting the logical memory block 2 is configured as a clock-asynchronous type, resulting in a mixed configuration with clock-synchronous types.

[0031] The logical memory block 2 is equipped with a clock-asynchronous SRAM 21, which allows for signal transmission without being affected by the clock period when there is no change in the truth values ​​related to input / output between SRAMs 21 within the logical memory block 2 or between the logical memory blocks 2.

[0032] Specifically, when the asynchronous SRAM 21 performs signal input and output, if the input value is 0 and the output value is also 0 (or if the input value is 1 and the output value is also 1), there is no need to change the output value (write information to the SRAM 21). Therefore, the input of a signal and the output of the same signal do not need to be synchronized with the clock period, and the signal with an input value of 0 can be transmitted to the next SRAM 21 without being affected by the clock period.

[0033] In other words, if there is no change in the truth values ​​at input and output, the asynchronous SRAM 21 can behave like a simple wiring that only transmits signals. This significantly reduces the time wasted in signal transmission and contributes to improving the operating speed of the semiconductor device SE.

[0034] In other words, when synchronized with the clock period, even if there is no change in the truth value, the operation will proceed as if there is no change in accordance with the clock period, and the operation will take longer because it is synchronized with the clock period. Therefore, the logical memory block 2 according to the present invention can eliminate this operation time.

[0035] Furthermore, in the case of a clock-synchronous type, even if the truth value does not change, it will operate as if there is no change in accordance with the clock period. Therefore, even if the truth value (output value) for the input value is the same, it will operate and consume power with each clock period.

[0036] The asynchronous SRAM 21 simply transmits the input value as is when there is no change in the truth value, thus effectively reducing power consumption by eliminating any operational steps.

[0037] Furthermore, when generating the logic for an FPGA, that is, during the development and design of an FPGA, programming is performed using a language called RTL (Register Transfer Level) for logic design.

[0038] This RTL language performs logic design along a time axis managed by a clock. Therefore, programming in an RTL language requires writing the logic function design while considering synchronization with the clock operation, and development in this language requires a certain level of expertise.

[0039] However, the semiconductor device SE according to the present invention is equipped with a clock-asynchronous SRAM 21, which enables logic design without considering clock operation during development. Therefore, it becomes possible to program using a language that does not have the concept of a clock, such as C language.

[0040] Furthermore, the semiconductor device SE according to the present invention also includes a clock-synchronous SRAM 21, making it possible to use conventional development methods, namely, to write programs using the RTL language.

[0041] As shown in Figure 1, the signal lines 3 are arranged in a grid pattern between the logic memory blocks 2, which are arranged in a two-dimensional array, so that any signal path can be realized. In the following description, signal lines 3 arranged vertically with respect to the silicon chip 1 will be called vertical signal lines 31, and signal lines arranged horizontally will be called horizontal signal lines 32.

[0042] Also, the signal line 3 is connected to an input / output block (hereinafter referred to as IOB) that enables input / output with the outside arranged along the outer periphery of the silicon chip 1. This IOB 5 has pin terminals for connecting a so-called semiconductor device SE and an external device such as a CPU.

[0043] The cut-off switch block 4 is disposed at the intersection of the vertical signal line 31 and the horizontal signal line 32. As a specific configuration, as shown in FIG. 3, it is composed of a total of three switch mechanisms: a vertically provided cut-off switch 41 provided on the vertical signal line 31, a horizontally provided cut-off switch 42 provided on the horizontal signal line 32, and a bridging cut-off switch 43 bridged between the vertical signal line 31 and the horizontal signal line 32.

[0044] In explaining the function of the cut-off switch block 4, as shown in FIG. 3, the cut-off switch block 4 is illustrated in a rhombus shape for convenience. Also, the upper vertex portion of the rhombus-shaped cut-off switch block 4 is denoted by reference numeral 4a, the lower vertex portion by reference numeral 4b, the left vertex portion by reference numeral 4c, and the right vertex portion by reference numeral 4d for explanation. However, the shape of the cut-off switch block 4 is not limited to a rhombus shape.

[0045] The three switch mechanisms (vertically provided cut-off switch 41, horizontally provided cut-off switch 42, and bridging cut-off switch 43) of this cut-off switch block 4 are all in an on state as shown in FIG. 3(a) before the path design of the signal line 3.

[0046] Therefore, both the vertical signal line 31 and the horizontal signal line 32 corresponding to the intersection where the cut-off switch block 4 is provided are in a state where they can transmit signals (electricity can flow).

[0047] In the path design, when it is desired to construct a signal path from 4a to 4b, the cut-off switch block 4 is realized by turning off the horizontally provided cut-off switch 42 and the bridging cut-off switch 43 as shown in FIG. 3(b).

[0048] At this time, the disconnection switch block 4 turns off the horizontally installed disconnection switch 42 that enabled signal transmission on the horizontal signal line 32 and the installed disconnection switch 43 that enabled signal transmission between the vertical signal line 31 and the horizontal signal line 32, thereby electrically disconnecting the signal line 3 and blocking signal transmission.

[0049] Therefore, the signal flowing from the 4a side to the disconnection switch block 4 will be transmitted only in the 4b direction where transmission is possible.

[0050] Similarly, when the disconnection switch block 4 wants to construct a signal path from 4c to 4a in the path design, as shown in Fig. 3(c), it is realized by turning off the vertically installed disconnection switch 41.

[0051] At this time, the disconnection switch block 4 turns off the vertically installed disconnection switch 41 that enabled signal transmission on the vertical signal line 31, thereby electrically disconnecting it and blocking signal transmission.

[0052] Therefore, the signal flowing from the 4c side to the disconnection switch block 4 will be transmitted in the transmissible 4a direction and 4d direction. When it is desired to transmit it only in the 4a direction, turn off the horizontally installed disconnection switch 42 of the adjacent disconnection switch block 4 arranged to the right of the disconnection switch block 4 shown in Fig. 3(c). By doing so, the signal flowing in the 4d direction will be blocked by the adjacent disconnection switch block 4, and the flow of unwanted signals can be cut off.

[0053] That is, the disconnection switch block 4 can form a desired circuit by blocking the signal path passing through the disconnection switch block 4 by switching the on / off of the three switch mechanisms. Also, when the path through which the signal flows has two directions, it can be cut off by turning off the adjacent disconnection switch block 4 located on the extension other than the desired signal path, and a desired signal path can be formed.

[0054] As described above, even in other cases, the desired signal path can be constructed by turning off the switch mechanisms (vertical cutting switch 41, horizontal cutting switch 42, and overhead cutting switch 43) corresponding to the signal lines 3 that are not needed in the path through which the signal is to be transmitted.

[0055] This disconnection switch block 4 can realize the desired signal path using only three switch mechanisms (vertical disconnection switch 41, horizontal disconnection switch 42, and overhead disconnection switch 43).

[0056] Therefore, compared to the switch matrix used in conventional FPGAs, it has a simpler configuration and can be miniaturized.

[0057] This improves the wiring efficiency of the silicon chip 1 and reduces the area occupied by the signal lines 3 and disconnection switch block 4 necessary to realize the desired logic function.

[0058] Furthermore, by reducing the occupancy rate of signal lines 3 and disconnection switch blocks 4 on the silicon chip 1, the number of logic memory blocks 2 that can be mounted per unit area can be increased, enabling the realization of more complex logic functions.

[0059] The disconnection switch block 4 may be constructed using transistor switches, similar to conventional switch matrices. However, transistor switches have high resistance and slow transmission speed. While increasing the size of the transistors used in the transistor switches reduces the resistance, it has the disadvantage of increasing the area occupied on the chip.

[0060] Therefore, it is desirable that the disconnection switch block 4 be formed by a gate rather than a transistor switch. By using a gate, the resistance value can be lower compared to a transistor switch, and a switch mechanism with a faster transmission speed can be realized.

[0061] Furthermore, the semiconductor device SE may also be equipped with a junction switch 6 that connects two parallel vertical signal lines 31 or two horizontal signal lines 32, as shown in Figure 4(a).

[0062] By providing this junction switch 6, the degree of freedom in the overall circuit design of the semiconductor device SE is increased, and the length of the signal line 3 can be prevented as much as possible.

[0063] In particular, it is preferable that the junction switch 6 be provided along the outermost edge of the signal line 3, i.e., along the outer edge of the semiconductor device SE, as shown in Figure 4(b).

[0064] By arranging the junction switch 6 along the outer edge, all signal lines 3 can be connected in a single continuous line, which has the advantage of making it easier to wire signals that should be common to all logic memory blocks 2, such as the clock signal.

[0065] [2. Method for Generating Logic Circuit Construction Data] The logic circuit construction data generation method LM according to the present invention can be considered in two ways: when constructing a new logic circuit and when constructing a logic circuit based on existing design data (for example, logic function design data of FPGAs or other semiconductor devices that have been used up to the present). Each case will be explained with reference to the drawings.

[0066] The method LM for generating logic circuit construction data when constructing a new logic circuit includes, as shown in Figure 5, a functional design description step FS1, a description statement verification step FS2, a diagram generation step FS3, a terminal count comparison step FS4, a logic function assignment step FS5, a logic description step FS6, a verification data generation step VS1, a functional verification step VS2, a truth value calculation step VS3, and a programming data generation step VS4.

[0067] The functional design description process FS1 is a process in which the functional design is described using a predetermined language. Specifically, the logical functions of the semiconductor device SE desired by the designer are described in machine language. It is desirable to use a high-level language that is easy for humans to understand, and RTL language is particularly suitable. For convenience, in the following explanation, the description written in this process will be referred to as the functional design description.

[0068] Furthermore, while this embodiment uses a method in which the designer describes the desired logical function using machine language as an example, it is also conceivable that the designer describes the desired logical function using text instead of machine language, and that this description is automatically converted into machine language by a computer.

[0069] The description verification process FS2 is a process in which a computer, according to a program, extracts grammatical errors from the functional design description created by the designer and analyzes the content of the functional design description. If a grammatical error is found in the functional design description, the computer will inform the designer of this. Once the verification of the functional design description is completed in the description verification process FS2, the process proceeds to the next step, the diagram generation process FS3.

[0070] The diagram generation process FS3 is a process that groups how the logical functions that can be executed based on the description of the functional design statement will be executed in the logical memory block 2, and generates a diagram of the contents. This process is executed by a computer according to the program.

[0071] Specifically, logical functions are realized by performing multiple logical operations within the device. Therefore, the diagram generation process FS3 illustrates in a diagram how far the logical operations should be performed on one of the multiple logical operations, namely the logical memory block 2.

[0072] This diagram can be any diagram that allows us to understand the assignment of logical operations to logical memory block 2. For example, it may represent each logical operation processed by the same logical memory block 2 with small shapes, and the larger shape enclosing these small shapes may represent the logical memory block 2.

[0073] As described above, a single logical memory block 2 can perform multiple logical operations. However, the number of logical operations that can be processed by a single logical memory block 2 is limited by the number of terminals used for signal input and output.

[0074] Therefore, the number of input / output terminals required for one logic memory block 2 shown in the diagram must be less than or equal to the number of input / output terminals of the logic memory block 2 implemented in the semiconductor device SE.

[0075] Therefore, the terminal count comparison step FS4 is a step that compares the number of input / output terminals required for the logical memory block 2 shown in each diagram with the actual number of input / output terminals in the logical memory block 2, and verifies that there are no problems with the number of input / output terminals. This step is performed by a computer according to the program.

[0076] Furthermore, if the number of input / output terminals required for logical memory block 2 as shown in the diagram is greater than the number of input / output terminals in logical memory block 2, the corresponding group is decomposed and reconstructed. The number of input / output terminals of logical memory block 2 shown in all diagrams is then kept within the actual number of input / output terminals in logical memory block 2.

[0077] The logic function assignment process FS5 is the process of determining where to assign the arithmetic processing (logic function) of each group illustrated in the diagram to one of the multiple logic memory blocks 2 mounted on the actual semiconductor device SE. This process can be performed by the designer or by a computer according to a program.

[0078] At this point, it is also possible to cluster each group before assigning logical functions. That is, multiple groups are classified according to predetermined rules, and identical or similar classes are assigned to close locations. This makes it possible to shorten the length of signal line 3 as much as possible, enabling improved operating speed and reduced power consumption during operation.

[0079] Furthermore, the logic function assignment process FS5 also determines the path of the signal lines 3 between the logic memory blocks 2 to which the logic functions have been assigned. This path determination also includes information regarding the on / off state of the disconnection switch block 4. This step may also be separated into a different process.

[0080] The logical description process FS6 is a process that generates logical description statements to be written to the logical memory block 2 in order to execute logical functions.

[0081] This process may involve the designer directly writing the logical description statements for executing the logical functions corresponding to each logical memory block 2, or it may be a method in which the computer automatically generates them from the functional design description statements obtained in the functional design description process FS1. For convenience, in the following explanation, the description statements written in this process will be referred to as logical description statements.

[0082] This logical description can be written in any machine language; however, it is most preferably in an RTL language, which is commonly used for such descriptions.

[0083] The verification data generation process VS1 generates verification data for verifying the circuit data of the entire semiconductor device SE and the logic functions obtained from the circuit data, based on the information obtained through the processes described above. This process is executed by a computer according to a program.

[0084] Specifically, the circuit data for the entire semiconductor device SE is generated based on information such as which logic memory block 2 to assign the logic function determined in the logic function assignment process FS5, information regarding the paths of the signal lines 3 between each logic memory block 2, and information regarding the logic description statements to be written to the logic memory block 2 determined in the logic description process FS6.

[0085] Next, verification data is generated to verify the logic functions obtained from the circuit data and the operation of the circuits that realize them. This verification data is written in a language that can be read by the functional verification simulator used in the next step, functional verification step VS2. The language corresponding to this simulator can be any machine language, but Verilog-RTL is preferably used.

[0086] The functional verification process VS2 reads the verification data generated in the verification data generation process VS1 into the functional verification simulator and verifies whether there are any problems with the circuit design of the semiconductor device SE. In other words, the functional verification simulator verifies whether the desired logic functions can be realized and whether there are any inefficiencies in the operation when the actual semiconductor device SE is programmed according to the generated circuit data.

[0087] The truth value calculation process VS3 is performed after the function verification process VS2 has determined that there are no problems in realizing the logical functions, and calculates the results of each logical operation from the logical description statements written in each logical memory block 2. In other words, it is the process of converting the logical function description statements written in each logical memory block 2 into truth values ​​that are actually stored in the SRAM 21. This process is executed by a computer according to the program.

[0088] Incidentally, the SRAM 21 used in semiconductor device SE has the characteristic of losing the information it stores internally when the power supply is cut off. Therefore, when the power supply is restored, it is necessary to store the data (configuration data) to be stored in the SRAM 21 in a non-volatile memory, that is, a memory that retains information regardless of whether power is supplied or not (for example, ROM or flash memory).

[0089] The truth value information obtained in the truth value calculation process VS3 is also used as configuration data. Naturally, the semiconductor device SE in this embodiment is equipped with an internal storage device such as ROM or flash memory to hold this configuration data. Alternatively, the semiconductor device SE could be connected to an external storage device that holds the configuration data.

[0090] The programming data generation process VS4 generates programming data to be written to the actual semiconductor device SE, based on the truth values ​​(including configuration data) obtained in the truth value calculation process VS3 and the wiring information of the signal lines 3 for realizing the logic functions. This process is executed by a computer according to the program.

[0091] The programming data consists of truth values, which can be called logical design information, stored in each logical memory block 2, assignment information with external devices, and wiring information for connecting each logical memory block 2 to itself.

[0092] The wiring information consists of signal transmission paths between each logic memory block 2, i.e., path design information for signal lines 3, and on / off information for the disconnection switch block 4. However, the switch does not have to be the disconnection switch block 4; any switch that allows arbitrary selection of whether or not to transmit a signal to the signal lines 3, which are pre-arranged in a grid pattern, may be used.

[0093] Next, we will explain the case of constructing a logic circuit based on existing design data. Note that the verification data generation process VS1, the functional verification process VS2, the truth value calculation process VS3, and the programming data generation process VS4 described below are the same as the process when constructing a new logic circuit as described above, so their explanation will be omitted.

[0094] The method LM for generating logic circuit construction data when constructing a logic circuit based on existing design data includes, as shown in Figure 6, a logic function assignment step TS1, an external assignment setting step TS2, an internal assignment setting step TS3, an entity generation step TS4, a logic memory block design step TS5, a verification data generation step VS1, a function verification step VS2, a truth value calculation step VS3, and a programming data generation step VS4.

[0095] The logic function assignment process TS1 is a process that determines the assignment of logic functions, such as which logic memory block 2 will execute the functions that are performed by the logic description statements in the existing design data. The logic function assignment process TS1 is a process that includes the diagram generation process FS3, the terminal count comparison process FS4, and the logic function assignment process FS5 in the method for generating logic circuit construction data when constructing a new logic circuit as described above.

[0096] Specifically, the logical function assignment process TS1 includes details such as which logical memory block 2 to execute each logical operation on, how many logical operations to perform on a single logical memory block 2, and whether there are enough input / output terminals.

[0097] This logical function assignment process TS1 can be performed by the designer, or it can be executed by a computer using a program that reads existing design data and automatically assigns logical functions.

[0098] The external assignment setting process TS2 is the process of setting which terminal of the IOB5 on the semiconductor device SE will be assigned to connect to an external device. This is basically done by the designer, but it may also be performed by a computer according to a program.

[0099] The internal assignment setting process TS3 sets the assignments between each logic memory block 2, which has its logic function set in the logic function assignment process TS1. It also sets the wiring paths of the signal lines 3 and the disconnection switch blocks 4 to realize the desired logic function. This is basically done by the designer, but it may also be performed by a computer according to the program.

[0100] The entity generation process TS4 is a process in which an entity file for describing a logical function in each logical memory block 2 is automatically generated by a computer.

[0101] In the logical memory block design process TS5, the designer writes a logical description statement for each logical memory block 2 according to the entity file generated in the entity generation process TS4.

[0102] The description of this logical statement is based on programming in the RTL language. Therefore, the entity file generated in the entity generation process TS4 serves as framework data for description in the RTL language.

[0103] However, logical descriptions do not necessarily have to be written in an RTL language; they may be written in other languages, such as C. Naturally, in that case, the entity files generated in the entity generation process TS4 will be framework data tailored to the language used.

[0104] Once the logical memory block design process TS5 is completed, the design work then proceeds in the following order: verification data generation process VS1, functional verification process VS2, truth value calculation process VS3, and programming data generation process VS4.

[0105] The logic circuit construction data generation method LM is performed using a program that causes a computer to sequentially execute the processes described above, whether a new logic circuit is being constructed or a logic circuit is being constructed based on existing design data.

[0106] Specifically, when constructing a new logic circuit, as shown in Figure 5, the computer executes the functional design description process FS1 to the logic description process FS6 using the function mapping program FMP, and the computer executes the verification data generation process VS1 to the programming data generation process VS4 using the verification and data generation program VGP.

[0107] Furthermore, the function mapping program FMP according to this embodiment is configured to require a description from the designer for the first step, the function design description step FS1, while the other steps are executed by the computer through the program.

[0108] In this case, it is preferable to have the computer programmatically display the input form in order to assist the designer in the functional design description process FS1.

[0109] However, this configuration is not always necessary; a mix of requests for descriptions from the designer and computer-based analysis may be considered. Furthermore, the execution scope of the function mapping program (FMP) may include the verification data generation process (VS1).

[0110] When constructing a logic circuit based on existing design data, as shown in Figure 6, the first steps, from the logic function setting step TS1 to the logic memory block design step TS5, are executed by the computer using the template mapping program TMP, and the verification data generation step VS1 to the programming data generation step VS4 are executed by the computer using the verification and data generation program VGP.

[0111] Furthermore, the template mapping program TMP is configured to request input from the designer during the logical function assignment process TS1, the external assignment setting process TS2, the internal assignment setting process TS3, and the logical memory block design process TS5, while the entity generation process TS4 is executed by the computer via a program.

[0112] However, this configuration is not always necessary; a mix of requests for descriptions from the designer and computer-based analysis may be considered. Furthermore, the execution scope of the template mapping program TMP may include the verification data generation process VS1.

[0113] Furthermore, the template mapping program TMP is configured to display input templates to assist with input during processes that require input from the designer. In other words, the designer can generate logic circuit construction data by making inputs according to the input templates.

[0114] Therefore, the logic circuit construction data generation method LM can facilitate the design of the logic functions of semiconductor device SE.

[0115] Furthermore, in the development of conventional FPGAs and similar semiconductor devices, after logic verification (the functional verification process in this embodiment), it is necessary to perform three verifications: logic synthesis, which replaces the descriptive statements with gate circuits; gate verification, which verifies the operation of the gate circuits replaced by logic synthesis; and timing verification, which verifies whether the calculations that realize the logic functions operate normally on the clock period.

[0116] In particular, timing verification in the development of semiconductor devices requires a vast number of verifications, which has been a factor in prolonging development.

[0117] However, in the logic circuit construction data generation method LM according to the present invention, the logic description statement verified by functional verification is converted into a truth value, and this information can be used as configuration data, thus eliminating the need to replace it with a gate circuit.

[0118] Furthermore, because the logic memory block 2 that stores truth values ​​functions in the same way as the logic blocks in an FPGA, and because the wiring is optimized by the disconnection switch block 4, delays caused by gate circuits and wiring are almost eliminated, thus eliminating the need for timing verification. Therefore, the development and design period for the semiconductor device SE can be significantly reduced.

[0119] [3. About Compilers] SoCs are manufactured by semiconductor manufacturers (including not only companies but also factories; hereinafter referred to as Fab) by placing discrete semiconductors such as memory and MPUs that conform to the standards onto a silicon chip during the manufacturing process.

[0120] Therefore, FPGAs, which require a special manufacturing process different from that of discrete semiconductors incorporated into SoCs, could not be included in the conventional SoC manufacturing process and thus could not be incorporated into existing standardized SoCs.

[0121] However, because FPGAs allow for logic circuit programming after manufacturing, there is high demand for the devices themselves, and at the same time, there is a strong desire to integrate them into SoCs.

[0122] The semiconductor device SE according to the present invention allows for the writing of logic circuits after manufacturing and can be used in the same way as a conventional FPGA. On the other hand, since the semiconductor device SE is composed of SRAM 21, unlike conventional FPGAs it does not involve a special manufacturing process and can be incorporated into an SoC in the same way as ordinary SRAM as memory.

[0123] Therefore, a compiler C for more easily integrating the semiconductor device SE according to the present invention into a SoC will be described.

[0124] As shown in Figure 7, compiler C outputs layout data CO1 and verification data CO2 based on predetermined input information, enabling easy integration of the semiconductor device SE into the SoC. By using the output layout data CO1, which is tailored to the SoC, the semiconductor device SE can be easily integrated into the SoC, just as an SRAM can be integrated into the SoC.

[0125] The information input to compiler C consists of at least Fab information CI1, which includes the design rules for the SoC; memory IP information CI2, which includes memory design data supplied from Fab; and semiconductor device information CI3, which includes the capacity and operating frequency of the semiconductor device SE to be incorporated into the SoC.

[0126] Memory IP information CI2 is the design information of the memory actually used by the Fab in the SoC. In other words, this corresponds to the design information of the SRAM 21 that constitutes the semiconductor device SE.

[0127] The output layout data CO1 consists of information about the semiconductor device SE and information about the logical memory block 2 that constitutes the semiconductor device SE.

[0128] Information regarding the semiconductor device SE includes circuit information of the semiconductor device SE (device circuit information CO11) and arrangement information of the logic memory blocks 2 that constitute the semiconductor device SE (block layout information CO12).

[0129] The information relating to the logic memory block 2 includes circuit information of the logic memory block 2 (block circuit information CO13) and arrangement information of the SRAM 21 constituting the logic memory block 2 (SRAM layout information CO14).

[0130] Incidentally, SoC requires functional verification of the entire integrated circuit it incorporates. Therefore, compiler C outputs the information of various verifications performed when generating layout data CO1 as verification data CO2.

[0131] Next, we will explain the compilation process using compiler C. Compiler C holds, as a database, the input format C1 for Fab information CI1, reference circuit information C2 for multiple pre-prepared logical memory blocks 2, and framework information C3 for the arrangement and wiring of SRAM 21 in the logical memory block 2.

[0132] Regarding the compilation process, as shown in Figure 8, first, compiler C requests the designer to input Fab information CI1, memory IP information CI2, and semiconductor device information CI3. At this time, the designer inputs Fab information CI1 according to input format C1 sent from compiler C. By standardizing the input format with input format C1, it is possible to make it easier for compiler C to read the data. However, input format C1 is not mandatory as long as Fab information CI1 can be input.

[0133] Compiler C generates the information from the logical memory block 2 within the layout data CO1 based on the input information.

[0134] Compiler C generates block circuit information CO13 by synthesizing the circuit of logic memory block 2. The circuit synthesis of logic memory block 2 is performed by referencing reference circuit information C2 held by compiler C, and using the input memory IP information CI2 and Fab information CI1 to automatically generate the circuit of logic memory block 2 in accordance with the SoC manufacturing process of the specified Fab.

[0135] The circuit of the automatically generated logical memory block 2 will be verified to ensure it functions correctly through functional testing. Specifically, a netlist will be extracted from the generated logical memory block 2 circuit, and the logical functions of that netlist will be verified using a simulator.

[0136] The circuit information of logic memory block 2, which has been determined to be correct through functional verification, becomes block circuit information CO13. In addition, the data obtained when verifying the circuit of logic memory block 2 (functional verification data CO21) becomes one of the verification data CO2 that is output later.

[0137] Next, based on the generated block circuit information CO13, the SRAM 21 is automatically arranged according to the design rules included in the input Fab information CI1 and the framework information C3 held by the compiler C.

[0138] Once the placement of the SRAM 21 is complete, a layout verification is performed to check whether the placement conforms to the design rules and whether it is constructed according to the block circuit information CO13.

[0139] If the layout verification confirms that there are no problems with the placement of SRAM 21, this placement information becomes SRAM layout information CO14. Furthermore, the data obtained during the verification of the SRAM 21 placement (SRAM layout verification data CO22) becomes one of the verification data CO2 outputs later.

[0140] Next, compiler C generates device circuit information CO11 by performing circuit synthesis of the semiconductor device SE. Circuit synthesis of the semiconductor device SE automatically generates the circuit of the semiconductor device SE, which constitutes the logic memory block 2, based on the semiconductor device information CI3 input by the designer.

[0141] The automatically generated semiconductor device (SE) circuit is verified to ensure there are no problems with the connections between each logic memory block 2. Specifically, a netlist is extracted from the generated semiconductor device (SE) circuit, and the connections are verified using a simulator against that netlist.

[0142] The circuit information of the semiconductor device SE that is determined to be correct through connection verification becomes the device circuit information CO11. In addition, the data obtained when verifying the connection of the semiconductor device SE circuit (connection verification data CO23) becomes one of the verification data CO2 that is output later.

[0143] Next, based on the generated device circuit information CO11, the logical memory block 2 is automatically arranged according to the design rules contained in the input Fab information CI1.

[0144] Once the placement of the logic memory block 2 is complete, a layout verification is performed to check whether the placement conforms to the design rules and whether it is constructed according to the device circuit information CO11.

[0145] If the layout verification confirms that there are no problems with the placement of SRAM 21, this placement information becomes block layout information CO12. Additionally, the data obtained when verifying the placement of logical memory block 2 (block layout verification data CO24) becomes one of the verification data CO2 outputs later.

[0146] Once compiler C has finished generating block layout information CO12, it outputs block circuit information CO13, SRAM layout information CO14, device circuit information CO11, and block layout information CO12 as layout data CO1. It also outputs function verification data CO21, SRAM layout verification data CO22, connection verification data CO23, and block layout verification data CO24 as verification data CO2.

[0147] As described above, the compiler C receives Fab information CI1, memory IP information CI2, and semiconductor device information CI3 as input from the designer. Based on the various input information and the input format C1, reference circuit information C2, and framework information C3 that the compiler C holds as a database, it can output layout data CO1 and verification data CO2.

[0148] The semiconductor device SE can be easily integrated into the SoC provided by Fab by using the outputted layout data CO1 and verification data CO2.

[0149] The compiler C according to the present invention can generate layout data CO1 for integration into an SoC with a user experience similar to that of a conventional memory compiler. However, its distinguishing feature is that, unlike a simple memory compiler, it performs a two-stage compilation process: first for the layout of the SRAM 21 constituting the logical memory block 2, and then for the layout of the logical memory block 2 constituting the semiconductor device SE.

[0150] Furthermore, the compiler C according to the present invention performs various verifications in conjunction with generating layout data CO1. Another feature is that the verification data CO2 obtained at this time can be used to verify the entire integrated circuit of the SoC.

[0151] Furthermore, compiler C can also output document data CO3, which includes specification information for the semiconductor device SE that generated the layout data CO1, as part of the output data.

[0152] The above exemplifies embodiments of the semiconductor device, logic circuit construction data generation method, program, and compiler according to the present invention, but it goes without saying that these are not intended to limit the technical scope of the present invention. These novel embodiments can be realized in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the present invention. These embodiments and their variations are included in the scope and spirit of the present invention, as well as in the claims and their equivalents.

[0153] SE Semiconductor Equipment 1 Silicon Chip 2 Logical Memory Block 21 SRAM 22 Internal Wiring 3 Signal Lines 31 Vertical Signal Lines 32 Horizontal Signal Lines 4 Disconnection Switch Block 41 Vertical Disconnection Switch 42 Horizontal Disconnection Switch 43 Overhead Disconnection Switch 5 IOB 6 Junction Switch LM Method for Generating Logical Circuit Construction Data FMP Function Mapping Program FS1 Functional Design Description Process FS2 Description Statement Verification Process FS3 Diagram Generation Process FS4 Terminal Count Comparison Process FS5 Logical Function Assignment Process FS6 Logical Description Process TMP Template Mapping Program TS1 Logical Function Assignment Process TS2 External Assignment Setting Process TS3 Internal Assignment Setting Process TS4 Entity Generation Process TS5 Logical Memory Block Design Process VGP Verification and Data Generation Program VS1 Verification Data Generation Process VS2 Functional Verification Process VS3 Truth Value Calculation Process VS4 Programming Data Generation Process C Compiler C1 Input Format C2 Reference Circuit Information C3 Framework Information CI1 Fab Information CI2 Memory IP Information CI3 Semiconductor Device Information CO1 Layout Data CO11 Device Circuit Information CO12 Block Layout Information CO13 Block Circuit Information CO14 SRAM Layout Information CO2 Verification Data CO21 Functional Verification Data CO22 SRAM Layout Verification Data CO23 Connection Verification Data CO24 Block Layout Verification Data CO3 Document Data

Claims

1. A semiconductor device comprising: a plurality of logic memory blocks each having SRAM that realizes a logic function by storing a predetermined output value corresponding to an arbitrary input value; signal lines arranged in a grid pattern to connect the logic memory blocks, with the logic memory blocks arranged in a two-dimensional array; and disconnection switch blocks arranged at the intersections of the signal lines.

2. The semiconductor device according to claim 1, wherein the disconnection switch block has at least three switch mechanisms: a vertical disconnection switch provided on a vertical signal line arranged vertically among the signal lines, a horizontal disconnection switch provided on a horizontal signal line arranged horizontally, and a horizontal disconnection switch installed across the vertical signal line and the horizontal signal line.

3. The semiconductor device according to claim 1 or 2, wherein the SRAM is clock-asynchronous.

4. The semiconductor device according to claim 1 or 2, wherein the SRAM is clock-synchronous.

5. The semiconductor device according to claim 1 or 2, wherein the SRAM comprises a mixture of clock-synchronous and clock-asynchronous types.

6. The semiconductor device according to any one of claims 1 to 5, wherein the logical memory block has four SRAMs.

7. A semiconductor device according to any one of claims 1 to 6, comprising a junction switch for connecting two parallel signal lines, wherein any logic circuit can be constructed by switching the junction switch on or off.

8. A method for generating logic circuit construction data for constructing an arbitrary logic circuit in a semiconductor device having a plurality of logic memory blocks, comprising: a function design description step for designing a predetermined logic function for the semiconductor device; a diagram generation step for generating a diagram showing the grouping of the logic memory blocks for executing the logic function; a terminal number comparison step for comparing the number of input terminals required for each group with the number of input terminals on the actual logic memory block; a logic function assignment step for determining how to assign the groups to the plurality of actual logic memory blocks; a logic description step for generating logic description statements to be written to the logic memory blocks in order to realize the logic function; a verification data generation step for generating verification data for functional verification of the circuit data of the semiconductor device; a function verification step for performing functional verification based on the verification data; a truth value calculation step for calculating the truth value of each logic operation from the logic description statements; and a programming data generation step for generating programming data to be implemented on the semiconductor device in order to realize the logic function based on the truth value and the circuit data.

9. A method for generating logic circuit construction data for constructing an arbitrary logic circuit in a semiconductor device having a plurality of logic memory blocks, comprising: a logic function assignment step of determining how to assign predetermined logic functions to the actual devices of the plurality of logic memory blocks; an external assignment setting step of determining which terminals to assign external devices connected to the semiconductor device to; an internal assignment setting step of setting the assignment of terminals used for connecting the plurality of logic memory blocks to each other; an entity generation step of generating framework data relating to logic description statements to be written to each of the logic memory blocks in order to realize the logic functions; a logic memory block design step of writing the logic description statements according to the framework data; a verification data generation step of generating verification data for functional verification of the circuit data of the semiconductor device; a functional verification step of performing functional verification based on the verification data; a truth value calculation step of calculating the truth value of each logic operation from the logic description statements; and a programming data generation step of generating programming data to be implemented in the semiconductor device in order to realize the logic functions based on the truth values ​​and the circuit data.

10. A program that causes a computer to execute the following steps: a function design description step for designing a predetermined logic function for a semiconductor device; a diagram generation step for generating a diagram showing the grouping of logic memory blocks for executing the logic function; a terminal number comparison step for comparing the number of input terminals required for each group with the number of input terminals on the actual logic memory block; a logic function assignment step for determining how to assign the groups to multiple actual logic memory blocks; a logic description step for generating logic description statements to be written to the logic memory blocks in order to realize the logic function; a verification data generation step for generating verification data for functional verification of the circuit data of the semiconductor device; a function verification step for performing functional verification based on the verification data; a truth value calculation step for calculating the truth value of each logic operation from the logic description statements; and a programming data generation step for generating programming data to be implemented on the semiconductor device in order to realize the logic function based on the truth value and the circuit data.

11. A program that causes a computer to execute the following steps: a logic function assignment step of determining how to assign predetermined logic functions to multiple actual logic memory blocks; an external assignment setting step of determining which terminals to assign external devices connected to the semiconductor device to; an internal assignment setting step of setting the assignment of terminals used for connecting multiple logic memory blocks to each other; an entity generation step of generating framework data for logic description statements to be written to each of the logic memory blocks in order to realize the logic functions; a logic memory block design step of writing the logic description statements according to the framework data; a verification data generation step of generating verification data for functional verification of the circuit data of the semiconductor device; a functional verification step of performing functional verification based on the verification data; a truth value calculation step of calculating the truth value of each logic operation from the logic description statements; and a programming data generation step of generating programming data to be implemented in the semiconductor device in order to realize the logic functions based on the truth value and the circuit data.

12. A compiler capable of generating layout data for incorporating a semiconductor device having multiple logic memory blocks consisting of multiple SRAMs into an SoC, the compiler automatically compiles based on predetermined input information and outputs layout data including design information for the logic memory blocks and design information for the semiconductor device.

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