Data receiving circuit and memory

Abstract

A data receiving circuit, comprising: an amplifier circuit (80), which receives input data and an initial reference voltage, amplifies a voltage difference between same, and outputs double-ended signals; a first adjustment circuit (20), which receives and amplifies a voltage difference between the double-ended signals, when a signal at a first clock terminal or a second clock terminal is in an active state, on the basis of signals at a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal, adjusts an amplified result to perform decision feedback equalization, and outputs first double-ended adjusted signals; and a first sampling circuit (30) and a second sampling circuit (40), which both receive the first double-ended adjusted signals, and when a signal at a clock terminal is in an active state, on the basis of a signal at a control terminal, amplify and latch a voltage difference between the first double-ended adjusted signals, and respectively generate a first output signal and a third output signal. The first adjustment circuit (20) receives a fourth clock signal and a second clock signal, the first sampling circuit (30) receives a first clock signal, and the second sampling circuit (40) receives a third clock signal. The present invention reduces the number of adjustment circuits, and reduces the circuit area and lowers circuit power consumption while reducing inter-symbol interference of signals.

Description

Data receiving circuit and memory

[0001] This application claims priority to Chinese Patent Application No. 202510007734.0, filed on January 2, 2025, entitled “Data Receiving Circuit and Memory”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor circuit design, and in particular to a data receiving circuit and a memory. Background Technology

[0003] As signal transmission rates increase and clock frequencies rise, channel loss has a greater impact on the quality of input data signals, making memory signals more susceptible to inter-symbol interference (ISI) during transmission.

[0004] Intersymbol interference (ISI) refers to the phenomenon where previously transmitted input data affects currently transmitted input data due to channel bandwidth limitations. Currently, equalization circuits are typically used to compensate for input data and reduce the adverse effects of ISI. These equalization circuits can be either CTLE (Continuous Time Linear Equalizer) or DFE (Decision Feedback Equalizer). However, current circuit designs for mitigating ISI in memory devices occupy a significant amount of chip area and consume considerable power. Summary of the Invention

[0005] This disclosure provides a data receiving circuit and a memory, which at least helps to improve the inter-symbol interference problem while reducing the circuit area and power consumption.

[0006] In a first aspect, one embodiment of this disclosure provides a data receiving circuit, the data receiving circuit comprising:

[0007] An amplifier circuit receives input data and an initial reference voltage, and is configured to amplify the voltage difference between the input data and the initial reference voltage, and output a two-terminal signal.

[0008] The first adjustment circuit receives the dual-ended signal and is configured to amplify the voltage difference between the dual-ended signals. When the signal at the first clock terminal or the second clock terminal is in an active state, the circuit adjusts the amplification based on the signals at the first control terminal, the second control terminal, the third control terminal, and the fourth control terminal to perform decision feedback equalization and output the first dual-ended adjustment signal.

[0009] The first sampling circuit receives the first dual-ended adjustment signal and is configured to, when the signal received at the clock terminal is in an active state, amplify and latch the voltage difference of the first dual-ended adjustment signal based on the signal at the control terminal to generate a first output signal.

[0010] The second sampling circuit receives the first dual-ended adjustment signal and is configured to, when the signal received at the clock end is in an active state, amplify and latch the voltage difference of the first dual-ended adjustment signal based on the signal at the control end to generate a third output signal.

[0011] In this circuit, the first clock terminal of the first adjustment circuit receives the fourth clock signal, the second clock terminal receives the second clock signal, the clock terminal of the first sampling circuit receives the first clock signal, and the clock terminal of the second sampling circuit receives the third clock signal. The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially 90 degrees out of phase.

[0012] In some embodiments, when the signal at the first clock terminal of the first adjustment circuit is in an active state, the signal at the first control terminal responds to the first tap coefficient, the signal at the second control terminal responds to the second tap coefficient, the signal at the third control terminal responds to the third tap coefficient, and the signal at the fourth control terminal responds to the fourth tap coefficient, performing decision feedback equalization; when the signal at the second clock terminal of the first adjustment circuit is in an active state, the signal at the first control terminal responds to the third tap coefficient, the signal at the second control terminal responds to the fourth tap coefficient, the signal at the third control terminal responds to the first tap coefficient, and the signal at the fourth control terminal responds to the second tap coefficient, performing decision feedback equalization.

[0013] In some embodiments, the data receiving circuit further includes:

[0014] The second adjustment circuit receives the dual-ended signal and is configured to amplify the voltage difference between the dual-ended signals. When the signal at the first clock terminal or the second clock terminal is in an active state, the circuit adjusts the amplification result based on the signals at the first control terminal, the second control terminal, the third control terminal, and the fourth control terminal to perform decision feedback equalization and output a second dual-ended adjustment signal.

[0015] The third sampling circuit receives the second double-ended adjustment signal and is configured to, when the signal received at the clock terminal is in an active state, amplify and latch the voltage difference of the second double-ended adjustment signal based on the signal at the control terminal to generate a second output signal.

[0016] The fourth sampling circuit receives the second double-ended adjustment signal and is configured to, when the signal received at the clock terminal is in an active state, amplify and latch the voltage difference of the second double-ended adjustment signal based on the signal at the control terminal to generate a fourth output signal.

[0017] In this circuit, the first clock terminal of the second adjustment circuit receives a first clock signal, the second clock terminal receives a third clock signal, the clock terminal of the third sampling circuit receives the second clock signal, and the clock terminal of the fourth sampling circuit receives the fourth clock signal.

[0018] In some embodiments, the first control terminal of the first adjustment circuit receives a fourth feedback signal, the second control terminal receives a third feedback signal, the third control terminal receives a second feedback signal, and the fourth control terminal receives a first feedback signal; the first control terminal of the second adjustment circuit receives the first feedback signal, the second control terminal receives the fourth feedback signal, the third control terminal receives the third feedback signal, and the fourth control terminal receives the second feedback signal; the control terminal of the first sampling circuit receives the fourth feedback signal; the control terminal of the second sampling circuit receives the second feedback signal; the control terminal of the third sampling circuit receives the first feedback signal; and the control terminal of the fourth sampling circuit receives the third feedback signal; wherein the first feedback signal originates from the first output signal, the second feedback signal originates from the second output signal, the third feedback signal originates from the third output signal, and the fourth feedback signal originates from the fourth output signal.

[0019] In some embodiments, the first adjustment circuit and the second adjustment circuit have the same structure.

[0020] In some embodiments, the first adjustment circuit includes:

[0021] The first amplification module receives the dual-ended signal and is configured to amplify the voltage difference between the dual-ended signals, output a first adjustment sub-signal at a first node, and output a second adjustment sub-signal at a second node. The first dual-ended adjustment signal includes the first adjustment sub-signal and the second adjustment signal.

[0022] The first decision feedback equalization module, electrically connected to the first node and the second node, is configured to adjust the voltage difference between the first node and the second node by responding to the first tap coefficient when the signal at the first clock terminal of the first adjustment circuit is in an active state, or by responding to the third tap coefficient when the signal at the second clock terminal of the first adjustment circuit is in an active state.

[0023] The second decision feedback equalization module, electrically connected to the first node and the second node, is configured to adjust the voltage difference between the first node and the second node by responding to the second tap coefficient when the signal at the first clock terminal of the first adjustment circuit is in an active state, or by responding to the fourth tap coefficient when the signal at the second clock terminal of the first adjustment circuit is in an active state.

[0024] The third decision feedback equalization module, electrically connected to the first node and the second node, is configured to adjust the voltage difference between the first node and the second node by responding to the third tap coefficient when the signal at the first clock terminal of the first adjustment circuit is in an active state, or by responding to the first tap coefficient when the signal at the second clock terminal of the first adjustment circuit is in an active state.

[0025] The fourth decision feedback equalization module, electrically connected to the first node and the second node, is configured to adjust the voltage difference between the first node and the second node by responding to the fourth tap coefficient when the signal at the first clock terminal of the first adjustment circuit is in an active state, or by responding to the second tap coefficient when the signal at the second clock terminal of the first adjustment circuit is in an active state.

[0026] In some embodiments, the first decision feedback equalization module includes:

[0027] The first selection unit is configured such that a first input terminal receives a signal from a first control terminal of the first adjustment circuit, a second input terminal receives a signal that is inversely related to the signal from the first input terminal, a control terminal receives an equalization direction control signal, and in response to the equalization direction control signal, a first output terminal outputs the signal from the first input terminal, and a second output terminal outputs the signal from the second input terminal, or a first output terminal outputs the signal from the second input terminal, and a second output terminal outputs the signal from the first input terminal.

[0028] The first MOSFET has its first terminal connected to the first variable current source and its control terminal connected to the first clock terminal of the first adjustment circuit.

[0029] The second MOSFET has its first terminal connected to the second variable current source and its control terminal connected to the second clock terminal of the first adjustment circuit.

[0030] The third MOSFET has its first end connected to the second end of the first MOSFET, its second end connected to the first node, and its control end connected to the first output terminal of the first selection unit.

[0031] The fourth MOSFET has its first terminal connected to the second terminal of the second MOSFET, its second terminal connected to the second node, and its control terminal connected to the second output terminal of the first selection unit.

[0032] The current value of the first variable current source responds to the first tap coefficient, and the current value of the second variable current source responds to the third tap coefficient.

[0033] In some embodiments, the second decision feedback equalization module includes:

[0034] The second selection unit is configured such that a first input terminal receives a signal from a second control terminal of the first adjustment circuit, the signal received at the second input terminal is inversely phase to the signal at the first input terminal, the control terminal receives an equalization direction control signal, and in response to the equalization direction control signal, a first output terminal outputs the signal at the first input terminal, and a second output terminal outputs the signal at the second input terminal, or a first output terminal outputs the signal at the second input terminal, and a second output terminal outputs the signal at the first input terminal.

[0035] The fifth MOSFET has its first terminal connected to the third variable current source and its control terminal connected to the first clock terminal of the first adjustment circuit.

[0036] The sixth MOSFET has its first terminal connected to the fourth variable current source and its control terminal connected to the second clock terminal of the first adjustment circuit.

[0037] The seventh MOSFET has its first terminal connected to the second terminal of the fifth MOSFET, its second terminal connected to the first node, and its control terminal connected to the first output terminal of the second selection unit.

[0038] The eighth MOSFET has its first terminal connected to the second terminal of the sixth MOSFET, its second terminal connected to the second node, and its control terminal connected to the second output terminal of the second selection unit.

[0039] The current value of the third variable current source responds to the second tap coefficient, and the current value of the fourth variable current source responds to the fourth tap coefficient.

[0040] The third decision feedback equalization module includes:

[0041] The third selection unit is configured such that a first input terminal receives a signal from the third control terminal of the first adjustment circuit, a second input terminal receives a signal that is inverted from the signal at the first input terminal, a control terminal receives an equalization direction control signal, and in response to the equalization direction control signal, a first output terminal outputs the signal at the first input terminal, and a second output terminal outputs the signal at the second input terminal, or a first output terminal outputs the signal at the second input terminal, and a second output terminal outputs the signal at the first input terminal.

[0042] The ninth MOSFET has its first terminal connected to the fifth variable current source and its control terminal connected to the first clock terminal of the first adjustment circuit.

[0043] The tenth MOSFET has its first terminal connected to the sixth variable current source and its control terminal connected to the second clock terminal of the first adjustment circuit.

[0044] The eleventh MOSFET has its first terminal connected to the second terminal of the ninth MOSFET, its second terminal connected to the first node, and its control terminal connected to the first output terminal of the third selection unit.

[0045] The twelfth MOSFET has its first terminal connected to the second terminal of the tenth MOSFET, its second terminal connected to the second node, and its control terminal connected to the second output terminal of the third selection unit.

[0046] The current value of the fifth variable current source responds to the third tap coefficient, and the current value of the sixth variable current source responds to the first tap coefficient.

[0047] The fourth decision feedback equalization module includes:

[0048] The fourth selection unit is configured such that a first input terminal receives a signal from the fourth control terminal of the first adjustment circuit, a second input terminal receives a signal that is inverted from the signal at the first input terminal, a control terminal receives an equalization direction control signal, and in response to the equalization direction control signal, a first output terminal outputs the signal at the first input terminal, and a second output terminal outputs the signal at the second input terminal, or a first output terminal outputs the signal at the second input terminal, and a second output terminal outputs the signal at the first input terminal.

[0049] The thirteenth MOSFET has its first terminal connected to the seventh variable current source and its control terminal connected to the first clock terminal of the first adjustment circuit.

[0050] The fourteenth MOSFET has its first terminal connected to the eighth variable current source and its control terminal connected to the second clock terminal of the first adjustment circuit.

[0051] The fifteenth MOSFET has its first terminal connected to the second terminal of the thirteenth MOSFET, its second terminal connected to the first node, and its control terminal connected to the first output terminal of the fourth selection unit.

[0052] The sixteenth MOSFET has its first terminal connected to the second terminal of the fourteenth MOSFET, its second terminal connected to the second node, and its control terminal connected to the second output terminal of the fourth selection unit.

[0053] The current value of the seventh variable current source responds to the fourth tap coefficient, and the current value of the eighth variable current source responds to the second tap coefficient.

[0054] In some embodiments, the first adjustment circuit further includes a first negative capacitor equalizer, which is electrically connected to the first node and the second node to increase the gain of the first adjustment circuit.

[0055] In some embodiments, the first sampling circuit further receives a first reference voltage and a second reference voltage, wherein the voltage value of the first reference voltage is greater than the voltage value of the second reference voltage;

[0056] The step of amplifying and latching the voltage difference of the first dual-terminal adjustment signal based on the signal from the control terminal to generate the first output signal includes: based on the signal from the control terminal, selecting to increase or decrease the voltage difference between the first dual-terminal adjustment signal by equivalently increasing or decreasing the voltage difference between the first reference voltage and the second reference voltage, amplifying and latching the voltage difference of the first dual-terminal adjustment signal to generate the first output signal.

[0057] In some embodiments, the first dual-ended adjustment signal includes a first adjustment sub-signal and a second adjustment sub-signal; the first sampling circuit includes:

[0058] The selection adjustment circuit is configured to, when the signal at the clock terminal is active, select, based on the signal at the control terminal, to adjust the branch current of the branch where the first adjustment sub-signal is located by the first reference voltage, and to adjust the branch current of the branch where the second adjustment sub-signal is located by the second reference voltage.

[0059] Alternatively, the branch current of the branch containing the second adjustment sub-signal can be adjusted by the first reference voltage, and the branch current of the branch containing the first adjustment sub-signal can be adjusted by the second reference voltage.

[0060] A latching circuit, electrically connected to the selection adjustment circuit, is configured to amplify and latch the voltage difference of the first dual-ended adjustment signal to generate the first output signal.

[0061] In some embodiments, the selection adjustment circuit includes:

[0062] The first NMOS transistor has a control terminal for receiving the first adjustment sub-signal and a first terminal connected to the latch circuit.

[0063] The second NMOS transistor has a control terminal for receiving the second adjustment sub-signal, a first terminal connected to the latch circuit, and a second terminal connected to the second terminal of the first NMOS transistor.

[0064] The first switching NMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal electrically connected to the second terminal of the first NMOS transistor, and its second terminal grounded.

[0065] The first adjustment NMOS transistor has a control terminal used to receive the first reference voltage, and its first terminal is connected to the first terminal of the second NMOS transistor.

[0066] The second adjustment NMOS transistor has a control terminal for receiving the second reference voltage, a first terminal connected to the first terminal of the first NMOS transistor, and a second terminal connected to the second terminal of the first adjustment NMOS transistor.

[0067] The second switching NMOS transistor has its control terminal connected to the control terminal of the first sampling circuit, and its first terminal connected to the second terminal of the second adjustment NMOS transistor.

[0068] The third switching NMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal connected to the second terminal of the second switching NMOS transistor, and its second terminal grounded.

[0069] The third adjustment NMOS transistor has a control terminal used to receive the second reference voltage, and its first terminal is connected to the first terminal of the second NMOS transistor.

[0070] The fourth adjusting NMOS transistor has a control terminal for receiving the first reference voltage, a first terminal connected to the first terminal of the first NMOS transistor, and a second terminal connected to the second terminal of the third adjusting NMOS transistor.

[0071] The fourth switching NMOS transistor has a control terminal used to receive the inverted signal of the control terminal signal of the first sampling circuit, and its first terminal is connected to the second terminal of the fourth adjustment NMOS transistor.

[0072] The fifth NMOS switch has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal connected to the second terminal of the fourth NMOS switch, and its second terminal grounded.

[0073] In some embodiments, the latching circuit includes:

[0074] The first PMOS transistor has its first terminal used to receive the power supply voltage.

[0075] The second PMOS transistor has its first terminal used to receive the power supply voltage.

[0076] The third NMOS transistor has its control terminal connected to the control terminal of the first PMOS transistor, its first terminal connected to the second terminal of the first PMOS transistor, and its second terminal connected to the first terminal of the first NMOS transistor.

[0077] The fourth NMOS transistor has its control terminal connected to the control terminal of the second PMOS transistor, its first terminal connected to the second terminal of the second PMOS transistor, and its second terminal connected to the first terminal of the second NMOS transistor.

[0078] The control terminal of the third NMOS transistor is also connected to the first terminal of the fourth NMOS transistor to serve as the first output terminal of the latch circuit, and the control terminal of the fourth NMOS transistor is also connected to the first terminal of the third NMOS transistor to serve as the second output terminal of the latch circuit.

[0079] In some embodiments, the first sampling circuit further includes a reset circuit connected to the clock terminal of the first sampling circuit and the latch circuit, for resetting the first output terminal and the second output terminal of the latch circuit in response to the clock terminal signal of the first sampling circuit.

[0080] In some embodiments, the reset circuit includes:

[0081] The first reset PMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal used to receive the power supply voltage, and its second terminal connected to the first output terminal of the latch circuit.

[0082] The second reset PMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal used to receive the power supply voltage, and its second terminal connected to the second output terminal of the latch circuit.

[0083] In some embodiments, the reset circuit further includes:

[0084] The third reset PMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal used to receive the power supply voltage, and its second terminal connected to the second terminal of the third NMOS transistor.

[0085] The fourth reset PMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal used to receive the power supply voltage, and its second terminal connected to the second terminal of the fourth NMOS transistor.

[0086] In some embodiments, the reset circuit further includes:

[0087] The fifth reset PMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its second terminal connected to the first output terminal of the latch circuit, and its third terminal connected to the second output terminal of the latch circuit.

[0088] In some embodiments, the first sampling circuit, the second sampling circuit, the third sampling circuit, and the fourth sampling circuit have the same structure.

[0089] In some embodiments, the amplification circuit includes:

[0090] A continuous-time linear equalizer, receiving the input data and the initial reference voltage, is configured to amplify the voltage difference between the input data and the initial reference voltage in the first stage.

[0091] The second negative capacitor equalizer, electrically connected to the continuous-time linear equalizer, is configured to amplify the voltage difference between the input data and the initial reference voltage in a second stage, and output the dual-ended signal.

[0092] In a second aspect, embodiments of this disclosure provide a memory that includes the data receiving circuitry described in the first aspect.

[0093] This disclosure provides a data receiving circuit and a memory. The data receiving circuit includes: an amplification circuit, configured to receive input data and an initial reference voltage, amplify the voltage difference between the input data and the initial reference voltage, and output a dual-ended signal; a first adjustment circuit, configured to receive the dual-ended signal, amplify the voltage difference between the dual-ended signal, and, when the signal at a first clock terminal or a second clock terminal is active, adjust the amplification result based on the signals at a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal to perform decision feedback equalization and output a first dual-ended adjustment signal; and a first sampling circuit, configured to receive the first dual-ended adjustment signal, and, when the signal received at the clock terminal is active, adjust the amplification result based on the signals at a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal to perform decision feedback equalization and output a first dual-ended adjustment signal; and a first sampling circuit, configured to ... at the clock terminal is active, adjust the amplification result based on the signals at a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal to perform decision feedback equalization and output a first dual-ended adjustment signal; and a first sampling circuit, configured to, when the signal at the clock terminal is active, adjust the amplification result based on the signals at a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal to perform decision feedback equalization and output a first dual-ended adjustment signal. In the active state, based on the signal from the control terminal, the voltage difference of the first dual-ended adjustment signal is amplified and latched to generate a first output signal. The second sampling circuit receives the first dual-ended adjustment signal and is configured to, when the signal received at the clock terminal is active, amplify and latch the voltage difference of the first dual-ended adjustment signal based on the signal from the control terminal to generate a third output signal. The first clock terminal of the first adjustment circuit receives a fourth clock signal, the second clock terminal receives a second clock signal, the clock terminal of the first sampling circuit receives the first clock signal, and the clock terminal of the second sampling circuit receives the third clock signal. The phases of the first, second, third, and fourth clock signals differ by 90 degrees sequentially. Thus, the first adjustment circuit corresponds to the first and second sampling circuits; that is, one adjustment circuit corresponds to two sampling circuits. By multiplexing the DFE, the number of adjustment circuits is reduced, thereby improving the inter-symbol interference problem while reducing the circuit area and power consumption. Attached Figure Description

[0094] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0095] Figure 1 is a schematic diagram of a data receiving circuit;

[0096] Figure 2 is a schematic diagram of the structure of a data receiving circuit provided in an embodiment of the present disclosure;

[0097] Figure 3 is a schematic diagram of the structure of a data receiving circuit provided in another embodiment of this disclosure;

[0098] Figure 4 is a signal waveform diagram of a data receiving circuit provided in an embodiment of the present disclosure;

[0099] Figure 5 is a schematic diagram of the structure of a first adjustment circuit provided in an embodiment of the present disclosure;

[0100] Figure 6a is a schematic diagram of the structure of the first decision feedback equalization module of the first adjustment circuit provided in an embodiment of the present disclosure;

[0101] Figure 6b is a schematic diagram of the structure of the second decision feedback equalization module of the first adjustment circuit provided in an embodiment of the present disclosure;

[0102] Figure 6c is a schematic diagram of the structure of the third decision feedback equalization module of the first adjustment circuit provided in an embodiment of the present disclosure;

[0103] Figure 6d is a schematic diagram of the structure of the fourth decision feedback equalization module of the first adjustment circuit provided in an embodiment of the present disclosure;

[0104] Figure 7a is a schematic diagram of the structure of the first decision feedback equalization module of the second adjustment circuit provided in an embodiment of the present disclosure;

[0105] Figure 7b is a schematic diagram of the structure of the second decision feedback equalization module of the second adjustment circuit provided in an embodiment of the present disclosure;

[0106] Figure 7c is a schematic diagram of the structure of the third decision feedback equalization module of the second adjustment circuit provided in an embodiment of the present disclosure;

[0107] Figure 7d is a schematic diagram of the structure of the fourth decision feedback equalization module of the second adjustment circuit provided in an embodiment of the present disclosure;

[0108] Figure 8 is a schematic diagram of the structure of a first adjustment circuit provided in yet another embodiment of this disclosure;

[0109] Figure 9 is a schematic diagram of the structure of a first negative capacitor equalizer provided in an embodiment of the present disclosure;

[0110] Figure 10 is a schematic diagram of the structure of a data receiving circuit provided in another embodiment of the present disclosure;

[0111] Figure 11 is a schematic diagram of the structure of a first sampling circuit provided in an embodiment of the present disclosure;

[0112] Figure 12 is a schematic diagram of the amplifier circuit provided in an embodiment of the present disclosure;

[0113] Figure 13 is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure. Embodiments of the present invention

[0114] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant applications and not for limiting the applications. It should also be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0115] Dynamic Random Access Memory (DRAM)

[0116] Synchronous Dynamic Random Access Memory (SDRAM)

[0117] Double Data Rate SDRAM (DDR)

[0118] Low-power DDR (LPDDR)

[0119] The nth generation DDR standard (DDRn Specification, DDRn), such as DDR3, DDR4, DDR5, DDR6.

[0120] The nth generation LPDDR standard (LPDDRn Specification, LPDDRn), such as LPDDR3, LPDDR4, LPDDR5, LPDDR6

[0121] Decision Feedback Equalizer (DFE)

[0122] Continuous-Time Linear Equalizer (CTLE)

[0123] Inter-symbol interference (ISI)

[0124] Variable Gain Amplifier (VGA)

[0125] Negative Capacitor Equalizer (NCE)

[0126] The data receiving circuit can be applied to a memory, which can be either DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). In some embodiments, the data receiving circuit can be applied to SDRAM (Synchronous Dynamic Random Access Memory), which can be DDR (Double Data Rate) SDRAM, such as DDR4, DDR5, DDR6, LPDDR4, LPDDR5, or LPDDR6 memory.

[0127] Currently, memory suffers from inter-symbol interference (ISI) during input data signal reception, affecting the quality of the received signal. To address ISI, decision feedback equalization circuits are commonly used to process the input data signal and improve signal transmission quality.

[0128] Depending on the number of bits in the input data participating in the decision feedback equalization in the previously transmitted input data, the decision feedback equalization circuit in the data receiving circuit can be divided into 1-tap, 2-tap, 3-tap, and 4-tap equalization circuits. In practical applications, the decision feedback equalization circuit can even have more taps (i.e., the number of taps can be greater than 4), where tap refers to a click. It can be understood that the decision feedback equalization circuit can include multiple tap adjustment circuits, each corresponding to a tap signal. Each tap signal corresponds to one bit of previously transmitted input data, adjusting the currently transmitted input data according to the tap signal. Specifically, the 1-tap equalization circuit adjusts the current input data based on the first 1 bit of previously transmitted input data, the 2-tap equalization circuit adjusts the current input data based on the first 2 bits of previously transmitted input data, and so on, with the n-tap equalization circuit adjusting the current input data based on the first n bits of previously transmitted input data.

[0129] Since DDR5 commonly uses a four-phase clock for data transmission, this embodiment uses a 4-tap equalization circuit as an example to illustrate the data receiving circuit provided in this embodiment. This does not constitute a limitation on this embodiment. In other embodiments, the 4-tap equalization circuit can be extended to an n-tap equalization circuit.

[0130] For the four-phase clock signals, the clock signals are CLK-0, CLK-90, CLK-180, and CLK-270. Clock signal CLK-0 is used to sample and acquire input data DQ-0. The previously transmitted input data for DQ-0 are: DQ-270, DQ-180, DQ-90, DQ-0, DQ-270… Clock signal CLK-90 is used to sample and acquire input data DQ-90. The previously transmitted input data for DQ-90 are: DQ-0, DQ-270… Clock signal CLK-180, DQ-180, DQ-90, DQ-0... is used to sample and acquire input data DQ-180. The previously transmitted input data of DQ-180 are: DQ-90, DQ-0, DQ-270, DQ-180, DQ-90... Clock signal CLK-270 is used to sample and acquire input data DQ-270. The previously transmitted input data of DQ-270 are: DQ-180, DQ-90, DQ-0, DQ-270, DQ-180...

[0131] In some embodiments, referring to FIG1, the data receiving circuit includes a comparison circuit 101 and four data paths 201. The four data paths 201 are respectively used to sample the input data DQ to obtain DQ-0, DQ-90, DQ-180 and DQ-270 (the phase difference between DQ-0 and DQ-90 is 90°, the phase difference between DQ-90 and DQ-180 is 90°, the phase difference between DQ-180 and DQ-270 is 90°, and the phase difference between DQ-270 and DQ-0 is 90°). The following description uses the data path for obtaining DQ-0 as an example for illustration. Those skilled in the art can replace the corresponding signals to obtain other data paths. The specific implementation methods will not be repeated in this embodiment.

[0132] Specifically, the comparator circuit 101 receives input data DQ and reference voltages Vref_ADD / Vref_SUB from an external source. The voltage value of Vref_ADD is greater than the voltage value of Vref_SUB. The comparator circuit amplifies the voltage difference between the input data DQ and the reference voltages Vref_ADD / Vref_SUB to generate a two-terminal signal SS1 / SS2. The two-terminal signal SS1 / SS2 is input to the data path 201, which includes an adjustment circuit 2011 and a sampling circuit 2012. The adjustment circuit 2011 is used to fine-tune the dual-ended signals SS1 / SS2 according to the previously transmitted 2nd, 3rd and 4th bits of data to output dual-ended adjusted data SS3 / SS4. The sampling circuit 2012 samples the dual-ended adjusted data SS3 / SS4 based on the clock signal CLK-0 to generate alternative data DQ-0-ADD / DQ-0-SUB. Then, the selector 301 selects alternative data DQ-0-ADD or alternative data DQ-0-SUB based on the previously transmitted 1st bit data DQ-270 to obtain DQ-0.

[0133] More specifically, alternative data DQ-0-ADD is generated based on reference voltage Vref-ADD, alternative data DQ-0-SUB is generated based on reference voltage Vref-SUB, and selector 301 selects different alternative data DQ-0-ADD / DQ-0-SUB based on the previous first bit data DQ-270 to obtain input data DQ-0, that is, selects the sampling result based on reference voltage Vref-ADD or reference voltage Vref-SUB.

[0134] For the data receiving circuit in the example of Figure 1, the data receiving circuit adjusts the current input data based on the feedback of the previous multi-bit input data, which reduces the impact of ISI on the current input data. However, there are many repetitive circuits and the circuit area is large. In practical applications, it may occupy a large memory layout, which may affect the storage capacity of the memory. In addition, the power consumption of the circuit is also large.

[0135] Based on this, this disclosure provides a data receiving circuit, comprising: an amplification circuit, configured to receive input data and an initial reference voltage, amplify the voltage difference between the input data and the initial reference voltage, and output a dual-ended signal; a first adjustment circuit, configured to receive the dual-ended signal, amplify the voltage difference between the dual-ended signal, and, when the signal at a first clock terminal or a second clock terminal is valid, adjust the amplification result based on the signals at a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal to perform decision feedback equalization, and output a first dual-ended adjustment signal; and a first sampling circuit, configured to receive the first dual-ended adjustment signal, and, when the signal received at the clock terminal is valid, adjust the amplification result based on the signals at a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal to perform decision feedback equalization, and output a first dual-ended adjustment signal; and a first sampling circuit, configured to ... at the clock terminal is valid, adjust the amplification result based on the signals at a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal to perform decision feedback equalization, and output a first dual-ended adjustment signal; and a first sampling circuit, configured to, when the signal at the clock terminal is valid, adjust the amplification result based on the signals at a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal to perform decision feedback equalization, and output a first dual-ended adjustment signal; and a first sampling circuit, configured to, when the signal at the clock terminal is valid, adjust the amplification result based on the signals at a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal to perform decision feedback equalization, and output a first dual-ended adjustment signal. In the active state, based on the signal from the control terminal, the voltage difference of the first dual-ended adjustment signal is amplified and latched to generate a first output signal. The second sampling circuit receives the first dual-ended adjustment signal and is configured to, when the signal received at the clock terminal is active, amplify and latch the voltage difference of the first dual-ended adjustment signal based on the signal from the control terminal to generate a third output signal. The first clock terminal of the first adjustment circuit receives a fourth clock signal, the second clock terminal receives a second clock signal, the clock terminal of the first sampling circuit receives the first clock signal, and the clock terminal of the second sampling circuit receives the third clock signal. The phases of the first, second, third, and fourth clock signals differ by 90 degrees sequentially. Thus, the first adjustment circuit corresponds to the first and second sampling circuits; that is, one adjustment circuit corresponds to two sampling circuits. By multiplexing the DFE, the number of adjustment circuits is reduced, thereby improving the inter-symbol interference problem while reducing the circuit area and power consumption.

[0136] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0137] In one embodiment of this disclosure, referring to FIG2, a schematic diagram of the composition structure of a data receiving circuit 10 provided in this embodiment is shown. As shown in FIG2, the data receiving circuit 10 includes:

[0138] Amplifier circuit 80 receives input data DQ and initial reference voltage Vref, and is configured to amplify the voltage difference between input data DQ and initial reference voltage Vref, and output two-terminal signals SS1 / SS2.

[0139] The first adjustment circuit 20 receives the dual-ended signal SS1 / SS2 and is configured to amplify the voltage difference between the dual-ended signals SS1 / SS2. When the signal at the first clock terminal or the second clock terminal is in an active state, the circuit adjusts the amplification result based on the signals of the first control terminal FB1, the second control terminal FB2, the third control terminal FB3 and the fourth control terminal FB4 to perform decision feedback equalization and output the first dual-ended adjustment signal SS3 / SS4.

[0140] The first sampling circuit 30 receives the first dual-ended adjustment signals SS3 / SS4 and is configured to, when the signal received at the clock terminal is in an active state, amplify and latch the voltage difference of the first dual-ended adjustment signals SS3 / SS4 based on the signal at the control terminal to generate the first output signal DQ_I.

[0141] The second sampling circuit 40 receives the first dual-ended adjustment signal SS3 / SS4 and is configured to, when the signal received at the clock end is in an active state, amplify and latch the voltage difference of the first dual-ended adjustment signal SS3 / SS4 based on the signal at the control end to generate the third output signal DQ_IB.

[0142] In this circuit, the first clock terminal of the first adjustment circuit 20 receives the fourth clock signal DQS_QB, the second clock terminal receives the second clock signal DQS_Q, the clock terminal of the first sampling circuit 30 receives the first clock signal DQS_I, and the clock terminal of the second sampling circuit 40 receives the third clock signal DQS_IB. The phases of the first clock signal DQS_I, the second clock signal DQS_Q, the third clock signal DQS_IB, and the fourth clock signal DQS_QB are 90 degrees apart.

[0143] It is understood that the phases of the first clock signal DQS_I, the second clock signal DQS_Q, the third clock signal DQS_IB, and the fourth clock signal DQS_QB are successively 90 degrees apart; that is, the phase difference between DQS_I and DQS_Q is 90 degrees, the phase difference between DQS_Q and DQS_IB is 90 degrees, the phase difference between DQS_IB and DQS_QB is 90 degrees, and the phase difference between DQS_QB and DQS_I is 90 degrees. Furthermore, DQS_I and DQS_IB are out of phase, and DQS_Q and DQS_QB are out of phase. It should be understood that the limitations on phase differences in this disclosure allow for a certain degree of error. Subsequent limitations regarding phase values, signal edge alignment, or identical signal waveforms all refer to the range of permissible errors.

[0144] Amplifier circuit 80 receives input data DQ and amplifies the voltage difference between input data DQ and the initial reference voltage Vref in the first stage to obtain the dual-ended signal SS1 / SS2. First adjustment circuit 20 amplifies the dual-ended signal SS1 / SS2 in the second stage, and simultaneously receives the first 4 bits of the current input data through first control terminal FB1, second control terminal FB2, third control terminal FB3, and fourth control terminal FB4. Based on the first 4 bits, it performs decision feedback equalization on the current input data to generate the first dual-ended adjusted signal SS3 / SS4. Here, first adjustment circuit 20 is equivalent to a 4-tap equalization circuit. The control terminal of first sampling circuit 30 receives the first bit of the current input data. When DQS_I is valid, it amplifies and latches the voltage difference of the first dual-ended adjusted signal SS3 / SS4 based on the first bit, generating the first output signal DQ_I. The control terminal of the second sampling circuit 40 receives the first bit of the current input data. When DQS_IB is valid, it amplifies and latches the voltage difference between the first dual-ended adjustment signals SS3 / SS4 based on the first bit of data, generating the third output signal DQ_IB. While sampling the current data, the first sampling circuit 30 and the second sampling circuit 40 also utilize the first bit of data to perform decision feedback equalization on the current input data, effectively including a 1-tap equalization circuit. Here, the first adjustment circuit 20 corresponds to the first sampling circuit 30 and the second sampling circuit 40; that is, one adjustment circuit corresponds to two sampling circuits. By multiplexing the DFE, the number of adjustment circuits is reduced. Simultaneously, due to the reduction in the number of adjustment circuits, the amplifier circuit used to drive the adjustment circuit in the previous stage can also be reduced to one, thereby improving the inter-symbol interference problem while significantly reducing the circuit area and power consumption.

[0145] In some embodiments, when the signal DQS_QB at the first clock terminal is active, the first control terminal FB1 responds to the first tap coefficient, the second control terminal FB2 responds to the second tap coefficient, the third control terminal FB3 responds to the third tap coefficient, and the fourth control terminal FB4 responds to the fourth tap coefficient, performing decision feedback equalization; when the signal DQS_Q at the second clock terminal is active, the first control terminal FB1 responds to the third tap coefficient, the second control terminal FB2 responds to the fourth tap coefficient, the third control terminal FB3 responds to the first tap coefficient, and the fourth control terminal FB4 responds to the second tap coefficient, performing decision feedback equalization.

[0146] When the first adjustment circuit 20 is active at the first clock signal DQS_QB, the first control terminal FB1 responds to the first tap coefficient, the second control terminal FB2 responds to the second tap coefficient, the third control terminal FB3 responds to the third tap coefficient, and the fourth control terminal FB4 responds to the fourth tap coefficient. That is, the signal of FB1 is used as feedback for the first tap (tap1) of the DFE, the signal of FB2 is used as feedback for the second tap (tap2) of the DFE, the signal of FB3 is used as feedback for the third tap (tap3) of the DFE, and the signal of FB4 is used as feedback for the fourth tap (tap4) of the DFE, thus performing decision feedback equalization. When the first adjustment circuit 20 is active at the second clock signal DQS_Q, the signal of FB1 is used as feedback for tap3 of the DFE, the signal of FB2 is used as feedback for tap4 of the DFE, the signal of FB3 is used as feedback for tap1 of the DFE, and the signal of FB4 is used as feedback for tap2 of the DFE, thus performing decision feedback equalization. Because the signals DQS_QB at the first clock terminal and DQS_Q at the second clock terminal are inversely related, when DQS_QB is active, DQS_Q is inactive, and vice versa. With this configuration, the first adjustment circuit 20 can perform two types of decision feedback equalization under the control of the signals DQS_QB at the first clock terminal and DQS_Q at the second clock terminal. Since only one of DQS_QB and DQS_Q is active at any given time, the two decision feedback equalizations are performed independently and in a time-division manner, without affecting each other. By multiplexing the DFE in this way, one adjustment circuit can correspond to two sampling circuits, reducing the number of adjustment circuits. This improves inter-symbol interference while reducing circuit area and power consumption.

[0147] In another embodiment of this disclosure, referring to FIG3, a schematic diagram of the composition structure of a data receiving circuit 10 provided in another embodiment of this disclosure is shown. As shown in FIG3, the data receiving circuit 10 further includes:

[0148] The second adjustment circuit 50 receives the dual-ended signals SS1 / SS2 and is configured to amplify the voltage difference between the dual-ended signals SS1 / SS2. When the signals at the first clock terminal or the second clock terminal are in an active state, the circuit adjusts the amplification result based on the signals at the first control terminal FB1, the second control terminal FB2, the third control terminal FB3 and the fourth control terminal FB4 to perform decision feedback equalization and output the second dual-ended adjustment signal SS5 / SS6.

[0149] The third sampling circuit 60 receives the second dual-ended adjustment signals SS5 / SS6 and is configured to, when the signal received at the clock end is in an active state, amplify and latch the voltage difference of the second dual-ended adjustment signals SS5 / SS6 based on the signal at the control end to generate the second output signal DQ_Q.

[0150] The fourth sampling circuit 70 receives the second dual-ended adjustment signals SS5 / SS6 and is configured to amplify and latch the voltage difference between the second dual-ended adjustment signals SS5 / SS6 based on the signal at the control terminal when the signal received at the clock terminal is in an active state, so as to generate the fourth output signal DQ_QB.

[0151] Specifically, the first clock terminal of the second adjustment circuit 50 receives the first clock signal DQS_I, the second clock terminal receives the third clock signal DQS_IB, the clock terminal of the third sampling circuit 60 receives the second clock signal DQS_Q, and the clock terminal of the fourth sampling circuit 70 receives the fourth clock signal DQS_QB.

[0152] It is understandable that the working principles of the second adjustment circuit 50, the third sampling circuit 60 and the fourth sampling circuit 70 are similar to those of the first adjustment circuit 20, the first sampling circuit 30 and the second sampling circuit 40 mentioned above, and will not be repeated here.

[0153] In some embodiments, the first control terminal FB1 of the first adjustment circuit 20 receives the fourth feedback signal DQ_QB_OUTT, the second control terminal FB2 receives the third feedback signal DQ_IB_OUTT, the third control terminal FB3 receives the second feedback signal DQ_Q_OUTT, and the fourth control terminal FB4 receives the first feedback signal DQ_I_OUTT; the first control terminal FB1 of the second adjustment circuit 50 receives the first feedback signal DQ_I_OUTT, the second control terminal FB2 receives the fourth feedback signal DQ_QB_OUTT, the third control terminal FB3 receives the third feedback signal DQ_IB_OUTT, and the fourth control terminal FB4 receives the second feedback signal DQ_Q_OUTT; the first sampling... The control terminal of the first sampling circuit 30 receives the fourth feedback signal DQ_QB_OUTT; the control terminal of the second sampling circuit 40 receives the second feedback signal DQ_Q_OUTT; the control terminal of the third sampling circuit 60 receives the first feedback signal DQ_I_OUTT; and the control terminal of the fourth sampling circuit 70 receives the third feedback signal DQ_IB_OUTT. The first feedback signal DQ_I_OUTT originates from the first output signal DQ_I, the second feedback signal DQ_Q_OUTT originates from the second output signal DQ_Q, the third feedback signal DQ_IB_OUTT originates from the third output signal DQ_IB, and the fourth feedback signal DQ_QB_OUTT originates from the fourth output signal DQ_QB. Here, the four control terminals of the first adjustment circuit 20 and the second adjustment circuit 50 are associated with different phases, and each control terminal is responsible for processing the data feedback of its corresponding phase.

[0154] It is understandable that DQ_I_OUTT is in phase with DQ_I, DQ_Q_OUTT is in phase with DQ_Q, DQ_IB_OUTT is in phase with DQ_IB, and DQ_QB_OUTT is in phase with DQ_QB. DQ_I can be directly used as DQ_I_OUTT, DQ_Q as DQ_Q_OUTT, DQ_IB as DQ_IB_OUTT, and DQ_QB as DQ_QB_OUTT. Alternatively, several driving circuits can be added after DQ_I to generate the corresponding DQ_I_OUTT, thereby enhancing the driving capability of DQ_I_OUTT. The cases for DQ_Q_OUTT, DQ_IB_OUTT, and DQ_QB_OUTT are similar and will not be elaborated further.

[0155] Referring to Figure 4, a signal waveform diagram of a data receiving circuit provided in an embodiment of this disclosure is shown. As shown in Figure 4, DQS is the initial clock signal received, and DQS_I, DQS_Q, DQS_IB, and DQS_QB are four-phase clock signals obtained by dividing the initial clock signal DQS by two internally within the chip. The phase difference between DQS_I and DQS_Q is 90 degrees, the phase difference between DQS_Q and DQS_IB is 90 degrees, the phase difference between DQS_IB and DQS_QB is 90 degrees, and the phase difference between DQS_QB and DQS_I is 90 degrees. Furthermore, DQS_I and DQS_IB are out of phase, DQS_Q and DQS_QB are out of phase, and the duty cycle of DQS_I, DQS_Q, DQS_IB, and DQS_QB is 50% within the allowable error range. DQ represents the input data. DQ_I is the first output signal sampled at the rising edge of the first clock signal DQS_I, DQ_Q is the second output signal sampled at the rising edge of the second clock signal DQS_Q, DQ_IB is the third output signal sampled at the rising edge of the third clock signal DQS_IB, and DQ_QB is the fourth output signal sampled at the rising edge of the fourth clock signal DQS_QB. If the data transmitted in the current bit is DQ_I sampled at the rising edge of DQS_I, then the previously transmitted first bit is in DQ_QB, the previously transmitted second bit is in DQ_IB, the previously transmitted third bit is in DQ_Q, and the previously transmitted fourth bit is in DQ_I. Therefore, DQ_QB should be used for tap1 feedback of the DFE, DQ_IB should be used for tap2 feedback of the DFE, DQ_IB should be used for tap3 feedback of the DFE, and DQ_I should be used for tap4 feedback of the DFE. For the current bit transmission... For other data scenarios, see Table 1 below, which details the signals for each corresponding tap.

[0156] Table 1

[0157] Based on the foregoing analysis, if the data transmitted in the current bit corresponds to the rising edge of DQS_I, then the DQS_QB received by the first clock terminal of the first adjustment circuit 20 is at a high level (taking a high level as the valid state as an example). The fourth feedback signal DQ_QB_OUTT received by the first control terminal FB1 of the first adjustment circuit 20 originates from the fourth output signal DQ_QB, and in response to the first tap coefficient, feedback is performed on the first tap (tap1) of the DFE; the third feedback signal DQ_IB_OUTT received by the second control terminal FB2 originates from the third output signal DQ_IB, and in response to the second... The tap coefficient is used to perform feedback for the second tap (tap2) of the DFE; the second feedback signal DQ_Q_OUTT received by the third control terminal FB3 originates from the second output signal DQ_Q and, in response to the third tap coefficient, performs feedback for the third tap (tap3) of the DFE; the first feedback signal DQ_I_OUTT received by the fourth control terminal FB4 originates from the first output signal DQ_I and, in response to the fourth tap coefficient, performs feedback for the fourth tap (tap4) of the DFE; thus, the first adjustment circuit 20 performs 4-tap decision feedback equalization on the current bit data based on the previous 4 bits of data. The clock terminal of the first sampling circuit 30 receives DQS_I, and the control terminal receives the fourth feedback signal DQ_QB_OUTT, thus using the previous 1 bit of data to perform decision feedback equalization on the current input data to generate the first output signal DQ_I.

[0158] If the data transmitted in the current bit corresponds to the rising edge of DQS_IB, then the DQS_Q received at the second clock terminal of the first adjustment circuit 20 is at a high level. The fourth feedback signal DQ_QB_OUTT received by the first control terminal FB1 of the first adjustment circuit 20 originates from the fourth output signal DQ_QB and, in response to the third tap coefficient, performs feedback of the third tap (tap3) of DFE. The third feedback signal DQ_IB_OUTT received by the second control terminal FB2 originates from the third output signal DQ_IB and, in response to the fourth tap coefficient, performs feedback of the fourth tap of DFE. Feedback at tap 4; the second feedback signal DQ_Q_OUTT received by the third control terminal FB3 originates from the second output signal DQ_Q, and in response to the first tap coefficient, performs feedback at the first tap (tap 1) of the DFE; the first feedback signal DQ_I_OUTT received by the fourth control terminal FB4 originates from the first output signal DQ_I, and in response to the second tap coefficient, performs feedback at the second tap (tap 2) of the DFE; thus, the first adjustment circuit 20 performs 4-tap decision feedback equalization on the current bit data based on the previous 4 bits of data. The clock terminal of the second sampling circuit 40 receives DQS_IB, and the control terminal receives the second feedback signal DQ_Q_OUTT, thus using the previous 1 bit of data to perform decision feedback equalization on the current input data to generate the third output signal DQ_IB.

[0159] With this configuration, when the currently transmitted input data corresponds to the rising edge of either DQS_I or DQS_IB, the first adjustment circuit 20 can perform 4-tap decision feedback equalization. Then, the first sampling circuit 30 generates the first output data DQ_I, and the second sampling circuit 40 generates the third output signal DQ_IB. This multiplexing of the DFE allows the first adjustment circuit 20 to correspond to both the first sampling circuit 30 and the second sampling circuit 40, reducing the number of adjustment circuits. This improves inter-symbol interference while reducing circuit area and power consumption.

[0160] If the data transmitted in the current bit corresponds to the rising edge of DQS_Q, then the DQS_I received by the first clock terminal of the second adjustment circuit 50 is at a high level. The first feedback signal DQ_I_OUTT received by the first control terminal FB1 of the second adjustment circuit 50 originates from the first output signal DQ_I and, in response to the first tap coefficient, performs feedback of the first tap (tap1) of DFE. The fourth feedback signal DQ_QB_OUTT received by the second control terminal FB2 originates from the fourth output signal DQ_QB and, in response to the second tap coefficient, performs feedback of the second tap (tap1) of DFE. The third control terminal FB3 receives the third feedback signal DQ_IB_OUTT, which originates from the third output signal DQ_IB. Responding to the third tap coefficient, it performs feedback at the third tap (tap3) of the DFE. The fourth control terminal FB4 receives the second feedback signal DQ_Q_OUTT, which originates from the second output signal DQ_Q. Responding to the fourth tap coefficient, it performs feedback at the fourth tap (tap4) of the DFE. Thus, the second adjustment circuit 50 performs 4-tap decision feedback equalization on the current bit data based on the previous 4 bits of data. The clock terminal of the third sampling circuit 60 receives DQS_Q, and the control terminal receives the first feedback signal DQ_I_OUTT. Therefore, it uses the previous 1 bit of data to perform decision feedback equalization on the current input data to generate the second output signal DQ_Q.

[0161] If the data transmitted in the current bit corresponds to the rising edge of DQS_QB, then the DQS_IB received at the second clock terminal of the second adjustment circuit 50 is at a high level. The first feedback signal DQ_I_OUTT received by the first control terminal FB1 of the second adjustment circuit 50 originates from the first output signal DQ_I and, in response to the third tap coefficient, performs feedback of the third tap (tap3) of the DFE. The fourth feedback signal DQ_QB_OUTT received by the second control terminal FB2 originates from the fourth output signal DQ_QB and, in response to the fourth tap coefficient, performs feedback of the fourth tap of the DFE. Feedback at (tap4); the third feedback signal DQ_IB_OUTT received by the third control terminal FB3 originates from the third output signal DQ_IB, and in response to the first tap coefficient, performs feedback at the first tap (tap1) of DFE; the second feedback signal DQ_Q_OUTT received by the fourth control terminal FB4 originates from the second output signal DQ_Q, and in response to the second tap coefficient, performs feedback at the second tap (tap2) of DFE; thus, the second adjustment circuit 50 performs 4-tap decision feedback equalization on the current bit data based on the data of the previous 4 bits. The clock terminal of the fourth sampling circuit 70 receives DQS_QB, and the control terminal receives the third feedback signal DQ_IB_OUTT, thus using the data of the previous 1 bit to perform decision feedback equalization on the current input data to generate the fourth output signal DQ_QB.

[0162] With this configuration, when the currently transmitted input data corresponds to the rising edge of either DQS_Q or DQS_QB, the second adjustment circuit 50 can perform 4-tap decision feedback equalization. Then, the third sampling circuit 60 generates the second output signal DQ_Q, and the fourth sampling circuit 70 generates the fourth output signal DQ_QB. This multiplexing of the DFE allows the second adjustment circuit 50 to correspond to both the third and fourth sampling circuits 60, reducing the number of adjustment circuits. This improves inter-symbol interference while reducing circuit area and power consumption.

[0163] In some embodiments, the first adjustment circuit 20 and the second adjustment circuit 50 have the same structure. It is understood that the only difference between the first adjustment circuit 20 and the second adjustment circuit 50 is the signals received at their respective first control terminal, second control terminal, third control terminal, fourth control terminal, first clock terminal, and second clock terminal; however, their internal circuit structures are identical. This design facilitates matching the path delays for generating the first output signal DQ_I, the second output signal DQ_Q, the third output signal DQ_IB, and the fourth output signal DQ_QB, improving signal quality, and also simplifying circuit design and saving design time.

[0164] In some embodiments, referring to FIG5, the first adjustment circuit 20 includes:

[0165] The first amplification module 250 receives the dual-ended signals SS1 / SS2 and is configured to amplify the voltage difference between the dual-ended signals SS1 / SS2. It outputs a first adjustment sub-signal SS3 at the first node net1 and a second adjustment signal SS4 at the second node net2. The first dual-ended adjustment signal SS3 / SS4 includes the first adjustment sub-signal SS3 and the second adjustment signal SS4.

[0166] The first decision feedback equalization module 210, electrically connected to the first node net1 and the second node net2, is configured to adjust the voltage difference between the first node net1 and the second node net2 when the signal DQS_QB at the first clock terminal of the first adjustment circuit 20 is in an active state, the signal of the first control terminal FB1 of the first adjustment circuit 20 responds to the first tap coefficient, or when the signal DQS_Q at the second clock terminal of the first adjustment circuit 20 is in an active state, the signal of the first control terminal FB1 of the first adjustment circuit 20 responds to the third tap coefficient.

[0167] The second decision feedback equalization module 220, electrically connected to the first node net1 and the second node net2, is configured to adjust the voltage difference between the first node net1 and the second node net2 when the signal DQS_QB at the first clock terminal of the first adjustment circuit 20 is in an active state, and the signal FB2 at the second control terminal of the first adjustment circuit 20 responds to the second tap coefficient; or, when the signal DQS_Q at the second clock terminal of the first adjustment circuit 20 is in an active state, the signal FB2 at the second control terminal of the first adjustment circuit 20 responds to the fourth tap coefficient.

[0168] The third decision feedback equalization module 230, electrically connected to the first node net1 and the second node net2, is configured to adjust the voltage difference between the first node net1 and the second node net2 when the signal DQS_QB at the first clock terminal of the first adjustment circuit 20 is in an active state, the signal at the third control terminal FB3 of the first adjustment circuit 20 responds to the third tap coefficient, or when the signal DQS_Q at the second clock terminal of the first adjustment circuit 20 is in an active state, the signal at the third control terminal FB3 of the first adjustment circuit 20 responds to the first tap coefficient.

[0169] The fourth decision feedback equalization module 240, electrically connected to the first node net1 and the second node net2, is configured to adjust the voltage difference between the first node net1 and the second node net2 when the signal DQS_QB at the first clock terminal of the first adjustment circuit 20 is active, the signal at the fourth control terminal FB4 of the first adjustment circuit 20 responds to the fourth tap coefficient, or when the signal DQS_Q at the second clock terminal of the first adjustment circuit 20 is active, the signal at the fourth control terminal FB4 of the first adjustment circuit 20 responds to the second tap coefficient.

[0170] The first amplification module 250 in the first adjustment circuit 20 amplifies the voltage difference between the two-terminal signals SS1 / SS2, which is equivalent to performing a second-stage amplification on the voltage difference between the input data DQ and the initial reference voltage Vref. The first decision feedback equalization module 210, the second decision feedback equalization module 220, the third decision feedback equalization module 230, and the fourth decision feedback equalization module 240 correspond to the signals of the first control terminal FB1, the second control terminal FB2, the third control terminal FB3, and the fourth control terminal FB4, respectively. Under the control of the signal DQS_QB at the first clock terminal or the signal DQS_Q at the second clock terminal, they respond to specific tap coefficients to realize the decision feedback equalization function as described above.

[0171] In some embodiments, referring to FIG5, the first amplification module 250 includes: a fifth NMOS transistor N5, whose control terminal receives SS1 of the two-terminal signal, whose first terminal is connected to a first current source I1, and whose second terminal is connected to a second node net2; a sixth NMOS transistor N6, whose control terminal receives SS2 of the two-terminal signal, whose first terminal is connected to the first current source I1, and whose second terminal is connected to the first node net1; a first resistor R1, whose first terminal receives the power supply voltage VDD, and whose second terminal is connected to the second node; a second resistor R2, whose first terminal receives the power supply voltage VDD, and whose second terminal is connected to the first node; and a first current source I1, whose first terminal is connected to the second terminal of the fifth NMOS transistor, and whose second terminal is grounded. It is understood that the first amplification module 250 can also be composed of other structures, as long as it can realize the voltage difference between the two-terminal signals SS1 / SS2 and meet the design requirements.

[0172] In some embodiments, referring to FIG6a, the first decision feedback equalization module 210 includes:

[0173] The first selection unit 2101 is configured such that its first input terminal receives a signal DQ_QB_OUTT from the first control terminal of the first adjustment circuit 20, and the second input terminal receives a signal DQ_QB_OUTB that is inverted with the signal from the first input terminal. The control terminal receives an equalization direction control signal EN. In response to the equalization direction control signal EN, the first output terminal outputs the signal from the first input terminal, and the second output terminal outputs the signal from the second input terminal, or the first output terminal outputs the signal from the second input terminal, and the second output terminal outputs the signal from the first input terminal.

[0174] The first MOSFET M1 has its first terminal connected to the first variable current source IT1, and its control terminal connected to the first clock terminal of the first adjustment circuit 20.

[0175] The second MOSFET M2 has its first terminal connected to the second variable current source IT2, and its control terminal connected to the second clock terminal of the first adjustment circuit 20.

[0176] The third MOSFET M3 has its first end connected to the second end of the first MOSFET M1, its second end connected to the first node net1, and its control end connected to the first output terminal of the first selection unit 2101.

[0177] The fourth MOSFET M4 has its first terminal connected to the second terminal of the second MOSFET M2, its second terminal connected to the second node net2, and its control terminal connected to the second output terminal of the first selection unit 2101.

[0178] The current value of the first variable current source IT1 responds to the first tap coefficient, and the current value of the second variable current source IT2 responds to the third tap coefficient.

[0179] Figure 6a shows an example where the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 are NMOS transistors, and the first variable current source IT1 and the second variable current source IT2 are grounded. In actual design, M1, M2, M3, and M4 can also be configured as PMOS transistors, and the first variable current source IT1 and the second variable current source IT2 can be connected to the power supply voltage. It is understood that the selection and design of M1, M2, M3, M4, IT1, and IT2 need to be considered in conjunction with the effective levels of the signals at the first and second clock terminals of the first adjustment circuit 20, ensuring that the corresponding MOSFET can be turned on when the signal at the first or second clock terminal is in an effective state.

[0180] This explanation uses NMOS transistors M1, M2, M3, and M4 as examples, with the first variable current source IT1 and the second variable current source IT2 grounded. When the fourth clock signal DQS_QB received by the first clock terminal of the first adjustment circuit 20 is high, and the second clock signal DQS_Q is low, M1 is turned on and M2 is turned off. Therefore, IT1 is active, and IT2 is inactive. Since the current value of IT1 responds to the first tap coefficient, the first decision feedback equalization module 210 can, based on the received fourth feedback signal DQ_QB_OUTT, respond to the first tap coefficient to perform feedback on the first tap (tap1) of the DFE. When the second clock signal DQS_Q received by the second clock terminal of the first adjustment circuit 20 is high, and the fourth clock signal DQS_QB is low, M2 is turned on and M1 is turned off. Therefore, IT2 is active, and IT1 is inactive. Since the current value of IT2 responds to the third tap coefficient, the first decision feedback equalization module 210 can, based on the received fourth feedback signal DQ_QB_OUTT, respond to the third tap coefficient to perform feedback at the third tap (tap3) of the DFE. This configuration allows the first decision feedback equalization module 210 to be used as both tap1 and tap3 feedback, achieving DFE multiplexing. This improves inter-symbol interference while reducing circuit area and power consumption.

[0181] The current values ​​of the first variable current source IT1 and the second variable current source IT2 can be set through coding, and each coding corresponds to the first tap coefficient and the third tap coefficient. That is, the tap coefficients can be converted into codes to adjust the current values ​​of their respective current sources. In practice, each tap coefficient can be adjusted according to the channel conditions and actual needs, so the corresponding codes and current values ​​are also adjustable.

[0182] The function of the first selection unit 2101 is to control the direction of the decision feedback equalization. Under the control of the equalization direction control signal EN, DQ_QB_OUTT is connected to the control terminal of M3 and DQ_QB_OUTB is connected to the control terminal of M4, or DQ_QB_OUTT is connected to the control terminal of M4 and DQ_QB_OUTB is connected to the control terminal of M3. In some embodiments, as shown in FIG6a, the first selection unit 2101 may be composed of four transmission gates T1, T2, T3 and T4. The input terminal of T1 receives DQ_QB_OUTT, the first control terminal receives the equalization direction control signal EN, the second control terminal receives the inverted signal ENB of EN, and the output terminal is connected to the control terminal of M3. The input terminal of T2 receives DQ_QB_OUTT, the first control terminal receives ENB, the second control terminal receives EN, and the output terminal is connected to the control terminal of M4. The input terminal of T3 receives DQ_QB_OUTB, the first control terminal receives ENB, the second control terminal receives EN, and the output terminal is connected to the control terminal of M3. The input terminal of T4 receives DQ_QB_OUTB, the first control terminal receives EN, the second control terminal receives ENB, and the output terminal is connected to the control terminal of M4. If EN is active, when DQ_QB_OUTT is high and DQ_QB_OUTB is low, M3 is turned on, M4 is turned off, and the voltage of net1 is pulled down. When DQ_QB_OUTT is low and DQ_QB_OUTB is high, M4 is turned on, M3 is turned off, and the voltage of net2 is pulled down. If EN is inactive and ENB is active, when DQ_QB_OUTT is high and DQ_QB_OUTB is low, M4 is turned on, M3 is turned off, and the voltage of net2 is pulled down. When DQ_QB_OUTT is low and DQ_QB_OUTB is high, M3 is turned on, M4 is turned off, and the voltage of net1 is pulled down. With this configuration, the equalization direction of the fourth feedback signal DQ_QB_OUTT for the current bit data can be controlled, which is more conducive to adjusting the effect of decision feedback equalization and improving the problem of inter-symbol interference.

[0183] In some embodiments, referring to FIG6b, the second decision feedback equalization module 220 includes:

[0184] The second selection unit 2201 is configured such that its first input terminal receives a signal DQ_IB_OUTT from the second control terminal of the first adjustment circuit 20, and the signal DQ_IB_OUTB received at the second input terminal is inverted with the signal at the first input terminal. The control terminal receives an equalization direction control signal EN. In response to the equalization direction control signal EN, the first output terminal outputs the signal at the first input terminal, and the second output terminal outputs the signal at the second input terminal, or the first output terminal outputs the signal at the second input terminal, and the second output terminal outputs the signal at the first input terminal.

[0185] The fifth MOSFET M5 has its first terminal connected to the third variable current source IT3, and its control terminal connected to the first clock terminal of the first adjustment circuit 20.

[0186] The sixth MOSFET M6 has its first terminal connected to the fourth variable current source IT4, and its control terminal connected to the second clock terminal of the first adjustment circuit 20.

[0187] The seventh MOSFET M7 has its first terminal connected to the second terminal of the fifth MOSFET M5, its second terminal connected to the first node net1, and its control terminal connected to the first output terminal of the second selection unit 2201.

[0188] The eighth MOSFET M8 has its first terminal connected to the second terminal of the sixth MOSFET M6, its second terminal connected to the second node net2, and its control terminal connected to the second output terminal of the second selection unit 2201.

[0189] The current value of the third variable current source IT3 responds to the second tap coefficient, and the current value of the fourth variable current source IT4 responds to the fourth tap coefficient.

[0190] In some embodiments, referring to FIG6c, the third decision feedback equalization module 230 includes:

[0191] The third selection unit 2301 is configured such that its first input terminal receives the signal DQ_Q_OUTT from the third control terminal of the first adjustment circuit 20, the signal DQ_Q_OUTB received at its second input terminal is inverted with the signal at the first input terminal, the control terminal receives the equalization direction control signal EN, and in response to the equalization direction control signal EN, the first output terminal outputs the signal at the first input terminal, and the second output terminal outputs the signal at the second input terminal, or the first output terminal outputs the signal at the second input terminal, and the second output terminal outputs the signal at the first input terminal.

[0192] The ninth MOSFET M9 has its first terminal connected to the fifth variable current source IT5, and its control terminal connected to the first clock terminal of the first adjustment circuit 20.

[0193] The tenth MOSFET M10 has its first terminal connected to the sixth variable current source IT6, and its control terminal connected to the second clock terminal of the first adjustment circuit 20.

[0194] The eleventh MOSFET M11 has its first terminal connected to the second terminal of the ninth MOSFET M9, its second terminal connected to the first node net1, and its control terminal connected to the first output terminal of the third selection unit 2301.

[0195] The twelfth MOSFET M12 has its first terminal connected to the second terminal of the tenth MOSFET M10, its second terminal connected to the second node net2, and its control terminal connected to the second output terminal of the third selection unit 2301.

[0196] The current value of the fifth variable current source IT5 responds to the third tap factor, and the current value of the sixth variable current source IT6 responds to the first tap factor.

[0197] In some embodiments, referring to FIG6d, the fourth decision feedback equalization module 240 includes:

[0198] The fourth selection unit 2401 is configured such that its first input terminal receives the signal DQ_I_OUTT from the fourth control terminal of the first adjustment circuit 20, the signal DQ_I_OUTB received at its second input terminal is inverted with the signal at the first input terminal, the control terminal receives the equalization direction control signal EN, and in response to the equalization direction control signal EN, the first output terminal outputs the signal at the first input terminal, and the second output terminal outputs the signal at the second input terminal, or the first output terminal outputs the signal at the second input terminal, and the second output terminal outputs the signal at the first input terminal.

[0199] The thirteenth MOSFET M13 has its first terminal connected to the seventh variable current source IT7, and its control terminal connected to the first clock terminal of the first adjustment circuit 20.

[0200] The fourteenth MOSFET M14 has its first terminal connected to the eighth variable current source IT8, and its control terminal connected to the second clock terminal of the first adjustment circuit 20.

[0201] The fifteenth MOSFET M15 has its first terminal connected to the second terminal of the thirteenth MOSFET M13, and its second terminal connected to the first node net1. Its control terminal is connected to the first output terminal of the fourth selection unit 2401.

[0202] The sixteenth MOSFET M16 has its first terminal connected to the second terminal of the fourteenth MOSFET M14, its second terminal connected to the second node net2, and its control terminal connected to the second output terminal of the fourth selection unit 2401.

[0203] The current value of the seventh variable current source IT7 responds to the fourth tap factor, and the current value of the eighth variable current source IT8 responds to the second tap factor.

[0204] It is understandable that the structure and working principle of the second decision feedback equalization module 220, the third decision feedback equalization module 230, and the fourth decision feedback equalization module 240 are similar to those of the first decision feedback equalization module 210, and will not be described again here. The first decision feedback equalization module 210, the second decision feedback equalization module 220, the third decision feedback equalization module 230, and the fourth decision feedback equalization module 240 correspond to the first control terminal FB1, the second control terminal FB2, the third control terminal FB3, and the fourth control terminal FB4 of the first adjustment circuit 20, respectively, and are associated with different phases. Each decision feedback equalization module is responsible for processing the data feedback of the corresponding phase.

[0205] If the data transmitted in the current bit corresponds to the rising edge of DQS_I, and the DQS_QB received at the first clock terminal of the first adjustment circuit 20 is at a high level, then M1, M5, M9, and M13 are turned on, M2, M6, M10, and M14 are turned off, IT1, IT3, IT5, and IT7 are active, and IT2, IT4, IT6, and IT8 are inactive. Therefore, DQ_QB_OUTT responds to the first tap coefficient and provides feedback for the first tap (tap1) of the DFE; DQ_IB_OUTT responds to the second tap coefficient and provides feedback for the second tap (tap2) of the DFE; DQ_Q_OUTT responds to the third tap coefficient and provides feedback for the third tap (tap3) of the DFE; and DQ_I_OUTT responds to the fourth tap coefficient and provides feedback for the fourth tap (tap4) of the DFE. Thus, when the current bit data is in DQ_I, the first adjustment circuit 20 implements a 4-tap decision feedback equalization of the current bit data based on the previous 4 bits, as shown in Table 1.

[0206] If the data transmitted in the current bit corresponds to the rising edge of DQS_IB, and the DQS_Q received at the second clock terminal of the first adjustment circuit 20 is at a high level, then M1, M5, M9, and M13 are turned off, M2, M6, M10, and M14 are turned on, IT1, IT3, IT5, and IT7 are inactive, and IT2, IT4, IT6, and IT8 are active. Therefore, DQ_QB_OUTT responds to the third tap coefficient and provides feedback for the third tap (tap3) of the DFE; DQ_IB_OUTT responds to the fourth tap coefficient and provides feedback for the fourth tap (tap4) of the DFE; DQ_Q_OUTT responds to the first tap coefficient and provides feedback for the first tap (tap1) of the DFE; and DQ_I_OUTT responds to the second tap coefficient and provides feedback for the second tap (tap2) of the DFE. Thus, when the current bit data is in DQ_IB, the first adjustment circuit 20 implements a 4-tap decision feedback equalization of the current bit data based on the previous 4 bits, as shown in Table 1.

[0207] With this configuration, when the currently transmitted input data corresponds to the rising edge of either DQS_I or DQS_IB, the first adjustment circuit 20 can perform 4-tap decision feedback equalization. Then, the first sampling circuit 30 generates the first output data DQ_I, and the second sampling circuit 40 generates the third output signal DQ_IB. This multiplexing of the DFE allows the first adjustment circuit 20 to correspond to both the first sampling circuit 30 and the second sampling circuit 40, reducing the number of adjustment circuits. This improves inter-symbol interference while reducing circuit area and power consumption.

[0208] In some embodiments, referring to Figures 7a, 7b, 7c, and 7d, a schematic diagram of the structure of the first decision feedback equalization module 510, the second decision feedback equalization module 520, the third decision feedback equalization module 530, and the fourth decision feedback equalization module 540 of the second adjustment circuit 50 is shown. The first decision feedback equalization module 510 receives the signal DQ_I_OUTT from the first control terminal of the second adjustment circuit 50; the second decision feedback equalization module 520 receives the signal DQ_QB_OUTT from the second control terminal of the second adjustment circuit 50; the third decision feedback equalization module 530 receives the signal DQ_IB_OUTT from the third control terminal of the second adjustment circuit 50; and the fourth decision feedback equalization module 540 receives the signal DQ_Q_OUTT from the fourth control terminal of the second adjustment circuit 50. The first decision feedback equalization module 510, the second decision feedback equalization module 520, the third decision feedback equalization module 530, and the fourth decision feedback equalization module 540 all receive the first clock signals DQS_I and DQS_IB. The first decision feedback equalization module 510, the second decision feedback equalization module 520, the third decision feedback equalization module 530, and the fourth decision feedback equalization module 540 of the second adjustment circuit 50 are the same as the first decision feedback equalization module 210, the second decision feedback equalization module 220, the third decision feedback equalization module 230, and the fourth decision feedback equalization module 240 of the first adjustment circuit 20, except for the received signals. Their internal circuit structures are the same and their working principles are similar, so they will not be described in detail here.

[0209] If the data transmitted in the current bit corresponds to the rising edge of DQS_Q, and the DQS_I received at the first clock terminal of the second adjustment circuit 50 is at a high level, then M1, M5, M9, and M13 are turned on, M2, M6, M10, and M14 are turned off, IT1, IT3, IT5, and IT7 are active, and IT2, IT4, IT6, and IT8 are inactive. Therefore, DQ_I_OUTT responds to the first tap coefficient and provides feedback for the first tap (tap1) of the DFE; DQ_QB_OUTT responds to the second tap coefficient and provides feedback for the second tap (tap2) of the DFE; DQ_IB_OUTT responds to the third tap coefficient and provides feedback for the third tap (tap3) of the DFE; and DQ_Q_OUTT responds to the fourth tap coefficient and provides feedback for the fourth tap (tap4) of the DFE. Thus, when the current bit data is in DQ_Q, the first adjustment circuit 20 implements a 4-tap decision feedback equalization of the current bit data based on the previous 4 bits, as shown in Table 1.

[0210] If the data transmitted in the current bit corresponds to the rising edge of DQS_QB, and the second clock terminal of the second adjustment circuit 50 receives DQS_IB at a high level, then M1, M5, M9, and M13 are turned off, M2, M6, M10, and M14 are turned on, IT1, IT3, IT5, and IT7 are inactive, and IT2, IT4, IT6, and IT8 are active. Therefore, DQ_I_OUTT responds to the third tap coefficient and provides feedback for the third tap (tap3) of the DFE; DQ_QB_OUTT responds to the fourth tap coefficient and provides feedback for the fourth tap (tap4) of the DFE; DQ_IB_OUTT responds to the first tap coefficient and provides feedback for the first tap (tap1) of the DFE; and DQ_Q_OUTT responds to the second tap coefficient and provides feedback for the second tap (tap2) of the DFE. Thus, when the current bit data is in DQ_QB, the first adjustment circuit 20 implements a 4-tap decision feedback equalization of the current bit data based on the previous 4 bits, as shown in Table 1.

[0211] With this configuration, when the currently transmitted input data corresponds to the rising edge of either DQS_Q or DQS_QB, the second adjustment circuit 50 can perform 4-tap decision feedback equalization. Then, the third sampling circuit 60 generates the second output signal DQ_Q, and the fourth sampling circuit 70 generates the fourth output signal DQ_QB. This multiplexing of the DFE allows the second adjustment circuit 50 to correspond to both the third and fourth sampling circuits 60, reducing the number of adjustment circuits. This improves inter-symbol interference while reducing circuit area and power consumption.

[0212] In some embodiments, as shown in FIG8, the first adjustment circuit 20 further includes a first negative capacitor equalizer 260, which is electrically connected to the first node net1 and the second node net2 to increase the gain of the first adjustment circuit 20. Specifically, the first negative capacitor equalizer 260 can improve the high-frequency gain of the first adjustment circuit 20, thus helping to increase the bandwidth of the circuit.

[0213] In some embodiments, as shown in FIG9, the first negative capacitor equalizer 260 includes: a ninth NMOS transistor N9, whose control terminal receives a first bias voltage Vbias1 and whose first terminal is grounded; a tenth NMOS transistor N10, whose control terminal receives a first bias voltage Vbias1 and whose first terminal is grounded; a seventh NMOS transistor N7, whose control terminal is connected to the second node net2, whose first terminal is connected to the second terminal of the ninth NMOS transistor N9, and whose second terminal is connected to the first node net1; an eighth NMOS transistor N8, whose control terminal is connected to the first node net1, whose first terminal is connected to the second terminal of the tenth NMOS transistor N10, and whose second terminal is connected to the second node net2; and a first capacitor C1, whose first terminal is connected to the second terminal of the ninth NMOS transistor N9, and whose second terminal is connected to the second terminal of the tenth NMOS transistor N10. This is beneficial for increasing the voltage difference between the first node net1 and the second node net2 at high frequencies.

[0214] In some embodiments, referring to FIG10, a schematic diagram of another data receiving circuit 10 is shown. As shown in FIG10, the first sampling circuit 30 also receives a first reference voltage Vref1 and a second reference voltage Vref2, wherein the voltage value of the first reference voltage Vref1 is greater than the voltage value of the second reference voltage Vref2; based on the signal DQ_QB at the control terminal, the voltage difference of the first dual-terminal adjustment signals SS3 / SS4 is amplified and latched to generate a first output signal DQ_I, including: based on the signal DQ_QB at the control terminal, selecting to equivalently increase or decrease the voltage difference between the first dual-terminal adjustment signals SS3 / SS4 through the voltage difference of the first reference voltage Vref1 and the second reference voltage Vref2, amplifying and latching the voltage difference of the first dual-terminal adjustment signals SS3 / SS4 to generate the first output signal DQ_I. Here, the signal DQ_QB at the control terminal is equivalent to the previous bit of DQ_I, and the current input data is subjected to tap1 decision feedback equalization to generate the first output signal DQ_I.

[0215] As shown in Figure 10, the second sampling circuit 40, the third sampling circuit 60 and the fourth sampling circuit 70 also receive the first reference voltage Vref1 and the second reference voltage Vref2. Their working principle is similar to that of the first sampling circuit 30, so it will not be described in detail here.

[0216] In some embodiments, as shown in FIG11, a schematic diagram of the structure of the first sampling circuit 30 is illustrated. The first dual-ended adjustment signal SS3 / SS4 includes a first adjustment sub-signal SS3 and a second adjustment sub-signal SS4; the first sampling circuit 30 includes:

[0217] The selection adjustment circuit 310 is configured to, when the clock signal is in an active state, select, based on the control signal, to adjust the branch current of the branch where the first adjustment sub-signal SS3 is located by the first reference voltage Vref1, and to adjust the branch current of the branch where the second adjustment sub-signal SS4 is located by the second reference voltage Vref2.

[0218] Alternatively, the branch current of the branch containing the second adjustment sub-signal SS4 can be adjusted by the first reference voltage Vref1, and the branch current of the branch containing the first adjustment sub-signal SS3 can be adjusted by the second reference voltage Vref2.

[0219] The latch circuit 320, electrically connected to the selection adjustment circuit 310, is configured to amplify and latch the voltage difference of the first dual-ended adjustment signals SS3 / SS4 to generate the first output signal DQ_I.

[0220] In some embodiments, referring to FIG11, the selection adjustment circuit 310 includes:

[0221] The first NMOS transistor N01 has a control terminal used to receive the first adjustment sub-signal SS3, and the first terminal is connected to the latch circuit 320.

[0222] The second NMOS transistor N02 has a control terminal for receiving the second adjustment sub-signal SS4, a first terminal connected to the latch circuit 320, and a second terminal connected to the second terminal of the first NMOS transistor N01.

[0223] The first switching NMOS transistor KN01 has its control terminal connected to the clock terminal DQS_I of the first sampling circuit 30. The first terminal is electrically connected to the second terminal of the first NMOS transistor N01, and the second terminal is grounded.

[0224] The first adjustment NMOS transistor TN01 has a control terminal used to receive the first reference voltage Vref1, and its first terminal is connected to the first terminal of the second NMOS transistor N02.

[0225] The second adjustment NMOS transistor TN02 has a control terminal for receiving the second reference voltage Vref2, a first terminal connected to the first terminal of the first NMOS transistor N01, and a second terminal connected to the second terminal of the first adjustment NMOS transistor TN01.

[0226] The second switching NMOS transistor KN02 has its control terminal connected to the control terminal of the first sampling circuit 30, and its first terminal connected to the second terminal of the second adjusting NMOS transistor TN02.

[0227] The third switch NMOS transistor KN03 has its control terminal connected to the clock terminal of the first sampling circuit 30, its first terminal connected to the second terminal of the second switch NMOS transistor KN02, and its second terminal grounded.

[0228] The third adjustment NMOS transistor TN03 has a control terminal used to receive the second reference voltage Vref2, and its first terminal is connected to the first terminal of the second NMOS transistor N02.

[0229] The fourth adjusting NMOS transistor TN04 has a control terminal used to receive the first reference voltage Vref1. The first terminal is connected to the first terminal of the first NMOS transistor N01, and the second terminal is connected to the second terminal of the third adjusting NMOS transistor TN03.

[0230] The fourth switching NMOS transistor KN04 has a control terminal used to receive the inverted signal of the control terminal signal of the first sampling circuit 30, and its first terminal is connected to the second terminal of the fourth adjusting NMOS transistor TN04.

[0231] The fifth switch NMOS transistor KN05 has its control terminal connected to the clock terminal of the first sampling circuit 30, its first terminal connected to the second terminal of the fourth switch NMOS transistor KN04, and its second terminal grounded.

[0232] In some embodiments, referring to FIG11, the latch circuit 320 includes:

[0233] The first PMOS transistor P01 has its first terminal used to receive the power supply voltage VDD.

[0234] The second PMOS transistor P02 has its first terminal used to receive the power supply voltage VDD.

[0235] The third NMOS transistor N03 has its control terminal connected to the control terminal of the first PMOS transistor P01, its first terminal connected to the second terminal of the first PMOS transistor P01, and its second terminal connected to the first terminal of the first NMOS transistor N01.

[0236] The fourth NMOS transistor N04 has its control terminal connected to the control terminal of the second PMOS transistor P02, its first terminal connected to the second terminal of the second PMOS transistor P02, and its second terminal connected to the first terminal of the second NMOS transistor N02.

[0237] The control terminal of the third NMOS transistor N03 is also connected to the first terminal of the fourth NMOS transistor N04 to serve as the first output terminal OUT of the latch circuit 320. The control terminal of the fourth NMOS transistor N04 is also connected to the first terminal of the third NMOS transistor N03 to serve as the second output terminal OUTB of the latch circuit 320.

[0238] In some embodiments, referring to FIG11, the first sampling circuit 30 further includes a reset circuit 330, which is connected to the clock terminal of the first sampling circuit 30 and the latch circuit 320, and is used to reset the first output terminal and the second output terminal of the latch circuit 320 in response to the clock terminal signal of the first sampling circuit 30.

[0239] The working principle of the first sampling circuit 30 is as follows: When DQS_I is low, i.e., the first clock signal DQS_I is invalid, the first output signal DQ_I is not generated. The first switch NMOS transistor KN01, the third switch NMOS transistor KN03, and the fifth switch NMOS transistor KN05 are all turned off, the selection adjustment circuit 330 is turned off, and the reset circuit 330 resets the first sampling circuit 30. When DQS_I is high, i.e., the first clock signal DQS_I is valid, the current first output signal DQ_I is generated.

[0240] If the voltage value of the input data DQ is greater than the voltage value of the initial reference voltage Vref, based on the previous content, the voltage value of the first adjustment sub-signal SS3 is greater than the voltage value of the second adjustment sub-signal SS4. The first switch NMOS transistor KN01 is turned on based on DQS_I, making the potential of the first terminal of the first NMOS transistor N01 less than the potential of the first terminal of the second NMOS transistor N02. For the latch circuit 320, ideally, the potential of the first output terminal OUT is greater than the potential of the second output terminal OUTB, and DQ_I is at a high level.

[0241] If the first bit of data DQ_QB is high, then the fourth feedback signal DQ_QB_OUTT is high and DQ_QB_OUTB is low. The second NMOS transistor KN02 is turned on, the third NMOS transistor KN03 is turned on based on DQS_I, and the fourth NMOS transistor KN04 is turned off. At this time, the second regulating NMOS transistor TN02 pulls down the second terminal potential of the third NMOS transistor N03, the first regulating NMOS transistor TN01 pulls down the second terminal potential of the fourth NMOS transistor N04, and the voltage value of the first reference voltage Vref1 is greater than the second reference voltage. The voltage value of Vref2 means that the pull-down capability of the first regulating NMOS transistor TN01 is greater than that of the second regulating NMOS transistor TN02. This makes the drop in the potential of the second terminal of the third NMOS transistor N03 less than the drop in the potential of the second terminal of the fourth NMOS transistor N04. This is equivalent to increasing the value of the initial reference voltage Vref. However, since the first bit of data DQ_QB is high, the change in the input data DQ is not significant, and DQ_I still needs to be sampled as high. The increased initial reference voltage Vref does not affect the sampling of the data receiving circuit, and DQ_I is still sampled as high.

[0242] If the first bit of data DQ_QB is low, then the fourth feedback signal DQ_QB_OUTT is low, DQ_QB_OUTB is high, the fourth NMOS transistor KN04 is turned on, the fifth NMOS transistor KN05 is turned on based on DQS_I, and the second NMOS transistor KN02 is turned off. At this time, the fourth regulating NMOS transistor TN04 pulls down the second terminal potential of the third NMOS transistor N03, and the third regulating NMOS transistor TN03 pulls down the second terminal potential of the fourth NMOS transistor N04. Furthermore, the voltage value of the first reference voltage Vref1 is greater than the voltage value of the second reference voltage Vref2, so the pull-down of the fourth regulating NMOS transistor TN04 is effective. The force is greater than the pull-down capability of the third regulating NMOS transistor TN03, making the drop in the potential of the second terminal of the third NMOS transistor N03 greater than the drop in the potential of the second terminal of the fourth NMOS transistor N04. This is equivalent to reducing the value of the initial reference voltage Vref, so that the rising input data DQ can rise to a voltage value greater than the initial reference voltage Vref in a shorter time. This ensures that, in actual conditions, the potential of the second terminal of the third NMOS transistor N03 is less than the potential of the second terminal of the fourth NMOS transistor N04. For the latch circuit 320, the potential of the first output terminal OUT is greater than the potential of the second output terminal OUTB, and DQ_I is still sampled as high level.

[0243] If the voltage value of the input data DQ is less than the voltage value of the initial reference voltage Vref, based on the previous content, the voltage value of the first adjustment sub-signal SS3 is less than the voltage value of the second adjustment sub-signal SS4. The first switch NMOS transistor KN01 is turned on based on DQS_I, making the potential of the first terminal of the first NMOS transistor N01 greater than the potential of the first terminal of the second NMOS transistor N02. For the latch circuit 320, ideally, the potential of the first output terminal OUT is less than the potential of the second output terminal OUTB, and DQ_I is at a low level.

[0244] If the first bit of data DQ_QB is high, then the fourth feedback signal DQ_QB_OUTT is high and DQ_QB_OUTB is low. The second NMOS transistor KN02 is turned on, the third NMOS transistor KN03 is turned on based on DQS_I, and the fourth NMOS transistor KN04 is turned off. At this time, the second regulating NMOS transistor TN02 pulls down the second terminal potential of the third NMOS transistor N03, and the first regulating NMOS transistor TN01 pulls down the second terminal potential of the fourth NMOS transistor N04. Furthermore, the voltage value of the first reference voltage Vref1 is greater than the voltage value of the second reference voltage Vref2, so the pull-down of the first regulating NMOS transistor TN01 is effective. The force is greater than the pull-down capability of the second regulating NMOS transistor TN02, so that the drop in the potential of the second terminal of the third NMOS transistor N03 is less than the drop in the potential of the second terminal of the fourth NMOS transistor N04. This is equivalent to increasing the value of the initial reference voltage Vref, so that the decreasing input data DQ can drop to a voltage value less than the initial reference voltage Vref in a shorter time. This ensures that the potential of the second terminal of the third NMOS transistor N03 is greater than the potential of the second terminal of the fourth NMOS transistor N04 in actual conditions. For the latch circuit 320, the potential of the first output terminal OUT is less than the potential of the second output terminal OUTB, and DQ_I is still sampled as low level.

[0245] If the first bit of data DQ_QB is low, then the fourth feedback signal DQ_QB_OUTT is low, DQ_QB_OUTB is high, the fourth NMOS transistor KN04 is turned on, the fifth NMOS transistor KN05 is turned on based on DQS_I, and the second NMOS transistor KN02 is turned off. At this time, the fourth regulating NMOS transistor TN04 pulls down the second terminal potential of the third NMOS transistor N03, the third regulating NMOS transistor TN03 pulls down the second terminal potential of the fourth NMOS transistor N04, and the voltage value of the first reference voltage Vref1 is greater than the second reference voltage. The voltage value of Vref2 means that the pull-down capability of the fourth regulating NMOS transistor TN04 is greater than that of the third regulating NMOS transistor TN03. This causes the potential at the second terminal of the third NMOS transistor N03 to drop more than that at the second terminal of the fourth NMOS transistor N04, which is equivalent to reducing the value of the initial reference voltage Vref. However, since the first bit of data DQ_QB is low, the change in the input data DQ is not significant, and DQ_I still needs to be sampled as low. The reduced initial reference voltage Vref does not affect the sampling of the data receiving circuit, and DQ_I is still sampled as low.

[0246] In some embodiments, referring to FIG11, the reset circuit 330 includes:

[0247] The first reset PMOS transistor FP01 has its control terminal connected to the clock terminal of the first sampling circuit 30, its first terminal used to receive the power supply voltage VDD, and its second terminal connected to the first output terminal OUT of the latch circuit 320.

[0248] The second reset PMOS transistor FP02 has its control terminal connected to the clock terminal of the first sampling circuit 30, its first terminal used to receive the power supply voltage VDD, and its second terminal connected to the second output terminal OUTB of the latch circuit 320.

[0249] When the clock signal DQS_I received by the first sampling circuit 30 is low, that is, when the first clock signal DQS_I is invalid, the first output signal DQ_I is not generated at this time. The first switch NMOS transistor KN01, the third switch NMOS transistor KN03 and the fifth switch NMOS transistor KN05 are all turned off, the selection adjustment circuit 330 is turned off, the first reset PMOS transistor FP01 and the second reset PMOS transistor FP02 are both turned on, and the first output terminal OUT and the second output terminal OUTB of the latch circuit 320 are pulled up to the power supply voltage VDD.

[0250] In some embodiments, referring to FIG11, the reset circuit 330 further includes:

[0251] The third reset PMOS transistor FP03 has its control terminal connected to the clock terminal of the first sampling circuit 30. The first terminal is used to receive the power supply voltage VDD, and the second terminal is connected to the second terminal of the third NMOS transistor N03.

[0252] The fourth reset PMOS transistor FP04 has its control terminal connected to the clock terminal of the first sampling circuit 30. The first terminal is used to receive the power supply voltage VDD, and the second terminal is connected to the second terminal of the fourth NMOS transistor N04.

[0253] When the clock signal DQS_I received by the first sampling circuit 30 is low, the third reset PMOS transistor FP03 and the fourth reset PMOS transistor FP04 are both turned on, pulling up the second terminals of the third NMOS transistor N03 and the fourth NMOS transistor N04 in the latch circuit 320 to the power supply voltage VDD, thereby resetting the latch circuit 320.

[0254] In some embodiments, referring to FIG11, the reset circuit 330 further includes:

[0255] The fifth reset PMOS transistor FP05 has its control terminal connected to the clock terminal of the first sampling circuit 30, its second terminal connected to the first output terminal OUT of the latch circuit 320, and its third terminal connected to the second output terminal OUTB of the latch circuit 320.

[0256] When the clock terminal of the first sampling circuit 30 receives a low level DQS_I, the fifth reset PMOS transistor FP05 turns on, pulling the first output terminal OUT and the second output terminal OUTB of the latch circuit 320 to the same potential, thus resetting the latch circuit 320.

[0257] In some embodiments, the first sampling circuit 30, the second sampling circuit 40, the third sampling circuit 60, and the fourth sampling circuit 70 have the same structure. It is understood that the clock and control terminals of the first sampling circuit 30, the second sampling circuit 40, the third sampling circuit 60, and the fourth sampling circuit 70 receive different signals to generate different output signals (DQ_I, DQ_Q, DQ_IB, and DQ_QB), but their internal circuit structures are the same and their working principles are similar, so they will not be described in detail here.

[0258] In some embodiments, as shown in FIG12, the amplifier circuit 80 includes:

[0259] The continuous-time linear equalizer 810 receives input data DQ and an initial reference voltage Vref, and is configured to amplify the voltage difference between the input data DQ and the initial reference voltage Vref in the first stage.

[0260] The second negative capacitor equalizer 820, electrically connected to the continuous-time linear equalizer 810, is configured to amplify the voltage difference between the input data DQ and the initial reference voltage Vref in a second stage, and output the dual-ended signals SS1 / SS2.

[0261] Amplifier circuit 80 senses and amplifies the input signal DQ. Specifically, amplifier circuit 80 employs a two-stage design. First, a continuous-time linear equalizer 810 (CTLE) is used for initial enhancement of the input signal DQ. Next, a second negative capacitor equalizer 820 (NCE) forms the second stage, providing a larger output voltage swing. The amplifier circuit 80, consisting of the CTLE and NCE, forms a variable gain amplifier (VGA), thus meeting the stringent operating requirements of subsequent circuits and improving the overall system efficiency and flexibility. The core task of amplifier circuit 80 is to compensate for attenuation caused by the channel. Since the channel is essentially a low-pass filter, it causes attenuation differences between high and low frequency signals, resulting in uneven signal attenuation across the frequency spectrum. By using VGA, this attenuation difference can be effectively compensated, restoring the integrity of the transmitted signal. VGA exhibits high-pass filter-like behavior through its gain curve, effectively compensating for signal loss caused by channel attenuation and ensuring the quality of the input signal.

[0262] In some embodiments, as shown in FIG12, the continuous-time linear equalizer 810 includes: a thirteenth NMOS transistor N13, whose control terminal receives input data DQ, and whose second terminal is connected to the first terminal of a first resistor R1; a fourteenth NMOS transistor N14, whose control terminal receives an initial reference voltage Vref, and whose second terminal is connected to the first terminal of a second resistor R2; the second terminal of the first resistor R1 is connected to the power supply voltage VDD; the second terminal of the second resistor R2 is connected to the power supply voltage VDD; the first terminal of a third resistor R3 is connected to the first terminal of the thirteenth NMOS transistor N13, and the second terminal is connected to the first terminal of the fourteenth NMOS transistor N14; the first terminal of the second capacitor C2 is connected to the tenth NMOS transistor N14. The first terminal of the three NMOS transistors N13 and N14 are connected to each other. The first terminal of the fourteenth NMOS transistor N14 is connected to the second terminal of the thirteenth NMOS transistor N13. The first terminal of the fifth resistor R5 is connected to the second terminal of the fourteenth NMOS transistor N14, and the second terminal is connected to the second terminal of the fourth resistor R4. The control terminal of the eleventh NMOS transistor N11 is connected to the second terminal of the fourth resistor R4, with the first terminal grounded and the second terminal connected to the first terminal of the thirteenth NMOS transistor N13. The control terminal of the twelfth NMOS transistor N12 is connected to the second terminal of the fourth resistor R4, with the first terminal grounded and the second terminal connected to the first terminal of the fourteenth NMOS transistor N14. R4 and R5 are used as the common-mode bias voltages for N11 and N12. The parallel connection of R3 and C2 provides a zero point at high frequencies, causing the frequency spectrum of the continuous-time linear equalizer 810 to exhibit a boost effect at high frequencies, thereby increasing the high-frequency gain to offset the frequency loss introduced by the transmission channel.

[0263] In some embodiments, as shown in FIG12, the second negative capacitor equalizer 820 includes: a fifteenth NMOS transistor N15, the control terminal of which is connected to the second terminal of the fourth resistor R4, and the first terminal of which is grounded; a sixteenth NMOS transistor N16, the control terminal of which is connected to the second terminal of the thirteenth NMOS transistor N13, the first terminal of which is connected to the second terminal of the fifteenth NMOS transistor N15, the second terminal of which is connected to the first terminal of the sixth resistor R6, and outputs SS1 in the two-terminal signal; a seventeenth NMOS transistor N17, the control terminal of which is connected to the second terminal of the fourteenth NMOS transistor N14, the first terminal of which is connected to the second terminal of the fifteenth NMOS transistor N15, the second terminal of which is connected to the first terminal of the seventh resistor R7, and outputs SS2 in the two-terminal signal; the second terminal of the sixth resistor R6 is connected to the power supply voltage VDD; the second terminal of the seventh resistor R7 is connected to the power supply... Voltage VDD; the control terminal of the eighteenth NMOS transistor N18 is connected to the second terminal of the fourth resistor R4, and the first terminal is grounded; the control terminal of the nineteenth NMOS transistor N19 is connected to the second terminal of the fourth resistor R4, and the first terminal is grounded; the first terminal of the third capacitor C3 is connected to the second terminal of the eighteenth NMOS transistor N18, and the second terminal is connected to the second terminal of the nineteenth NMOS transistor N19; the control terminal of the twentieth NMOS transistor N20 is connected to the second terminal of the seventeenth NMOS transistor N17, the first terminal is connected to the second terminal of the sixteenth NMOS transistor N16, and the second terminal is connected to the first terminal of the third capacitor C3; the control terminal of the twenty-first NMOS transistor N21 is connected to the second terminal of the sixteenth NMOS transistor N16, the first terminal is connected to the second terminal of the seventeenth NMOS transistor N17, and the second terminal is connected to the second terminal of the third capacitor C3. This configuration helps to increase high-frequency gain and broaden the operating bandwidth of the circuit.

[0264] The data receiving circuit provided in this embodiment includes: an amplification circuit, configured to receive input data and an initial reference voltage, amplify the voltage difference between the input data and the initial reference voltage, and output a dual-ended signal; a first adjustment circuit, configured to receive the dual-ended signal, amplify the voltage difference between the dual-ended signal, and, when the signal at a first clock terminal or a second clock terminal is valid, adjust the amplification result based on the signals at a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal to perform decision feedback equalization and output a first dual-ended adjustment signal; and a first sampling circuit, configured to, when the signal received at the .... The control terminal signal amplifies and latches the voltage difference of the first dual-ended adjustment signal to generate a first output signal. The second sampling circuit receives the first dual-ended adjustment signal and is configured to amplify and latch the voltage difference of the first dual-ended adjustment signal based on the control terminal signal when the signal received at the clock terminal is valid, to generate a third output signal. The first clock terminal of the first adjustment circuit receives a fourth clock signal, the second clock terminal receives a second clock signal, the clock terminal of the first sampling circuit receives the first clock signal, and the clock terminal of the second sampling circuit receives the third clock signal. The phases of the first, second, third, and fourth clock signals differ by 90 degrees sequentially. Thus, the first adjustment circuit corresponds to the first and second sampling circuits; that is, one adjustment circuit corresponds to two sampling circuits. By multiplexing the DFE (Distributed Electronic Factor), the number of adjustment circuits is reduced, thereby improving inter-symbol interference while reducing circuit area and power consumption.

[0265] It should be noted that the features disclosed in the data receiving circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new data receiving circuit embodiments.

[0266] Another embodiment of this disclosure provides a memory 90, including the data receiving circuit 10 provided in the above embodiments, which at least helps to reduce the circuit area and reduce the circuit power consumption while improving the inter-symbol interference problem.

[0267] Memory can be a storage cell or device based on semiconductor devices or components. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0268] As can be seen from the above analysis, while improving the inter-symbol interference problem, the area of ​​the data receiving circuit is compressed as much as possible, without affecting the storage capacity of the memory; in addition, the reduction in the number of circuits also reduces the power consumption of the circuit.

[0269] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0270] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0271] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0272] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0273] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0274] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0275] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A data receiving circuit, characterized in that, include: An amplifier circuit receives input data and an initial reference voltage, and is configured to amplify the voltage difference between the input data and the initial reference voltage, and output a two-terminal signal. The first adjustment circuit receives the dual-ended signal and is configured to amplify the voltage difference between the dual-ended signals. When the signal at the first clock terminal or the second clock terminal is in an active state, the circuit adjusts the amplification based on the signals at the first control terminal, the second control terminal, the third control terminal, and the fourth control terminal to perform decision feedback equalization and output the first dual-ended adjustment signal. The first sampling circuit receives the first dual-ended adjustment signal and is configured to, when the signal received at the clock terminal is in an active state, amplify and latch the voltage difference of the first dual-ended adjustment signal based on the signal at the control terminal to generate a first output signal. The second sampling circuit receives the first dual-ended adjustment signal and is configured to, when the signal received at the clock end is in an active state, amplify and latch the voltage difference of the first dual-ended adjustment signal based on the signal at the control end to generate a third output signal. In this circuit, the first clock terminal of the first adjustment circuit receives the fourth clock signal, the second clock terminal receives the second clock signal, the clock terminal of the first sampling circuit receives the first clock signal, and the clock terminal of the second sampling circuit receives the third clock signal. The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially 90 degrees out of phase.

2. The data receiving circuit according to claim 1, characterized in that, When the signal at the first clock terminal of the first adjustment circuit is in an active state, the signal at the first control terminal responds to the first tap coefficient, the signal at the second control terminal responds to the second tap coefficient, the signal at the third control terminal responds to the third tap coefficient, and the signal at the fourth control terminal responds to the fourth tap coefficient, and a decision feedback equalization is performed. When the signal at the second clock terminal of the first adjustment circuit is in an active state, the signal at the first control terminal responds to the third tap coefficient, the signal at the second control terminal responds to the fourth tap coefficient, the signal at the third control terminal responds to the first tap coefficient, and the signal at the fourth control terminal responds to the second tap coefficient, thereby performing decision feedback equalization.

3. The data receiving circuit according to claim 1, characterized in that, Also includes: The second adjustment circuit receives the dual-ended signal and is configured to amplify the voltage difference between the dual-ended signals. When the signal at the first clock terminal or the second clock terminal is in an active state, the circuit adjusts the amplification result based on the signals at the first control terminal, the second control terminal, the third control terminal, and the fourth control terminal to perform decision feedback equalization and output a second dual-ended adjustment signal. The third sampling circuit receives the second double-ended adjustment signal and is configured to, when the signal received at the clock terminal is in an active state, amplify and latch the voltage difference of the second double-ended adjustment signal based on the signal at the control terminal to generate a second output signal. The fourth sampling circuit receives the second double-ended adjustment signal and is configured to, when the signal received at the clock terminal is in an active state, amplify and latch the voltage difference of the second double-ended adjustment signal based on the signal at the control terminal to generate a fourth output signal. In this circuit, the first clock terminal of the second adjustment circuit receives a first clock signal, the second clock terminal receives a third clock signal, the clock terminal of the third sampling circuit receives the second clock signal, and the clock terminal of the fourth sampling circuit receives the fourth clock signal.

4. The data receiving circuit according to claim 3, characterized in that, The first control terminal of the first adjustment circuit receives a fourth feedback signal, the second control terminal receives a third feedback signal, the third control terminal receives a second feedback signal, and the fourth control terminal receives a first feedback signal. The first control terminal of the second adjustment circuit receives the first feedback signal, the second control terminal receives the fourth feedback signal, the third control terminal receives the third feedback signal, and the fourth control terminal receives the second feedback signal; the control terminal of the first sampling circuit receives the fourth feedback signal; the control terminal of the second sampling circuit receives the second feedback signal; the control terminal of the third sampling circuit receives the first feedback signal; and the control terminal of the fourth sampling circuit receives the third feedback signal; wherein, the first feedback signal originates from the first output signal, the second feedback signal originates from the second output signal, the third feedback signal originates from the third output signal, and the fourth feedback signal originates from the fourth output signal.

5. The data receiving circuit according to claim 3, characterized in that, The first adjustment circuit has the same structure as the second adjustment circuit.

6. The data receiving circuit according to claim 2, characterized in that, The first adjustment circuit includes: The first amplification module receives the dual-ended signal and is configured to amplify the voltage difference between the dual-ended signals, output a first adjustment sub-signal at a first node, and output a second adjustment sub-signal at a second node. The first dual-ended adjustment signal includes the first adjustment sub-signal and the second adjustment signal. The first decision feedback equalization module, electrically connected to the first node and the second node, is configured to adjust the voltage difference between the first node and the second node by responding to the first tap coefficient when the signal at the first clock terminal of the first adjustment circuit is in an active state, or by responding to the third tap coefficient when the signal at the second clock terminal of the first adjustment circuit is in an active state. The second decision feedback equalization module, electrically connected to the first node and the second node, is configured to adjust the voltage difference between the first node and the second node by responding to the second tap coefficient when the signal at the first clock terminal of the first adjustment circuit is in an active state, or by responding to the fourth tap coefficient when the signal at the second clock terminal of the first adjustment circuit is in an active state. The third decision feedback equalization module, electrically connected to the first node and the second node, is configured to adjust the voltage difference between the first node and the second node by responding to the third tap coefficient when the signal at the first clock terminal of the first adjustment circuit is in an active state, or by responding to the first tap coefficient when the signal at the second clock terminal of the first adjustment circuit is in an active state. The fourth decision feedback equalization module, electrically connected to the first node and the second node, is configured to adjust the voltage difference between the first node and the second node by responding to the fourth tap coefficient when the signal at the first clock terminal of the first adjustment circuit is in an active state, or by responding to the second tap coefficient when the signal at the second clock terminal of the first adjustment circuit is in an active state.

7. The data receiving circuit according to claim 6, characterized in that, The first decision feedback equalization module includes: The first selection unit is configured such that a first input terminal receives a signal from a first control terminal of the first adjustment circuit, a second input terminal receives a signal that is inversely related to the signal from the first input terminal, a control terminal receives an equalization direction control signal, and in response to the equalization direction control signal, a first output terminal outputs the signal from the first input terminal, and a second output terminal outputs the signal from the second input terminal, or a first output terminal outputs the signal from the second input terminal, and a second output terminal outputs the signal from the first input terminal. The first MOSFET has its first terminal connected to the first variable current source and its control terminal connected to the first clock terminal of the first adjustment circuit. The second MOSFET has its first terminal connected to the second variable current source and its control terminal connected to the second clock terminal of the first adjustment circuit. The third MOSFET has its first end connected to the second end of the first MOSFET, its second end connected to the first node, and its control end connected to the first output terminal of the first selection unit. The fourth MOSFET has its first terminal connected to the second terminal of the second MOSFET, its second terminal connected to the second node, and its control terminal connected to the second output terminal of the first selection unit. The current value of the first variable current source responds to the first tap coefficient, and the current value of the second variable current source responds to the third tap coefficient.

8. The data receiving circuit according to claim 6, characterized in that, The second decision feedback equalization module includes: The second selection unit is configured such that a first input terminal receives a signal from a second control terminal of the first adjustment circuit, the signal received at the second input terminal is inversely phase to the signal at the first input terminal, the control terminal receives an equalization direction control signal, and in response to the equalization direction control signal, a first output terminal outputs the signal at the first input terminal, and a second output terminal outputs the signal at the second input terminal, or a first output terminal outputs the signal at the second input terminal, and a second output terminal outputs the signal at the first input terminal. The fifth MOSFET has its first terminal connected to the third variable current source and its control terminal connected to the first clock terminal of the first adjustment circuit. The sixth MOSFET has its first terminal connected to the fourth variable current source and its control terminal connected to the second clock terminal of the first adjustment circuit. The seventh MOSFET has its first terminal connected to the second terminal of the fifth MOSFET, its second terminal connected to the first node, and its control terminal connected to the first output terminal of the second selection unit. The eighth MOSFET has its first terminal connected to the second terminal of the sixth MOSFET, its second terminal connected to the second node, and its control terminal connected to the second output terminal of the second selection unit. The current value of the third variable current source responds to the second tap coefficient, and the current value of the fourth variable current source responds to the fourth tap coefficient. The third decision feedback equalization module includes: The third selection unit is configured such that a first input terminal receives a signal from the third control terminal of the first adjustment circuit, a second input terminal receives a signal that is inverted from the signal at the first input terminal, a control terminal receives an equalization direction control signal, and in response to the equalization direction control signal, a first output terminal outputs the signal at the first input terminal, and a second output terminal outputs the signal at the second input terminal, or a first output terminal outputs the signal at the second input terminal, and a second output terminal outputs the signal at the first input terminal. The ninth MOSFET has its first terminal connected to the fifth variable current source and its control terminal connected to the first clock terminal of the first adjustment circuit. The tenth MOSFET has its first terminal connected to the sixth variable current source and its control terminal connected to the second clock terminal of the first adjustment circuit. The eleventh MOSFET has its first terminal connected to the second terminal of the ninth MOSFET, its second terminal connected to the first node, and its control terminal connected to the first output terminal of the third selection unit. The twelfth MOSFET has its first terminal connected to the second terminal of the tenth MOSFET, its second terminal connected to the second node, and its control terminal connected to the second output terminal of the third selection unit. The current value of the fifth variable current source responds to the third tap coefficient, and the current value of the sixth variable current source responds to the first tap coefficient. The fourth decision feedback equalization module includes: The fourth selection unit is configured such that a first input terminal receives a signal from the fourth control terminal of the first adjustment circuit, a second input terminal receives a signal that is inverted from the signal at the first input terminal, a control terminal receives an equalization direction control signal, and in response to the equalization direction control signal, a first output terminal outputs the signal at the first input terminal, and a second output terminal outputs the signal at the second input terminal, or a first output terminal outputs the signal at the second input terminal, and a second output terminal outputs the signal at the first input terminal. The thirteenth MOSFET has its first terminal connected to the seventh variable current source and its control terminal connected to the first clock terminal of the first adjustment circuit. The fourteenth MOSFET has its first terminal connected to the eighth variable current source and its control terminal connected to the second clock terminal of the first adjustment circuit. The fifteenth MOSFET has its first terminal connected to the second terminal of the thirteenth MOSFET, its second terminal connected to the first node, and its control terminal connected to the first output terminal of the fourth selection unit. The sixteenth MOSFET has its first terminal connected to the second terminal of the fourteenth MOSFET, its second terminal connected to the second node, and its control terminal connected to the second output terminal of the fourth selection unit. The current value of the seventh variable current source responds to the fourth tap coefficient, and the current value of the eighth variable current source responds to the second tap coefficient.

9. The data receiving circuit according to claim 6, characterized in that, The first adjustment circuit further includes a first negative capacitor equalizer, which is electrically connected to the first node and the second node to increase the gain of the first adjustment circuit.

10. The data receiving circuit according to claim 1, characterized in that, The first sampling circuit also receives a first reference voltage and a second reference voltage, wherein the voltage value of the first reference voltage is greater than the voltage value of the second reference voltage; The step of amplifying and latching the voltage difference of the first dual-terminal adjustment signal based on the signal from the control terminal to generate the first output signal includes: based on the signal from the control terminal, selecting to increase or decrease the voltage difference between the first dual-terminal adjustment signal by equivalently increasing or decreasing the voltage difference between the first reference voltage and the second reference voltage, amplifying and latching the voltage difference of the first dual-terminal adjustment signal to generate the first output signal.

11. The data receiving circuit according to claim 10, characterized in that, The first dual-ended adjustment signal includes a first adjustment sub-signal and a second adjustment sub-signal; the first sampling circuit includes: The selection adjustment circuit is configured to, when the signal at the clock terminal is active, select, based on the signal at the control terminal, to adjust the branch current of the branch where the first adjustment sub-signal is located by the first reference voltage, and to adjust the branch current of the branch where the second adjustment sub-signal is located by the second reference voltage. Alternatively, the branch current of the branch containing the second adjustment sub-signal can be adjusted by the first reference voltage, and the branch current of the branch containing the first adjustment sub-signal can be adjusted by the second reference voltage. A latching circuit, electrically connected to the selection adjustment circuit, is configured to amplify and latch the voltage difference of the first dual-ended adjustment signal to generate the first output signal.

12. The data receiving circuit according to claim 11, characterized in that, The selection adjustment circuit includes: The first NMOS transistor has a control terminal for receiving the first adjustment sub-signal and a first terminal connected to the latch circuit. The second NMOS transistor has a control terminal for receiving the second adjustment sub-signal, a first terminal connected to the latch circuit, and a second terminal connected to the second terminal of the first NMOS transistor. The first switching NMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal electrically connected to the second terminal of the first NMOS transistor, and its second terminal grounded. The first adjustment NMOS transistor has a control terminal used to receive the first reference voltage, and its first terminal is connected to the first terminal of the second NMOS transistor. The second adjustment NMOS transistor has a control terminal for receiving the second reference voltage, a first terminal connected to the first terminal of the first NMOS transistor, and a second terminal connected to the second terminal of the first adjustment NMOS transistor. The second switching NMOS transistor has its control terminal connected to the control terminal of the first sampling circuit, and its first terminal connected to the second terminal of the second adjustment NMOS transistor. The third switching NMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal connected to the second terminal of the second switching NMOS transistor, and its second terminal grounded. The third adjustment NMOS transistor has a control terminal used to receive the second reference voltage, and its first terminal is connected to the first terminal of the second NMOS transistor. The fourth adjusting NMOS transistor has a control terminal for receiving the first reference voltage, a first terminal connected to the first terminal of the first NMOS transistor, and a second terminal connected to the second terminal of the third adjusting NMOS transistor. The fourth switching NMOS transistor has a control terminal used to receive the inverted signal of the control terminal signal of the first sampling circuit, and its first terminal is connected to the second terminal of the fourth adjustment NMOS transistor. The fifth NMOS switch has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal connected to the second terminal of the fourth NMOS switch, and its second terminal grounded.

13. The data receiving circuit according to claim 11, characterized in that, The latching circuit includes: The first PMOS transistor has its first terminal used to receive the power supply voltage. The second PMOS transistor has its first terminal used to receive the power supply voltage. The third NMOS transistor has its control terminal connected to the control terminal of the first PMOS transistor, its first terminal connected to the second terminal of the first PMOS transistor, and its second terminal connected to the first terminal of the first NMOS transistor. The fourth NMOS transistor has its control terminal connected to the control terminal of the second PMOS transistor, its first terminal connected to the second terminal of the second PMOS transistor, and its second terminal connected to the first terminal of the second NMOS transistor. The control terminal of the third NMOS transistor is also connected to the first terminal of the fourth NMOS transistor to serve as the first output terminal of the latch circuit, and the control terminal of the fourth NMOS transistor is also connected to the first terminal of the third NMOS transistor to serve as the second output terminal of the latch circuit.

14. The data receiving circuit according to claim 13, characterized in that, The first sampling circuit further includes a reset circuit connected to the clock terminal of the first sampling circuit and the latch circuit, used to reset the first output terminal and the second output terminal of the latch circuit in response to the clock terminal signal of the first sampling circuit.

15. The data receiving circuit according to claim 14, characterized in that, The reset circuit includes: The first reset PMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal used to receive the power supply voltage, and its second terminal connected to the first output terminal of the latch circuit. The second reset PMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal used to receive the power supply voltage, and its second terminal connected to the second output terminal of the latch circuit.

16. The data receiving circuit according to claim 15, characterized in that, The reset circuit also includes: The third reset PMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal used to receive the power supply voltage, and its second terminal connected to the second terminal of the third NMOS transistor. The fourth reset PMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its first terminal used to receive the power supply voltage, and its second terminal connected to the second terminal of the fourth NMOS transistor.

17. The data receiving circuit according to claim 15, characterized in that, The reset circuit also includes: The fifth reset PMOS transistor has its control terminal connected to the clock terminal of the first sampling circuit, its second terminal connected to the first output terminal of the latch circuit, and its third terminal connected to the second output terminal of the latch circuit.

18. The data receiving circuit according to claim 3, characterized in that, The first sampling circuit, the second sampling circuit, the third sampling circuit, and the fourth sampling circuit have the same structure.

19. The data receiving circuit according to claim 1, characterized in that, The amplifier circuit includes: A continuous-time linear equalizer, receiving the input data and the initial reference voltage, is configured to amplify the voltage difference between the input data and the initial reference voltage in the first stage. The second negative capacitor equalizer, electrically connected to the continuous-time linear equalizer, is configured to amplify the voltage difference between the input data and the initial reference voltage in a second stage, and output the dual-ended signal.

20. A memory, characterized in that, Includes the data receiving circuit as described in any one of claims 1 to 19.

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