Pixel driving circuit, display substrate, and display apparatus
By using a third and fourth transistor connected in series to control the input in the pixel driving circuit, the problem of unstable image quality in the prior art is solved, and a stable display effect is achieved where the driving current is not affected by the transistor threshold voltage.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2025-12-22
- Publication Date
- 2026-07-09
AI Technical Summary
Existing pixel driving circuits cannot effectively maintain stable image quality.
The third and fourth transistors connected in series in the compensation module are used to control the input, and the control electrode of one of the transistors shares a signal with the transistor in the reset module to prevent the compensation module signal from interfering with the drive module during high-frequency reset.
It effectively prevents the compensation module signal from interfering with the drive module during high-frequency reset, ensuring the uniformity of image brightness output from the display panel, unaffected by the threshold voltage of the drive transistor, and maintaining stable image quality.
Smart Images
Figure CN2025144184_09072026_PF_FP_ABST
Abstract
Description
Pixel driving circuit, display substrate and display device Technical Field
[0001] This invention relates to the field of display technology, and in particular to a pixel driving circuit, a display substrate, and a display device. Background Technology
[0002] AMOLED (Active Matrix Organic Light Emitting Diode) is one of the hottest research topics in the field of displays today. Compared with liquid crystal displays (LCDs), OLEDs have advantages such as low energy consumption, low production cost, self-emissiveness, wide viewing angle, and fast response speed. Currently, OLED displays are beginning to replace traditional LCD displays in mobile phones, PDAs, digital cameras, and other display fields. Among them, the pixel driving circuit is the core technology of AMOLED displays and has significant research value.
[0003] Existing pixel driving circuits cannot maintain the image quality of the displayed image well during operation. Summary of the Invention
[0004] The purpose of this application is to provide a pixel driving circuit, a display substrate, and a display device that can provide stable image quality.
[0005] This application discloses a pixel driving circuit, comprising: a light-emitting unit; a driving module configured to control the light emission of the light-emitting unit under the control of a data signal; a compensation module configured to compensate the data signal; the compensation module includes a third transistor and a fourth transistor, the first terminal of the third transistor being connected to the driving module, the second terminal of the third transistor being connected to the first terminal of the fourth transistor, and the second terminal of the fourth transistor being connected to a constant voltage source; the control terminal of one of the third transistor and the fourth transistor being connected to a first control signal terminal, and the control terminal of the other transistor being connected to a second control signal terminal; and a reset module configured to reset the pixel driving circuit; the reset module includes an eighth transistor, the first terminal of the eighth transistor being connected to a constant voltage source, the second terminal being connected to the light-emitting unit, and the control terminal being connected to the first control signal terminal.
[0006] Optionally, the driving module includes a first transistor, wherein a first electrode of the first transistor is connected to a third node, a second electrode is connected to a second node, and a control electrode is connected to a first node; the first electrode of the third transistor is connected to the third node.
[0007] Optionally, the reset module further includes a ninth transistor, the first terminal of which is connected to a constant voltage source, the second terminal of which is connected to the first node, and the control terminal of which is connected to the second control signal terminal.
[0008] Optionally, the compensation module further includes a second capacitor, the first terminal of which is connected to the second node and the second terminal of which is connected to the first node; the pixel driving circuit further includes a data writing module, the data writing module including a second transistor, the first terminal of which is connected to a data signal terminal and the second terminal of which is connected to the first node, and the control terminal of which is connected to a third control signal terminal.
[0009] Optionally, the pixel driving circuit further includes a light-emitting control module; the light-emitting control module includes a sixth transistor and a seventh transistor; the first electrode of the seventh transistor is connected to the light-emitting unit, the second electrode is connected to the third node, and the control electrode is connected to the first light-emitting control signal terminal; the first electrode of the sixth transistor is connected to the second power supply signal terminal, the second electrode is connected to the second node, and the control electrode is connected to the second light-emitting control signal terminal.
[0010] Optionally, the pixel driving circuit further includes a light-emitting control module; the light-emitting control module includes a sixth transistor and a seventh transistor; the first electrode of the seventh transistor is connected to the light-emitting unit, and the second electrode is connected to the third node; the first electrode of the sixth transistor is connected to a second power supply signal terminal, and the second electrode is connected to the second node; the control electrodes of the sixth transistor and the seventh transistor are connected to the same light-emitting control signal terminal; the reset module further includes a tenth transistor, the first electrode of the tenth transistor is connected to a constant voltage source, the second electrode is connected to the second node, and the control electrode is connected to a fourth control signal terminal.
[0011] Optionally, the difference between the potential of the constant voltage source connected to the first terminal of the ninth transistor and the potential of the second power supply signal terminal is greater than the threshold voltage of the third transistor.
[0012] Optionally, the potential difference between the constant voltage source connected to the first terminal of the ninth transistor and the constant voltage source connected to the first terminal of the tenth transistor is greater than the threshold voltage of the third transistor.
[0013] Optionally, the reset module further includes a ninth transistor, the first terminal of which is connected to a constant voltage source, the second terminal of which is connected to a fifth node, and the control terminal of which is connected to the second control signal terminal; the compensation module further includes a fifth transistor, the first terminal of which is connected to the second node, the second terminal of which is connected to the first node, and the control terminal of which is connected to the second control signal terminal; the pixel driving circuit further includes a data writing module, the data writing module including a second transistor and a first capacitor, the first terminal of which is connected to a data signal terminal, the second terminal of which is connected to the fifth node, and the control terminal of which is connected to a third control signal terminal; the first terminal of the first capacitor is connected to the fifth node, and the second terminal of which is connected to the first node.
[0014] Optionally, the pixel driving circuit further includes a light-emitting control module; the light-emitting control module includes a sixth transistor and a seventh transistor; the first electrode of the seventh transistor is connected to the light-emitting unit, the second electrode is connected to the third node, and the control electrode is connected to the first light-emitting control signal terminal; the first electrode of the sixth transistor is connected to the second power supply signal terminal, the second electrode is connected to the second node, and the control electrode is connected to the second light-emitting control signal terminal.
[0015] Optionally, the pixel driving circuit further includes a light-emitting control module; the light-emitting control module includes a sixth transistor and a seventh transistor; the first electrode of the seventh transistor is connected to the light-emitting unit, and the second electrode is connected to the third node; the first electrode of the sixth transistor is connected to the second power supply signal terminal, and the second electrode is connected to the second node; the control electrodes of the sixth transistor and the seventh transistor are connected to the same light-emitting control signal terminal; the reset module further includes a tenth transistor, the first electrode of the tenth transistor is connected to a constant voltage source, the second electrode is connected to the first node, and the control electrode is connected to the fourth control signal terminal.
[0016] Optionally, the pixel driving circuit further includes a light-emitting control module; the light-emitting control module includes a sixth transistor and a seventh transistor; the first electrode of the seventh transistor is connected to the light-emitting unit, and the second electrode is connected to the third node; the first electrode of the sixth transistor is connected to the second power supply signal terminal, and the second electrode is connected to the second node; the control electrodes of the sixth transistor and the seventh transistor are connected to the same light-emitting control signal terminal; the reset module further includes a tenth transistor, the first electrode of the tenth transistor is connected to a constant voltage source, the second electrode is connected to the second node, and the control electrode is connected to the fourth control signal terminal.
[0017] Optionally, the driving module includes a first transistor, wherein a first electrode of the first transistor is connected to a third node, a second electrode is connected to a second node, and a control electrode is connected to a first node; the first electrode of the third transistor is connected to the second node.
[0018] Optionally, the compensation module further includes a fifth transistor, wherein the first electrode of the fifth transistor is connected to the third node, the second electrode is connected to the first node, and the control electrode is connected to the second control signal terminal.
[0019] Optionally, the pixel driving circuit further includes a fourth capacitor, the first terminal of which is connected to a constant voltage source, and the second terminal of which is connected to the fifth node.
[0020] This application also provides a display substrate, which includes the pixel driving circuit described above.
[0021] This application also provides a display device, which includes the display substrate described above.
[0022] Compared with related technologies, the compensation module of this application uses a third transistor and a fourth transistor connected in series to control the input. The control electrode of one of the transistors shares a signal with the transistor of the reset module, which effectively prevents the compensation module signal from interfering with the drive module during high-frequency reset.
[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description
[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the specification, serve to explain the principles of this specification.
[0025] Figure 1 is a schematic diagram of a pixel driving circuit in one embodiment of this application.
[0026] Figure 2 is a timing diagram of the circuit shown in Figure 1 in one embodiment of this application.
[0027] Figure 3 is a schematic diagram of a pixel driving circuit in one embodiment of this application.
[0028] Figure 4 is a timing diagram of the circuit shown in Figure 3 in one embodiment of this application.
[0029] Figure 5 is a schematic diagram of a pixel driving circuit in one embodiment of this application.
[0030] Figure 6 is a timing diagram of the circuit shown in Figure 5 in one embodiment of this application.
[0031] Figure 7 is a schematic diagram of a pixel driving circuit in one embodiment of this application.
[0032] Figure 8 is a timing diagram of the circuit shown in Figure 7 in one embodiment of this application.
[0033] Figure 9 is a schematic diagram of a pixel driving circuit in one embodiment of this application.
[0034] Figure 10 is a timing diagram of the circuit shown in Figure 9 in one embodiment of this application.
[0035] Figure 11 is a schematic diagram of a pixel driving circuit in one embodiment of this application.
[0036] Figure 12 is a timing diagram of the circuit shown in Figure 11 in one embodiment of this application. Detailed Implementation
[0037] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.
[0038] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movements between components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.
[0039] As shown in Figure 1, this application provides a pixel driving circuit, which includes a driving module 10, a compensation module 30, a reset module 50, and a light-emitting unit 60.
[0040] The driving module 10 is configured to control the light emission of the light-emitting unit 60 under the control of the data signal. The compensation module 30 is configured to compensate the data signal. The compensation module 30 includes a third transistor T3 and a fourth transistor T4. The first terminal of the third transistor T3 is connected to the driving module 10, the second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4, and the second terminal of the fourth transistor T4 is connected to a constant voltage source. The control terminal of one of the third transistor T3 and the fourth transistor T4 is connected to the first control signal terminal GB, and the control terminal of the other is connected to the second control signal terminal GW.
[0041] The reset module 50 is configured to reset the pixel driving circuit. The reset module 50 includes an eighth transistor T8, the first terminal of which is connected to a constant voltage source, the second terminal of which is connected to the light-emitting unit 60, and the control terminal of which is connected to the first control signal terminal GB.
[0042] The compensation module of this application uses a series-connected third and fourth transistor for control input. The control electrode of one of the transistors shares a signal with the transistor of the reset module, which effectively prevents the compensation module signal from interfering with the drive module during high-frequency reset.
[0043] The following will provide a detailed description of various embodiments of this application that conform to the above-described inventive concept.
[0044] The signal terminals connected to the pixel driving circuit provided in this application include a first power signal terminal ELVDD, a second power signal terminal ELVSS, a first reference signal terminal Vref, a light emission control signal terminal EM, a first light emission control signal terminal EM1, a second light emission control signal terminal EM2, a data signal terminal Vdata, a first control signal terminal GB, a second control signal terminal GC, a third control signal terminal GW, a fourth control signal terminal GI, a first reset signal terminal Vint1, and a second reset signal terminal Vint2. Each of these signal terminals is configured to output a corresponding signal to the pixel driving circuit. The first power signal, the second power signal, the first reference signal, the first reset signal, and the second reset signal are signals with constant potentials. The light emission control signal, the first light emission control signal, the second light emission control signal, the data signal, the first control signal, the second control signal, the third control signal, and the fourth control signal are signals with variable potentials. The light emission control signal, the first light emission control signal, the second light emission control signal, the first control signal, the second control signal, the third control signal, and the fourth control signal are each emitted by multiple sets of shift register units located at the bezel of the display panel, with each signal corresponding to one set of shift register units. The data signal is emitted by the source drive circuit located at the bezel of the display panel.
[0045] Unless otherwise specified, the transistors used in this application can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of a transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.
[0046] In actual operation, when the transistor is a bipolar junction transistor (BJT), the control electrode can be the base, the first electrode can be the collector, and the second electrode can be the emitter; or, the control electrode can be the base, the first electrode can be the emitter, and the second electrode can be the collector.
[0047] In practical operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; or, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain. In the embodiments of this application, the transistors are all thin-film transistors.
[0048] As shown in Figure 1, this application provides a pixel driving circuit, which includes a driving module 10, a data writing module 20, a compensation module 30, a light emission control module 40, a reset module 50, and a light emission unit 60.
[0049] The driving module 10 is configured to control the light emission of the light-emitting unit 60 under the control of the data signal. The data writing module 20 is configured to write data signals to the driving module 10. The compensation module 30 is configured to compensate the data signal. The light emission control module 40 is configured to control the light emission of the light-emitting unit 60. The reset module 50 is configured to reset the pixel driving circuit.
[0050] As shown in Figure 1, Figure 1 is a circuit diagram of a pixel driving circuit in an optional embodiment. The driving module 10 may include a first transistor T1, the first electrode of the first transistor T1 is connected to the third node N3, the second electrode of the first transistor T1 is connected to the second node N2, and the control electrode of the first transistor T1 is connected to the first node N1.
[0051] The data writing module 20 may include a second transistor T2, the first terminal of the second transistor T2 is connected to the data signal terminal Vdata, the second terminal of the second transistor T2 is connected to the first node N1, and the control terminal of the second transistor T2 is connected to the third control signal terminal GW.
[0052] The compensation module 30 may include a third transistor T3, a fourth transistor T4, and a second capacitor C2. The first terminal of the third transistor T3 is connected to the driving module 10, the second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4, and the second terminal of the fourth transistor T4 is connected to a constant voltage source. The control terminal of one of the third transistor T3 and the fourth transistor T4 is connected to the first control signal terminal GB, and the control terminal of the other is connected to the second control signal terminal GC. In this embodiment, the connection between the control terminal of the third transistor T3 and the second control signal terminal GC, and the connection between the control terminal of the fourth transistor T4 and the first control signal terminal GB, are used as an example. The first terminal of the second capacitor C2 is connected to the second node N2, and the second terminal is connected to the first node N1. Specifically, the first terminal of the third transistor T3 is connected to the third node N3. The second terminal of the fourth transistor T4 may be connected to the first power supply signal terminal ELVDD, the first reference signal terminal Vref, the first reset signal terminal Vint1, or other constant voltage sources. In this embodiment, the second terminal of the fourth transistor T4 is connected to the first power supply signal terminal ELVDD.
[0053] The light-emitting control module 40 may include a sixth transistor T6 and a seventh transistor T7. The first terminal of the seventh transistor T7 is connected to the light-emitting unit 60, the second terminal of the seventh transistor T7 is connected to the third node N3, and the control terminal of the seventh transistor T7 is connected to the first light-emitting control signal terminal EM1. The first terminal of the sixth transistor T6 is connected to the second power supply signal terminal ELVSS, the second terminal of the sixth transistor T6 is connected to the second node N2, and the control terminal of the sixth transistor T6 is connected to the second light-emitting control signal terminal EM2. Specifically, the first terminal of the seventh transistor T7 is connected to the fourth node N4.
[0054] The reset module 50 may include an eighth transistor T8 and a ninth transistor T9. The first terminal of the eighth transistor T8 is connected to a constant voltage source, the second terminal of the eighth transistor T8 is connected to the light-emitting unit 60, and the control terminal of the eighth transistor T8 is connected to the first control signal terminal GB. The first terminal of the ninth transistor T9 is connected to a constant voltage source, the second terminal of the ninth transistor T9 is connected to the first node N1, and the control terminal of the ninth transistor T9 is connected to the second control signal terminal GC. Specifically, the first terminal of the eighth transistor T8 may be connected to the first reset signal terminal Vint1, and the second terminal of the eighth transistor T8 may be connected to the fourth node N4. The first terminal of the ninth transistor T9 may be connected to the first power supply signal terminal ELVDD, the first reference signal terminal Vref, the first reset signal terminal Vint1, or other constant voltage sources. It is only necessary to ensure that the difference between the potential of the constant voltage source connected to the first terminal of the ninth transistor T9 and the potential of the second power supply signal terminal ELVSS is greater than the threshold voltage Vth of the first transistor T1. In this embodiment, the first terminal of the ninth transistor T9 is connected to the first reference signal terminal Vref.
[0055] Optionally, the pixel driving circuit further includes a third capacitor C3. The first terminal of the third capacitor C3 is connected to the second node N2, and the second terminal of the third capacitor C3 is connected to a constant voltage source. Specifically, the second terminal of the third capacitor C3 can be connected to the first power supply signal terminal ELVDD, the second power supply signal terminal ELVSS, the first reference signal terminal Vref, the first reset signal terminal Vint1, the second reset signal terminal Vint2, or other constant voltage sources. In this embodiment, the second terminal of the third capacitor C3 is connected to the first power supply signal terminal ELVDD. Optionally, a transistor can be disposed between the third capacitor C3 and the second node N2, which can be turned off during the light-emitting stage.
[0056] The control electrodes of the third transistor T3 and the ninth transistor T9 are connected to the same control signal terminal, as are the control electrodes of the fourth transistor T4 and the eighth transistor T8. This effectively reduces the number of shift register units at the display panel bezel, facilitating a reduction in the bezel width and simplifying the wiring design of the display area. The third transistor T3 and the fourth transistor T4 are connected in series to jointly control the input, effectively preventing interference from the compensation module 30 signal to the drive module 10 during high-frequency reset.
[0057] The circuit in Figure 1 will be described below with reference to Figure 2, which is a timing diagram of the circuit shown in Figure 1 in one embodiment.
[0058] During the S1 period, all control signals are at a low level, and all transistors are turned off.
[0059] During period S2, the second control signal and the second light emission control signal transition to a high potential. The third transistor T3, the sixth transistor T6, and the ninth transistor T9 are turned on. The first reference signal terminal Vref resets the first node N1, and the second power supply signal terminal ELVSS resets the second node N2.
[0060] During period S3, the second light-emitting control signal transitions to a low potential, and the first control signal transitions to a high potential. The sixth transistor T6 is turned off, while the fourth transistor T4 and the eighth transistor T8 are turned on. Since the difference between the potential of the first reference signal terminal Vref and the potential of the second power supply signal terminal ELVSS is greater than the threshold voltage Vth of the first transistor T1, the first transistor T1 is turned on. The potential of the first power supply signal terminal ELVDD is written to the second node N2 via the fourth transistor T4, the third transistor T3, and the first transistor T1, and coupled to the first node N1 through the second capacitor C2. The first transistor T1 is turned off when the potential of the second node N2 is equal to the potential of the first reference signal terminal Vref minus Vth. The eighth transistor T8 is turned on, and the first reset signal terminal Vint1 resets the fourth node N4.
[0061] During period S4, the second control signal transitions to a low potential, and the third control signal transitions to a high potential. The third transistor T3 and the ninth transistor T9 are turned off, while the second transistor T2 is turned on. The data signal Vdata at the data signal terminal is written to the first node N1 via the second transistor T2. Due to the voltage division by the third capacitor C3, the potential of the second node N2 changes.
[0062] Vref-Vth+C2×(Vdata-Vref) / (C2+C3).
[0063] During period S5, the first and third control signals go low. The second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned off.
[0064] During period S6, both the first and second light-emitting control signals transition to a high potential. The second power supply signal terminal ELVSS is written to the second node N2 via the sixth transistor T6, causing the second node N2 to transition to:
[0065] N2=Vs=ELVSS ①
[0066] Due to the coupling of the second capacitor C2, the first node N1 transforms into:
[0067] N1=Vg=Vdata+ELVSS-[Vref-Vth+C2×(Vdata-Vref) / (C2+C2)] ②
[0068] The drive current Id can be expressed by the equation:
[0069] Id=u*Cox*W / 2L*(Vgs-Vth)^2 ③
[0070] Substituting ① and ② into ③, we get:
[0071] Id=u*Cox*W / 2L*{Vdata+ELVSS-[Vref-Vth+C2*(Vdata-Vref) / (C2+C2)]-ELVSS-Vth}^2
[0072] =u*Cox*W / 2L*[C3*(Vdata-Vref) / (C2+C3)]^2
[0073] = k(Vdata-Vref)^2
[0074] “μ” and “Cox” are constants, “W” is the channel width of the first transistor T1, “L” is the channel length of the first transistor T1, and “Vgs” is the differential voltage between the gate and source of the first transistor T1. “μ”, “Cox”, “W”, “L”, “C2”, and “C3” are fixed values after the circuit module is manufactured, i.e., constants, and can therefore be replaced by k. Finally, from Id = k(Vdata - Vref)^2, it can be seen that the driving current Id flowing through the light-emitting unit 60 during time S6 is unaffected by the threshold voltage (Vth) of the first transistor T1, thus the brightness of the image output by the display panel can be maintained uniformly, independent of the characteristics (Vth) of the first transistor T1.
[0075] In subsequent display frames of the display panel, the pixel driving circuit repeats the above steps S1-S6 to refresh the display panel.
[0076] As shown in Figure 3, Figure 3 is a circuit diagram of the pixel driving circuit in an optional embodiment. Compared with the embodiment shown in Figure 1, in this embodiment, the control electrodes of the sixth transistor T6 and the seventh transistor T7 of the light-emitting control module 40 are connected to the same light-emitting control signal terminal EM. The second electrode of the fourth transistor T4 can be connected to the first power supply signal terminal ELVDD, the first reference signal terminal Vref, the first reset signal terminal Vint1, or other constant voltage sources. In this embodiment, the second electrode of the fourth transistor T4 is connected to the first reference signal terminal Vref. In this embodiment, the reset module 50 also includes a tenth transistor T10. The first electrode of the tenth transistor T10 is connected to a constant voltage source, the second electrode of the tenth transistor T10 is connected to the second node N2, and the control electrode of the tenth transistor T10 is connected to the fourth control signal terminal GI. The potential difference between the constant voltage source connected to the first electrode of the ninth transistor T9 and the constant voltage source connected to the first electrode of the tenth transistor T10 is greater than the threshold voltage Vth of the first transistor T1. In this embodiment, the first electrode of the tenth transistor T10 is connected to the second reset signal terminal Vint2.
[0077] The structure of the other parts is the same as that of the embodiment shown in Figure 1, and will not be described in detail here.
[0078] The circuit in Figure 3 will be described below with reference to Figure 4, which is a timing diagram of the circuit shown in Figure 3 in one embodiment.
[0079] This embodiment differs from the embodiment shown in Figure 2 only in time period S2. In this embodiment, during time period S2, the second and fourth control signals go to a high potential, the third transistor T3, the ninth transistor T9, and the tenth transistor T10 are turned on, the first reference signal terminal Vref resets the first node N1, and the second reset signal terminal Vint2 resets the second node N2. The other time periods are the same as in the above embodiment and will not be described in detail here.
[0080] As shown in Figure 5, Figure 5 is a circuit diagram of the pixel driving circuit in an optional embodiment.
[0081] The driving module 10 may include a first transistor T1, the first terminal of the first transistor T1 is connected to the third node N3, the second terminal of the first transistor T1 is connected to the second node N2, and the control terminal of the first transistor T1 is connected to the first node N1.
[0082] The data writing module 20 may include a second transistor T2 and a first capacitor C1. The first terminal of the second transistor T2 is connected to the data signal terminal Vdata, the second terminal of the second transistor T2 is connected to the fifth node N5, and the control terminal of the second transistor T2 is connected to the third control signal terminal GW. The first terminal of the first capacitor C1 is connected to the fifth node N5, and the second terminal is connected to the first node N1.
[0083] The compensation module 30 may include a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The first terminal of the third transistor T3 is connected to the driving module 10, the second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4, and the second terminal of the fourth transistor T4 is connected to a constant voltage source. The control terminal of one of the third transistor T3 and the fourth transistor T4 is connected to the first control signal terminal GB, and the control terminal of the other is connected to the second control signal terminal GC. In this embodiment, the connection of the control terminal of the third transistor T3 to the first control signal terminal GB and the control terminal of the fourth transistor T4 to the second control signal terminal GC is used as an example. Specifically, the first terminal of the third transistor T3 is connected to the third node N3. The second terminal of the fourth transistor T4 may be connected to the first power supply signal terminal ELVDD, the first reference signal terminal Vref, the first reset signal terminal Vint1, or other constant voltage sources. The constant voltage source connected to the second terminal of the fourth transistor T4 must satisfy the condition that the potential of the first node N1 after reset - the potential of the constant voltage source connected to the second terminal of the fourth transistor T4 > the Vth of the first transistor T1. In this embodiment, the second terminal of the fourth transistor T4 is connected to the first reference signal terminal Vref. The first terminal of the fifth transistor T5 is connected to the second node N2, the second terminal of the fifth transistor T5 is connected to the first node N1, and the control terminal of the fifth transistor T5 is connected to the second control signal terminal GC.
[0084] The light-emitting control module 40 may include a sixth transistor T6 and a seventh transistor T7. The first terminal of the seventh transistor T7 is connected to the light-emitting unit 60, the second terminal of the seventh transistor T7 is connected to the third node N3, and the control terminal of the seventh transistor T7 is connected to the first light-emitting control signal terminal EM1. The first terminal of the sixth transistor T6 is connected to the second power supply signal terminal ELVSS, the second terminal of the sixth transistor T6 is connected to the second node N2, and the control terminal of the sixth transistor T6 is connected to the second light-emitting control signal terminal EM2. Specifically, the first terminal of the seventh transistor T7 is connected to the fourth node N4.
[0085] The reset module 50 may include an eighth transistor T8 and a ninth transistor T9. The first terminal of the eighth transistor T8 is connected to a constant voltage source, the second terminal of the eighth transistor T8 is connected to the light-emitting unit 60, and the control terminal of the eighth transistor T8 is connected to the first control signal terminal GB. The first terminal of the ninth transistor T9 is connected to a constant voltage source, the second terminal of the ninth transistor T9 is connected to the fifth node N5, and the control terminal of the ninth transistor T9 is connected to the second control signal terminal GC. Specifically, the first terminal of the eighth transistor T8 may be connected to the first reset signal terminal Vint1, and the second terminal of the eighth transistor T8 is connected to the fourth node N4. The first terminal of the ninth transistor T9 may be connected to the first reference signal terminal Vref.
[0086] Optionally, the pixel driving circuit further includes a fourth capacitor C4. The first terminal of the fourth capacitor C4 is connected to the fifth node N5, and the second terminal of the fourth capacitor C4 is connected to a constant voltage source. Specifically, the second terminal of the fourth capacitor C4 can be connected to the first power supply signal terminal ELVDD, the second power supply signal terminal ELVSS, the first reference signal terminal Vref, the first reset signal terminal Vint1, the second reset signal terminal Vint2, or other constant voltage sources. In this embodiment, the second terminal of the fourth capacitor C4 is connected to the first power supply signal terminal ELVDD.
[0087] The control electrodes of the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 are connected to the same control signal terminal. Similarly, the control electrodes of the third transistor T3 and the eighth transistor T8 are also connected to the same control signal terminal. This effectively reduces the number of shift register units at the display panel bezel, facilitating a reduction in the bezel width and simplifying the wiring design of the display area. The third transistor T3 and the fourth transistor T4 are connected in series to jointly control the input, effectively preventing interference from the compensation module 30 signal to the drive module 10 during high-frequency reset.
[0088] The circuit in Figure 5 will be described below with reference to Figure 6, which is a timing diagram of the circuit shown in Figure 5 in one embodiment.
[0089] During the S1 period, all control signals are at a low level, and all transistors are turned off.
[0090] During period S2, the second control signal and the second light emission control signal transition to a high potential. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on. The first reference signal terminal Vref resets the fifth node N5, and the second power supply signal terminal ELVSS resets the second node N2 and the first node N1.
[0091] During period S3, the second light-emitting control signal transitions to a low potential, and the first control signal transitions to a high potential. The sixth transistor T6 is turned off, while the third transistor T3 and the eighth transistor T8 are turned on. Since the difference between the potential of the second power supply signal terminal ELVSS and the potential of the first reference signal terminal Vref is greater than the threshold voltage Vth of the first transistor T1, the first transistor T1 is turned on. The potential of the first reference signal terminal Vref is written to the second node N2 via the fourth transistor T4, the third transistor T3, and the first transistor T1, and then written to the first node N1 via the fifth transistor T5. The first transistor T1 is turned off when the potential of the first node N1 reaches the potential of the first reference signal terminal Vref + Vth. The eighth transistor T8 is turned on, and the first reset signal terminal Vint1 resets the fourth node N4.
[0092] During period S4, the second control signal transitions to a low potential, and the third control signal transitions to a high potential. The fourth transistor T4 and the ninth transistor T9 are turned off, while the second transistor T2 is turned on. The data signal at the data signal terminal Vdata is written to the fifth node N5 via the second transistor T2 and coupled to the first node N1 through the first capacitor C1. The potential of the first node N1 becomes:
[0093] N1 = Vdata + Vth.
[0094] During period S5, the first and third control signals go low. The second transistor T2, the third transistor T3, and the eighth transistor T8 are turned off.
[0095] During time S6, the first and second light-emitting control signals go to a high level. The seventh transistor T7, the first transistor T1, and the sixth transistor T6 are turned on, and the light-emitting unit 60 emits light.
[0096] The drive current Id can be expressed by the equation:
[0097] Id=u*Cox*W / 2L*(Vgs-Vth)^2
[0098] =u*Cox*W / 2L*(Vdata+Vth-ELVSS-Vth)^2
[0099] =u*Cox*W / 2L*(Vdata-ELVSS)^2
[0100] "μ" and "Cox" are constants, "W" is the channel width of the first transistor T1, "L" is the channel length of the first transistor T1, and "Vgs" is the differential voltage between the gate and source of the first transistor T1. "μ", "Cox", "W", "L", "C2", and "C3" are fixed values after the circuit module is manufactured. Finally, from Id = u*Cox*W / 2L*(Vdata-ELVSS)^2, it can be seen that the driving current Id flowing through the light-emitting unit 60 during the S6 period is not affected by the threshold voltage (Vth) of the first transistor T1, so the brightness of the image output by the display panel can be maintained uniformly, regardless of the characteristics (Vth) of the first transistor T1.
[0101] In subsequent display frames of the display panel, the pixel driving circuit repeats the above steps S1-S6 to refresh the display panel.
[0102] As shown in Figure 7, which is a circuit diagram of the pixel driving circuit in an optional embodiment, compared to the embodiment shown in Figure 5, in this embodiment, the control electrodes of the sixth transistor T6 and the seventh transistor T7 of the light-emitting control module 40 are connected to the same light-emitting control signal terminal EM. In this embodiment, the reset module 50 further includes a tenth transistor T10, the first electrode of which is connected to a constant voltage source, the second electrode of which is connected to the first node N1, and the control electrode of which is connected to the fourth control signal terminal GI. In this embodiment, the first electrode of the tenth transistor T10 is connected to the second reset signal terminal Vint2.
[0103] The structure of the other parts is the same as that of the embodiment shown in Figure 5, and will not be described in detail here.
[0104] The circuit in Figure 7 will be described below with reference to Figure 8, which is a timing diagram of the circuit shown in Figure 7 in one embodiment.
[0105] This embodiment differs from the embodiment shown in Figure 6 only in time period S2. In this embodiment, during time period S2, the second and fourth control signals become high, and the fourth transistor T4, the fifth transistor T5, the ninth transistor T9, and the tenth transistor T10 are turned on. The first reference signal terminal Vref resets the fifth node N5, and the second reset signal terminal Vint2 resets the second node N2 and the first node N1. The other time periods are the same as in the above embodiment and will not be described in detail here.
[0106] As shown in Figure 9, which is a circuit diagram of the pixel driving circuit in an optional embodiment, compared to the embodiment shown in Figure 7, in this embodiment, the first terminal of the tenth transistor T10 of the reset module 50 is connected to a constant voltage source, the second terminal of the tenth transistor T10 is connected to the second node N2, and the control terminal of the tenth transistor T10 is connected to the fourth control signal terminal GI. In this embodiment, the first terminal of the tenth transistor T10 is connected to the second reset signal terminal Vint2.
[0107] The structure of the other parts is the same as that of the embodiment shown in Figure 7, and will not be described in detail here.
[0108] The circuit in Figure 9 will be described below with reference to Figure 10, which is a timing diagram of the circuit shown in Figure 9 in one embodiment.
[0109] This embodiment differs from the embodiment shown in Figure 8 only in time period S2. In this embodiment, during time period S2, the second and fourth control signals become high, and the fourth transistor T4, the fifth transistor T5, the ninth transistor T9, and the tenth transistor T10 are turned on. The first reference signal terminal Vref resets the fifth node N5, and the second reset signal terminal Vint2 resets the first node N1 and the second node N2. The other time periods are the same as in the above embodiment and will not be described in detail here.
[0110] As shown in Figure 11, Figure 11 is a circuit diagram of the pixel driving circuit in an optional embodiment. Compared with the embodiment shown in Figure 7, in this embodiment, the compensation module 30 may include a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The first terminal of the third transistor T3 is connected to the driving module 10, the second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4, and the second terminal of the fourth transistor T4 is connected to a constant voltage source. The control terminal of one of the third transistor T3 and the fourth transistor T4 is connected to the first control signal terminal GB, and the control terminal of the other is connected to the second control signal terminal GC. In this embodiment, the connection of the control terminal of the third transistor T3 to the second control signal terminal GC and the connection of the control terminal of the fourth transistor T4 to the first control signal terminal GB are used as an example. Specifically, the first terminal of the third transistor T3 is connected to the second node N2. The second terminal of the fourth transistor T4 may be connected to the first power supply signal terminal ELVDD, the first reference signal terminal Vref, the first reset signal terminal Vint1, or other constant voltage sources. The constant voltage source connected to the second terminal of the fourth transistor T4 must satisfy the condition that the potential of the first node N1 after reset - the potential of the constant voltage source connected to the second terminal of the fourth transistor T4 > the Vth of the first transistor T1. In this embodiment, the second terminal of the fourth transistor T4 is connected to the first reference signal terminal Vref. The first terminal of the fifth transistor T5 is connected to the third node N3, the second terminal of the fifth transistor T5 is connected to the first node N1, and the control terminal of the fifth transistor T5 is connected to the second control signal terminal GC. The structure of other parts is consistent with the embodiment shown in Figure 7, and will not be described in detail here.
[0111] The circuit in Figure 11 will be described below with reference to Figure 12, which is a timing diagram of the circuit shown in Figure 11 in one embodiment.
[0112] The operating principle of this embodiment is basically the same as that of the embodiment shown in Figure 8. On this basis, the functions of the second node N2 and the third node N3 are swapped during the reset and compensation process, so it will not be described in detail here.
[0113] Optionally, the tenth transistor T10 in the reset module 50 can also be directly connected between the third node N3 and the second reset signal terminal Vint1. In this way, the operating principle of the circuit becomes similar to that of the circuit shown in Figure 9, except that the functions of the original second node N2 and the third node N3 are swapped.
[0114] This application also provides a display substrate, which includes the pixel driving circuit described above.
[0115] This application also provides a display device, which includes the display substrate described above.
[0116] In one embodiment, the display device further includes a housing, and the display substrate is disposed within the housing.
[0117] The display device provided in this application embodiment can be any device with display function, such as a mobile phone, tablet computer, television, laptop computer, or vehicle-mounted equipment.
[0118] It should be noted that the technical solutions or features described in the above embodiments can be combined or complemented by each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A pixel driving circuit, characterized in that, include: Light-emitting unit; The driving module is configured to control the light emission of the light-emitting unit under the control of a data signal; A compensation module is configured to compensate the data signal; the compensation module includes a third transistor and a fourth transistor, the first terminal of the third transistor is connected to the driving module, the second terminal of the third transistor is connected to the first terminal of the fourth transistor, and the second terminal of the fourth transistor is connected to a constant voltage source; the control terminal of one of the third transistor and the fourth transistor is connected to a first control signal terminal, and the control terminal of the other transistor is connected to a second control signal terminal. A reset module is configured to reset the pixel driving circuit; the reset module includes an eighth transistor, the first terminal of the eighth transistor is connected to a constant voltage source, the second terminal is connected to the light-emitting unit, and the control terminal is connected to the first control signal terminal.
2. The pixel driving circuit according to claim 1, characterized in that, The driving module includes a first transistor, wherein the first electrode of the first transistor is connected to a third node, the second electrode is connected to a second node, and the control electrode is connected to the first node. The first electrode of the third transistor is connected to the third node.
3. The pixel driving circuit according to claim 2, characterized in that, The reset module further includes a ninth transistor, the first terminal of which is connected to a constant voltage source, the second terminal of which is connected to the first node, and the control terminal of which is connected to the second control signal terminal.
4. The pixel driving circuit according to claim 3, characterized in that, The compensation module further includes a second capacitor, the first terminal of which is connected to the second node, and the second terminal of which is connected to the first node; The pixel driving circuit further includes a data writing module, which includes a second transistor. The first electrode of the second transistor is connected to the data signal terminal, the second electrode is connected to the first node, and the control electrode is connected to the third control signal terminal.
5. The pixel driving circuit according to claim 4, characterized in that, The pixel driving circuit further includes a light-emitting control module; the light-emitting control module includes a sixth transistor and a seventh transistor; The first electrode of the seventh transistor is connected to the light-emitting unit, the second electrode is connected to the third node, and the control electrode is connected to the first light-emitting control signal terminal; The first electrode of the sixth transistor is connected to the second power supply signal terminal, the second electrode is connected to the second node, and the control electrode is connected to the second light emission control signal terminal.
6. The pixel driving circuit according to claim 4, characterized in that, The pixel driving circuit further includes a light-emitting control module; the light-emitting control module includes a sixth transistor and a seventh transistor; The first electrode of the seventh transistor is connected to the light-emitting unit, and the second electrode is connected to the third node; the first electrode of the sixth transistor is connected to the second power supply signal terminal, and the second electrode is connected to the second node; the control electrodes of the sixth transistor and the seventh transistor are connected to the same light-emitting control signal terminal. The reset module also includes a tenth transistor, the first terminal of which is connected to a constant voltage source, the second terminal of which is connected to the second node, and the control terminal of which is connected to the fourth control signal terminal.
7. The pixel driving circuit according to claim 5, characterized in that, The difference between the potential of the constant voltage source connected to the first terminal of the ninth transistor and the potential of the second power signal terminal is greater than the threshold voltage of the third transistor.
8. The pixel driving circuit according to claim 6, characterized in that, The difference between the potential of the constant voltage source connected to the first terminal of the ninth transistor and the potential of the constant voltage source connected to the first terminal of the tenth transistor is greater than the threshold voltage of the third transistor.
9. The pixel driving circuit according to claim 2, characterized in that, The reset module further includes a ninth transistor, the first terminal of which is connected to a constant voltage source, the second terminal of which is connected to a fifth node, and the control terminal of which is connected to the second control signal terminal. The compensation module further includes a fifth transistor, the first electrode of which is connected to the second node, the second electrode of which is connected to the first node, and the control electrode of which is connected to the second control signal terminal; The pixel driving circuit also includes a data writing module, which includes a second transistor and a first capacitor. The first electrode of the second transistor is connected to the data signal terminal, the second electrode is connected to the fifth node, and the control electrode is connected to the third control signal terminal. The first terminal of the first capacitor is connected to the fifth node, and the second terminal is connected to the first node.
10. The pixel driving circuit according to claim 9, characterized in that, The pixel driving circuit further includes a light-emitting control module; the light-emitting control module includes a sixth transistor and a seventh transistor; The first electrode of the seventh transistor is connected to the light-emitting unit, the second electrode is connected to the third node, and the control electrode is connected to the first light-emitting control signal terminal; The first electrode of the sixth transistor is connected to the second power supply signal terminal, the second electrode is connected to the second node, and the control electrode is connected to the second light emission control signal terminal.
11. The pixel driving circuit according to claim 9, characterized in that, The pixel driving circuit further includes a light-emitting control module; the light-emitting control module includes a sixth transistor and a seventh transistor; The first electrode of the seventh transistor is connected to the light-emitting unit, and the second electrode is connected to the third node; the first electrode of the sixth transistor is connected to the second power supply signal terminal, and the second electrode is connected to the second node; the control electrodes of the sixth transistor and the seventh transistor are connected to the same light-emitting control signal terminal. The reset module also includes a tenth transistor, the first terminal of which is connected to a constant voltage source, the second terminal of which is connected to the first node, and the control terminal of which is connected to a fourth control signal terminal.
12. The pixel driving circuit according to claim 9, characterized in that, The pixel driving circuit further includes a light-emitting control module; the light-emitting control module includes a sixth transistor and a seventh transistor; The first electrode of the seventh transistor is connected to the light-emitting unit, and the second electrode is connected to the third node; the first electrode of the sixth transistor is connected to the second power supply signal terminal, and the second electrode is connected to the second node; the control electrodes of the sixth transistor and the seventh transistor are connected to the same light-emitting control signal terminal. The reset module also includes a tenth transistor, the first terminal of which is connected to a constant voltage source, the second terminal of which is connected to the second node, and the control terminal of which is connected to the fourth control signal terminal.
13. The pixel driving circuit according to claim 1, characterized in that, The driving module includes a first transistor, wherein the first electrode of the first transistor is connected to a third node, the second electrode is connected to a second node, and the control electrode is connected to the first node. The first electrode of the third transistor is connected to the second node.
14. The pixel driving circuit according to claim 13, characterized in that, The compensation module further includes a fifth transistor, the first terminal of which is connected to the third node, the second terminal of which is connected to the first node, and the control terminal of which is connected to the second control signal terminal.
15. The pixel driving circuit according to claim 14, characterized in that, The pixel driving circuit also includes a fourth capacitor, the first terminal of which is connected to a constant voltage source, and the second terminal of which is connected to the fifth node.
16. A display substrate, characterized in that, The display substrate includes a pixel driving circuit as described in any one of claims 1-15.
17. A display device, characterized in that, The display device includes the display substrate as described in claim 16.