Oscillator frequency modulation circuit and communication chip

Abstract

Provided in the present application are an oscillator frequency modulation circuit and a communication chip. The oscillator frequency modulation circuit comprises: a first resonance region, comprising a first resonance circuit, and a first coupling transistor (Mn) and a second coupling transistor (Mp) which are crosswise coupled to the first resonance circuit; and a second resonance region, comprising a second resonance circuit. The second resonance circuit comprises: a first branch electrically connected to the first coupling transistor (Mn); a second branch electrically connected to the second coupling transistor (Mp); a first tail inductor (Ln) connected in series on the first branch; a second tail inductor (Lp) connected in series on the second branch; and a differential capacitor array (Ct) connected in parallel between the first branch and the second branch. The oscillator frequency modulation circuit and the communication chip of the present disclosure can achieve low noise in a wide frequency band range, have an anti-interference capability, meanwhile occupy small area, and can continuously output high-quality signals for multi-protocol systems.

Description

Oscillator frequency modulation circuit and communication chip Technical Field

[0001] This disclosure relates to the field of communication chips, and more specifically, to oscillator frequency modulation circuits and communication chips. Background Technology

[0002] With the continuous development of communication protocols, the demand for high-quality, broadband transmission is increasing, requiring a single communication chip to support the parallel operation of multiple communication protocols. Examples of these protocols include, but are not limited to, Wi-Fi, Bluetooth, Thread, and ZigBee. As a crucial module for signal transmission, the voltage-controlled oscillator (VCO) with a tail inductor resonant structure can provide high-quality signal output at a single frequency, but its performance is poor over a wide bandwidth. Furthermore, the common tail inductor design occupies a large chip area, and its resonant frequency is easily interfered with by systems with multiple coexisting protocols, making it difficult to continuously output high-quality signals to the system. Summary of the Invention

[0003] The purpose of this disclosure is to provide an improved oscillator frequency modulation circuit that can solve at least one or more of the above-mentioned problems.

[0004] In one aspect of this disclosure, an oscillator frequency modulation circuit is provided, including a first resonant region comprising a first resonant circuit and a first coupling transistor and a second coupling transistor cross-coupled with the first resonant circuit; and a second resonant region comprising a second resonant circuit, wherein the second resonant circuit comprises: a first branch electrically connected to the first coupling transistor; a second branch electrically connected to the second coupling transistor; a first tail inductor connected in series on the first branch; a second tail inductor connected in series on the second branch; and a differential capacitor array connected in parallel between the first branch and the second branch.

[0005] In some examples, the differential capacitor array may be arranged near the common source node of the first and second coupled transistors.

[0006] In some examples, the second resonant circuit also includes a decoupling capacitor connected in parallel between the first branch and the second branch.

[0007] In some examples, the first tail inductor can be arranged on the first branch between the differential capacitor array and the decoupling capacitor, and the second tail inductor can be arranged on the second branch between the differential capacitor array and the decoupling capacitor.

[0008] In some examples, the differential capacitor array may include multiple branches connected in parallel between the first branch and the second branch, wherein each branch includes at least one switch and at least one capacitor.

[0009] In some examples, each of the at least one switch may be selected from an N-type switch or a P-type switch, wherein at least one capacitor may be arranged on one or both sides of the at least one switch.

[0010] In some examples, each of the plurality of branches may include at least one of a single NMOS transistor and a single-sided MOM capacitor, a single PMOS transistor and a single-sided MOM capacitor, a single NMOS transistor and a double-sided MOM capacitor, and a single PMOS transistor and a double-sided MOM capacitor.

[0011] In some examples, the capacitance value of the differential capacitor array can be determined by the state of the at least one switch.

[0012] In some examples, the state of the at least one switch can be determined by the control word of the differential capacitor array.

[0013] In some examples, the control word of the differential capacitor array can be determined based on the calibrated control word of the first resonant region.

[0014] In some examples, the coupling coefficient between the first tail inductor and the second tail inductor can be configured to be adjusted between 0 and 1 according to the capacitance value of the differential capacitor array.

[0015] In some examples, the first branch can be connected to a power source, and the second branch can be grounded.

[0016] In some examples, the first resonant circuit may have a PMOS structure, an NMOS structure, or a CMOS structure.

[0017] In some examples, the decoupling capacitor can be a high-Q capacitor.

[0018] In some examples, the first resonant circuit includes a main inductor, a variable capacitor, and a fixed capacitor connected in parallel. In another aspect of this disclosure, a communication chip is provided, including a processor, a memory, a communication interface, and an oscillator frequency modulation circuit according to this disclosure.

[0019] In some examples, the power supply for the oscillator frequency modulation circuit can be an on-chip LDO or an off-chip LDO.

[0020] By way of example and not limitation, the advantages of the oscillator frequency modulation circuit and communication chip provided in this disclosure may include: achieving low noise over a wide frequency band, having anti-interference capabilities, occupying a small area, and continuously outputting high-quality signals for multi-protocol systems.

[0021] Specifically, the oscillator frequency modulation circuit and inductor architecture provided in this disclosure can provide one or more of the following and other advantages:

[0022] (1) By setting a frequency modulation circuit at the tail of the voltage-controlled oscillator and selecting different differential capacitors in different frequency bands, a second or fourth harmonic relative to the main resonant frequency can be generated. This design not only avoids interference, but also the low parasitic characteristics of the differential capacitors broaden the frequency range of noise suppression of the oscillator, thereby improving the anti-interference capability and overall performance of the voltage-controlled oscillator in a wide frequency band.

[0023] (2) By concealing the centrally symmetrical differential capacitor array below the center of the digital 8-type inductor and optimizing the ratio of capacitor to inductor, for example, increasing the differential capacitor value while reducing the inductor value while keeping the tail resonant frequency unchanged, the area of ​​the tail oscillator can be significantly reduced without affecting the performance.

[0024] (3) A new type of digital 8-type inductor is adopted, with the input and output terminals placed on opposite sides of the inductor. This design not only separates the decoupling capacitor and differential capacitor in terms of spatial layout, reducing wiring complexity and improving area utilization, but also ensures that the two-turn magnetic flux of the inductor flows in opposite directions, balancing the entry and exit of spatial interference and effectively improving anti-interference capability. In addition, if the power supply tail and ground tail inductors are implemented using a stacked structure, the coupling coefficient can be increased to reduce common-mode noise while further saving half of the area.

[0025] (4) This disclosure introduces a scheme that incorporates an oscillator frequency modulation circuit and an inductor architecture while maintaining the original main design, without increasing the area or power consumption, thereby effectively saving manufacturing costs. At the same time, due to the versatility of the design, this scheme can be widely applied to various voltage-controlled oscillators, helping to achieve the goals of broadband high performance, anti-interference, and low area.

[0026] It should be understood that the technical problems and advantages listed above are merely examples and not limitations of this disclosure. Furthermore, this disclosure is not limited to technical solutions that simultaneously solve all of the above-mentioned technical problems; the technical solutions of this disclosure can be implemented to solve one or more of the above-mentioned or other technical problems, and to provide one or more of the above-mentioned or other advantages. Attached Figure Description

[0027] Figure 1 shows a schematic circuit diagram of an oscillator frequency modulation circuit according to an embodiment of the present disclosure;

[0028] Figure 2 shows a schematic diagram of an inductor according to an embodiment of the present disclosure;

[0029] Figure 3 shows a schematic diagram of an inductor according to another embodiment of the present disclosure;

[0030] Figure 4 shows a schematic diagram of the spatial layout of an inductor architecture according to some embodiments of the present disclosure;

[0031] Figure 5 shows a schematic diagram of an inductor architecture according to some other embodiments of the present disclosure;

[0032] Figure 6 shows a schematic diagram of the layout of the oscillator inductor and capacitor according to some embodiments of the present disclosure;

[0033] Figure 7 shows a schematic diagram of the layout of the oscillator inductor and capacitor according to some other embodiments of the present disclosure;

[0034] Figure 8 shows a schematic diagram of the layout of the oscillator inductor and capacitor according to some embodiments of the present disclosure;

[0035] Figure 9 shows a schematic diagram of the layout of the oscillator inductor and capacitor according to some embodiments of the present disclosure;

[0036] Figure 10 shows a schematic diagram of an inductor architecture according to the prior art and an inductor architecture according to some embodiments of the present disclosure; and

[0037] Figure 11 shows a schematic diagram of the layout of the oscillator inductors and capacitors according to some embodiments of the present disclosure. Detailed Implementation

[0038] The present disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments shown in the drawings and described below are merely illustrative and are not intended to limit the present disclosure.

[0039] In the context of this disclosure, unless otherwise specifically stated, ordinal numbers such as "first," "second," etc., are used only to distinguish different elements and not to specify their order.

[0040] The inventors of this disclosure fully recognize the shortcomings of the prior art and have proposed creative improvements and optimizations to aspects such as the oscillator frequency modulation circuit, inductor, inductor architecture, and the inductor-capacitor layout of the oscillator frequency modulation circuit. The improvements in various aspects will be described in detail below with reference to exemplary embodiments of this disclosure.

[0041] Oscillator frequency modulation circuit

[0042] Figure 1 shows a schematic circuit diagram of an oscillator frequency modulation circuit 100 according to an embodiment of the present disclosure. As shown in Figure 1, the oscillator frequency modulation circuit 100 includes a first resonant region 102 and a second resonant region 104. The first resonant region includes a first resonant circuit 106 and a first coupling transistor 110 and a second coupling transistor 112 cross-coupled with the first resonant circuit 106. In one embodiment, the first coupling transistor 110 may be implemented as an N-type coupling transistor (which may be denoted as coupling transistor Mn), and the second coupling transistor may be implemented as a P-type coupling transistor (which may be denoted as coupling transistor Mp). Those skilled in the art will understand that the implementation of the present disclosure is not limited thereto, and different types of coupling transistors may be used without departing from the scope of the present disclosure.

[0043] In the first resonant region 102, the first resonant circuit 110 may include a main inductor 110 (which may be represented as a main inductor Lm), a variable capacitor 112 (which may be represented as a variable capacitor Cv), and a fixed capacitor 114 (which may be represented as a fixed capacitor Cm) connected in parallel. Those skilled in the art will understand that the first resonant circuit may employ different circuit structures without departing from the scope of this disclosure.

[0044] The second resonant region 104 includes a second resonant circuit 108. The second resonant circuit 108 may include a first branch 116 electrically connected to the first coupling transistor 110 and a second branch 118 electrically connected to the second coupling transistor 112. A first tail inductor 120 (which may be represented as tail inductor Ln) is connected in series in the first branch 116, and a second tail inductor (which may be represented as tail inductor Lp) is connected in series in the second branch 118.

[0045] The second resonant circuit 108 further includes a differential capacitor array 124 (which may be represented as a capacitor array Ct) connected in parallel between the first branch 116 and the second branch 118. Optionally, the second resonant circuit 108 may also include a decoupling capacitor 126 (which may be represented as a decoupling capacitor Cd) connected in parallel between the first branch 116 and the second branch 118.

[0046] In some embodiments of this disclosure, the first resonant region constitutes the main resonant cavity of the voltage-controlled oscillator, responsible for continuously adjusting the clock frequency and providing it to the system. The second resonant region is used to suppress common-mode noise in the first resonant region, utilizing the high impedance generated by resonance to prevent common-mode noise backflow. Typically, the second resonant frequency is chosen to be two or four times the first resonant frequency.

[0047] In some embodiments, the second resonant region of this disclosure provides a unique circuit structure, for example, by connecting the power supply tail inductor path and the ground tail inductor path through a set of capacitor arrays, near the common source node of the coupling transistors Mn and Mp. Generally, the first resonant region is frequency-calibrated using software or hardware algorithms to compensate for deviations in the chip's capacitors during mass production; the calibrated control word then maps the deviation value of the chip's capacitors. The second resonant region, linked to the capacitor array control word of the first resonant region, can change the resonant frequencies of the tail inductors Lp and Ln by adjusting the control word of the tail inductor differential capacitor array Ct, thereby widening the resonant frequency range and effectively suppressing common-mode noise across the entire frequency band.

[0048] In some embodiments, as shown in FIG1, the differential capacitor array 124 may be arranged near the common source node of the first coupling tube 110 and the second coupling tube 112.

[0049] In some embodiments, the first tail inductor 120 is arranged on the first branch 116 between the differential capacitor array 124 and the decoupling capacitor 126, and the second tail inductor 122 is arranged on the second branch 118 between the differential capacitor array 124 and the decoupling capacitor 126.

[0050] In some embodiments, the differential capacitor array 116 includes a plurality of branches 128a, 128b, etc., connected in parallel between the first branch 116 and the second branch 118, wherein each branch includes at least one switch and at least one capacitor. As shown in FIG1, branch 128a includes a switch 132 and two capacitors 130. Those skilled in the art will understand that the implementation of the present disclosure is not limited thereto.

[0051] It should be understood that differential capacitor arrays can be constructed from N-type switches, P-type switches, or combinations of single-sided and double-sided capacitors, depending on the circuit structure and application requirements.

[0052] In some embodiments, each of the at least one switch is selected from an N-type switch or a P-type switch, wherein at least one capacitor 130 may be arranged on one or both sides of the at least one switch.

[0053] In some embodiments, each of the plurality of branches may include at least one of a single NMOS transistor and a single-sided MOM capacitor, a single PMOS transistor and a single-sided MOM capacitor, a single NMOS transistor and a double-sided MOM capacitor, and a single PMOS transistor and a double-sided MOM capacitor.

[0054] In some embodiments, the capacitance value of the differential capacitor array 124 is determined by the state of at least one switch.

[0055] In some embodiments, the state of at least one switch is determined by a control word of the differential capacitor array 124.

[0056] In some embodiments, the control word of the differential capacitor array 124 is further determined based on the calibrated control word of the first resonant region 106.

[0057] In some embodiments, the coupling coefficient between the first tail inductor 120 and the second tail inductor 122 is configured to be adjusted between 0 and 1 according to the capacitance value of the differential capacitor array 124.

[0058] In some embodiments, the coupling coefficient between the tail inductors Lp and Ln can be determined according to the system environment and design objectives to eliminate common-mode noise between the power supply and ground sides through magnetic coupling. Furthermore, the power supply can be provided by an on-chip LDO or an off-chip LDO, and the decoupling capacitor can be a high-Q capacitor to ensure a current loop between the power supply and ground, while eliminating the influence of additional parasitic inductance and ensuring the accurate resonant frequency of the second resonant region.

[0059] In some embodiments, the first branch 116 is connected to the power supply, and the second branch 118 is grounded.

[0060] It should be understood that the first resonant circuit may have a PMOS structure, an NMOS structure, or a CMOS structure, or other equivalent structures, without departing from the scope of this disclosure.

[0061] In some embodiments, the oscillator frequency modulation circuit employs a differential capacitor array, placed between the power supply tail inductor path and the ground tail inductor path, near the common source node of the differential coupling transistor of the voltage-controlled oscillator. The two tail inductors can be configured to have a certain coupling coefficient. By adjusting the capacitance value of the differential capacitor array, the second resonant frequency can be tuned to approximately two or four times the main resonant frequency, thus hindering the return current of common-mode noise or avoiding interference from spurious signals at the same frequency. Compared to the scheme using two sets of single-ended capacitor arrays, using a differential capacitor array simplifies the design to using only one set of switches and utilizes only half the capacitor area. By reducing the parasitic capacitance and resistance of the array, the adjustment range of the second resonant frequency is expanded, and the Q value of the second resonant cavity is improved. Furthermore, this design is easy to implement in a layout, significantly improving area utilization.

[0062] In different application scenarios, the oscillator frequency modulation circuit can use PMOS, NMOS or CMOS structure as the core architecture of the voltage-controlled oscillator.

[0063] Depending on the performance requirements and layout, the coupling coefficients of the two sets of tail inductors can be adjusted from close to 0 to close to 1 to achieve the best balance between noise, area and anti-interference performance.

[0064] This disclosure also provides a communication chip, including a processor, a memory, a communication interface, and an oscillator frequency modulation circuit according to this disclosure.

[0065] In some embodiments, the power supply for the oscillator frequency modulation circuit can be an on-chip LDO or an off-chip LDO.

[0066] Inductor

[0067] This disclosure also provides an improved inductor.

[0068] Figure 2 shows a schematic diagram of an inductor 200 according to an embodiment of the present disclosure.

[0069] As shown in Figure 2, the inductor 200 includes an input terminal 202, an output terminal 206, and an even number of coils made of electrical conductors connected between the input terminal 202 and the output terminal 204. For example, coils 206 and 208. As shown in Figure 2, the input terminal 202 and the output terminal 204 are arranged on opposite sides of the inductor 200, rather than on the same side.

[0070] Furthermore, in inductor 200, half of the even-numbered coils are arranged symmetrically with respect to the other half and in opposite directions. In this way, the two coils exhibit opposite magnetic flux flows, effectively canceling out interference at the same frequency.

[0071] Figure 3 shows a schematic diagram of an inductor 300 according to another embodiment of the present disclosure. Unlike the embodiment shown in Figure 2, the inductor 300 includes four coils 306a, 306b, 308a, and 308b made of electrical conductors connected between an input terminal 302 and an output terminal 304. In some embodiments, half of the even-numbered coils are nested in a ring, and the other half of the even-numbered coils are nested in a ring.

[0072] In other embodiments, half of the even-numbered coils are concentric, and the other half of the even-numbered coils are concentric.

[0073] In some embodiments, the inductor consists of at least one turn. Furthermore, it may be extended to two or more turns as needed.

[0074] As shown in Figures 2 and 3, the inductor according to the embodiments of this disclosure may be referred to herein as a "digital 8-type inductor" due to its shape characteristics.

[0075] In some embodiments, inductor 200 or 300 is an on-chip inductor.

[0076] In some embodiments, half of the even-numbered coils and the other half are disposed on the same metal layer.

[0077] In some embodiments, half of the even-numbered coils and the other half of the coils are connected by a skip layer where there is a cross line between them, while the rest are disposed on the same metal layer.

[0078] In some embodiments, half of the even-numbered coils and portions of the other half are disposed in the first metal layer, and the remainder is disposed in the second metal layer.

[0079] It should be understood that on-chip inductors are very sensitive to noise, area and noise immunity, therefore the improvements proposed in this disclosure can bring significant performance improvements to on-chip inductors.

[0080] In some embodiments, the even number of coils includes two coils.

[0081] In some embodiments, an even number of coils includes four coils.

[0082] In some embodiments, the inductor 200 or 300 is configured to have an integral structure.

[0083] Inductor architecture

[0084] This disclosure also provides an improved inductor architecture including a first inductor and a second inductor, and a differential capacitor array connected in parallel between the first inductor and the second inductor, wherein the first inductor and the second inductor are at least partially stacked above the differential capacitor array.

[0085] In some embodiments, the first inductor and the second inductor are arranged in an overlapping manner.

[0086] In a further embodiment, the first inductor and the second inductor are stacked together on top of the differential capacitor array.

[0087] In some embodiments, the first inductor and the second inductor are disposed separately, and the differential capacitor array is split into a first differential capacitor array and a second differential capacitor array, wherein the first inductor is configured to be at least partially stacked on top of the first differential capacitor array, and the second inductor is configured to be at least partially stacked on top of the second differential capacitor array.

[0088] In some embodiments, the inductor architecture is an on-chip inductor architecture.

[0089] In some embodiments, the first inductor and the second inductor are disposed on different metal layers.

[0090] In some embodiments, portions of the first inductor and the second inductor are disposed in the first metal layer, and the remainders are disposed in the second metal layer.

[0091] In some embodiments, the first inductor and the second inductor are configured to have mirror shapes.

[0092] In some embodiments, the first inductor and the second inductor are tail inductors of an oscillator frequency modulation circuit.

[0093] In some embodiments, each of the first inductor and the second inductor is an inductor according to this disclosure.

[0094] Figure 4 shows a schematic diagram of the spatial layout of inductor architectures 402 and 404 according to some embodiments of the present disclosure.

[0095] Figure 4(a) shows the structure including a single-turn inductor and the capacitor array below it, and Figure 4(b) shows the structure including the capacitor array below the inductor. This architecture uses at least two layers of metal, with the upper layer metal employing a symmetrical figure-eight-like design as the main body of the inductor in the second resonant region, with the input and output located on opposite sides of the inductor. Unlike traditional figure-eight-like inductor architectures, which use simple traditional symmetrical winding methods that place the input and output on the same side, requiring more signal flow wiring connections in the same area, ultimately increasing signal crosstalk and layout complexity. As shown in Figures 4(a) and 4(b), the lower layer metal is suspended below the center of the inductor, leading out from the input and output sides respectively. Due to the figure-eight-like design, the magnetic flux of the two turns of the inductor flows in opposite directions, effectively reducing co-frequency interference. This spatial layout scheme can effectively reduce the area, bringing significant cost advantages to the chip. The dual-turn inductor is similar to the single-turn inductor, but the crossover line in the middle needs to be connected using a higher layer of metal.

[0096] Figure 4(c) shows the capacitor array. In the illustrated embodiment, the capacitor array is arranged in a centrally symmetrical manner. Taking a 4-bit binary code as an example, the capacitors CAP1X, CAP2X, CAP4X, and CAP8X in the capacitor array correspond to unit codes 1, 2, 4, and 8, respectively. CAP1XD is a dummy cell of CAP1X, used for overall matching. Further, as shown in Figure 4(c), the position of switch sw is close to the capacitor unit and can be adjusted according to the actual layout. The layout shown in Figure 4 is only an example and not a limitation.

[0097] Figure 5 shows a schematic diagram of inductor architectures 506 and 512 according to other embodiments of the present disclosure.

[0098] Figure 5 is a schematic diagram of another inductor architecture provided by an embodiment of this disclosure. By arranging the inductors in a vertical plane, dual inductors can be implemented within the same area. Its advantages include a higher coupling coefficient and a smaller area. The figure shows the direction of common-mode current flow; the magnetic flux of the stacked metals flows in the same direction and is superimposed. Dual inductors can be implemented using two completely independent metal layers, or each inductor group can occupy half of two metal layers, combined with a planar and spatial arrangement. The capacitor array layout shown in Figure 5 can be similar to that in Figure 4, and can be concealed below the inductors, facilitating a differential capacitor layout. The overall quasi-digital 8-type inductor has a strong suppression effect on near-frequency interference.

[0099] Layout of oscillator inductors and capacitors

[0100] In the oscillator frequency modulation circuit 100 shown in Figure 1 according to one embodiment of the present disclosure, the first tail inductor 112 and each of the tail inductors are implemented as inductors according to the present disclosure.

[0101] In some embodiments, the first tail inductor and the second tail inductor are configured to have mirror images of each other. As a non-limiting example, Figure 6 shows tail inductors 608 and 610 that are mirror images of each other. It should be understood that "mirror images of each other" means that the overall shape of the coils is generally mirror images of each other, and does not require that all parts of the two coils be in a mirror relationship.

[0102] In some embodiments, the first tail inductor and the second tail inductor are stacked above the differential capacitor array. For example, tail inductors 608 and 610 shown in FIG. 6(a) are stacked above differential capacitor arrays 612 and 614.

[0103] In some embodiments, the first tail inductor and the second tail inductor are arranged approximately axially symmetrically with respect to the central axis of the main inductor, as shown in Figures 6-8, for example.

[0104] In some embodiments, the first tail inductor and the second tail inductor are arranged at the input and output terminals of the inductance coil of the main inductor, respectively. For example, tail inductors 608 and 610 are shown in FIG. 6(a).

[0105] In some embodiments, the first tail inductor and the second tail inductor are arranged at an angle relative to the central axis of the inductor coil of the main inductor. For example, tail inductors 808 and 810 are shown in FIG8(a).

[0106] In some embodiments, the first tail inductor and the second tail inductor are inclined at 45 degrees relative to the central axis of the inductor coil of the main inductor. For example, tail inductors 818 and 820 are shown in FIG8(b).

[0107] In some embodiments, the first tail inductor and the second tail inductor are arranged overlapping each other. For example, tail inductors 908 and 910 are shown in FIG9(a).

[0108] The inductor architecture disclosed herein primarily employs a digital-8 type inductor. Unlike conventional inductors, the inductor of this disclosure is characterized by input from one side and output from the other side after winding. Furthermore, a capacitor array network is placed below the winding at the center of the inductor. Based on the current flow direction, the two coils of the digital-8 type inductor exhibit opposite magnetic flux directions, effectively canceling co-frequency interference and suppressing its absorption of spurious emissions from similar frequency bands, without affecting the main inductor. Simultaneously, the input and output terminals are separated in the layout, allowing decoupling capacitors and frequency modulation capacitors to be distributed on both sides of the inductor, avoiding the occupation of the same area. Both sides can utilize high-layer metal low-resistance connections, reducing wiring complexity and significantly improving area utilization.

[0109] In some embodiments, the capacitor array is implemented by adding low-layer parallel metal lines on the inductor input side and low-layer vertical metal lines on the output side, extending outwards and then folding inwards to the parallel side. The basic units of the overall capacitor array are arranged using binary encoding, and the centrally symmetrical layout ensures the balance of the inductor. Since the central region of the quasi-digital 8-type inductor is not the main magnetic flux concentration area, and the magnetic flux flows in opposite directions on both sides, the impact of the centrally symmetrical capacitor array embedded here on the inductor performance is negligible. When this inductor architecture is combined with the oscillator frequency modulation circuit, it not only achieves high-performance broadband frequency modulation, but also improves anti-interference capability while reducing area.

[0110] Furthermore, in some embodiments, at least one set of tail inductors is included. When using two sets of tail inductors, they can be implemented using the same layer of metal in different areas, or in the same area using stacked metal. When using stacked metal, the stacking method can be optimized according to the required inductance coupling coefficient. Optionally, the capacitor array of this solution can be connected through the input and output of a single-sided inductor respectively, or interconnected through the output terminals of two sets of inductors. The layout of the capacitor array can be flexibly selected according to the top-level design; it can be concealed directly below the inductors or arranged near the inductors to adapt to different application requirements.

[0111] The following example illustrates the oscillator inductor-capacitor layout according to an embodiment of the present disclosure.

[0112] Figure 6 shows a schematic diagram of oscillator inductor and capacitor layouts 602 and 604 according to some embodiments of the present disclosure.

[0113] Figures 6(a) and 6(b) are schematic diagrams of the layout of a complete oscillator inductor and capacitor according to an embodiment of this disclosure. Two sets of tail inductors, using single-turn metal wire, are located on either side of the first resonant region inductors 606 and 616, respectively. The magnetic flux flow direction of the tail inductors is indicated in the figures. The symmetrical layout ensures a balanced magnetic flux distribution, without affecting the first resonant region inductors 606 and 616. The tail inductors can be arranged laterally or vertically as needed. In this embodiment, the coupling capacitor (located in the region between VDD and VSS, not shown in the figures) and the capacitor array of the second resonant region are spatially separated, effectively reducing winding and area. The differential inductor array of the second resonant region is respectively disposed on both sides of the first resonant region inductor. This symmetrical design increases space utilization and reduces the overall circuit area.

[0114] Figure 7 shows a schematic diagram of oscillator inductor and capacitor layouts 702 and 704 according to other embodiments of the present disclosure.

[0115] Figure 7 shows another complete oscillator inductor and capacitor layout provided in an embodiment of this disclosure. Compared to Figure 4, the two sets of tail inductors use double-turn metal wires. For the same resonant frequency, the double-turn inductors produce a larger inductance value, enabling the required inductance to be achieved in a smaller area, further reducing the layout area.

[0116] Figure 8 shows a schematic diagram of oscillator inductor and capacitor layouts 802 and 804 according to some embodiments of the present disclosure.

[0117] Figure 8 shows another complete oscillator inductor and capacitor layout provided in this embodiment. Compared to Figure 5, the two sets of tail inductors are tilted at a 45-degree angle to the main inductor. Since the flux polarity bisector of the quasi-digit 8 inductor is basically perpendicular to the hypotenuse current line of the octagonal inductor in the first resonant region, the tail inductors have minimal impact on the inductor in the first resonant region. This layout allows the tail inductors to be closer to the main inductor, further improving area utilization. Optionally, as shown in Figure 8, the differential capacitor array can be set at the output terminals of the two sets of tail inductors, close to the extension line of the inductor in the first resonant region. Furthermore, the tail inductors can also be implemented using single-turn inductors.

[0118] Figure 9 shows schematic diagrams of oscillator inductor and capacitor layouts 902 and 904 in some embodiments according to the present disclosure.

[0119] Figure 9 shows another complete oscillator inductor and capacitor layout provided in this embodiment, with two sets of tail inductors placed directly below the first resonant inductor. The magnetic flux flow of the tail inductors is symmetrically distributed, having almost no effect on the first resonant inductor. In terms of layout, the quasi-digital 8 inductor still has a strong suppression effect on near-frequency interference. The differential capacitor array can be placed below the center of the quasi-digital 8 inductor. By mapping with the capacitor control word of the first resonant region, the control word of the differential capacitor array can be adjusted to adjust the resonant frequency of the second resonant region, covering the target frequency point of the entire frequency band. Figures 9(c) and 9(d) further show exploded views of the two sets of tail inductors superimposed with the common differential capacitor array.

[0120] It should be understood that if the two tail inductors Ln and Lp are overlapped (as shown in Figure 9), then only one set of differential capacitor arrays needs to be set up and placed below the two overlapping inductors. If the two tail inductors Ln and Lp are not overlapped and are placed separately as mirror images, then one set of differential capacitor arrays can be split into two sets of half-size differential capacitor arrays, each placed below the corresponding inductor, and Lp and Ln are respectively connected to the other inductor leads (as shown in Figures 6 to 8).

[0121] Figure 10 shows schematic diagrams of inductor architectures 1002 and 1004 according to the prior art and inductor architectures 1006 and 1008 according to some embodiments of the present disclosure. In inductor architecture 1002 shown in Figure 10(a), a figure-eight inductor 1010 according to the prior art is connected to a capacitor 1012. Similarly, in Figure 10(b), an octagonal inductor 1014 according to the prior art is also connected to a capacitor 1016.

[0122] In contrast, Figure 10(c) shows a single-turn inductor 1018 arranged above the differential capacitor array 1020, and Figure 10(d) shows a double-turn inductor 1022 arranged above the differential capacitor array 1024. In this way, compared to the scheme with two sets of single-ended capacitor arrays, using a differential capacitor array simplifies the process to using only one set of switches, while using only half the capacitor area, significantly reducing the area of ​​the tail oscillator, and making it easier to implement in the layout.

[0123] Figure 11 shows schematic diagrams of oscillator inductor and capacitor layouts 1102, 1104, 1106, and 1108 according to some embodiments of the present disclosure. As shown in Figure 11, layouts 1102 and 1104 are similar to those shown in Figure 6, but the differential capacitor array is not directly arranged below the inductor. Similarly, layouts 1106 and 1108 are similar to those shown in Figure 7, but again the differential capacitor array is not directly arranged below the inductor. In this way, the inductor can be partially stacked above the differential capacitor array without departing from the scope of the present disclosure.

[0124] While various embodiments of various aspects of this disclosure have been described for the purposes of this disclosure, they should not be construed as limiting the teachings of this disclosure to these embodiments. Features disclosed in one specific embodiment are not limited to that embodiment, but can be combined with features disclosed in different embodiments. For example, one or more features and / or functions of a product according to this disclosure described in one embodiment can also be applied individually, in combination, or holistically to another embodiment. Those skilled in the art will understand that many more possible alternative implementations and variations exist, and various changes and modifications can be made to the above structure without departing from the scope of protection of this disclosure.

Claims

1. An oscillator frequency modulation circuit, comprising: The first resonant region includes a first resonant circuit and a first coupling transistor (Mn) and a second coupling transistor (Mp) that are cross-coupled with the first resonant circuit. as well as The second resonant region includes a second resonant circuit, wherein the second resonant circuit includes: The first branch electrically connected to the first coupling tube (Mn); The second branch is electrically connected to the second coupling tube (Mp); The first inductor (Ln) is connected in series in the first branch; The second tail inductor (Lp) connected in series in the second branch; and A differential capacitor array (Ct) is connected in parallel between the first branch and the second branch.

2. The oscillator frequency modulation circuit according to claim 1, characterized in that, The differential capacitor array (Ct) is arranged near the common source node of the first coupling transistor (Mn) and the second coupling transistor (Mp).

3. The oscillator frequency modulation circuit according to claim 1, characterized in that, The second resonant circuit also includes a decoupling capacitor (Cd) connected in parallel between the first branch and the second branch.

4. The oscillator frequency modulation circuit according to claim 3, characterized in that, The first tail inductor (Ln) is arranged between the differential capacitor array (Ct) and the decoupling capacitor (Cd) on the first branch, and the second tail inductor (Lp) is arranged between the differential capacitor array (Ct) and the decoupling capacitor (Cd) on the second branch.

5. The oscillator frequency modulation circuit according to claim 1, characterized in that, The differential capacitor array (Ct) includes multiple branches connected in parallel between the first branch and the second branch, wherein each branch includes at least one switch and at least one capacitor.

6. The oscillator frequency modulation circuit according to claim 4, characterized in that, Each of the at least one switch is selected from an N-type switch or a P-type switch, wherein at least one capacitor is arranged on one or both sides of the at least one switch.

7. The oscillator frequency modulation circuit according to claim 5, characterized in that, Each of the plurality of branches includes at least one of a single NMOS transistor and a single-sided MOM capacitor, a single PMOS transistor and a single-sided MOM capacitor, a single NMOS transistor and a double-sided MOM capacitor, and a single PMOS transistor and a double-sided MOM capacitor.

8. The oscillator frequency modulation circuit according to claim 4, characterized in that, The capacitance value of the differential capacitor array (Ct) is determined by the state of the at least one switch.

9. The oscillator frequency modulation circuit according to claim 7, characterized in that, The state of at least one switch is determined by the control word of the differential capacitor array (Ct).

10. The oscillator frequency modulation circuit according to claim 8, characterized in that, The control word of the differential capacitor array (Ct) is determined based on the calibrated control word of the first resonant region.

11. The oscillator frequency modulation circuit according to claim 1, characterized in that, The coupling coefficient between the first tail inductor (Ln) and the second tail inductor (Lp) is configured to be adjusted between 0 and 1 according to the capacitance value of the differential capacitor array (Ct).

12. The oscillator frequency modulation circuit according to claim 1, characterized in that, The first branch is connected to the power supply, and the second branch is grounded.

13. The oscillator frequency modulation circuit according to claim 2, characterized in that, The first resonant circuit has a PMOS structure, an NMOS structure, or a CMOS structure.

14. The oscillator frequency modulation circuit according to claim 3, characterized in that, The decoupling capacitor (Cd) is a high-Q capacitor.

15. [Amended according to Rule 26, 20.01.2026] The oscillator frequency modulation circuit according to claim 1 is characterized in that, The first resonant circuit includes a main inductor (Lm), a variable capacitor (Cv), and a fixed capacitor (Cm) connected in parallel.

16. A communication chip, comprising a processor, a memory, a communication interface, and an oscillator frequency modulation circuit according to any one of claims 1 to 15.

17. The communication chip according to claim 15, characterized in that, The power supply for the oscillator frequency modulation circuit is an on-chip LDO or an off-chip LDO.

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