Signal delay circuit, data receiving chip and debugging method

Abstract

The present disclosure relates to a signal delay circuit, a data receiving chip and a debugging method. The signal delay circuit comprises: a plurality of registers and a signal selector; the plurality of registers respectively sample an enable signal on the basis of a clock edge of a clock signal and output delay signals, wherein delays of the delay signals outputted by different registers are different; and the signal selector selects one signal from among the plurality of delay signals and the enable signal as a target enable signal, wherein a signal edge of the target enable signal falls within a valid data interval of a data signal, and the signal edge of the target enable signal is used for indicating a time when a data receiving module reads the data signal. In embodiments of the present disclosure, precise delay control on the enable signal is realized by selecting delay signals of different delay amounts, thereby improving the delay precision and the accuracy of data reading.

Description

A signal delay circuit, a data receiving chip, and a debugging method.

[0001] This application claims priority to Chinese Patent Application No. 202411997954.4, filed on December 31, 2024, entitled "A Signal Delay Circuit, Data Receiving Chip and Debugging Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of computer technology, and in particular to a signal delay circuit, a data receiving chip, and a debugging method. Background Technology

[0003] In chip-to-chip communication, the data sender typically sends an enable signal along with the data signal. The receiving chip uses this enable signal as a clock to sample the data signal and thus acquire the data. When sending the signal, the sender ensures that the enable signal and the data signal are perfectly synchronized, meaning there is no delay between them. However, because the enable signal and the data signal are transmitted to the receiver via different traces, a delay deviation exists between them. This delay deviation is uncertain, leading to an uncertain phase relationship between the enable signal and the data signal received by the receiver.

[0004] Therefore, if the receiver directly uses the received enable signal to sample the data, sampling errors may occur. For example, the sampling time may be off-target, resulting in the acquisition of the previous or next data bit, thus failing to receive the correct data.

[0005] In related technologies, delay is controlled by adding traces to the printed circuit board (PCB) to reduce the delay difference between the data signal and the enable signal. However, it is uncertain how many traces need to be added to achieve accurate delay, and the trace length cannot be precisely controlled in actual production, resulting in low delay accuracy. Summary of the Invention

[0006] This disclosure proposes a signal delay technology solution.

[0007] According to one aspect of this disclosure, a signal delay circuit is provided, comprising: a plurality of registers and a signal selector;

[0008] The multiple registers sample the enable signal based on the clock edge of the clock signal and output a delay signal; the delay signals output by different registers have different delays.

[0009] The signal selector selects one signal from a plurality of the delay signals and the enable signals as a target enable signal. The signal edge of the target enable signal falls within the valid data range of the data signal, and the signal edge of the target enable signal is used to indicate the time for the data receiving module to read the data signal.

[0010] In one possible implementation, the plurality of registers includes:

[0011] A positive edge register that samples based on the rising edge of a clock signal; the positive edge registers are connected in series so that the time interval between the delay signals output by each positive edge register is one clock signal period;

[0012] or,

[0013] The negative edge registers are sampled based on the falling edge of the clock signal. The negative edge registers are connected in series so that the time interval of the delay signal output by each negative edge register is one clock signal period.

[0014] In one possible implementation, the plurality of registers includes: a positive edge register and a negative edge register;

[0015] The positive edge register and the negative edge register are connected in series or in parallel so that the time interval between the delay signals output by the positive edge register and the negative edge register is half a clock signal period.

[0016] In one possible implementation, the period of the enable signal is an even multiple of the period of the clock signal.

[0017] In one possible implementation, the time interval between the delay signals output by the plurality of registers is at least one-quarter of the enable signal.

[0018] In one possible implementation, the number of the plurality of registers is greater than or equal to the ratio of the period of the enable signal to the time interval.

[0019] In one possible implementation, the signal selector determines a target enable signal from a plurality of the delay signals and the enable signal based on a pre-configured target selection signal.

[0020] According to one aspect of this disclosure, a data receiving chip is provided, comprising: the aforementioned signal delay circuit and a data receiving module, wherein:

[0021] The signal delay circuit delays the received enable signal based on the clock edge of the clock signal to obtain a target enable signal, and then sends the target enable signal to the data receiving module.

[0022] The data receiving module receives the target enable signal and samples the data in the data signal along the signal edge of the target enable signal.

[0023] According to one aspect of this disclosure, a data receiving chip debugging method is provided, applied to the aforementioned chip, comprising:

[0024] The candidate selection signal is input to the signal selector of the chip. The selection signal is used to instruct the signal selector to select a candidate enable signal from the original enable signal and multiple delay signals.

[0025] From multiple candidate selection signals, determine the target selection signal that enables the candidate signal to fall within the effective data range of the data signal.

[0026] Configure the selection signal of the signal selector as the target selection signal.

[0027] In one possible implementation, determining a target selection signal from a plurality of candidate selection signals that causes the signal of the candidate enable signal to fall within the effective data range of the data signal includes:

[0028] The sampled data obtained by the chip based on multiple candidate enable signals is determined;

[0029] The sampled data are compared with the original data, which is the accurate data sent by the sending end.

[0030] The candidate selection signal that makes the sampled data consistent with the original data is used as the target selection signal.

[0031] In one possible implementation, determining a target selection signal from a plurality of candidate selection signals that causes the signal of the candidate enable signal to fall within the effective data range of the data signal includes:

[0032] In the presence of multiple target selection signals, the target selection signal that enables the candidate enable signal to fall at the midpoint of the effective data interval of the data signal is taken as the final target selection signal.

[0033] In this embodiment, multiple registers sample the enable signal based on the clock edge of the clock signal and output a delay signal. Then, a signal selector selects a target enable signal from the multiple delay signals and the enable signal, whose signal edge falls within the valid data range of the data signal. The signal edge of this target enable signal indicates the time for the data receiving module to read the data signal. Therefore, since the clock edge of the clock signal is fixed and periodic, based on the accuracy and stability of the clock edge, each sampling by the register generates a delay signal with a fixed delay relative to the original enable signal. Obviously, the clock edge-based delay method has higher accuracy and controllability compared to other delay methods that rely on non-fixed factors (such as line length, component performance variations, etc.).

[0034] Furthermore, by sampling the enable signal using multiple registers, multiple delay signals with different delays can be generated. These delay signals provide the signal selector with multiple options, allowing it to choose the delay signal with the most suitable delay amount. Thus, even if the time delay difference between the enable signal and the data signal cannot be predetermined, precise delay control of the enable signal can be achieved by selecting delay signals with different delay amounts, improving delay accuracy and data read accuracy.

[0035] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0037] Figure 1 shows a schematic diagram of the timing relationship of a signal provided in an embodiment of this disclosure.

[0038] Figure 2 shows a schematic diagram of the timing relationship of another signal provided in an embodiment of this disclosure.

[0039] Figure 3 shows a schematic diagram of the signal delay circuit according to an embodiment of the present disclosure.

[0040] Figure 4 shows a schematic diagram of the enable signal after register delay according to an embodiment of the present disclosure.

[0041] Figure 5 shows a schematic diagram of the enable signal after a register delay in another embodiment of this disclosure.

[0042] Figure 6 shows a schematic diagram of a series signal delay circuit according to an embodiment of the present disclosure.

[0043] Figure 7 shows a schematic diagram of the enable signal after a register delay in another embodiment of this disclosure.

[0044] Figure 8 shows a schematic diagram of a parallel signal delay circuit according to an embodiment of the present disclosure.

[0045] Figure 9 shows a schematic diagram of the enable signal after a register delay in another embodiment of this disclosure.

[0046] Figure 10 shows a schematic diagram of the enable signal after a register delay in another embodiment of this disclosure.

[0047] Figure 11 shows a schematic diagram of delay using a forward-edge register cascading method in an embodiment of this disclosure.

[0048] Figure 12 shows a schematic diagram of a delay method using a positive edge register and a negative edge register connected in parallel according to an embodiment of the present disclosure.

[0049] Figure 13 shows a schematic diagram of a delay method using a positive edge register and a negative edge register connected in parallel according to an embodiment of the present disclosure.

[0050] Figure 14 shows a schematic diagram of the structure of a data receiving chip according to an embodiment of the present disclosure.

[0051] Figure 15 shows a flowchart of a data receiving chip debugging method according to an embodiment of the present disclosure. Detailed Implementation

[0052] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0053] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0054] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0055] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0056] As described in the background section, during the transmission of a signal from the sender to the receiver, the delay deviation between the enable signal and the data signal of the data sender is uncertain. This delay deviation often originates from multiple factors, including the internal circuit delay of the sender, the influence of PCB board traces, and the influence of the internal traces of the receiver's chip.

[0057] When the enable signal and data signal reach the receiver chip through different traces on the PCB board, and then reach the sampling point through the internal traces of the receiver chip, the different paths they take lead to the uncertainty of the delay deviation.

[0058] In related technologies, delay is often controlled by routing traces on a PCB board. Specifically, the transmission time of the signal is changed by adjusting the length of the signal lines on the PCB board, thereby controlling the delay. However, precisely controlling the trace length requires extremely high process precision and manufacturing level, because even a small change in length can cause significant fluctuations in delay. In addition, it is impossible to determine in advance how much delay needs to be added, leading to uncertainty about whether the required increase in trace length on the PCB board is necessary.

[0059] Alternatively, delay units (such as AND gates, OR gates, or combinations thereof) can be used internally within the chip to control the delay. This involves adding extra circuit elements inside the chip to change the signal transmission path and time, thereby controlling the delay. However, the performance of delay units is affected by voltage and temperature. When voltage or temperature changes, the delay characteristics of the delay unit also change, thus affecting the accuracy and stability of the delay.

[0060] Figure 1 illustrates a timing relationship diagram of a signal provided in an embodiment of this disclosure. As shown in Figure 1, the data receiver reads data from the data signal based on the signal edges (rising and falling edges) of the enable signal, i.e., at the position indicated by the arrow in the figure. At this time, the correct data 01101 can be read. However, if there is an offset between the enable signal and the data signal, Figure 2 illustrates another timing relationship diagram of a signal provided in an embodiment of this disclosure. As shown in Figure 2, due to the different delays between the enable signal and the data signal, the phases of the two signals are offset, and the data signal is offset sequentially, resulting in the read data becoming 00110.

[0061] To improve the accuracy of signal delay and the accuracy of data received by the receiver, this disclosure provides a signal delay circuit, a data receiving chip, and a debugging method.

[0062] Figure 3 shows a schematic diagram of the signal delay circuit according to an embodiment of the present disclosure. As shown in Figure 3, the circuit 100 includes a plurality of registers 101 and a signal selector 102, wherein:

[0063] The plurality of registers 101 sample the enable signal and output a delay signal based on the clock edge of the clock signal; wherein the delay signals output by different registers have different delays;

[0064] The signal selector 102 selects one signal from a plurality of the delay signals and the enable signals as a target enable signal. The signal edge of the target enable signal falls within the valid data range of the data signal, and the signal edge of the target enable signal is used to indicate the time for the data receiving module to read the data signal.

[0065] A register is a sequential logic circuit element controlled by a clock signal. It can perform data reading and writing operations based on the clock signal, which provides the reference for the register's sampling operations. The register can sample the input enable signal at a specific edge of the clock signal (such as the rising or falling edge), that is, capture the level state of the input enable signal at that moment, and then send the sampled enable signal to the output port for output. In this process, the register does not need to temporarily store the sampled enable signal; that is, it sends the enable signal immediately after sampling.

[0066] A clock signal is a periodic signal used to synchronize the operation of digital circuits and to define the timing of circuit operations. The signal edge of a clock signal can be used to trigger the sampling operation of a register. A signal edge is the moment when a signal changes, specifically divided into rising edges and falling edges. When a signal transitions from a low level (e.g., 0) to a high level (e.g., 1), this point is called the rising edge of the signal; conversely, when a signal transitions from a high level (e.g., 1) to a low level (e.g., 0), this point is called the falling edge of the signal.

[0067] Since the phase relationship between the clock signal and the enable signal is uncertain, the signal edges of the clock signal and the enable signal are likely to be out of sync. When the register samples according to the clock edge, it will collect the enable signal at this time and send it out. Therefore, there will be a delay between the enabled signal sent out after collection and the original enable signal.

[0068] Figure 4 shows a schematic diagram of the enable signal after register delay according to an embodiment of the present disclosure. In the schematic diagram, the register samples the enable signal at each rising edge of the clock signal (the signal changes from low level to high level). At the first register sampling point on the left side of the figure, a high level is sampled, the second sampling point samples a low level, and so on, and the bottom delayed signal is sampled and output. As can be seen from the figure, the delayed signal is delayed relative to the enable signal.

[0069] If the delayed signal acquired in Figure 4 is input into the next register, and the next register further delays (acquires and outputs) based on the same clock signal, a second delay of the delayed signal can be achieved. If both registers are sampling registers based on the rising edge, then the delay interval of the delayed signal output by the two parallel registers will be one clock cycle. If the two registers are sampling registers based on the rising edge and the falling edge, respectively, then the delay interval of the delayed signal output by the two registers will be half a clock cycle. For details, please refer to the possible implementation methods provided in this article, which will not be elaborated here.

[0070] Clearly, by delaying the enable signal using multiple registers connected in series or parallel, multiple delayed signals can be obtained, with different delays output by different registers. Therefore, one of these delayed signals can be selected whose signal edge falls within the valid data range of the data signal. The data receiving module can then correctly read the data signal based on this delayed signal.

[0071] Figure 5 shows a schematic diagram of the enable signal after register delay in another embodiment of the present disclosure. In this schematic diagram, two registers are used to delay the enable signal respectively. Specifically, the enable signal is sampled by a positive edge register d0+ at each rising edge of the clock signal (the signal changes from low level to high level) to obtain the delay signal 1. Then, the delay signal 1 is sampled by a negative edge register d0- at each falling edge of the clock signal (the signal changes from high level to low level) to obtain the delay signal 2.

[0072] As shown in Figure 2, sampling the data signal based on the signal edge of delay signal 2 has been able to correctly sample the data 0110, while sampling based on delay signal 1 has not yet yielded accurate sampled data. Therefore, the delay signal 2 output from register d0 can be selected as the target enable signal.

[0073] Signal selection can be achieved using a signal selector, which selects one output signal from multiple input signals. In practical applications, a signal selector can be implemented as a data selector. Specifically, the signal selector selects one output signal from multiple input signals based on a selection signal (such as binary code). For example, an 8-to-1 signal selector can select one output signal from eight input signals based on a 3-bit binary selection signal.

[0074] The signal selector can select one signal from multiple delayed signals and the original enable signal as the target enable signal. Since the data receiving module reads the data signal based on the signal edge of the target enable signal, the signal selector will select the delayed signal whose signal edge falls within the valid data range of the data signal as the target enable signal sent to the data receiving module.

[0075] In this embodiment, multiple registers sample the enable signal based on the clock edge of the clock signal and output a delay signal. Then, a signal selector selects a target enable signal from the multiple delay signals and the enable signal, whose signal edge falls within the valid data range of the data signal. The signal edge of this target enable signal indicates the time for the data receiving module to read the data signal. Therefore, since the clock edge of the clock signal is fixed and periodic, based on the accuracy and stability of the clock edge, each sampling by the register generates a delay signal with a fixed delay relative to the original enable signal. Obviously, the clock edge-based delay method has higher accuracy and controllability compared to other delay methods that rely on non-fixed factors (such as line length, component performance variations, etc.).

[0076] Furthermore, by sampling the enable signal using multiple registers, multiple delay signals with different delays can be generated. These delay signals provide the signal selector with multiple options, allowing it to choose the delay signal with the most suitable delay amount. Thus, even if the time delay difference between the enable signal and the data signal cannot be predetermined, precise delay control of the enable signal can be achieved by selecting delay signals with different delay amounts, improving delay accuracy and data read accuracy.

[0077] In one possible implementation, the plurality of registers includes: a positive edge register that samples based on the rising edge of a clock signal; the positive edge registers are connected in series such that the time interval between the delay signals output by each positive edge register is one clock signal period; or, a negative edge register that samples based on the falling edge of a clock signal, the negative edge registers being connected in series such that the time interval between the delay signals output by each negative edge register is one clock signal period.

[0078] The rising edge register samples the input enable signal on the rising edge of the clock signal. When the clock signal changes from low to high, the rising edge register captures the level of the enable signal at that moment. As shown in Figure 5, delay signal 1 is obtained by sampling the enable signal through the rising edge register.

[0079] Figure 6 shows a schematic diagram of a series signal delay circuit according to an embodiment of the present disclosure. As shown in Figure 6, three positive edge registers are connected in series, and the multiple positive edge registers respectively obtain three delay signals. Selector 102 selects the three delay signals and an initial enable signal to obtain a target enable signal.

[0080] When multiple positive-edge registers are connected in series, the first register directly samples the input enable signal and outputs the first delayed signal; the second register samples the delayed signal output by the first register and outputs the second delayed signal. Therefore, the second delayed signal is actually a delay of the first delayed signal. This process continues, with each subsequent positive-edge register sampling the delayed signal output by the previous register and outputting a new delayed signal.

[0081] Since each positive edge register samples on the rising edge of the clock signal, the time interval between their output delay signals is exactly one clock cycle. If there are N (N is a positive integer) positive edge registers connected in series, then N delay signals with different delay amounts will be obtained, and the delay difference between these delay signals is one clock cycle.

[0082] Figure 7 illustrates a schematic diagram of the enable signal after register delay in another embodiment of this disclosure. In this diagram, two registers are used to delay the enable signal respectively. Specifically, a positive edge register d0+ samples the enable signal at each rising edge of the clock signal to obtain delay signal 1; then, another positive edge register d1+ samples delay signal 1 at each rising edge of the clock signal to obtain delay signal 2. Obviously, the delay difference between delay signal 1 and delay signal 2 is one clock cycle.

[0083] Negative edge registers sample the input enable signal on the falling edge of the clock signal. When the clock signal changes from high to low, the negative edge register captures the level of the enable signal at that moment. Similar to positive edge registers, multiple negative edge registers can be connected in series. The first negative edge register directly samples the input enable signal and outputs the first delayed signal, while subsequent negative edge registers sample the previous delayed signal and output a new delayed signal.

[0084] Similarly, since each negative-edge register samples on the falling edge of the clock signal, the time interval between their output delay signals is also one clock cycle. This time interval is one clock cycle. Further details are omitted here.

[0085] In this embodiment, a series of delay signals with different delay amounts can be obtained by cascading positive-edge registers or negative-edge registers. The time interval between these delay signals is one clock cycle. A signal selector can select the most suitable delay signal from these delay signals as the target enable signal, thereby ensuring that the data receiving module reads the data signal at the correct time. This implementation not only improves delay accuracy but also provides great flexibility and adaptability. The range of delay amounts can be significantly adjusted by simply increasing or decreasing the number of cascaded registers.

[0086] In one possible implementation, the plurality of registers includes a positive edge register and a negative edge register; the positive edge register and the negative edge register are connected in series or in parallel such that the time interval between the delay signals output by the positive edge register and the negative edge register is half a clock signal period.

[0087] As mentioned earlier, the positive edge register samples the input enable signal on the rising edge of the clock signal, and the delayed signal output by the series-connected positive edge register has a full clock cycle delay. Conversely, the negative edge register samples the input enable signal on the falling edge of the clock signal, and the delayed signal output by the series-connected negative edge register also has a full clock cycle delay.

[0088] The positive edge register and the negative edge register can be connected in parallel or in series. The two methods are explained below:

[0089] Positive edge register and negative edge register in parallel: Both positive edge register and negative edge register can be used simultaneously to sample the same enable signal. Positive edge register can be connected in series with multiple positive edge registers, and negative edge register can be connected in series with multiple negative edge registers.

[0090] Figure 8 shows a schematic diagram of a parallel signal delay circuit according to an embodiment of the present disclosure. As shown in Figure 8, four positive edge registers d0 to d3 are connected in series, four negative edge registers d4 to d7 are connected in series, and the positive edge registers and negative edge registers are connected in parallel. These eight registers respectively generate eight delay signals. Selector 102 selects from the eight delay signals and an initial enable signal to obtain a target enable signal.

[0091] As shown in Figure 5, the enable signal is delayed by parallel positive-edge registers and negative-edge registers. Specifically, a positive-edge register d0+ samples the enable signal at each rising edge of the clock signal (signal transitioning from low to high), obtaining delay signal 1. Then, a negative-edge register d0- samples delay signal 1 at each falling edge of the clock signal (signal transitioning from high to low), obtaining delay signal 2. As can be seen from Figure 2, delay signal 1 output by the negative-edge register is delayed by half a clock cycle compared to delay signal 2 output by the positive-edge register.

[0092] Positive-edge registers and negative-edge registers are connected in series. In a series connection, positive-edge registers and negative-edge registers can be connected alternately. For example, the first is a positive-edge register that samples the enable signal on the first rising edge of the clock signal; then its output can be connected to a negative-edge register, which samples the output of the previous positive-edge register on the first falling edge of the clock signal (i.e., half a clock cycle after the positive-edge register's sampling). In this way, the delayed signal output by the negative-edge register is half a clock cycle later than the delayed signal output by the positive-edge register.

[0093] In this way, positive edge registers and negative edge registers can be used alternately to generate delayed signal sequences with a half-clock cycle time interval.

[0094] In this embodiment of the disclosure, by connecting the positive edge register and the negative edge register in series or in parallel, the enable signal is delayed, which can generate a delayed signal with a time interval of half a clock cycle. This can reduce the delay interval of the delayed signal, more accurately control the delay amount of the enable signal, and meet the needs of various application scenarios.

[0095] In one possible implementation, the period of the enable signal is an even multiple of the period of the clock signal.

[0096] When the period of the enable signal is an even multiple of the period of the clock signal, it ensures that the high and low levels of the clock signal experience the same number of complete cycles within each enable cycle. Thus, regardless of the clock signal's duty cycle, the proportion of time occupied by the high and low levels of the clock signal when the enable signal is triggered remains consistent with the initial clock signal's duty cycle.

[0097] Duty cycle refers to the proportion of time a signal is at a high level (or active level) within one cycle. Maintaining a consistent duty cycle is crucial for ensuring the stability and reliability of clock and enable signals.

[0098] If the period of the enable signal is not an even multiple of the clock signal period, the time ratio of the high and low levels of the clock signal may change within one enable signal period, resulting in the duty cycle of the delayed signal being inconsistent with the initial signal.

[0099] Changes in duty cycle can cause signal distortion, which in turn affects the performance and stability of the circuit. In the embodiments of this disclosure, by keeping the enable signal period an even multiple of the clock signal period, the possibility of signal distortion can be reduced, ensuring the stability and reliability of the circuit.

[0100] In one possible implementation, the time interval between the delay signals output by the plurality of registers is at least one-quarter of the enable signal.

[0101] The enable signal is used to trigger a data read operation on the data signal. The signal edge of the enable signal must be within the valid range of the data signal; that is, the data read operation must be triggered within the valid range of the data signal. The valid range of the data signal is the time period during which the data is stable and can be reliably read.

[0102] If the enable signal edge falls at or outside the ends of the valid data range, a read error may occur because the data may be changing or not yet stable. When a digital signal changes (from high to low or from low to high), it experiences a transition region, which is the edge of the valid range. Near these edges, the signal level may be unstable and susceptible to noise and other interference.

[0103] If the minimum delay interval between two delayed signals is half an enable signal cycle, then the signal edges of two adjacent delayed signals may fall exactly at the two edges of the valid data interval. In this case, neither delayed signal will fall within the valid data interval, and even a small timing deviation may lead to a read error.

[0104] Therefore, to ensure that the positive edge of the delayed enable signal does not fall on or outside the edge of the valid data range, the time interval can be further reduced from half the enable signal period. Since the period of the enable signal is an even multiple of the period of the clock signal, the time interval of the delay signal can be set to at least a quarter of the enable signal period. This ensures that at least one edge of the delayed signal falls within the valid data range, thereby reducing the risk of reading incorrect data when reading data based on the signal edge.

[0105] Figure 9 shows a schematic diagram of the enable signal after a register delay in another embodiment of this disclosure. As shown in Figure 9, the time interval between delay signal 1 and delay signal 2 is half the period of the enable signal. At this time, the signal edges of delay signal 1 and delay signal 2 both fall at the edge of the valid data signal range, making it impossible to read data from the data signal based on the signal edge of either delay signal.

[0106] As shown in Figure 5, the time interval between delay signal 1 and delay signal 2 is one-quarter of the enable signal period. This ensures that delay signal 2 falls within the valid range of the data signal, allowing data to be read from its signal edge. Similarly, as shown in Figure 7, the time interval between delay signal 1 and delay signal 2 is also one-quarter of the enable signal period. This again ensures that delay signal 2 falls within the valid range of the data signal, allowing data to be read from its signal edge.

[0107] In this embodiment of the disclosure, the time interval between the delay signals output by the multiple registers is at least one-quarter of the enable signal. Even if there are clock jitter, signal delay and other uncertainties, it can be ensured that there is an enable signal whose signal edge falls near the center of the valid data interval in the delayed enable signal. This enables data reading based on the enable signal, thereby improving the accuracy and stability of data reading.

[0108] In one possible implementation, the number of the plurality of registers is greater than or equal to the ratio of the period of the enable signal to the time interval.

[0109] Since the delay difference between the enable signal and the data signal is often no more than one cycle of the enable signal, when delaying through multiple registers, the delay signal output by the registers should be able to delay the enable signal by at least one cycle.

[0110] Therefore, provided that the time interval between the delay signals output by multiple registers is at least one-quarter of the enable signal, the number of registers (N) should be greater than or equal to the period (T) of the enable signal. _enable The ratio of the delay signal to the time interval (Δt) of each delay signal is required to ensure that the maximum delay of the delay signals output by multiple registers can at least cover a complete enable signal cycle.

[0111] Furthermore, considering that the first register might sample the enable signal just after it has changed at the clock edge, it might not be able to effectively delay the enable signal. Figure 10 shows a schematic diagram of the delayed enable signal of another register in an embodiment of this disclosure. As shown in Figure 10, when the first register samples at the rising edge of the clock, the enable signal has just changed from low to high. At this time, the register samples the high level of the enable signal, and samples the high level of the enable signal at the next rising edge of the clock, and so on. As can be seen from Figure 10, the delayed signal 1 sampled by the register is only delayed for a very short period of time, and does not effectively delay the enable signal. The second register, connected in series with the first register, can further delay the delayed signal output by the first register by one clock cycle.

[0112] Therefore, since the first register may not be able to effectively delay the enable signal, the number of registers (N) should be greater than or equal to the period (T) of the enable signal. _enable The ratio of N to the time interval (Δt) of each delayed signal, plus 1, is required to ensure that the delayed signals output by multiple registers can cover at least one complete enable signal cycle. That is, N ≥ T. _enable Only by using / Δt+1 can we ensure that the delayed signals output by multiple registers can cover at least one complete enable signal cycle.

[0113] In this embodiment, by ensuring that the number of registers is greater than or equal to the ratio of the enable signal period to the time interval plus one, it can be guaranteed that the delayed signals output by the multiple registers can cover at least one complete enable signal period. This ensures that among the delayed signals output by the multiple registers, there is a signal that can delay the enable signal by one complete period. Thus, even if the delay difference between the enable signal and the data signal is one period, the enable signal can still be delayed by one period, and the data can then be accurately sampled using the delayed enable signal. By specifying a minimum number of registers, costs can be minimized while maintaining performance.

[0114] The following examples illustrate the number of registers in this disclosure.

[0115] To illustrate the worst-case scenario, the data signal is offset by one enable signal cycle relative to the enable signal, and the first register does not provide an effective delay for the enable signal.

[0116] Example 1: Implementation using cascading registers on the positive edge.

[0117] Figure 11 illustrates a schematic diagram of delay using a forward-edge register cascaded configuration according to an embodiment of this disclosure. The data signal in Figure 11 is shifted backward by one enable signal cycle relative to its position in Figure 1. Furthermore, the sampling time of the first register in Figure 11 coincides with the change in the enable signal's potential; therefore, the delayed signal output by the first register does not effectively delay the enable signal.

[0118] In this example, five cascaded positive edge registers d0+, d1+, d2+, d3+, and d4+ are used to delay the enable signal, as shown in Figure 11. In this example, the clock signal frequency is four times the enable signal frequency. Therefore, the time interval between the delay signals output by two adjacent registers is one-quarter of the enable signal's time. This continues until the signal edge of the delay signal 5 output by the fifth register d4+ falls exactly within the valid data range of the data signal. Obviously, a total of five registers are needed so that the maximum delay of the delay signal can just cover one clock cycle of the enable signal.

[0119] In the example in Figure 11, the ratio of the enable signal period to the time interval is 4, and since the first register does not effectively delay the enable signal, the minimum number of registers required is 4 + 1 = 5.

[0120] Example 2: The implementation uses a parallel connection of a positive edge register and a negative edge register.

[0121] Figure 12 illustrates a schematic diagram of a delay using a parallel connection of a positive-edge register and a negative-edge register in an embodiment of this disclosure. The data signal in Figure 12 is shifted backward by one enable signal cycle relative to its position in Figure 1. Furthermore, the sampling time of the first register in Figure 12 coincides with the change in the enable signal's potential; therefore, the delayed signal output by the first register does not effectively delay the enable signal.

[0122] In this example, five cascaded positive edge registers d0+, d1+, d2+, d3+, d4+, and d5+ are used to delay the enable signal, and four cascaded negative edge registers d0-, d1-, d2-, d3-, and d4- are used to delay the enable signal. The five cascaded positive edge registers and the four negative edge registers are connected in parallel.

[0123] As shown in Figure 12, in this example, the clock signal frequency is 4 times the enable signal frequency. Therefore, the time interval between the delay signals output by two adjacent registers is one-eighth of the enable signal. This continues until the signal edge of the delay signal 9 output by the 9th register d5+ falls within the effective data range of the data signal. Obviously, a total of 9 registers are needed so that the maximum delay of the delay signal can just cover the clock cycle of one enable signal.

[0124] In the example in Figure 12, the ratio of the enable signal period to the time interval is 8, and since the first register does not effectively delay the enable signal, the minimum number of registers required is 8 + 1 = 9.

[0125] Example 3: The implementation uses a parallel connection of a positive edge register and a negative edge register.

[0126] This example illustrates a non-worst-case scenario. Figure 13 shows a schematic diagram of a delay using a parallel connection of a positive-edge register and a negative-edge register according to an embodiment of this disclosure. The data signal in Figure 13 is shifted backward by half an enable signal cycle relative to its position in Figure 1. Furthermore, the sampling time of the first register in Figure 13 is not when the enable signal potential has just changed; therefore, the delayed signal output by the first register is an effective delay of the enable signal.

[0127] In this example, the same series-parallel connection method as in Example 2 is still used, that is, the five series positive edge registers d0+, d1+, d2+, d3+, d4+, and d5+ delay the enable signal respectively, and the four series negative edge registers d0-, d1-, d2-, d3-, and d4- delay the enable signal respectively. The five series positive edge registers and the four negative edge registers are connected in parallel.

[0128] As shown in Figure 13, in this example, the clock signal frequency is 4 times the enable signal frequency. Therefore, the time interval between the delay signals output by two adjacent registers is one-eighth of the enable signal. The signal edge of the delay signal 6 output by the 6th register d2 falls exactly within the effective data range of the data signal.

[0129] It should be noted that since developers cannot determine the delay difference between the enable signal and the data signal in advance, they cannot determine the duration of the delay required for the enable signal, nor can they determine whether the first register can effectively delay the enable signal. Therefore, even in the general case shown in Figure 13, developers need to use 9 registers to ensure that, in the worst case, the enable signal can still be delayed by one cycle, and then the delayed enable signal can be used to accurately sample the data.

[0130] In one possible implementation, the signal selector determines a target enable signal from a plurality of the delay signals and the enable signal based on a pre-configured target selection signal.

[0131] A signal selector has multiple input terminals, each of which can receive one signal. These input terminals receive delayed signals from the output of each register and the original enable signal, respectively. The selection signal is used to instruct the signal selector to select one signal from the input terminals for output. That is, it selects a candidate enable signal from the original enable signal and multiple delayed signals. Therefore, the selection signal determines which input signal of the signal selector will be transmitted to the output terminal.

[0132] Since the original enable signal and the multiple delay signals have different delays, at least one of the original enable signal and the multiple delay signals will enable the receiver to accurately sample the data in the data signal. For ease of description, this signal is called the target enable signal.

[0133] Therefore, by configuring the selection signal, a target enable signal can be selected from the original enable signal and multiple delay signals, and finally output to the data receiving module.

[0134] Furthermore, based on the embodiments provided in this disclosure, the data signal can also be delayed so that the clock edge of the enable signal falls within the valid data range of the data signal; this will not be elaborated further here. Any person skilled in the art can easily conceive of various variations or substitutions of the embodiments of this disclosure within the scope of the technology disclosed herein, and these should all be covered within the protection scope of this disclosure.

[0135] According to one aspect of this disclosure, a data receiving chip is provided. Figure 14 shows a schematic diagram of the structure of a data receiving chip according to an embodiment of this disclosure. As shown in Figure 14, the data receiving chip 200 includes: a signal delay circuit 100 and a data receiving module 201, wherein:

[0136] The signal delay circuit 100 delays the received enable signal based on the clock edge of the clock signal to obtain a target enable signal, and sends the target enable signal to the data receiving module.

[0137] The data receiving module 201 receives the target enable signal and samples the data in the data signal along the signal edge of the target enable signal.

[0138] The enable signal and the data signal originate from the data transmitter and are sent by the data transmitter. During the signal transmission process, a delay will occur. Since the enable signal and the data signal are transmitted through different leads, their delays are different, resulting in a delay difference.

[0139] The clock signal originates from within the data receiving chip and can be generated by its internal high-speed clock. The frequency of the clock signal is an even multiple of the enable signal frequency. The data receiving chip delays the received enable signal based on the clock edge of the clock signal to obtain the target enable signal, which is then sent to the data receiving module. For the specific implementation of the signal delay circuit for delaying the enable signal, please refer to the possible implementations of the signal delay circuit provided in this disclosure; details will not be elaborated here.

[0140] The data receiving module receives the target enable signal and the data signal, and samples the data signal according to the signal edge of the received target enable signal to obtain the data in the data signal. The data receiving module samples the data signal at the moment indicated by the signal edge of the target enable signal. That is, after receiving the target enable signal, the data receiving module waits for the moment when the signal state of the target enable signal changes (such as from low level to high level, or from high level to low level) before performing the data acquisition operation to collect the required data from the data signal.

[0141] In this embodiment of the disclosure, by adding a signal delay circuit to the data receiving chip, the circuit can perform precise delay control on the enable signal based on the signal edge of the clock signal. The data receiving module can sample the data in the data signal at the correct time point based on the delayed enable signal, thereby improving the accuracy and stability of data reception.

[0142] According to one aspect of this disclosure, a data receiver chip debugging method is provided. Figure 15 shows a flowchart of the data receiver chip debugging method according to an embodiment of this disclosure. As shown in Figure 15, the method includes:

[0143] In step S301, a candidate selection signal is input to the signal selector of the chip. The selection signal is used to instruct the signal selector to select a candidate enable signal from the original enable signal and multiple delay signals.

[0144] A signal selector is a circuit component with multiple inputs, each receiving a signal. These signals include a raw enable signal and a delayed signal generated by multiple registers. The selection signal is a control signal that indicates which input the signal selector will choose for output. Since the most suitable delayed signal (or raw enable signal) is not determined before debugging, multiple candidate selection signals will be input to the signal selector.

[0145] After the selection signal is input to the chip's signal selector, the signal selector will output the corresponding candidate enable signal. Each selection signal corresponds to one candidate enable signal, and different candidate enable signals have different delays for the enable signal.

[0146] Assume a signal selector has 10 inputs, receiving the original enable signal and 9 delayed signals. This results in 10 candidate selection signals, each corresponding to one input of the signal selector and one candidate enable signal at the selector's output.

[0147] In step S302, from a plurality of candidate selection signals, a target selection signal is determined that enables the signal edge of the candidate enable signal to fall within the effective data range of the data signal.

[0148] Each selection signal instructs the signal selector to output a candidate enable signal. Furthermore, it can be evaluated whether the signal edge of this candidate enable signal falls within the valid data range of the data signal. Among multiple candidate enable signals, at least one signal's signal edge will fall within the valid data range of the data signal. Therefore, for the obtained multiple candidate enable signals, it is possible to further evaluate which candidate enable signal's signal edge falls within the valid data range of the data signal.

[0149] In one possible implementation, determining the target selection signal from multiple candidate selection signals such that the signal edge of the candidate enable signal falls within the effective data range of the data signal includes: determining sampled data obtained by the chip from sampling the data signal based on the multiple candidate enable signals; comparing the multiple sampled data with the original data, wherein the original data is the accurate data sent by the transmitting end; and selecting the signal from the candidate selection signals that makes the sampled data consistent with the original data as the target selection signal.

[0150] After obtaining the candidate enable signals, they can be input into the chip's data receiving module. The data receiving module then samples the data signal based on the signal edges of the candidate enable signals to obtain sampled data. Since there is a time delay difference between each candidate enable signal, each signal edge corresponds to a different sampling time, thereby triggering the data receiving module to sample the data signal at different sampling times to obtain the corresponding sampled data.

[0151] If the edge of the candidate enable signal falls within the valid data range of the data signal, the sampled data triggered by the candidate enable signal to be sampled by the data receiving module should be the same as the original data. Here, the original data is the data sent by the transmitter and expected to be received by the receiver. For example, if the transmitter sends 01101, then the original data is 01101.

[0152] Therefore, the sampled data obtained under each candidate enable signal can be compared with the original data sent by the transmitter to determine the sampled data that is completely consistent with the original data. The control chip obtains the selection signal of this sampled data, which is the target selection signal that can correctly trigger the data receiving module to sample the data signal.

[0153] For example, the data receiving chip selects 10 candidate enable signals based on 10 selection signals, and samples the data signal to obtain 10 sampled data. These 10 sampled data are compared with the original data, and it is determined that the candidate enable signal selected by the 5th selection signal can make the sampled data consistent with the original data. Then, the 5th selection signal can be used as the target selection signal.

[0154] In this embodiment, the validity of the candidate enable signal is verified by comparing the sampled data obtained based on the candidate enable signal with the original data. This allows for the accurate determination of the candidate enable signal that ensures correct data acquisition within the valid data range, and further, the accurate determination of the target selection signal that can select from the candidate enable signal. Therefore, based on the selected target selection signal, data signal sampling is performed within the valid data range, achieving accurate data reception and improving the reliability of the data receiving chip.

[0155] In step S303, the selection signal of the signal selector is configured as the target selection signal.

[0156] After determining the target selection signal, the selection signal of the signal selector can be configured to this target selection signal. In this way, the signal selector can select the final enable signal from the original enable signal and multiple delay signals based on this target selection signal.

[0157] When configuring the target selection signal, the register used to indicate the selection signal can be configured. The signal selector can generate the corresponding selection signal according to the value configured in the register, and then select the target enable signal based on the selection signal.

[0158] For example, after determining the fifth selection signal as the target selection signal, it can be configured as the selection signal of the signal selector. Then, regardless of how the data signal changes, the signal selector will select the optimal enable signal from the original enable signal and delay signal based on the fifth selection signal to ensure that the data is acquired at the correct time.

[0159] In this embodiment, when the delay difference between the enable signal and the data signal cannot be determined in advance, multiple delay signals are obtained by setting multiple registers. Then, multiple selection signals are used to select different delay signals as candidate enable signals to acquire the data signal. From these candidate selection signals, a target selection signal is determined that ensures the signal edge of the candidate enable signal falls within the effective data range of the data signal. Based on the target selection signal, the data receiving module can sample within the effective data range of the data signal, improving the accuracy and stability of the data received by the data receiving chip.

[0160] Furthermore, this debugging method can select the optimal delay signal from multiple candidate signals based on the actual signal delay. Even if the operating conditions or environment of the data receiving chip change, the delay of the enable signal can be dynamically adjusted to adapt to changes in signal transmission, further improving the accuracy and stability of the data receiving chip.

[0161] In one possible implementation, determining the target selection signal from multiple candidate selection signals that causes the signal edge of the candidate enable signal to fall within the effective data interval of the data signal includes: when multiple target selection signals exist, taking the target selection signal that causes the signal edge of the candidate enable signal to fall near the midpoint of the effective data interval of the data signal as the final target selection signal.

[0162] In practical applications, there may be multiple candidate enable signals whose signal edges fall within the effective data range of the data signal. As shown in Figure 12, the rising edges of delay signals 3, 4, 5, and 6 (candidate enable signals) all fall within the effective data range of the data signal. Therefore, the selection signals corresponding to delay signals 3, 4, 5, and 6 can all be used as target selection signals, and one of them can be randomly selected as the target selection signal.

[0163] Furthermore, to improve the accuracy and stability of data sampling, a further selection strategy can be used to determine the final target selection signal. Specifically, the target selection signal can be chosen as the signal that causes the candidate enable signal to fall near the midpoint of the effective data interval of the data signal. Therefore, for the delay signals 3, 4, 5, and 6 in Figure 12, the selection signal corresponding to 4 or 5 can be selected as the target selection signal.

[0164] Specifically, given that the connection method of multiple registers is known, the order of the registers can be obtained by sorting them according to the delay duration of the enable signal. If multiple registers can ensure that the signal edge of the candidate enable signal falls within the valid data range, the register in the middle position among these registers can be selected as the final target selection signal according to this order. If there are two registers in the middle position, either one can be selected as the final target selection signal.

[0165] For example, in the register connection method shown in Figure 8, the order is either order 1: (d0, d4, d1, d5, d2, d6, d3, d7) or order 2: (d4, d0, d5, d1, d6, d2, d7, d3). For order 1, if there are four registers d1, d5, d2, and d6 that ensure the signal edges of the candidate enable signals fall within the valid data range, then obviously the candidate enable signals selected by d5 and d2 are closer to the midpoint of the valid data range than d1 and d6. Therefore, the target selection signal corresponding to d5 or d2 can be selected as the final target selection signal. For order 2, if there are four registers d5, d1, d6, and d2 that ensure the signal edges of the candidate enable signals fall within the valid data range, then obviously the candidate enable signals selected by d1 and d6 are closer to the midpoint of the valid data range than d5 and d2. Therefore, the target selection signal corresponding to d1 or d6 can be selected as the final target selection signal.

[0166] In this embodiment of the disclosure, by selecting a target selection signal close to the midpoint of the effective data interval, it can be ensured that data sampling occurs in the interval where the data signal is most stable and least affected by noise, thereby improving the accuracy and reliability of data reception.

[0167] According to one aspect of this disclosure, an electronic device is provided, including the low-power control circuit of the chip described above provided in this disclosure.

[0168] Other configurations of the chips or electronic devices in the above embodiments can be derived from various technical solutions now and in the future known to those skilled in the art, and will not be described in detail here.

[0169] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0170] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0171] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0172] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0173] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0174] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements have been described above. Of course, these are merely examples and are not intended to limit the scope of this disclosure. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0175] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A signal delay circuit, characterized in that, include: Multiple registers and signal selectors; The multiple registers sample the enable signal based on the clock edge of the clock signal and output a delay signal; the delay signals output by different registers have different delays. The signal selector selects one signal from a plurality of the delay signals and the enable signals as a target enable signal. The signal edge of the target enable signal falls within the valid data range of the data signal, and the signal edge of the target enable signal is used to indicate the time for the data receiving module to read the data signal.

2. The signal delay circuit according to claim 1, characterized in that, The plurality of registers includes: A positive edge register that samples based on the rising edge of a clock signal; the positive edge registers are connected in series so that the time interval between the delay signals output by each positive edge register is one clock signal period; or, The negative edge registers are sampled based on the falling edge of the clock signal. The negative edge registers are connected in series so that the time interval of the delay signal output by each negative edge register is one clock signal period.

3. The signal delay circuit according to claim 1, characterized in that, The plurality of registers includes: a positive edge register and a negative edge register; The positive edge register and the negative edge register are connected in series or in parallel so that the time interval between the delay signals output by the positive edge register and the negative edge register is half a clock signal period.

4. The signal delay circuit according to claim 1, characterized in that, The period of the enable signal is an even multiple of the period of the clock signal.

5. The signal delay circuit according to claim 1, characterized in that, The time interval between the delay signals output by the plurality of registers is at least one-quarter of the time interval between the enable signals.

6. The signal delay circuit according to claim 5, characterized in that, The number of the plurality of registers is greater than or equal to the ratio of the period of the enable signal to the time interval plus one.

7. The signal delay circuit according to claim 1, characterized in that, The signal selector determines a target enable signal from a plurality of the delay signals and the enable signals based on a pre-configured target selection signal.

8. A data receiving chip, characterized in that, include: The signal delay circuit and data receiving module as described in any one of claims 1 to 7, wherein: The signal delay circuit delays the received enable signal based on the clock edge of the clock signal to obtain a target enable signal, and then sends the target enable signal to the data receiving module. The data receiving module receives the target enable signal and samples the data in the data signal along the signal edge of the target enable signal.

9. A method for debugging a data receiving chip, characterized in that, Applied to the chip as described in claim 8, comprising: The candidate selection signal is input to the signal selector of the chip. The selection signal is used to instruct the signal selector to select a candidate enable signal from the original enable signal and multiple delay signals. From multiple candidate selection signals, determine the target selection signal that enables the candidate signal to fall within the effective data range of the data signal. Configure the selection signal of the signal selector as the target selection signal.

10. The method according to claim 9, characterized in that, The step of determining, from multiple candidate selection signals, a target selection signal that causes the signal of the candidate enable signal to fall within the effective data range of the data signal includes: The sampled data obtained by the chip based on multiple candidate enable signals is determined; The sampled data are compared with the original data, which is the accurate data sent by the sending end. The candidate selection signal that makes the sampled data consistent with the original data is used as the target selection signal.

11. The method according to claim 10, characterized in that, The step of determining, from multiple candidate selection signals, a target selection signal that causes the signal of the candidate enable signal to fall within the effective data range of the data signal includes: In the presence of multiple target selection signals, the target selection signal that enables the candidate enable signal to fall at the midpoint of the effective data interval of the data signal is taken as the final target selection signal.