Compute-in-memory system, control method, control apparatus, and electronic device

Abstract

The present invention relates to the technical field of compute-in-memory. Disclosed are a compute-in-memory system, a control method, a control apparatus, and an electronic device. The compute-in-memory system comprises: a memory circuit, a sensing circuit, and a control circuit. The memory circuit converts an input signal into an output signal on the basis of stored weight data; and the sensing circuit senses the output signal. The control circuit controls, during a first time period, the memory circuit to be in a first operating state and the sensing circuit to be in a disabled state, and controls, during a second time period, the memory circuit to be in a second operating state and the sensing circuit to be in an enabled state. In this way, the control circuit controls a memory cell group to implement establishment of a stable state in advance, thereby establishing conditions in advance for computation of the memory cell group; the sensing circuit is disabled in the condition establishment process, thereby preventing sensing and outputting of a non-computation result; and then the memory cell group is triggered to perform computation, and sensing of a computation result is triggered. This greatly improves computing efficiency, thereby improving computing performance of a compute-in-memory architecture.

Description

In-memory computing systems, control methods, control devices, and electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202411832568.X, filed on December 12, 2024, entitled "In-memory computing system, control method, control device and electronic device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more specifically, to a memory computing system, control method, control device, and electronic device. Background Technology

[0003] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0004] In-memory computing (IMC) architecture physically merges storage and computation, enabling computation through storage devices or storing data within computing devices. This reduces data transfer requirements, lowers latency and energy consumption, and significantly improves data processing efficiency. However, IMC architecture still faces challenges; for example, its computational performance needs further improvement. Summary of the Invention

[0005] This application provides a memory computing system, control method, control device, and electronic device that can improve the computing performance of a memory computing architecture.

[0006] In a first aspect, a storage computing system is provided, comprising: a storage circuit including a storage unit group comprising multiple storage units for storing weight data; the storage unit group receiving an input signal and converting the input signal into an output signal based on the weight data; a sensing circuit connected to the storage circuit for sensing the output signal of the storage circuit; and a control circuit controlling the storage unit group to be in a first operating state and controlling the sensing circuit to be in a disabled state during a first time period, and controlling the storage unit group to be in a second operating state and controlling the sensing circuit to be in an enabled state during a second time period; in the first operating state, the storage unit group establishes a stable state; and in the second operating state, the storage unit group converts the input signal into the output signal based on the weight data.

[0007] In some implementations of the first aspect, the operating time of the sensing circuit is less than or equal to the establishment time of the steady state of the memory cell group.

[0008] In some implementations of the first aspect, the control circuit is also used to control the memory cell group to alternately operate in a first operating state and a second operating state, and to control the sensing circuit to alternately operate in a de-enabled state and an enabled state.

[0009] In some implementations of the first aspect, the in-memory computing system further includes: a switching circuit comprising multiple switching units, one switching unit corresponding to one memory unit, and multiple switching units being in an on state during a first time period; wherein, the switching unit is located at the input terminal of the corresponding memory unit, and the control circuit controls the switching unit to be on or off based on the input signal to control the input state of the memory unit group; or, the switching unit is located at the output terminal of the corresponding memory unit, and the control circuit controls the switching unit to be on or off based on the input signal to control the output state of the memory unit group.

[0010] In some implementations of the first aspect, the control circuit is used to control the operating mode of the storage circuit, which includes a first operating mode or a second operating mode; in the first operating mode, the control circuit is used to control the storage cell group to be in a first operating state during a first time period and to control the sensing circuit to be in a disabled state during a second time period, and to control the storage cell group to be in a second operating state during a second time period; in the second operating mode, the control circuit is used to control the storage cell group to be in a second operating state.

[0011] In some implementations of the first aspect, the control circuit controls the operating mode of the storage circuit based on the operating time of the sensing circuit or the pattern of the input signal.

[0012] Secondly, a control method is provided for controlling a storage circuit and a sensing circuit. The storage circuit includes a storage unit group comprising multiple storage units for storing weight data. The storage unit group receives an input signal and converts the input signal into an output signal based on the weight data. The sensing circuit senses the output signal of the storage circuit. The method includes: controlling the storage unit group to be in a first operating state during a first time period and controlling the sensing circuit to be in a disabled state during a second time period; controlling the storage unit group to be in a second operating state during a second time period and controlling the sensing circuit to be in an enabled state during a second time period; in the first operating state, the storage unit group establishes a stable state; and in the second operating state, the storage unit group converts the input signal into an output signal based on the weight data.

[0013] For a description of the beneficial effects of the second aspect, please refer to the description of the beneficial effects of the first aspect, which will not be repeated here.

[0014] In some implementations of the second aspect, the operating time of the sensing circuit is less than or equal to the establishment time of the steady state of the memory cell group.

[0015] In some implementations of the second aspect, the method further includes: controlling the memory cell group to alternately operate in a first operating state and a second operating state; and controlling the sensing circuit to alternately operate in a de-enabled state and an enabled state.

[0016] In some implementations of the second aspect, the method further includes: controlling the operating mode of the storage circuit, the operating mode including a first operating mode or a second operating mode, wherein in the first operating mode, the control circuit is used to control the storage cell group to be in a first operating state in a first time period and control the sensing circuit to be in a disabled state, and in the second time period, the control circuit is used to control the storage cell group to be in a second operating state and control the sensing circuit to be in an enabled state; in the second operating mode, the control circuit is used to control the storage cell group to be in the second operating state.

[0017] In some implementations of the second aspect, the method further includes: controlling the operating mode of the storage circuit based on the operating time of the sensing circuit or the pattern of the input signal.

[0018] Thirdly, a control device is provided, including a unit or means for performing any of the control methods of the second aspect.

[0019] For a description of the third aspect, please refer to the description of the first aspect; it will not be repeated here.

[0020] Fourthly, a control device is provided, comprising at least one processor and an interface circuit, the interface circuit being signal-connected to a storage circuit and a sensing circuit, the at least one processor being used to execute any of the control methods of the second aspect.

[0021] Fifthly, a control device is provided, configured to perform any of the control methods of the second aspect.

[0022] In a sixth aspect, an electronic device is provided, comprising any of the storage and computing systems of the first aspect.

[0023] In the aforementioned in-memory computing system, the control circuit can pre-establish a stable state for the storage cell group within the storage circuit, thus setting the conditions for the calculation of the storage cell group in advance. During the condition establishment process, the sensing circuit is enabled to prevent the sensing and output of non-calculation results. Then, the storage cell group is triggered to execute the calculation, and the sensing of the calculation result is also triggered. Because the storage cell group has established a stable state in advance, it can quickly respond to input signals and perform fast and stable outputs during calculation execution, greatly improving computational efficiency and thus enhancing the computing performance of the in-memory computing architecture. Attached Figure Description

[0024] Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0025] Figure 2 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0026] Figure 3 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0027] Figure 4 shows a signal diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0028] Figure 5 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0029] Figure 6 shows a schematic diagram of the connection relationship between several switching units and storage units according to exemplary embodiments of this application.

[0030] Figure 7 shows a schematic diagram of the connection relationship between several switching units and storage units according to exemplary embodiments of this application.

[0031] Figure 8 shows schematic diagrams of different operating modes of the storage circuit according to exemplary embodiments of this application.

[0032] Figure 9 shows a flowchart of a control method according to an exemplary embodiment of this application.

[0033] Figure 10 shows a schematic block diagram of a control device according to an exemplary embodiment of the present application.

[0034] Figure 11 shows a schematic diagram of an electronic device according to an exemplary embodiment of this application. Detailed Implementation

[0035] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0036] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0037] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0038] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0039] In a memory-based computing architecture, the memory-based computing system can perform in-memory computation (or operations) using memory as the carrier. This memory can include: non-volatile memory (NVM) or volatile memory (VM). Volatile memory can include, but is not limited to: static random access memory (SRAM); non-volatile memory can include, but is not limited to: flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), or phase change memory (PCM), etc.

[0040] For ease of understanding, Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0041] As shown in Figure 1, the in-memory computing system 100 includes a storage circuit 110 and a control circuit 120. The storage circuit 110 stores weight data (also known as weights); the control circuit 120 controls the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0042] The memory cell utilizes the conduction capability of a semiconductor device, such as electrical conductance or transconductance, to store weight data. For example, the memory cell may include a resistive memory device or a transistor memory device. For instance, weight data can be stored by controlling the electrical conductance of a resistive memory device, or by controlling the transconductance of a transistor memory device.

[0043] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group can achieve an equivalent multiplication operation. The storage cell array includes a one-dimensional array or a two-dimensional array, etc., and the storage cell group includes multiple storage cells located in the same row or column, or multiple storage cells located in multiple rows or columns, etc. These multiple storage cells can output their output signals collinearly.

[0044] In some possible implementations, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 converts input data D1 into at least one input signal Sin and provides it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 converts the output signal Sout into output data D2 and outputs it. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0045] In some possible implementations, the output circuit 140 may include at least one conversion circuit that can sense the output signal Sout and convert the output signal Sout into output data D2 for subsequent circuits.

[0046] As an example, Figure 2 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0047] As shown in Figure 2, the in-memory computing system 200 includes a storage cell array 210, which includes multiple storage cells S. ij Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij Store weight data W ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit Sij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0048] In some possible implementations, the input data includes digital input signals, such as the input signal V of the storage cell array 210. i The input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible implementations, the input signal to the memory cell array 210 may include a digital signal, represented by waveform characteristics such as pulse width, amplitude, or area. The input circuit 230 adjusts the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array.

[0049] In some possible implementations, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For example, if the input signal includes a voltage signal and the output signal includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242. The second conversion can be implemented, for example, through a sampling circuit, and the signal converted by the first conversion circuit 241 can be further provided to the second conversion circuit 242 for a second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert the current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal and provide it to the subsequent circuit. Additionally, in the example of FIG. 2, the control circuit 220 can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0050] Figure 2 is only an example illustrating a connection method of memory cells in a memory cell array 210. Other connection methods can be used besides those shown in Figure 2. For example, the input terminals of the memory cells can be connected collinearly by columns, and the output terminals can be connected collinearly by rows. Furthermore, the input terminal of the memory cell may include the gate of a transistor memory device, or it may include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, the memory cell may include a floating gate transistor (FGT), a memristor, a magnetic tunnel junction (MTJ), or a phase-change structure. Furthermore, the memory cell may include multiple transistors; for example, the memory cell includes a first transistor and a second transistor, where the gate of one transistor is connected to the source or drain of the other transistor, and the gate is used to store charge. Optionally, the gate may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0051] In the storage circuit, after the input circuit 130 inputs the input signal Sin to the storage circuit 110, it waits for the state of the storage circuit 110 to stabilize before converting and outputting the output signal. However, the time it takes for the storage circuit to reach a stable state is affected by the parasitic electrical characteristics of the storage circuit itself, such as parasitic resistance and capacitance (RC), which results in a longer time for the storage circuit to reach a stable state, which may affect the computing efficiency of the in-memory computing system. In view of this, embodiments of this application provide an in-memory computing system that can improve the computing performance of an in-memory computing architecture.

[0052] For example, referring to Figure 3, a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown. As shown in Figure 3, the in-memory computing system 300 includes a storage circuit 310, a sensing circuit 320, and a control circuit 330. The storage circuit 310 is connected to the sensing circuit 320, and the control circuit 330 is connected to both the storage circuit 310 and the sensing circuit 320.

[0053] The storage circuit 310 includes one or more storage cell groups 311, each containing multiple storage cells. These storage cells can store weight data, and the weight data stored in the multiple storage cells can be used for calculations within the storage cell group. The storage cell group within the storage circuit 310 is used to receive the input signal Sin and convert the received input signal Sin into an output signal Sout based on the weight data stored in the storage cells within the group. A description of the storage circuit 310 can be found in the descriptions of Figures 1 and 2 above, and will not be repeated here.

[0054] The sensing circuit 320 is used to sense the output signal Sout of the storage circuit 310. For example, the sensing circuit 320 can perform at least one of the first conversion or the second conversion on the output signal Sout of the storage circuit 310.

[0055] In some possible implementations, the sensing circuit 320 may include the first conversion circuit 241 described above. The sensing circuit 320 senses the output signal Sout of the storage circuit 310, which can be understood as: the sensing circuit 320 performs a first conversion process on the output signal Sout of the storage circuit 310; for example, if the output signal Sout of the storage circuit 310 is a current signal, the sensing circuit 320 converts the current signal into a voltage signal.

[0056] In some possible implementations, the sensing circuit 320 may include the first conversion circuit 241 and the second conversion circuit 242 described above. Correspondingly, the sensing circuit 320 senses the output signal Sout of the storage circuit 310, which can be understood as: the sensing circuit 320 performs a first conversion process and a second conversion process on the output signal Sout of the storage circuit 310; for example, if the output signal Sout of the storage circuit 310 is a current signal, the sensing circuit 320 converts the current signal into a voltage signal and samples and outputs the voltage signal, for example, through analog-to-digital conversion.

[0057] In some possible implementations, the control circuit 330 can control the operating states of the storage circuit 310 and the sensing circuit 320 at different time periods. For example, in a first time period, the control circuit 330 controls the storage unit group 311 to be in a first operating state and controls the sensing circuit 320 to be in a disabled state (or non-operating state); in a second time period, the control circuit 330 controls the storage unit group 311 to be in a second operating state and controls the sensing circuit 320 to be in an enabled state (or operating state). In the first operating state, the storage unit group 311 establishes a stable state; in the second operating state, the storage unit group 311 converts the input signal Sin into the output signal Sout based on the weight data. The establishment of a stable state refers to the process by which the storage circuit 310 or the storage unit group 311 receives a signal at the input terminal and outputs a stable signal at the output terminal.

[0058] In the aforementioned in-memory computing system, the control circuit can pre-establish a stable state for the storage cell group within the storage circuit, thus setting the conditions for the calculation of the storage cell group in advance. During the condition establishment process, the sensing circuit is enabled to prevent the sensing and output of non-calculation results. Then, the storage cell group is triggered to execute the calculation, and the sensing of the calculation result is also triggered. Because the storage cell group has established a stable state in advance, it can quickly respond to input signals and perform fast and stable outputs during calculation execution, greatly improving computational efficiency and thus enhancing the computing performance of the in-memory computing architecture.

[0059] For example, referring to Figure 4, a signal diagram of a memory computing system according to an exemplary embodiment of this application is shown. In Figure 4, time period P1 represents a first time period, time period P2 represents a second time period, and signals S1-Sx represent multiple sub-signals coupled to the input terminals of the memory cell group. x represents the number of sub-signals or the number of input terminals of the memory cell group. Different sub-signals may be the same or different in the same time period. The signal coupled to the input terminal in time period P2 is the input signal. The input signals received by different input terminals may be the same or different, and may change based on the input data in different computing applications. Tr represents a trigger signal that triggers the operation of the sensing circuit 320. This trigger signal Tr enables or de-enables the operation of the sensing circuit 320. Figure 4 shows a high-level enable as an example. In some other embodiments, a low-level enable can be used to trigger the operation of the sensing circuit 320, and this disclosure does not limit this. As shown in Figure 4, the control circuit 330 controls the storage circuit 310 to be in a first operating state during time period P1. For example, in the first operating state, the sub-signals S1-Sx coupled to the input terminal are signals greater than 0. These signals can be provided to the storage cells, enabling the storage cell group to establish a stable state. For example, the voltage at the input terminal of the storage cell is pre-charged to a target value. This disclosure does not limit the value of the target value; it can have different values ​​in different application scenarios. In the first operating state, the sub-signals coupled to the input terminal of the storage circuit group are used to establish a stable state, not the actual input signal obtained from the input data. The control circuit 330 controls the sensing circuit 320 to be in a disabled state during time period P1, which can reduce the power consumption of the sensing circuit 320 and prevent the output of invalid signals. The control circuit 330 controls the storage circuit 310 to be in a second operating state during time period P2. At this time, the input signal can be provided to the input terminal of the storage cell group, and the storage cell group can complete the conversion from input signal to output signal based on the stored weight data. Control circuit 330 keeps sensing circuit 320 enabled during time period P2, reducing power consumption and enabling timely output of calculation results to subsequent circuits. Overall, the input signal can include sub-signals greater than "0" and sub-signals equal to "0". Within a certain time period, the input signal may exist in a state with only sub-signals greater than "0" or only sub-signals equal to "0". Since the input-coupled sub-signals S1-Sx have already helped establish a stable state for the storage cell group during time period P1, thus establishing the calculation conditions for the storage circuit, the storage circuit can quickly respond to the input signal and output a stable output signal during time period P2. Sensing circuit 320, in its active state, can also quickly output the output signal, greatly improving the computational efficiency of the in-memory computing system and significantly enhancing the performance of the in-memory computing architecture. This solution offers significant efficiency and performance advantages, especially for scenarios with high computational frequency, such as continuous inference or training.

[0060] In some possible implementations, the control circuit 330 can control some or all of the memory cell groups in the storage circuit 310 to be in a first operating state during time period P1 and in a second operating state during time period P2. In application, the number of memory cell groups in the storage circuit 310 that are in the first operating state during time period P1 and the number of memory cell groups that are in the second operating state during time period P2 can be flexibly controlled as needed.

[0061] After the sensing circuit 320 finishes sensing the calculation result, the storage circuit 310 and the sensing circuit 320 can return from the second working state to the first working state, and restore the state of the storage cell that was changed in the second working state to a stable state, for example, by recharging the voltage value at the input terminal of the storage cell to the target value.

[0062] In some possible implementations, the shorter the time it takes for the sensing circuit 320 to sense the calculation result, the faster the storage circuit 310 can initiate the process of returning to a stable state. Therefore, the smaller the change in the storage cells in the storage circuit 310, the faster it can return to a stable state, resulting in higher computational efficiency. In some embodiments, the operating time of the sensing circuit 320 is set to be less than or equal to the establishment time of the stable state of the storage cell group in the storage circuit 310. In this way, the sensing circuit 320 can complete the sensing of the calculation result before the state of the storage cell changes to the initial state when the coupling signal is 0, thereby further improving the computational efficiency of the in-memory computing system.

[0063] In some possible implementations, the control circuit 330 can control the memory cell group in the memory circuit 310 to alternately operate in a first operating state and a second operating state, and control the sensing circuit 320 to alternately operate in a disabled state and an enabled state. In this way, the state changes of the memory cells can be minimized, so that when the memory circuit returns to the first operating state, the memory cells can recover to a stable state more quickly, and the calculation conditions of the memory circuit can be restored as soon as possible.

[0064] In some possible implementations, inputs with a sub-signal of "0" can be quickly turned off via a switching circuit, effectively providing a sub-signal input of "0" to the memory cell group. For example, Figure 5 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application. As shown in Figure 5, the in-memory computing system 500 may include a storage circuit 510, a sensing circuit 520, a control circuit 530, and a switching circuit 540. The switching circuit 540 includes multiple switching units, with one switching unit (or switching element) corresponding to one or more memory cells. For example, for a memory cell group, one switching unit may correspond to one memory cell within the memory cell group, thereby enabling input of sub-signals "0" or non-"0" sub-signals by controlling the switching unit to be on or off. One switching unit may correspond to multiple memory cells in multiple memory cell groups, thus saving the number of switching units, reducing hardware overhead in the in-memory computing system, reducing costs, and saving chip area.

[0065] In some implementations, the switching unit is located at the input terminal of the corresponding memory cell, and the control circuit 520 controls the switching unit to be turned on or off based on the input signal to control the input state of the memory cell group. For example, for a non-"0" sub-signal in the input signal, the switching unit can be in the on state; for a sub-signal "0" in the input signal, the switching unit can be in the off state.

[0066] In some implementations, the switching unit is located at the output terminal of the corresponding memory cell, and the control circuit 520 controls the switching unit to be turned on or off based on the input signal to control the output state of the memory cell group. For example, for a non-"0" sub-signal in the input signal, the switching unit can be in the on state; for a sub-signal "0" in the input signal, the switching unit can be in the off state.

[0067] For example, Figure 6 shows a schematic diagram of the connection relationship between several switching units and memory units according to exemplary embodiments of this application. Figure 6 only illustrates a portion of the memory units in the memory circuit; for example, memory unit S. 11 Storage unit S 12 Storage unit S 21 and storage unit S 22 The storage circuit may also include more storage cells, which may optionally be arranged in a one-dimensional or two-dimensional array.

[0068] As shown in Figure 6(a), a switch unit is set for each memory cell, and this switch unit is set at the input terminal IN of the corresponding memory cell. For example, switch unit 1 corresponds to memory cell S. 11 Switching unit 1 is located in storage unit S 11 The input terminal; switch unit 2 corresponds to storage unit S.12 Switching unit 2 is located in storage unit S 12 The input terminal; switch unit 3 corresponds to storage unit S. 21 Switching unit 3 is located in storage unit S 21 The input terminal; switch unit 4 corresponds to the storage unit S. 22 Switching unit 4 is located in storage unit S 22 The input terminal. The control circuit controls the switching unit in the switching circuit to be turned on or off based on the input signal, so as to control the input signal of the memory cell group in the memory circuit. For example, the input signal includes "10", the control circuit controls the switching unit to be on based on "1", and controls the switching unit to be off based on "0". This connection method can support more flexible control of the input state of the memory cell.

[0069] As shown in Figure 6(b), memory cells within different memory cell groups can reuse a single switch unit, and memory cells within a memory cell group can reuse the same output terminal. For example, memory cell S 11 and storage unit S 12 Common output terminal OUT1, storage unit S 12 and storage unit S 22 The common output terminal is OUT2. The switching unit is located at the input terminal of the corresponding memory cell; for example, switching unit 1 corresponds to memory cell S. 11 and S 12 Switching unit 1 is located in storage unit S 11 and S 12 The input terminal, for example, is set in the storage unit S. 11 and S 12 Shared input lines; switch unit 2 corresponds to storage unit S 21 and S 22 Switching unit 2 is located in storage unit S 21 and S 22 The input terminal, for example, is set in the storage unit S. 11 and S 12 Shared input lines. The control circuit controls the memory unit S. 11 and S 12 When the first input signal of the memory cell group is received, the switching unit in the switching circuit can be controlled to turn on or off based on the first input signal. Similarly, the control circuit controls the memory cell S 21 and S 22When the second input signal of the memory cell group is received, the switching units in the switching circuit can be controlled to turn on or off based on this second input signal. The first and second input signals can be the same or different. When the first and second input signals are the same, the input signals of memory cell groups with the same input signal can be controlled simultaneously to further improve computing efficiency. The control method is similar to the description above and will not be repeated. This connection method can reduce the number of switching units, reduce the hardware overhead of the in-memory computing system, reduce costs, and save chip area.

[0070] As shown in Figure 6(c), a switch unit is set for each memory cell, and the switch unit is set at the output terminal of the corresponding memory cell. For example, switch unit 1 corresponds to memory cell S. 11 Switching unit 1 is located in storage unit S 11 The output terminal; switch unit 2 corresponds to storage unit S. 12 Switching unit 2 is located in storage unit S 12 The output terminal; switch unit 3 corresponds to storage unit S. 21 Switching unit 3 is located in storage unit S 21 The output terminal; switch unit 4 corresponds to storage unit S. 22 Switching unit 4 is located in storage unit S 22 The output terminal. The control circuit controls the switching circuit's memory cell to be turned on or off based on the input signal. Thus, controlling the output of the memory cell is equivalent to controlling the input of sub-signals "0" and non-"0". For example, if the input signal includes "10", the control circuit controls the switching cell to be on based on "1" and to be off based on "0". This connection method can support more flexible control of the memory cell's input state.

[0071] In some embodiments, the switching unit may include a semiconductor switching element, such as a transistor, and this disclosure does not limit the type of transistor.

[0072] This disclosure does not limit the connection or arrangement of storage cells within a storage cell group. For example, Figure 7 shows schematic diagrams of the connection relationships between several switching units and storage cells according to exemplary embodiments of this application. For example, as shown in Figures 7(a) and (b), storage cells can be arranged in one-dimensional rows and one-dimensional columns; or, as shown in Figure 7(c), storage cells can be arranged in two dimensions. Furthermore, as shown in Figure 7(a), storage cells can be connected in parallel; or, as shown in Figure 7(b), storage cells within a storage cell group can be connected in series; or, as shown in Figure 7(c), a combination of the above two connection methods can be used. In Figure 7, Si represents any sub-signal in the input signal.

[0073] The aforementioned pre-established calculation conditions operating mode of the storage circuit can be referred to as the first operating mode. The second operating mode involves the storage circuit not establishing calculation conditions in advance, but instead sensing the calculation result after receiving the input signal and waiting for a stable output signal. In some embodiments, the control circuit can also control the operating mode of the storage circuit, including either the first or second operating mode. In the first operating mode, the control circuit controls the storage circuit to be in a first operating state during a first time period, and controls the sensing circuit to be disabled; and controls the storage circuit to be in a second operating state during a second time period, and controls the sensing circuit to be enabled. This allows the storage circuit to flexibly operate in different modes according to the needs of the application scenario. In other embodiments, the storage circuit can default to operating in the first operating mode.

[0074] Figure 8 illustrates schematic diagrams of different operating modes of the storage circuit according to an exemplary embodiment of this application. As shown in Figure 8, in the first operating mode, the storage circuit establishes the calculation conditions in advance in the first operating state; optionally, it can simultaneously prepare the input, that is, use the establishment time of the calculation conditions to synchronously complete the preparation of the input signal, for example, the input circuit performs or completes the conversion of input data into an input signal. Then, the calculation is triggered, for example, by controlling the switching unit to turn on or off; and the sensing circuit is enabled to sense the calculation result. In the second operating mode, the storage cell group of the storage circuit receives the input signal, and when a stable output signal is output, the sensing circuit senses the calculation result. The first operating mode has higher calculation efficiency, and the second operating mode has relatively lower power consumption. The control circuit can flexibly control the operating mode of the storage circuit based on different scenario requirements. Alternatively, based on the application of the in-memory computing system, the in-memory computing system can be defaulted to operating in either the first or second operating mode.

[0075] This disclosure does not limit the control method of the control circuit for the above operating modes. For example, in some possible implementations, the control circuit can control the operating mode of the storage circuit based on the operating time of the sensing circuit or the pattern of the input signal. For example, if the operating time of the sensing circuit is short, for instance, less than or equal to a time threshold, the storage circuit and the sensing circuit can be controlled to operate in a first operating mode. This time threshold can be determined based on the establishment time of the stable state of the storage cell group. Furthermore, if the proportion of non-"0" signals in the input signal is high, or the proportion of "0" signals is low, the storage circuit and the sensing circuit can be controlled to operate in a first operating mode.

[0076] This application also provides a control method, which enables the control circuit to control the working state of the storage circuit and the sensing circuit at different time periods.

[0077] Figure 9 shows a flowchart of a control method according to an exemplary embodiment of this application. As shown in Figure 9, the method may include:

[0078] S901, during the first time period, the storage cell group of the control storage circuit is in the first working state, and the control sensing circuit is in the disabled state.

[0079] S902, during the second time period, the storage cell group of the control storage circuit is in the second working state, and the control sensing circuit is in the enabled state.

[0080] In the first operating state, the storage cell group establishes a stable state; and in the second operating state, the storage cell group converts the input signal into an output signal based on the weight data.

[0081] Based on the above control method, the control circuit can pre-establish a stable state for the storage cell group in the storage circuit, thus setting the conditions for the calculation of the storage cell group in advance. During the condition establishment process, the sensing circuit is enabled to prevent the sensing and output of non-calculation results. Then, the storage cell group is triggered to execute the calculation, and the sensing of the calculation result is triggered. Because the storage cell group has established a stable state in advance, it can quickly respond to input signals and perform fast and stable output during calculation, which greatly improves the calculation efficiency and thus improves the computing performance of the in-memory computing architecture.

[0082] In the above embodiments of this application, the method shown in FIG9 may also include other contents executed by the control circuit, which can be referred to in the above description and will not be repeated here.

[0083] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0084] This application also provides a control device that may be located within or include the control circuits 330 / 530 described above, and may be located within the control circuits 120 / 220 shown in FIG. 1 or FIG. 2, or independent of the control circuits 120 / 220. This control device can be used to execute any of the above control methods to control the operating state of the storage circuit and the sensing circuit.

[0085] The control device may include a unit or means for performing any of the above control methods.

[0086] This application also provides a control device, as shown in FIG10. FIG10 shows a schematic block diagram of a control device according to an exemplary embodiment of this application. As shown in FIG10, the control device includes: at least one processor 1010 and an interface circuit 1020, the interface circuit 1020 being used for signal connection with a storage circuit and a sensing circuit, and the at least one processor 1010 being used for executing any of the control methods provided in the above embodiments.

[0087] This application also provides an electronic device, as shown in FIG11. FIG11 illustrates a schematic diagram of an electronic device according to an exemplary embodiment of this application. As shown in FIG11, the electronic device may include any of the above-described in-memory computing systems 1110 for processing data of the electronic device. The electronic device may also include an input / output device 1120 for receiving user input or outputting processing results. This application does not limit the input type and output type. For example, input may include voice input, text input, image input, or video input, etc. The output may include text output, voice output, image output, or video output, etc. The electronic device may also include a processor 1130, which may process data provided to the in-memory computing system 1110 or process output data of the in-memory computing system 1110. The output of the input / output device 1120 may be based on the output of the processor 1130 or the output of the in-memory computing system 1110.

[0088] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0089] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. An in-memory computing system, characterized in that, include: A storage circuit includes a storage unit group, the storage unit group including multiple storage units, the multiple storage units being used to store weight data, the storage unit group being used to receive an input signal and convert the input signal into an output signal based on the weight data; A sensing circuit, connected to the storage circuit, is used to sense the output signal of the storage circuit; A control circuit is configured to control the storage unit group to be in a first working state and control the sensing circuit to be in a disabled state during a first time period, and to control the storage unit group to be in a second working state and control the sensing circuit to be in an enabled state during a second time period. In the first operating state, the storage unit group establishes a stable state; in the second operating state, the storage unit group converts the input signal into the output signal based on the weight data.

2. The in-memory computing system according to claim 1, characterized in that, The operating time of the sensing circuit is less than or equal to the establishment time of the stable state of the storage unit group.

3. The in-memory computing system according to claim 1 or 2, characterized in that, The control circuit is also used to control the storage unit group to alternately operate in the first working state and the second working state, and to control the sensing circuit to alternately operate in the disabled state and the enabled state.

4. The storage system according to any one of claims 1 to 3, characterized in that, The in-memory computing system also includes: A switching circuit, comprising multiple switching units, each corresponding to a storage unit, wherein the multiple switching units are in a conducting state during the first time period; wherein... The switching unit is located at the input terminal of the corresponding memory cell. The control circuit controls the switching unit to be turned on or off based on the input signal, thereby controlling the input state of the memory cell group; or, The switching unit is located at the output terminal of the corresponding storage unit. The control circuit controls the switching unit to be turned on or off based on the input signal, so as to control the output state of the storage unit group.

5. The storage system according to any one of claims 1 to 4, characterized in that, The control circuit is used to control the operating mode of the storage circuit, and the operating mode includes a first operating mode or a second operating mode. In the first working mode, the control circuit is used to control the storage unit group to be in the first working state and control the sensing circuit to be in the disabled state during the first time period, and to control the storage unit group to be in the second working state and control the sensing circuit to be in the enabled state during the second time period. In the second operating mode, the control circuit is used to control the storage unit group to be in the second operating state.

6. The storage system according to any one of claims 1 to 5, characterized in that, The control circuit controls the operating mode of the storage circuit based on the operating time of the sensing circuit or the pattern of the input signal.

7. A control method, characterized in that, For controlling storage circuits and sensing circuits, the storage circuit includes a storage unit group, the storage unit group includes multiple storage units, the multiple storage units are used to store weight data, the storage unit group is used to receive input signals, and convert the input signals into output signals based on the weight data; The sensing circuit is used to sense the output signal of the storage circuit; The method includes: In the first time period, the storage unit group is controlled to be in a first working state, and the sensing circuit is controlled to be in a disabled state. During the second time period, the storage unit group is controlled to be in a second working state, and the sensing circuit is controlled to be in an enabled state. In the first operating state, the storage unit group establishes a stable state; and in the second operating state, the storage unit group converts the input signal into the output signal based on the weight data.

8. The control method according to claim 7, characterized in that, The operating time of the sensing circuit is less than or equal to the establishment time of the stable state of the storage unit group.

9. The control method according to claim 7 or 8, characterized in that, Also includes: The storage unit group is controlled to alternately operate in the first working state and the second working state; The sensing circuit is controlled to operate alternately in the de-enabled state and the enabled state.

10. The control method according to any one of claims 7 to 9, characterized in that, Also includes: The operating mode of the storage circuit is controlled, and the operating mode includes a first operating mode or a second operating mode. In the first operating mode, the storage unit group is in a first operating state in a first time period and the sensing circuit is in a disabled state. In the second time period, the storage unit group is in a second operating state and the sensing circuit is in a disabled state. In the second working mode, the storage unit group is in the second working state.

11. The control method according to any one of claims 7 to 10, characterized in that, The operating modes for controlling the storage circuit include: The operating mode of the storage circuit is controlled based on the operating time of the sensing circuit or the pattern of the input signal.

12. A control device, characterized in that, It includes at least one processor and an interface circuit, the interface circuit being used for signal connection with a storage circuit and a sensing circuit, the at least one processor being used to execute the control method as described in any one of claims 7 to 11.

13. An electronic device, characterized in that, Includes the storage system as described in any one of claims 1 to 6.

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