Reducing offset in a sense amplifier

Abstract

In some examples, a method for reducing offset in a sense amplifier of multiple sense amplifiers comprises identifying, from the multiple sense amplifiers, a sense amplifier associated with an offset characteristic, selecting, from multiple bit lines, at least one bit line pair associated with the identified sense amplifier for de-offsetting, and applying a pulsed signal to the word line to initiate a discharge that adjusts a voltage on the selected bit line, whereby to reduce the offset in the sense amplifier.

Description

[0001] REDUCING OFFSET IN A SENSE AMPLIFIER

[0002] TECHNICAL FIELD

[0003] The present disclosure relates, in general, to improving memory read performance and reliability. Aspects of the disclosure relate to mitigating sense amplifier offsets during read operations by selectively adjusting bit line voltages.

[0004] BACKGROUND

[0005] Memory devices, such as static random-access memory, are critical components in modern computing systems, providing high-speed access to data. In such devices, sense amplifiers play a crucial role in detecting and amplifying the small voltage difference generated by the bit lines during read operations. Specifically, the sense amplifier determines whether the bit line or its complementary bit line has a higher voltage, thereby identifying the data stored in the memory cell.

[0006] One challenge associated with the use of sense amplifiers is the presence of statistical offset voltages. These offsets arise due to unavoidable variations during the physical manufacturing process, such as mismatches in transistor dimensions, doping levels, or parasitic capacitances. This offset can lead to errors when the voltage difference between the bit lines is smaller than the offset voltage of the SA, particularly in high-performance memory systems, where read speed and energy efficiency are critical.

[0007] To ensure accurate data reads, the word line driving the memory cells is typically activated for an extended period, allowing sufficient bit line separation to develop. However, this approach introduces significant delays in the memory read process. Longer read times not only reduce the overall performance of the memory but also increase power consumption, as the memory system must remain active for a prolonged duration.

[0008] The increasing demand for faster and more energy-efficient memory systems makes it essential to address the issue of sense amplifier offset effectively. Existing solutions rely on tolerating the offset by waiting for larger bit line separations to develop, which is suboptimal in highspeed, energy-constrained environments.SUMMARY

[0009] An objective of the present disclosure is to mitigate sense amplifier offsets during read operations.

[0010] The foregoing and other objectives are achieved by the features of the independent claims.

[0011] Further implementation forms are apparent from the dependent claims, the description and the Figures.

[0012] A first aspect of the present disclosure provides a method for reducing offset in a sense amplifier of multiple sense amplifiers, the method comprising identifying, from the multiple sense amplifiers, a sense amplifier associated with an offset characteristic, selecting, from multiple bit lines, at least one bit line pair associated with the identified sense amplifier for de-offsetting, and applying a pulsed signal to the word line to initiate a discharge that adjusts a voltage on the selected bit line, whereby to reduce the offset in the sense amplifier.

[0013] Advantageously, by selectively adjusting bit line voltages, the offset associated with the sense amplifier(s) may be reduced, therefore improving memory read performance and reliability.

[0014] The step of identifying the sense amplifier associated with an offset characteristic may further comprise performing a built-in self-test (BIST) on each sense amplifier to determine the offset characteristic.

[0015] The step of applying the pulsed signal to the word line may comprise configuring a duration of the pulse based on a level of offset detected in the identified sense amplifier.

[0016] The discharge initiated by the pulsed signal may apply a first voltage to the selected bit line to increase the bit line voltage by a pre-defined amount sufficient to reduce the offset in the associated sense amplifier.

[0017] The discharge initiated by the pulsed signal may apply a second voltage to the selected bit line to decrease the bit line voltage by a pre-defined amount sufficient to reduce the offset in the associated sense amplifier.The method may further comprise reconfiguring a pulse duration of the pulsed signal in response to a change in the offset characteristic detected in the identified sense amplifier.

[0018] The pulsed signal applied to the word line may selectively activate multiple bit cells associated with the selected bit line, each bit cell contributing a portion of the discharge, such that a combined discharge adjusts the voltage on the selected bit line by an amount configured to reduce the offset in the identified sense amplifier.

[0019] A second aspect of the present disclosure provides an apparatus for reducing offset in a sense amplifier of multiple sense amplifiers, the apparatus comprising the multiple sense amplifiers, a discharge circuit comprising multiple bit cells, wherein each bit cell of the multiple bit cells is connected to a corresponding sense amplifier of the multiple sense amplifiers via a bit line of multiple bit lines, a decoding circuit arranged to select a specific bit line of the multiple bit lines based on a control signal, wherein the discharge circuit is arranged to selectively discharge the selected bit line by a pre-defined voltage amount, wherein the decoding circuit is further arranged to apply a pulsed signal to the word line to drive the discharge circuit to selectively discharge the selected bit line, whereby to reduce the offset associated with the sense amplifier which the selected bit line is connected to.

[0020] The decoding circuit may comprise an AND gate and an OR gate, configured to receive an internal clock signal and a control signal for generating the pulsed signal.

[0021] The discharge circuit may comprise a dedicated offsetting circuit arranged to control a strength of the discharge applied to the selected bit line.

[0022] The decoding circuit may be arranged to store an identification of sense amplifiers requiring de-offsetting, based on data generated from a built-in self-test (BIST) operation.

[0023] The apparatus may further comprise a control register arranged to store pulse duration parameters for the pulsed signal, the parameters based on the offset characteristic of each sense amplifier of the multiple sense amplifiers.

[0024] The decoding circuit may be configured to vary a pulse duration of the pulsed signal based on a pre-determined configuration stored in the control register.Each bit cell pair in the discharge circuit may be configured to store logical states such that one bit cell of the pair stores a logical state opposite to the logical state of the selected bit line.

[0025] The decoding circuit may be further configured to activate multiple bit cells along the selected bit line, whereby to apply a combined discharge to reduce the offset associated with the sense amplifier which the selected bit line is connected to.

[0026] These and other aspects of the invention will be apparent from the embodiment(s) described below.

[0027] BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order that the present invention may be more readily understood, embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

[0029] Figure l is a flow chart of a method for reducing offset in a sense amplifier of multiple sense amplifiers according to an example;

[0030] Figure 2 is a schematic representation of an apparatus for reducing offset in a sense amplifier of multiple sense amplifiers according to an example; and

[0031] Figure 3 is a schematic representation of an apparatus for reducing offset in a sense amplifier of multiple sense amplifiers according to another example.

[0032] DETAILED DESCRIPTION

[0033] Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments can be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

[0034] Accordingly, while embodiments can be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistentlydenoted by the same reference numerals throughout the drawings and detailed description where appropriate.

[0035] The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and “the” are singular in that they have a single referent, however the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements referred to in the singular can number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

[0037] Examples in the present disclosure can be provided as methods, systems or machine-readable instructions, such as any combination of software, hardware, firmware or the like. Such machine-readable instructions may be included on a computer readable storage medium (including but not limited to disc storage, CD-ROM, optical storage, etc.) having computer readable program codes therein or thereon.

[0038] The present disclosure is described with reference to flow charts and / or block diagrams of the method, devices and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. In some examples, some blocks of the flow diagrams may not be necessary and / or additional blocks may be added. It shall be understood that each flow and / or block in the flow charts and / or block diagrams, as well as combinations of the flows and / or diagrams in the flow charts and / or block diagrams can be realized by machine readable instructions.Figure l is a flow chart of a method for reducing offset in a sense amplifier of multiple sense amplifiers according to an example. The method comprises, in block 101, identifying, from the multiple sense amplifiers, a sense amplifier associated with an offset characteristic. As used herein, the term “sense amplifier” refers to an electronic circuit used in memory systems to detect and amplify small voltage differences between a pair of bit lines, enabling accurate determination of the data stored in a memory cell. The offset in the sense amplifier is typically caused by manufacturing process variations, such as mismatches in transistor size, threshold voltage, or parasitic capacitances within the sense amplifier circuit. The significance of this offset lies in its potential to impair accurate data readout, especially when the bit line separation voltage is insufficient to overcome the offset, resulting in slower or erroneous reads.

[0039] Identifying the sense amplifier associated with the offset characteristic may comprise, for example, performing a built-in self-test (BIST) on each sense amplifier of the multiple sense amplifiers, whereby to determine the offset characteristic, allowing for identification of at least one sense amplifier associated with the offset characteristic. The BIST may comprise applying controlled voltage differentials (for example, test patterns) to the memory cells connected to the bit lines associated with each sense amplifier and observing the output to detect discrepancies that indicate an offset. These discrepancies may be used to calculate the magnitude and direction of the offset characteristic.

[0040] In block 102, the method comprises selecting, from multiple bit lines, at least one bit line pair associated with the identified sense amplifier (i.e., the sense amplifier associated with the offset characteristic) for de-offsetting. Bit lines may comprise conductive paths within a memory array that connect memory cells to sense amplifiers, allowing for the transfer of data during read and write operations.

[0041] Each sense amplifier may be connected to a complementary pair of bit lines (BL and BL#) which carry the differential signal used by the sense amplifier to detect data stored in the memory cells. The bit lines may be connected to the sense amplifiers directly or through a mux, with multiple bit lines sharing access to a single sense amplifier.

[0042] In block 103, the method comprises applying a pulsed signal to a word line to initiate a discharge that adjusts a voltage on the selected bit line, whereby to reduce the offset in the sense amplifier, thus realising the de-offsetting. A word line may comprise a control signal line thatselectively activates a row of memory cells in the memory array. Each word line may be connected to the gates of the access transistors in the memory cells, enabling or disabling the connection between the memory cell and its associated bit lines.

[0043] By applying a pulsed signal to the word line, specific memory cells along the activated row may be selected to contribute to the discharge of their connected bit lines, adjusting the voltage differential. In particular, the pulsed signal applied to the word line may selectively activate multiple bit cells associated with the selected bit line. Each bit cell contains a stored data that contributes incrementally to the overall discharge on the bit line, with the cumulative effect adjusting the voltage difference between the bit line pair BL and BL#. Each bit cell of the multiple bit cells may contribute a portion of the discharge, such that the combined discharge adjusts the voltage on the selected bit lines by an amount configured to reduce the offset in the identified sense amplifier.

[0044] A duration of the pulsed signal applied to the word line may be configured based on a level of offset detected in the identified sense amplifier. For example, for larger offset values, a longer pulse duration may be required to ensure sufficient discharge on the bit lines to counteract the offset. Conversely, for smaller offset values, shorter pulse durations may be sufficient.

[0045] The discharge initiated by the pulsed signal may apply a second voltage to the selected bit line to decrease the bit line voltage by a pre-defined amount sufficient to reduce the offset in the associated sense amplifier. The second voltage may be calibrated based on prior testing or simulation results.

[0046] The method may further comprise monitoring the offset characteristic detected in the identified sense amplifier. This monitoring step may involve periodic re-evaluation of the sense amplifier's output using the BIST or a similar diagnostic mechanism to ensure the offset has been sufficiently reduced. As a result of the monitoring, a change in the offset characteristic may be detected, for example, as a result of the pulsed signal being applied to the word line. In such case, if the offset characteristic is still present in the sense amplifier, another pulsed signal may be applied to the word line. The decision to reapply a pulse may be based on the residual offset magnitude measured during monitoring. The further pulsed signal may be associated with a different pulse duration, compared to the initial pulsed signal. This enables the fine-tuning the correction process to avoid over-correction or excessive energy usage.Figure 2 is a schematic representation of an apparatus for reducing offset in a sense amplifier of multiple sense amplifiers according to an example. The apparatus 200 comprises multiple sense amplifiers 210. In the drawing, each sense amplifier of the multiple sense amplifiers 210 is represented as “SA0, SAI, SA2, ..., SA-n”. Each of the multiple sense amplifiers 210 may be arranged to detect a signal from corresponding bit line of multiple bit lines 222. The apparatus 200 may comprise an internal clock.

[0047] The apparatus 200 comprises a discharge circuit 220 comprising multiple bit cells 221. The multiple bit cells 221 are denoted in the figure as “bitcellsO, bitcells 1 , bitcells2, ..., bitcells-n”. Each bit cell of the multiple bit cells 221 is connected to a corresponding sense amplifier of the multiple sense amplifiers 210 using respective bit lines of multiple bit lines 222. For example, a bit cell “bitcellsO” may be connected to a sense amplifier “SA0” using a complementary pair of bit lines. As mentioned earlier, each sense amplifier of the multiple sense amplifiers 210 may be connected to a complementary pair of bit lines of multiple bit lines 222. The multiple bit cells 221 may also be arranged in pairs, wherein each pair of the multiple bit cells 221 is arranged to store logical states such that one bit cell of the pair stores a logical state opposite to the logical state of the selected bit line.

[0048] The discharge circuit 223, 224 may be responsible for introducing controlled assistance to specific sense amplifiers of the multiple sense amplifiers 210 based on their offset characteristics. In the example shown in Figure 2, the sense amplifiers SA0, SAI and SA3 do not require de-offsetting, as they are already balanced; however, the sense amplifier SA2 has a weak ‘1’ signal and therefore requires assistance in the form of a help with ‘1’. Similarly, the sense amplifier SA-n has a weak ‘0’ signal and therefore requires assistance in the form of a help with ‘O’.

[0049] The apparatus 200 also comprises a decoding circuit 230 arranged to select a specific word line of the multiple lines at 220 based on a address signal. The decoding circuit 230 may comprise a pulsed decoder 231 and a standard decoder 232. The decoding circuit 230 may comprise multiple logic gates, for example, an AND gate and an OR gate. The multiple logic gates may be arranged to receive an internal clock signal from the internal clock, as well as a control signal for generating the pulsed signal.The pulsed decoder 231 may be arranged to generate pulsed word lines, which activate specific bit cells 221 for a configurable duration. The standard decoder 232 may generate standard word lines. Through this, offset correction may be realised. The pulsed word lines may be used to provide precise timing control for the offset correction, whereas the standard word lines may be used to handle conventional addressing for writing.

[0050] In particular, the discharge circuit 222, 223 is arranged to selectively discharge the selected bit line of multiple bit lines 222 by a pre-defined voltage amount. The voltage amount may be selected such that the discharge adjusts the voltage on the selected bit line by an amount sufficient to reduce the offset in a specific sense amplifier 210. The decoding circuit 231 is further arranged to apply the pulsed signal to the word line (i.e., pulsed word line) to drive the discharge circuit 222, 223 to selectively discharge the selected bit line of multiple bit lines 222, thereby reducing the offset associated with the sense amplifier 210 which the selected bit line is connected to.

[0051] The decoding circuit 230 may store an identification indicative of the identified sense amplifiers requiring de-offsetting, based on data generated from a built-in self-test (BIST) operation. Furthermore, the apparatus 200 may further comprise a control register arranged to store pulse duration parameters for the pulsed signal, wherein the pulse duration parameters are generated based on the offset characteristic of each sense amplifier of the multiple sense amplifiers 210.

[0052] Figure 3 is a schematic representation of an apparatus for reducing offset in a sense amplifier of multiple sense amplifiers according to another example. That is, the apparatus of Figure 3 shows an alternative implementation of the apparatus of Figure 3. The same reference numerals in Figures 2 and 3 denote the same elements, functioning likewise. Compared to the apparatus 200 of Figure 2, the apparatus 300 of Figure 3 may comprise a dedicated offsetting circuit 240 (other than standard bitcells) arranged to control a strength of the discharge selected to the bit line. Advantageously, both implementations enable de-offsetting of sense amplifiers associated with an offset, thereby reducing a reading time.

[0053] The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the instant disclosure.The embodiments disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the instant disclosure.

Claims

1. CLAIMS1. A method for reducing offset in a sense amplifier of multiple sense amplifiers, the method comprising:identifying, from the multiple sense amplifiers, a sense amplifier associated with an offset characteristic (101);selecting, from multiple bit lines, at least one bit line pair associated with the identified sense amplifier for de-offsetting (102); andapplying a pulsed signal to the word line to initiate a discharge that adjusts a voltage on the selected bit line, whereby to reduce the offset in the sense amplifier (103).

2. The method of claim 1, wherein the step of identifying the sense amplifier associated with an offset characteristic (101) further comprises performing a built-in self-test, BIST, on each sense amplifier to determine the offset characteristic.

3. The method of claim 1 or 2, wherein the step of applying the pulsed signal to the word line (103) comprises configuring a duration of the pulse based on a level of offset detected in the identified sense amplifier.

4. The method of any one of claims 1 to 3, wherein the discharge initiated by the pulsed signal applies a first voltage to the selected bit line to increase the bit line voltage by a predefined amount sufficient to reduce the offset in the associated sense amplifier.

5. The method of any one of claims 1 to 3, wherein the discharge initiated by the pulsed signal applies a second voltage to the selected bit line to decrease the bit line voltage by a predefined amount sufficient to reduce the offset in the associated sense amplifier.

6. The method of any one of claims 1 to 5, further comprising reconfiguring a pulse duration of the pulsed signal in response to a change in the offset characteristic detected in the identified sense amplifier.

7. The method of any one of claims 1 to 6, wherein the pulsed signal applied to the word line selectively activates multiple bit cells associated with the selected bit line, each bit cell contributing a portion of the discharge, such that a combined discharge adjusts the voltage onthe selected bit line by an amount configured to reduce the offset in the identified sense amplifier.

8. An apparatus (200) for reducing offset in a sense amplifier of multiple sense amplifiers (210), the apparatus (200) comprising:the multiple sense amplifiers (210);a discharge circuit (220) comprising multiple bit cells (221), wherein each bit cell of the multiple bit cells (221) is connected to a corresponding sense amplifier of the multiple sense amplifiers (210) via a bit line of multiple bit lines (222);a decoding circuit (230) arranged to select a specific bit line of the multiple bit lines (222) based on a control signal,wherein the discharge circuit (220) is arranged to selectively discharge the selected bit line by a pre-defined voltage amount,wherein the decoding circuit (230) is further arranged to apply a pulsed signal to the word line to drive the discharge circuit (220) to selectively discharge the selected bit line, whereby to reduce the offset associated with the sense amplifier which the selected bit line is connected to.

9. The apparatus (200) of claim 8, wherein the decoding circuit (230) comprises an AND gate and an OR gate, configured to receive an internal clock signal and a control signal for generating the pulsed signal.

10. The apparatus (200) of claim 8 or 9, wherein the discharge circuit (220) further comprises a dedicated offsetting circuit (240) arranged to control a strength of the discharge applied to the selected bit line.

11. The apparatus (200) of claim 8, 9 or 10, wherein the decoding circuit (230) is arranged to store an identification of sense amplifiers (210) requiring de-offsetting, based on data generated from a built-in self-test, BIST, operation.

12. The apparatus (200) of any one of claims 8 to 11, further comprising a control register arranged to store pulse duration parameters for the pulsed signal, the parameters based on the offset characteristic of each sense amplifier of the multiple sense amplifiers (210).

13. The apparatus (200) of claim 12, the decoding circuit (230) is configured to vary a pulse duration of the pulsed signal based on a pre-determined configuration stored in the control register.

14. The apparatus (200) of any one of claims 8 to 13, wherein each bit cell pair in the discharge circuit (230) is configured to store logical states such that one bit cell of the pair stores a logical state opposite to the logical state of the selected bit line.

15. The apparatus (200) of any one of claims 8 to 14, wherein the decoding circuit (230) is further configured to activate multiple bit cells (221) along the selected bit line, whereby to apply a combined discharge to reduce the offset associated with the sense amplifier which the selected bit line is connected to.

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