Sic-based composite structure and method for manufacturing a semiconductor structure for microelectronic components using the composite structure

Abstract

The invention relates to a composite structure comprising a useful layer made of monocrystalline silicon carbide arranged on an interlayer made of a metal or semiconductor material other than silicon carbide, the interlayer itself being arranged on a support substrate made of polycrystalline silicon carbide, the useful layer having a dopant concentration greater than or equal to 1.1018 / cm3, the composite structure being characterised in that: - the dopants of the useful layer are entirely or partially inactivated, such that the resistivity of the useful layer is greater than or equal to 1 ohm.cm, - the useful layer includes a free face having a surface roughness of less than or equal to 1 nm RMS, and - the interlayer is continuous in a plane substantially parallel to the free face of the useful layer. The invention also relates to a method for manufacturing a semiconductor structure for producing microelectronic components, using a composite structure as mentioned hereinbefore.

Description

SiC-based composite structure and process for manufacturing a semiconductor structure for microelectronic components from the composite structure FIELD OF INVENTION

[0001] The present invention relates to the field of semiconductor materials for microelectronic components. It relates in particular to a composite structure comprising a useful layer of single-crystal silicon carbide transferred onto a polycrystalline silicon carbide substrate, intended to undergo an epitaxial step to form an active layer on the useful layer. The invention also relates to a method for manufacturing a semiconductor structure, including the active layer and the composite structure, for the fabrication of microelectronic components.

[0002] TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] It is common to form a semiconductor structure by transferring a thin, high-quality semiconductor useful layer onto a lower-quality semiconductor support substrate. A well-known thin-film transfer solution is the Smart Cut process. TM This method is based on the implantation of light ions and assembly by direct bonding at a bonding interface. In addition to the economic advantages related to the rationalization of high-quality material for the useful layer, the semiconductor structure can also provide advantageous properties, for example, related to thermal and electrical conductivity or the mechanical compatibility of the supporting substrate.

[0004] In the field of power electronics, good electrical conduction between the active layer and the substrate is required for the fabrication of vertical components. For example, in the case of a structure comprising a monocrystalline silicon carbide (m-SiC) active layer and a polycrystalline silicon carbide (p-SiC) substrate, the bonding interface must have the lowest possible resistivity, preferably less than 1 mΩ·cm. 2 , or even less than 0.1 mohm.cm 2 .

[0005] As a reminder, to form vertical components, the first step is to grow an active layer by epitaxy on the useful layer. Classical steps such as structuring, doping, deposition, etc., can then be applied to this active layer to define the components.

[0006] Several approaches can be adopted to obtain a low-resistivity bonding interface. In particular, document WO2022129726 describes an interface zone between the m-SiC useful layer and the p-SiC support substrate. This interface zone comprises regions of direct contact between the useful layer and the support substrate, as well as aggregates of a material such as silicon, with a thickness of 250 nm or less. The useful layer and the support substrate have a resistivity of approximately 20 mΩ·cm, while the interface zone has a resistivity of 0.1 mΩ·cm or less. 2 .

[0007] When epitaxial growth is performed on such a composite structure, the applicant has observed that defects are likely to appear on the surface of the active layer and / or that the surface roughness of said active layer is sometimes degraded.

[0008] SUBJECT OF THE INVENTION

[0009] The present invention addresses this problem. It relates to a silicon carbide-based composite structure (m-SiC / p-SiC) capable of providing a high-quality active layer, i.e., one with an improved surface finish in terms of defects and roughness. The invention also relates to a method for manufacturing a semiconductor structure for the fabrication of microelectronic components, starting from such a composite structure.

[0010] BRIEF DESCRIPTION OF THE INVENTION

[0011] The invention relates to a composite structure comprising a useful layer of monocrystalline silicon carbide disposed on an interlayer of a metallic or semiconductor material other than silicon carbide, the interlayer itself being disposed on a support substrate of polycrystalline silicon carbide, the useful layer having a dopant concentration greater than or equal to 1.10 18 / cm 3 The composite structure is remarkable in that:

[0012] - the dopants of the useful layer are inactivated in whole or in part, so that the resistivity of the useful layer is greater than or equal to 1 ohm.cm,

[0013] - the useful layer has a free face with a surface roughness less than or equal to 1nm RMS,

[0014] - the intercalated layer is continuous in a plane substantially parallel to the free face of the useful layer.

[0015] According to other advantageous and non-limiting features of the invention, taken alone or in any technically feasible combination: the interlayer has a thickness between 2 nm and 40 nm; the material composing the interlayer is silicon, tungsten, or titanium; the substrate has a resistivity less than or equal to 10 mΩ·cm, or even less than or equal to 5 mΩ·cm; an interface zone of the composite structure, including the interlayer, an interface between the useful layer and the interlayer, and an interface between the interlayer and the substrate, has a resistivity greater than 1 mΩ·cm 2 , or even greater than 1 ohm.cm 2 .

[0016] The invention also relates to a method for manufacturing a semiconductor structure for the fabrication of microelectronic components, using a composite structure such as the one described above. The method comprises the following steps:

[0017] (a) the transfer of a useful layer of monocrystalline silicon carbide onto a support substrate of polycrystalline silicon carbide, via an interlayer of a metallic or semiconductor material other than silicon carbide, to form an intermediate structure comprising the useful layer disposed on the interlayer, itself disposed on the support substrate, the useful layer having a dopant concentration greater than or equal to 1.10 18 / cm 3, the dopants of the useful layer being inactivated in whole or in part, so that the resistivity of the useful layer is greater than or equal to 1 ohm.cm, the intercalated layer extending continuously in a plane substantially parallel to a free face of the useful layer;

[0018] b) smoothing the free face of the useful layer by mechanical or mechano-chemical polishing so as to obtain a surface roughness less than or equal to 1nm RMS, to form the composite structure;

[0019] c) Epitaxial growth of a single-crystal silicon carbide active layer on the useful layer of the composite structure, involving a temperature greater than or equal to 1500°C, to form a semiconducting structure. The process is remarkable in that, prior to step c), any heat treatment applied to the intermediate or composite structure is carried out at a temperature below a critical temperature from which the intercalated layer is likely to segment into nodules.

[0020] According to other advantageous and non-limiting features of the invention, taken alone or in any technically feasible combination: step a) comprises: - an implantation of light species in a donor substrate, to form a buried fragile plane which delimits, with a front face of the donor substrate, the useful layer to be transferred; - an assembly by molecular adhesion of the donor substrate on the support substrate, via the intercalated layer; - a separation at the level of the buried fragile plane, to form on the one hand the intermediate structure and on the other hand the rest of the donor substrate; step a) comprises, prior to the assembly, the deposition of a film of the metallic or semiconducting material of the intercalated layer on the front face of the donor substrate and / or on a face to be assembled of the support substrate, the thickness of said film being less than or equal to 40nm, 20nm, 10nm, or even 5nm;The interlayer has a thickness between 2nm and 40nm; the material composing the interlayer is silicon or tungsten or titanium; the substrate support has a resistivity less than or equal to 10 mohm.cm, or even less than or equal to 5 mohm.cm; the critical temperature is 1400°C or the critical temperature is 1350°C; the manufacturing process further includes the formation of microelectronic components in and / or on the active layer. BRIEF DESCRIPTION OF THE FIGURES

[0021] Other features and advantages of the invention will become apparent from the detailed description of the invention which follows with reference to the accompanying figures in which:

[0022] This presents a composite structure according to the invention;

[0023]

[0024]

[0025] Presents an image obtained by atomic force microscopy (AFM) of the surface of a raw active layer on a prior art (m-SiC / p-SiC) composite structure as illustrated in the figure; presents an AFM image of the surface of the useful layer of a prior art composite structure illustrated in the figure, after hydrogen etching carried out in an epitaxial reactor (preliminary etching to epitaxial growth);

[0026]

[0027]

[0028]

[0029]

[0030]

[0031] Figures 3a to 3f show sub-steps of a step a) of a manufacturing process according to the invention;

[0032] This presents step b) of a manufacturing process according to the present invention;

[0033] This presents step c) of a manufacturing process according to the present invention;

[0034] Presents surface finish (AFM image) and roughness (AFM measurement roughness values) results of the front face of the active layer for two semiconductor structures (A, B) fabricated according to a process according to the invention, and for a prior art semiconductor structure (C); the AFM measurements are performed on 30x30μm scans 2 ;

[0035] Presents a semiconductor structure produced by a manufacturing process according to the present invention, comprising microelectronic components fabricated in and on the active layer.

[0036] The same references in the figures can be used for elements of the same type. The figures are schematic representations which, for the sake of clarity, are not to scale. In particular, the layer thicknesses along the z-axis are not to scale with respect to the lateral dimensions along the x and y axes; and the relative thicknesses of the layers are not to scale in the figures. DETAILED DESCRIPTION OF THE INVENTION

[0037] The invention relates to a composite semiconductor structure 100 comprising a useful layer 10 of monocrystalline silicon carbide (m-SiC) disposed on an interlayer layer 20 of a metallic or semiconducting material other than silicon carbide, the interlayer layer 20 itself being disposed on a support substrate 30 of polycrystalline silicon carbide (p-SiC) ().

[0038] Advantageously, and as is usually the case in microelectronics, the composite structure 100 is in the form of a circular wafer with a diameter between 100 mm and 200 mm, or even up to 300 mm, and a total thickness typically between 250 micrometers and 1 mm. It follows that, in this case, the substrate 30 and the active layer 10 also have such a circular shape. The front (circular) faces 100a and the rear (circular) faces 100b of the wafer extend parallel to the principal plane (x,y) referenced in the figures.

[0039] The useful layer 10 can be polytype 4H or 6H m-SiC. To meet the requirements of power electronics applications, the useful layer 10 has a dopant concentration greater than or equal to 1 x 10 18 / cm 3Indeed, when the vertical components are developed on the composite structure 100, it will be required that the useful layer 10 have a resistivity less than or equal to 0.03 ohm.cm.

[0040] An important feature of the composite structure 100 according to the invention is that the dopants of the useful layer 10 are inactivated in whole or in part, such that the resistivity of the useful layer 10 is greater than or equal to 1 ohm.cm. This feature is due to the fact that: the useful layer 10 was transferred by a technique involving the implantation of light species, and consequently its single-crystal structure is significantly damaged and all or part of the dopants are inactivated; the composite structure 100, throughout its manufacturing process, never undergoes heat treatment at a sufficient temperature (typically above 1500°C) to allow the useful layer 10 to heal and the dopants to be reactivated.

[0041] Preferably, the substrate support 30 has a resistivity less than or equal to 10 mΩ·cm, or even less than or equal to 5 mΩ·cm. These resistivity levels provide good vertical conduction performance for microelectronic components intended to be fabricated on the composite structure 100.

[0042] Furthermore, the useful layer 10 of the composite structure 100 according to the invention comprises a free face, the front face 100a of the composite structure 100, which has a surface roughness less than or equal to 1 nm RMS. The roughness is advantageously less than or equal to 0.5 nm RMS, 0.3 nm RMS, 0.2 nm RMS, or even 0.1 nm RMS.

[0043] Surface roughness is typically measured by atomic force microscopy (AFM) on 5x5μm scans 2 and up to 20x20μm 2 even 30x30μm 2 .

[0044] Finally, the intermediate layer 20 of the composite structure 100 is continuous in a plane substantially parallel to the free face 100a of the useful layer 10, that is, substantially parallel to the principal plane (x,y). By continuous, we mean a layer not segmented into nodules or agglomerates, which covers the entire interface zone between the useful layer 10 and the supporting substrate 30. Note that the intermediate layer 20 may nevertheless contain point defects such as holes, but remains continuous and intact around and outside of these defects.

[0045] Advantageously, the interlayer 20 has a thickness between 2nm and 40nm. Such a thickness allows segmentation in the form of nodules or agglomerates, if the composite structure 100 is subjected to heat treatment at a temperature above a critical temperature above which it will be energetically more favorable for the material of the interlayer 20 to form nodules rather than remain as a continuous film in the interface zone.

[0046] Preferably, the material composing the interlayer 20 is silicon, titanium, or tungsten. The critical temperature is typically above 1200°C. For example, it can be around 1350°C, or even around 1400°C in the case of a silicon interlayer 20.

[0047] The resistivity of the interface zone (including the interlayer 20 and the interfaces with the useful layer 10 and the supporting substrate 30) is high: typically greater than 1 mΩ·cm 2 , or even greater than 1 ohm.cm 2 , or even more.

[0048] The composite structure 100 according to the invention is intended for the development of microelectronic components 200 and, as mentioned in the introduction, will first undergo epitaxial growth on the useful layer 10, to form an active layer 50 adapted to the definition of said components 200. The active layer 50 can have a thickness ranging from a few micrometers to a few tens of micrometers, for example 5μm, 10μm, 15μm, 20μm, 30μm, or even 50μm.

[0049] This m-SiC epitaxy step is usually carried out at a temperature between 1500°C and 1800°C, typically around 1650°C–1700°C. The thermal budget associated with epitaxy thus allows, in parallel with the growth of the active layer 50, the healing of the useful layer 10 and the reactivation of the dopants. The resistivity of the useful layer 10 is then restored to the desired level, typically around 20 mΩ·cm, consistent with the dopant concentration of the useful layer 10.

[0050] The high thermal budget of epitaxy also induces the segmentation of the intercalated layer 20 into nodules or agglomerates, separated from each other by regions of direct contact between the useful layer 10 and the supporting substrate 30. This configuration confers a very low resistivity to the interface zone, typically less than or equal to 0.1 mΩ·cm 2 , or even less than 0.01 mohm.cm 2 .

[0051] The composite structure 100 according to the invention allows obtaining an active layer 50, after epitaxy, exhibiting a very good surface finish. Of course, this roughness can depend on the epitaxy conditions applied, but typically surface roughnesses of less than 1.0 nm RMS, less than or equal to 0.90 nm RMS, less than or equal to 0.80 nm RMS, less than or equal to 0.70 nm RMS, less than or equal to 0.60 nm RMS, less than or equal to 0.50 nm RMS, or even less than or equal to 0.40 nm RMS are obtained (AFM, scan from 5 μm x 5 μm to 30 μm x 30 μm).

[0052] In comparison, it has been observed that the surface roughness of the active layer, epitaxially grown on a prior art composite structure ( 100'), can be degraded by the presence of defects, called "divots" due to their micro-crater shape ( ). The associated surface roughness can vary depending on the size and depth of the divot defects; it is typically greater than or equal to 1 nm RMS and can reach a few nm RMS. Even when the roughness remains close to 1 nm, the presence of these divot defects is likely to affect, at the local microscopic scale, the quality of the components that will be formed in the active layer.

[0053] One explanation proposed by the applicant is the presence of stress fields in the active layer 10' of the composite structure 100', according to the prior art, directly above the agglomerates 21' of the interface zone 20' (). These stresses, which do not affect the quality of the active layer 10', cause abnormal behavior of the latter during the hydrogen etching step, a preliminary step to silicon carbide growth in the epitaxial reactor: local areas, disturbed by these stresses, undergo preferential attack, generating micro-craters () which degrade the surface finish. The subsequent epitaxial growth generally smooths this surface finish, but the divot defects, although reduced in amplitude, remain on the surface of the active epitaxial layer.These divot defects could be a source of failure of microelectronic components that will be defined on and in the active layer; in particular, they could degrade the gate oxide behavior of MOSFET-type transistors (risk of leakage and premature breakdown).

[0054] The composite structure 100 according to the invention is therefore manufactured so that there is no stress field in the useful layer 10 likely to modify the behavior of said useful layer 10 during the epitaxial growth of the active layer 50 and to induce a degradation of the surface condition of said epitaxial active layer.

[0055] The manufacturing process of a semiconductor structure for the development of microelectronic components, from the composite structure 100, according to the invention, will now be detailed.

[0056] It includes firstly the manufacture of the composite structure 100, by implementing steps a) and b).

[0057] Step a) corresponds to the transfer of a useful layer 10 of monocrystalline silicon carbide onto a support substrate 30 of polycrystalline silicon carbide, via an interlayer layer 20 of a metallic or semiconducting material other than silicon carbide, to form an intermediate structure 90 comprising the useful layer 10 disposed on the interlayer layer 20, itself disposed on the support substrate 30.

[0058] According to a preferred embodiment, the useful layer 10 is obtained by transferring a surface layer from a donor substrate 1 made of single-crystal silicon carbide, in particular a layer transfer based on the Smart Cut process TM , as described below.

[0059] Step a) may thus include the implantation of light species, for example hydrogen, helium, or a combination of these two species, in said donor substrate 1, to form a buried fragile plane 11 which delimits, with a front face 10a of the donor substrate 1, the useful layer 10(). The implanted dose is typically between 2 e 16 and 8 e 16 / cm 2 and the implantation energy is between 50 keV and 130 keV to delimit a useful layer 10 with a thickness between 300 nm and 900 nm.

[0060] According to one variant, step a) comprises the formation of the donor substrate 1 by epitaxy of a donor layer 1' onto an initial substrate, prior to the implantation of the light species. This variant allows for the formation of a donor layer 1' with the structural and electrical characteristics required for the intended application. In particular, excellent crystalline quality can be obtained by epitaxy, and in situ doping of the donor layer 1' can be precisely controlled. The implantation of light species to form the buried brittle plane 11 is then carried out in the donor layer 1'.

[0061] The donor substrate 1 (or donor layer 1') has a dopant concentration similar to that expected for the useful layer 10.

[0062] Step a) may then include the provision of a polycrystalline silicon carbide support substrate 30. The support substrate 30 has a free face 30a for assembly in a subsequent step of the process, also called the front face 30a; it also has a back face 30b. The support substrate 30 advantageously has a resistivity less than or equal to 10 mΩ·cm, or even less than or equal to 5 mΩ·cm.

[0063] Furthermore, step a) may include the deposition of a film 2 of a semiconductor material other than silicon carbide or of a metallic material, on the free face to be assembled 10a of the useful layer 10 (part of the donor substrate 1) or on the free face to be assembled 30a of the support substrate 30 or, as illustrated in the figure, on both free faces to be assembled 10a,30a.

[0064] The material for film 2 can be chosen, for example, from silicon, titanium or tungsten.

[0065] The film 2 has a thickness of less than 40 nm, preferably less than or equal to 20 nm, less than or equal to 10 nm, or even less than or equal to 5 nm. Note that when a film 2 is deposited on both free faces 10a, 30a, the total deposited thickness, that is, the sum of the thicknesses of film 2 deposited on each free face 10a, 30a, is preferably less than 40 nm, preferably less than or equal to 20 nm, or even less than or equal to 5 nm. The deposited film(s) 2 will constitute the interlayer layer 20 in the intermediate structure 90.

[0066] The total thickness of the deposited film(s) 2 is kept low, so as to allow segmentation of the interlayer layer 20 into nodules or agglomerates at a later stage of the process.

[0067] The deposition of film 2 is preferably carried out under a controlled atmosphere, for example by a known chemical vapor deposition technique (plasma-assisted: PECVD, sub-atmospheric pressure: LPCVD), or a spraying technique using, to bombard the target, a neutral element or one whose residual presence in the deposited film is not problematic (Ar, Si, N…).

[0068] Step a) can then include an assembly of the free faces to be assembled 10a, 30a respectively of the useful layer 10 (part of the donor substrate 1) and of the support substrate 30, at the level of a bonding interface 15 extending along the principal plane (x,y) ().

[0069] This direct assembly is preferably achieved by molecular adhesion, consisting of bringing the faces to be joined 10a, 30a into contact without the addition of an intermediate adhesive. This may involve direct bonding between the donor substrate 1 and the film 2, when the latter has been deposited only on the support substrate 30, or direct bonding between the support substrate 30 and the film 2, when the latter has been deposited only on the donor substrate 1, or even direct bonding between two films 2, when they have been deposited on the donor substrate 1 and on the support substrate 30.

[0070] Direct assembly can be carried out in ambient atmosphere, or under a controlled atmosphere and in particular under a high vacuum, on the order of 10 -6 Pa or less.

[0071] Optionally, film 2 deposition and assembly are performed consecutively without breaking the vacuum, either in situ or in a multi-chamber system. For example, Canon's BV7000 Atomic Diffusion Bonding system allows for successive deposition and direct bonding while maintaining a controlled atmosphere.

[0072] The assembly results in a bonded assembly via the bonding interface 15, including the donor substrate 1, the support substrate 30 and the interlayer layer 20 ().

[0073] Step a) further includes separation at the level of the buried fragile plane 11, to form, on the one hand, the intermediate structure 90, and on the other hand, the remainder of the donor substrate 1'' (). Such separation can be carried out during a heat treatment capable of growing lenticular cavities ("platelets") and microcracks under pressure, induced by the implanted species, in the buried fragile plane 11. This heat treatment typically involves a temperature between 900°C and 1100°C. The separation can also be achieved by applying mechanical stress, or by a combination of thermal and mechanical stresses, as is well known in the Smart Cut process. TM .

[0074] At the end of step a), an intermediate structure 90 is obtained comprising the useful layer 10 disposed on the intercalated layer 20, itself disposed on the support substrate 30, the useful layer 10 having a dopant concentration greater than or equal to 1.10 18 / cm 3 The dopants of the useful layer 10 are nevertheless inactivated in whole or in part, so that the resistivity of the useful layer 10 is greater than or equal to 1 ohm.cm. The intermediate layer 20 extends continuously in a plane (x,y) substantially parallel to a free face 10b of the useful layer 10.

[0075] The manufacturing process according to the invention also includes a step b) of smoothing the free face 10b of the useful layer 10, in the intermediate structure 90 (). Indeed, it is known that separation along a buried brittle plane 11 defined by ion implantation of light species induces a certain level of surface roughness, typically on the order of 6 nm RMS (AFM, 5x5μm scan). 2 or 30x30μm 2 ), at the level of the separated faces 1''a, 10b.

[0076] The smoothing is carried out by a known mechanical polishing technique (including grinding techniques with diamond wheels) or mechano-chemical polishing technique.

[0077] At the end of step b), the composite structure 100 is obtained according to the present invention and as described above. The surface roughness of the useful layer 10, on the side of its free face 100a (front face of the composite structure 100), is less than or equal to 1 nm RMS, 0.5 nm RMS, 0.3 nm RMS, or even 0.1 nm RMS. The excellent quality of the free face of the useful layer 10 makes it very favorable for subsequent epitaxial growth of the high-quality active layer 50.

[0078] An important feature of the manufacturing process is that no heat treatment is applied to the intermediate structure 90 or the composite structure 100 at a temperature above a critical temperature from which the interlayer 20 is likely to segment into nodules, before the epitaxial growth step of the active layer 50. In other words, before step c), any heat treatment applied to the intermediate structure 90 or the composite structure 100 is carried out at a temperature below a critical temperature from which the interlayer 20 is likely to segment.

[0079] The critical temperature can of course vary depending on the nature of the interlayer 20. Typically, it is above 1200°C. When the interlayer 20 is made of silicon, the critical temperature is approximately 1400°C.

[0080] The manufacturing process then includes a step c) of epitaxial growth of an active layer 50 of single-crystal silicon carbide onto the useful layer 10 of the composite structure 100. Step c) involves a temperature greater than or equal to 1500°C, 1650°C, 1700°C, or even 1800°C. The temperature applied in step c) is above the critical temperature. The segmentation of the interlayer layer 20 will therefore occur during the epitaxial step. At the end of step c), a semiconductor structure 150 is obtained comprising, from top to bottom:

[0081] - the active layer 50,

[0082] - the useful layer 10,

[0083] - an interface zone 25 including nodules 21 resulting from the segmentation of the intercalated layer 20 and regions of direct contact between the useful layer 10 and the supporting substrate 30,

[0084] - the support substrate 30.

[0085] The thermal budget of the epitaxy also allows the activation of the dopants in the useful layer 10, which thus regains a resistivity consistent with its dopant concentration. Furthermore, the resistivity of the interface zone 25 is obtained at less than 1 mΩ·cm 2 , or even less than 0.1 mohm.cm 2 .

[0086] The absence of a stress field in the useful layer 10 (due to the presence of a continuous intercalated layer 20 and not in the form of nodules) at the time of the hydrogen etching step, preliminary to the epitaxial growth of m-SiC, makes it possible to eliminate the formation of divot defects on the surface of the useful layer 10 and then on the surface of the active layer 50.

[0087] Lamontre shows two examples (A, B) of AFM images of the surface of the active layer 50 of semiconductor structures 150 fabricated according to the invention. The interlayer 20 of the composite structures 100 that gave rise to the semiconductor structures 150 is made of silicon and has a thickness of 10 nm. It can be observed that the process of the invention makes it possible to obtain a surface free of divot defects, which is not the case for the prior art structure (C), which had an interlayer 20' made of silicon with a thickness of 10 nm and underwent heat treatment at 1700°C before the epitaxial step.

[0088] The surface condition of the active layer 50 is therefore significantly improved within the framework of the invention and it is further noted that the RMS roughness values ​​measured by AFM (scan 30μm x 30μm) are also improved for the composite structures 100 referenced A and B on the: 0.43nm RMS and 0.34nm RMS, versus 0.92nm RMS for structure (C).

[0089] In the field of m-SiC / p-SiC composite structures intended for the microelectronics industry, it is not common not to apply heat treatment at a temperature above 1350°C or 1400°C to a structure because it is known that the complete consolidation of the bonding interface as well as the reactivation of the dopants take place at higher temperatures.

[0090] The applicant observed that these two phenomena occurred correctly during the epitaxy stage, and that the composite structure 100 did not undergo degradation during this stage despite the prior non-application of very high temperatures to the intermediate structure 90 or the composite structure 100. The invention therefore provides a significant advantage with regard to the surface quality and surface defects of the active layer 50 (elimination of divot defects and associated roughness) while achieving the excellent performance levels of a composite structure (very high bonding interface strength, very good quality of the useful layer 10, restoration of its low resistivity and very low resistivity of the interface zone), immediately after the formation of the active layer 50.

[0091] Classical steps for defining microelectronic components 200 can then be carried out in and / or on the active layer 50 of the semiconductor structure 150 (). Example of implementation:

[0092] Donor substrate 1 is high-quality, single-crystal SiC4H and has a diameter of 150 mm. Donor substrate 1 is N-doped, with a resistivity of approximately 20 mΩ·cm, corresponding to a N-dopant concentration of 1 x 10⁻¹⁰ 18 / cm 3 It is implanted through its front face 1a, type "C" face, with hydrogen ions at a dose of 5 E 16 / cm 2 and an energy of 95keV. Around the implantation depth, a fragile buried plane 11 is thus defined, delimiting with the front face 10a of the donor substrate 1, the useful layer 10.

[0093] The support substrate 30 is made of polycrystalline SiC, with the same diameter as the donor substrate 1. It is N-doped, with a resistivity of the order of 5 mohm.cm.

[0094] Both substrates 1,30 undergo classic cleaning sequences to remove particles and other surface contaminants.

[0095] The 1,30 substrates are introduced into a first deposition chamber, integrated into a direct bonding system. A 4nm thick silicon film 2 is deposited on each of the front faces 10a,30a (free faces to be assembled) of the 1,30 substrates, under secondary vacuum, at 10 -6 PA and ambient temperature, by spraying.

[0096] The substrates 1,30 are introduced into a second bonding chamber, to be assembled at the level of their front faces 10a,30a, by bringing into direct contact the films 2 deposited respectively on the donor substrate 1 and on the support substrate 30. The atmosphere in the bonding chamber is the same as that in the deposition chamber.

[0097] After assembly, the bonded assembly comprises the donor substrate 1 linked to the support substrate 30 via a bonding interface 15, and the interlayer layer 20 formed from the two films 2 deposited and buried between the two substrates 1,30. The interlayer layer 20 has a thickness of approximately 8nm.

[0098] The bonded assembly is subjected to a heat treatment to induce separation at the level of the buried weak plane 11, at a temperature of approximately 900°C, for 30 minutes. This yields the intermediate structure 90, comprising a useful layer 10 with a thickness of 500nm, disposed on the intercalated layer 20, itself disposed on the supporting substrate 30.

[0099] Mechano-chemical cleaning and polishing sequences (commercial KMnO4-based slurry, IC1000 type polishing cloth, polishing time of one to a few minutes) are applied in such a way as to restore the correct level of defect and roughness to the surface 10b of the useful layer 10.

[0100] This results in a composite structure 100 whose useful layer 10 has a dopant concentration greater than or equal to 1.10 18 / cm 3with dopants that are wholly or partially inactivated, so that the resistivity of the useful layer 10 is on the order of 1 ohm·cm. The useful layer 10 has a free face 100a with a surface roughness of 0.4 nm RMS (or even less than 0.1 nm RMS). The interlayer layer 20 is continuous in a plane (x,y) substantially parallel to the free face 100a of the useful layer 10, because no very high-temperature heat treatment has caused segmentation of said layer.

[0101] This composite structure 100 is then used to develop an active layer 50 on the useful layer 10.

[0102] Silicon carbide epitaxy, for example, is carried out at a temperature of 1650°C and allows the growth of an active layer of 20μm.

[0103] The surface roughness obtained on the front face 150a of the active layer 50 is less than 1 nm RMS, less than or equal to 0.8 nm RMS, less than or equal to 0.6 nm RMS, or even less than or equal to 0.4 nm RMS. The thermal budget of the epitaxy also caused the segmentation of the interlayer layer 20 into nodules separated by regions of direct contact between the active layer 10 and the supporting substrate 30. The interface zone is thus perfectly consolidated and has a low resistivity of less than 0.1 mΩ·cm 2 Furthermore, this thermal budget reactivated the dopants of the useful layer 10 by healing the damage caused by the implantation of light species, restoring the resistivity of the order of 20mohm.cm of the useful layer 10.

[0104] 200 electronic components can be developed on and / or within the active layer 50. These components can notably address power applications. By way of non-limiting examples, these power components may include transistors, diodes, thyristors or passive components (capacitors, inductors, etc.).

[0105] Of course, the invention is not limited to the embodiments and examples described, and alternative embodiments may be introduced without departing from the scope of the invention as defined by the claims.

Claims

Composite structure (100) comprising a useful layer (10) of monocrystalline silicon carbide disposed on an interlayer layer (20) of a metallic or semiconductor material other than silicon carbide, the interlayer itself being disposed on a support substrate (30) of polycrystalline silicon carbide, the useful layer (10) having a dopant concentration greater than or equal to 1.10 18 / cm 3 , the composite structure (100) being characterized in that:- the dopants of the useful layer (10) are inactivated in whole or in part, so that the resistivity of the useful layer (10) is greater than or equal to 1 ohm.cm,- the useful layer (10) has a free face (100a) having a surface roughness less than or equal to 1nm RMS,- the intercalated layer (20) is continuous in a plane (x,y) substantially parallel to the free face (100a) of the useful layer (10). Composite structure (100) according to the preceding claim, wherein the interlayer layer (20) has a thickness between 2nm and 40nm. Composite structure (100) according to any one of the preceding claims, wherein the material composing the interlayer (20) is silicon or tungsten or titanium. Composite structure (100) according to any one of the preceding claims, wherein the supporting substrate (30) has a resistivity less than or equal to 10 mohm.cm, or even less than or equal to 5 mohm.cm. A composite structure (100) according to any one of the preceding claims, wherein an interface zone of the composite structure (100), including: - the interlayer (20), - an interface between the useful layer (10) and the interlayer (20), and - an interface between the interlayer (20) and the supporting substrate (30), has a resistivity greater than 1 mΩ·cm 2 , or even greater than 1 ohm.cm2 . A method for manufacturing a semiconductor structure (150) for the fabrication of microelectronic components (200), using a composite structure (100) according to any one of the preceding claims, comprising the following steps: a) transferring a useful layer (10) of monocrystalline silicon carbide onto a support substrate (30) of polycrystalline silicon carbide, via an interlayer layer (20) of a metallic or semiconductor material other than silicon carbide, to form an intermediate structure (90) comprising the useful layer (10) disposed on the interlayer layer (20), itself disposed on the support substrate (30), the useful layer (10) having a dopant concentration greater than or equal to 1.10 18 / cm 3, the dopants of the useful layer (10) being inactivated in whole or in part, so that the resistivity of the useful layer (10) is greater than or equal to 1 ohm.cm, the interlayer (20) extending continuously in a plane (x,y) substantially parallel to a free face (10b) of the useful layer (10); b) smoothing the free face (10b) of the useful layer (10) by mechanical or mechano-chemical polishing so as to obtain a surface roughness less than or equal to 1nm RMS, to form the composite structure (100); c) growth by epitaxy of an active layer (50) of single-crystal silicon carbide on the useful layer (10) of the composite structure (100), involving a temperature greater than or equal to 1500°C, to form a semiconducting structure (150); in which, before step c), any heat treatment applied to the intermediate structure (90) or to the composite structure (100), is carried out at a temperature less than a critical temperature from which the interlayer (20) is liable to segment into nodules. A manufacturing process according to the preceding claim, wherein step a) comprises: - an implantation of light species in a donor substrate (1), to form a buried fragile plane (11) which delimits, with a front face (10a) of the donor substrate (1), the useful layer (10) to be transferred; - an assembly by molecular adhesion of the donor substrate (1) onto the support substrate (30), via the intercalated layer (20); - a separation at the level of the buried fragile plane (11), to form on the one hand the intermediate structure (90) and on the other hand the remainder (1'') of the donor substrate. Manufacturing method according to the preceding claim, wherein step a) includes, prior to assembly, the deposition of a film (2) of the metallic or semiconducting material of the interlayer (20) on the front face of the donor substrate (1) and / or on a face to be assembled of the support substrate (30), the thickness of said film (2) being less than or equal to 40nm, 20nm, 10nm, or even 5nm. A manufacturing process according to one of the three preceding claims, wherein the interlayer layer (20) has a thickness between 2nm and 40nm. A manufacturing method according to one of the four preceding claims, wherein the material composing the interlayer (20) is silicon or tungsten or titanium. A manufacturing method according to one of the five preceding claims, wherein the support substrate (30) has a resistivity less than or equal to 10 mohm.cm, or even less than or equal to 5 mohm.cm. A manufacturing process according to one of the six preceding claims, wherein the critical temperature is 1400°C. A manufacturing process according to any one of claims 6 to 11, wherein the critical temperature is 1350°C. Manufacturing method according to one of the eight preceding claims, further comprising the formation of microelectronic components (200) in and / or on the active layer (50).

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