Wiring board and method of manufacturing same

Abstract

This wiring board comprises a base material, and a plurality of wiring layers and a plurality of interlayer insulating films that are alternately laminated on the base material. The base material contains a polymer and has a through hole. The plurality of wiring layers are electrically connected to each other via a first opening provided in each of the plurality of insulating films. Each of the plurality of wiring layers includes a first seed layer containing titanium, a second seed layer located on the first seed layer and containing copper, and a wiring located on the second seed layer and containing copper. The second seed layer in the lowermost wiring layer among the plurality of wiring layers is exposed from the base material via the through hole.

Description

Wiring Substrate and Method for Manufacturing the Same

[0001] One embodiment of the present invention relates to a wiring substrate and a method for manufacturing the same.

[0002] Semiconductor chips manufactured using semiconductor substrates are mounted on almost all electronic devices, providing various functions to the electronic devices. Terminals for inputting power and signals necessary for operation are provided on the semiconductor chips and mounted on the main substrate. At this time, a wiring substrate, also called an interposer, is provided between the semiconductor chip and the main substrate. Such a wiring substrate has a substrate, a plurality of wiring layers on the substrate, and an interlayer insulating film between adjacent wiring layers as basic components, and the plurality of wiring layers are laminated on the substrate in various layouts. Patent Documents 1 and 2 disclose a wiring substrate using polyimide as an interlayer insulating film and a method for manufacturing the same.

[0003] Japanese Patent Application Laid-Open No. 2021-114534, Japanese Patent Application Laid-Open No. 07-170072

[0004] One of the problems of one embodiment of the present invention is to provide a wiring substrate having a novel structure and a method for manufacturing the same. Alternatively, one of the problems of one embodiment of the present invention is to provide a highly reliable wiring substrate and a method for manufacturing the wiring substrate at low cost.

[0005] One embodiment of the present invention is a wiring substrate. This wiring substrate includes a base material and a plurality of wiring layers and a plurality of interlayer insulating films alternately laminated on the base material. The base material contains a polymer and has through holes. The plurality of wiring layers are electrically connected to each other through first openings provided in each of the plurality of interlayer insulating films. Each of the plurality of wiring layers has a first seed layer containing titanium, a second seed layer containing copper located on the first seed layer, and a wiring containing copper located on the second seed layer. The second seed layer in the lowermost wiring layer among the plurality of wiring layers is exposed from the base material through the through hole.

[0006] One embodiment of the present invention is a method for manufacturing a wiring substrate. This manufacturing method includes forming a substrate containing a polymer and having through holes on a support substrate, alternately laminating a plurality of wiring layers and a plurality of interlayer insulating films on the substrate, and peeling the substrate from the plurality of wiring layers and the plurality of interlayer insulating films. Each of the plurality of wiring layers is electrically connected to one another through a first opening provided in each of the plurality of interlayer insulating films. Each of the plurality of wiring layers is formed by sequentially laminating a first seed layer containing titanium, a second seed layer containing copper, and wiring containing copper. The second seed layer of the bottommost wiring layer among the plurality of wiring layers is formed to be exposed from the substrate through through holes.

[0007] A schematic end view of a wiring board according to one embodiment of the present invention. A schematic end view of a wiring board according to one embodiment of the present invention. A schematic end view of a wiring board according to one embodiment of the present invention. A schematic bottom view of a wiring board according to one embodiment of the present invention. A schematic end view of a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a wiring board according to one embodiment of the present invention.

[0008] The embodiments of the present invention will be described below with reference to the drawings and other materials. However, the present invention can be implemented in various forms without departing from its spirit, and is not to be interpreted as being limited to the embodiments described below.

[0009] While drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation, these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same function as those described with respect to previously shown drawings are denoted by the same reference numeral, and redundant explanations may be omitted. This reference numeral is used to indicate multiple identical or similar components collectively, and when these components are indicated individually, a hyphen and a natural number are used after the reference numeral. Furthermore, when indicating a part of a single component, a lowercase alphabet letter is used after the reference numeral.

[0010] In this specification and claims, when describing a manner in which one structure is placed on top of another structure, unless otherwise specified, the term "on top of" includes both cases: when one structure is placed directly on top of another structure so as to be in contact with it, and when another structure is placed above another structure via yet another structure.

[0011] In this specification and claims, the expression "one structure is exposed from another structure" means a part of one structure that is not covered by the other structure, and this part that is not covered by the other structure may be covered by yet another structure. The hierarchical relationship between one structure and the other structure is irrelevant. Furthermore, the embodiment described by this expression also includes a form in which one structure is not in contact with the other structure.

[0012] In this invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process, and have substantially the same layer structure, the same material, and the same morphology. Therefore, these multiple films are defined as existing in the same layer.

[0013] The following describes the structure and manufacturing method of a wiring board according to one embodiment of the present invention.

[0014] 1. Structure of the wiring board Figure 1 shows a schematic end view of the wiring board 100. The wiring board 100 also functions as an interposer. The wiring board 100 has a base material 102 and mainly comprises a plurality of wiring layers 110 and a plurality of interlayer insulating films 106 on the base material 102. The wiring layers 110 and interlayer insulating films 106 are alternately laminated on the base material 102. There is no restriction on the number of wiring layers 110 and interlayer insulating films 106. However, one wiring layer 110 is initially provided on the base material 102, and then interlayer insulating films 106 and wiring layers 110 are alternately provided on it. Also, no interlayer insulating film 106 is provided on the uppermost wiring layer 110, and a protective film 108 can be provided. Therefore, the number of interlayer insulating films 106 is the number of wiring layers 110 minus 1. The number of wiring layers 110 can be appropriately selected from, for example, a range of 1 to 10 or 1 to 5. In the example shown in Figure 1, the wiring board 100 is provided with three wiring layers (a first wiring layer 110-1, a second wiring layer 110-2, and a third wiring layer 110-3), and a first interlayer insulating film 106-1 and a second interlayer insulating film 106-2 are provided between the first wiring layer 110-1 and the second wiring layer 110-2, and between the second wiring layer 110-2 and the third wiring layer 110-3, respectively. The wiring board 100 may have flexibility to the extent that it can be plastically deformed, or it may have strength to the extent that it can be elastically deformed. These configurations will be described in detail below.

[0015] (1) The base material 102 contains a polymer, preferably a polymer with high heat resistance and high dielectric constant. Examples of such polymers include aromatic polyimide (hereinafter also simply referred to as polyimide) and aromatic polyamide (hereinafter also simply referred to as polyamide). The polymer may be in chain form or may be crosslinked between molecules. In addition to the polymer described above, the base material 102 may further contain fine particles such as silicon dioxide or glass fibers. The thickness of the base material 102 can be selected from, for example, a range of 1 μm to 30 μm. By setting the thickness of the base material 102 within this range, flexibility can be imparted to the wiring board 100.

[0016] The substrate 102 is provided with one or more through holes 102a depending on the application of the wiring board 100. There are no restrictions on the size or shape of the through holes 102a (shape on the top or bottom surface of the substrate 102, hereinafter the same). For example, the shape of the through hole 102a may be a circle, an ellipse, a polygon, or a shape whose outline is formed by straight lines and curves. If the shape of the through hole 102a is a circle, its diameter may be appropriately set in a range of, for example, 1 μm to 200 μm, depending on the application of the wiring board 100.

[0017] (2) Wiring Layers As shown in Figure 1, each of the plurality of wiring layers 110 comprises a first seed layer 112, a second seed layer 114 on the first seed layer 112, and wiring 116 on the second seed layer 114. In each wiring layer 110, the second seed layer 114 is in contact with the first seed layer 112 and the wiring 116. Also, adjacent wiring layers 110 in the vertical direction (normal direction of the substrate 102, the same applies hereafter) are in contact with each other. Although not shown, the planar layout of each wiring layer 110 may be appropriately determined according to the configuration of the semiconductor chip and main substrate connected to the wiring board, the functions required of the wiring board 100, etc.

[0018] The first seed layer 112 is a metal film containing titanium or substantially composed of titanium. The thickness of the first seed layer 112 is selected from a range of 1 nm to 50 nm, for example, 20 nm. As will be described later, the copper contained in the second seed layer 114 has low adhesion to inorganic compounds such as silicon dioxide contained in glass and polymers. In contrast, titanium has higher adhesion to inorganic compounds and polymers compared to copper. Therefore, by providing the first seed layer 112 in each wiring layer 110, high adhesion can be obtained between the wiring layer 110 and the substrate 102 or the inorganic insulating film 104 described later, between the first seed layer 112 and the second seed layer 114, and between adjacent wiring layers 110. As a result, defects such as the wiring layer 110 peeling off from the substrate 102 or delamination occurring inside the wiring layer 110 can be prevented during the manufacturing or use of the wiring substrate 100. These features contribute to improving the reliability of the wiring substrate 100.

[0019] The second seed layer 114 is a metal film containing copper or substantially composed of copper. The thickness of the first seed layer 112 is also selected from the range of 0.10 μm to 0.50 μm, for example, 0.3 μm. As will be described later, the wiring 116 on the second seed layer 114 is formed by electroplating. For this reason, the second seed layer 114 functions together with the first seed layer 112 as a power supply site for electroplating.

[0020] Similar to the second seed layer 114, the wiring 116 is a metal film containing or substantially composed of copper. Since the wiring 116 is the main component responsible for the conductive paths in the wiring substrate 100, it is formed to have a greater thickness than the first seed layer 112 and the second seed layer 114. For example, the wiring 116 can be formed to a thickness of 3 μm to 10 μm, typically 5 μm.

[0021] In this configuration, the first wiring layer 110-1, which is the lowest wiring layer, is separated from the through-hole 102a of the base material 102 and is not exposed from the base material 102. In other words, the first seed layer 112-1 does not cover the side wall of the through-hole 102a, does not overlap with the through-hole 102a in the vertical direction, and has an opening that surrounds the through-hole 102a. The base material 102 is exposed from the first seed layer 112-1 at this opening. In contrast, the second seed layer 114-1 not only covers the first seed layer 112-1 but is also located inside the through-hole 102a, is in contact with the side wall of the through-hole 102a, and covers at least a portion of the side wall. Therefore, the second seed layer 114-2 is exposed from the base material 102 at the through-hole 102a. The second seed layer 114 of this bottommost wiring layer 110 is used for electrical connection between the wiring board 100 and the main board. In the first wiring layer 110-1, the wiring 116-1 may be located inside the through hole 102a, or its bottom surface (the surface closest to the base material 102) may be coplanar with the top surface of the base material 102, or located above this top surface.

[0022] (3) Interlayer insulating film The interlayer insulating film 106 is provided so as to be sandwiched between adjacent wiring layers 110 in the vertical direction. Similar to the substrate 102, the interlayer insulating film 106 also contains the polymer described above. Preferably, a polyimide with a high dielectric constant is used. The thickness of the interlayer insulating film 106 is also appropriately set according to the size of the wiring substrate 100 and the current value flowing through the wiring substrate 100, and is appropriately determined, for example, in the range of 1 μm to 20 μm.

[0023] Each interlayer insulating film 106 covers at least a portion of the edge of the wiring layer 110 located directly beneath it. For example, in the example shown in Figure 1, the first interlayer insulating film 106-1 covers the edge of the first wiring layer 110-1 located beneath it, and the second interlayer insulating film 106-2 covers the edge of the second wiring layer 110-2 located beneath it. In addition, each interlayer insulating film 106 is partially covered by the wiring layer 110 located directly above it. In the example shown in Figure 1, a portion of the first interlayer insulating film 106-1 is covered by the second wiring layer 110-2 located above it, and a portion of the second interlayer insulating film 106-2 is covered by the third wiring layer 110-3 located above it. Each interlayer insulating film 106 is provided with an opening that overlaps with the wiring layer 110, and adjacent wiring layers 110 in the vertical direction are physically and electrically connected within this opening.

[0024] (4) Other components The wiring board 100 may further include an inorganic insulating film 104 covering the upper surface of the substrate 102. The inorganic insulating film 104 is in contact with the substrate 102 and the first seed layer 112-1 of the first wiring layer 110-1, and is sandwiched between them. A portion of the inorganic insulating film 104 may be in contact with the second seed layer 114-1 of the first wiring layer 110-1 and the first interlayer insulating film 106-1, which is the bottommost interlayer insulating film. The inorganic insulating film 104 is composed of one or more films containing silicon-containing inorganic compounds such as silicon nitride or silicon oxide, and its thickness is set to, for example, 0.1 μm or more and 0.3 μm or less. The interlayer insulating film 106 has a relatively large internal stress (tensile stress), and due to this internal stress, deformation of the substrate 102 and the wiring layer 110 may occur during the manufacture or use of the wiring board 100. Such deformation not only leads to misalignment during the manufacturing of the wiring board 100, but also causes damage to the wiring board 100, including delamination of the wiring layer 110. However, since the inorganic insulating film 104 has compressive stress, it cancels out the internal stress of the interlayer insulating film 106, and as a result, deformation of the wiring board 100 during manufacturing and use can be prevented.

[0025] As will be described later, the inorganic insulating film 104 also functions as a hard mask when forming the through hole 102a in the substrate 102. Therefore, the inorganic insulating film 104 does not exist inside the through hole 102a. In addition, the end of the inorganic insulating film 104 on the through hole 102a side may coincide with the side wall of the through hole 102a in the vertical direction.

[0026] The wiring board 100 may have a protective film 108 placed on the uppermost wiring layer (in the example shown in Figure 1, the third wiring layer 110-3). The protective film 108 is configured to contain a polymer such as polyimide, polyamide, epoxy resin, acrylic resin, or silicon resin. Alternatively, the protective film 108 may have a laminated structure of a film containing the above-mentioned polymer and a film containing a silicon-containing inorganic compound. One or more openings 108a are formed in the protective film 108 to expose the uppermost wiring layer 110. The openings 108a allow for electrical connection between the wiring board 100 and the semiconductor chip.

[0027] 2. Modifications of the Wiring Board The structure of the wiring board 100 is not limited to the above structure, and various modifications are possible. For example, as shown in the schematic end view of Figure 2, the end of the first wiring layer 110-1, which is the lowest wiring layer, on the side of the through hole 102a of the first seed layer 112-1 may coincide with the side wall of the through hole 102a in the vertical direction. In this case, the substrate 102 is not exposed from the first seed layer 112-1 between the through hole 102a and the first seed layer 112-1.

[0028] Furthermore, an inorganic insulating film 105 in contact with the substrate 102 may be provided beneath the substrate 102. The inorganic insulating film 105, like the inorganic insulating film 104, can be composed of one or more films containing silicon-containing inorganic compounds. The inorganic insulating film 105 is provided so as to block the through-holes 102a. By providing the inorganic insulating film 105, the internal stress of the interlayer insulating film 106 can be more effectively counteracted.

[0029] Alternatively, as shown in the schematic end view of Figure 3, the first seed layer 112-1 of the first wiring layer 110-1, which is the bottommost wiring layer, may cover the side wall of the through hole 102a of the base material 102. In this case, the second seed layer 114-1 of the first wiring layer 110-1 is separated from the side wall and covers the side wall via the first seed layer 112-1. Also, as shown in Figure 3, the first seed layer 112-1 may have a portion (the portion enclosed by the dotted ellipse in the figure) that extends in a direction parallel to the bottom surface of the base material 102 in the through hole 102a. Therefore, a part of the first seed layer 112-1 is exposed from the base material 102, and when the wiring board 100 is observed from the base material 102 side, it surrounds the second seed layer 114-1, as shown in Figure 4.

[0030] Alternatively, as shown in the schematic end view of Figure 5, the wiring board 100 may further have via metal 120 filling at least a portion of the through hole 102a. The via metal 120 contains copper or is substantially composed of copper. In this case, the first seed layer 112-1 of the first wiring layer 110-1, which is the bottommost wiring layer, is provided to cover the through hole 102a and the via metal 120. The first seed layer 112-1 is in contact with the via metal 120.

[0031] In the examples shown in Figures 1 to 3, the bottom surface 114-1a of the through-hole 102a of the second seed layer 114-1 of the first wiring layer 110-1, which is the lowest wiring layer (i.e., the lowest surface of the first wiring layer 110-1 when the base material 102 is placed on the bottom side), is on the same plane as the bottom surface 102b of the base material 102. However, the configuration of the wiring board 100 is not limited to this, and as shown in Figure 6, the bottom surface 114-1a of the second seed layer 114-1 may be located below the bottom surface 102b of the base material 102. In other words, the second seed layer 114-1 of the first wiring layer 110-1 may protrude downward from the bottom surface 102b of the base material 102. This configuration allows for more reliable electrical connection between the lowest first wiring layer 110-1 and the main board.

[0032] As can be seen from the manufacturing method of the wiring board 100 described below, by adopting the above-described structure, it becomes possible to provide the wiring board 100 at a low cost.

[0033] 3. Method for Manufacturing a Wired Board The method for manufacturing the wired board 100 will be described below. Here, the wiring board 100 shown in Figure 1 will be used as an example.

[0034] (1) Formation of the substrate First, as shown in Figure 7, the substrate 102 is formed on the support substrate 130. As the support substrate 130, a substrate that transmits ultraviolet light, specifically light with a wavelength of 190 nm to 360 nm, is used. More specifically, glass substrates and quartz substrates are examples of support substrates 130. The substrate 102 can be formed by applying a wet film formation method such as spin coating, slit coating, dip coating, inkjet, or printing to the support substrate 130, applying a solution of the polymer or its precursor as described above, and then performing heat treatment as necessary. Subsequently, an inorganic insulating film 104 is formed by using chemical vapor deposition (CVD) to form one or more films containing silicon-containing inorganic compounds on the substrate 102. For example, the inorganic insulating film 104 can be formed by laminating a film containing silicon oxide and a film containing silicon nitride. The substrate 102 and the inorganic insulating film 104 are formed over almost the entire surface of the support substrate 130. If an inorganic insulating film 105 (see Figure 2) is to be provided, the inorganic insulating film 105 can be formed on the support substrate 130 before the substrate 102 is formed using the CVD method.

[0035] Next, a resist mask 132 is formed so as to expose the region in which the through-hole 102a is to be formed. In forming the resist mask 132, first, a solution containing the corresponding photoresist is applied to the inorganic insulating film 104, or a resist film is attached to the inorganic insulating film 104. Heat treatment may be performed if necessary. After that, the resist mask 132 is formed by exposure through the photomask and subsequent development.

[0036] Next, the inorganic insulating film 104 is etched by dry etching. As a result, the inorganic insulating film 104 is selectively removed in the region where the through-hole 102a is formed, as shown in Figure 8.

[0037] Next, remove the resist mask 132 with the stripping solution or O ２ After removal by ashing, the inorganic insulating film 104 is used as a hard mask and applied to the substrate 102. ２By performing ashing, the portion of the substrate 102 exposed from the inorganic insulating film 104 is removed (Figure 9). At this time, the oxygen partial pressure is preferably controlled to 5 Pa or less in order to suppress an increase in plasma density. This prevents the formation of a layer that inhibits etching, which occurs due to an excessive rise in the surface temperature of the substrate 102. The resist mask 132 is also O ２ Since it can be removed by ashing, O to the base material 102 ２ Ashing may be performed while the resist mask 132 remains. This allows the formation of the through-holes 102a and the removal of the resist mask 132 to be performed in the same process. Through the above process, a substrate 102 having through-holes 102a can be formed on the support substrate 130.

[0038] (2) Formation of the first wiring layer Thereafter, a plurality of wiring layers 110 and interlayer insulating films 106 are alternately formed on the substrate 102. Specifically, first, the sputtering method is applied to form the first seed layer 112-1 on the inorganic insulating film 104 (or the substrate 102 if the inorganic insulating film 104 is not provided) (Figure 10). The first seed layer 112-1 is provided so as to cover not only the inorganic insulating film 104 but also the side walls of the through-hole 102a and the upper surface of the support substrate 130 that is exposed within the through-hole 102a. Thereafter, a resist mask 134 for forming the first seed layer 112-1 is formed. As shown in Figure 11, the resist mask 134 is provided so as not to cover the through-hole 102a. That is, the resist mask 134 is formed so that a part of the first seed layer 112-1 is exposed around the through-hole 102a. The resist mask 134 can be formed in the same way as the resist mask 132.

[0039] Subsequently, the first seed layer 112-1 is formed by dry etching, and the portion not covered by the resist mask 134 is removed. As a result, as shown in Figure 12, an opening 112-1a surrounding the through hole 102a is formed in the first seed layer 112-1, and as a result, the first seed layer 112-1 is separated from the through hole 102a, and a part of the substrate 102 is exposed at the opening 112-1a. The resist mask 134 is then removed by ashing or other methods.

[0040] Next, a second seed layer 114-1 is formed on the first seed layer 112-1 using a sputtering method. The second seed layer 114-1 covers the first seed layer 112-1 and is provided so as to cover the side walls of the through holes 102a and the upper surface of the support substrate 130 exposed from the through holes 102a (FIG. 13). Therefore, at the stage when the second seed layer 114-1 is formed, the first seed layer 112-1 does not contact the support substrate 130, and the second seed layer 114-1 contacts the support substrate 130.

[0041] Thereafter, a resist mask 136 is formed on the second seed layer 114-1 (FIG. 14). The resist mask 136 is formed so as to cover the region where the wiring 116-1 is not provided. The resist mask 136 may also be formed in the same manner as the resist masks 132 and 134.

[0042] Thereafter, the wiring 116-1 is formed using electroplating. Specifically, power is supplied to the first seed layer 112-1 and the second seed layer 114-1 in an electrolytic solution containing copper ions. Thereby, the wiring 116-1 grows from the surface of the second seed layer 114-1 (FIG. 15). Thereafter, the resist mask 136 is removed using a stripping solution or ashing or the like (FIG. 16). In this state, wet etching is performed on the wiring 116, the second seed layer 114-1, and the first seed layer 112-1. The wet etching is performed until at least the portions of the first seed layer 112-1 and the second seed layer 114-1 exposed from the wiring 116 disappear and the inorganic insulating film 104 (or the base material 102 if the inorganic insulating film 104 is not provided) is exposed from the wiring 116 (FIG. 17). Thereby, insulation is performed from other wirings existing in the same wiring layer 110. At this time, the thickness of the wiring 116 is also reduced by etching. Also, since the wiring 116 also functions as a mask, it is possible to position the side surfaces of the wiring 116, the first seed layer 112-1, and the second seed layer 114-1 on the same plane. Through the above steps, the first wiring layer 110-1, which is the bottommost wiring layer, is formed.

[0043] (3) Formation of Interlayer Insulating Film Next, a first interlayer insulating film 106-1 is formed on the first wiring layer 110-1. Specifically, a solution of a polymer or its precursor contained in the interlayer insulating film 106 is applied onto the first wiring layer 110-1 using a wet film-forming method. If necessary, the applied polymer or its precursor is heated. Then, exposure is performed through a photomask (not shown). By developing the exposed polymer, an opening 106-1a is formed to cover the end portion of the first wiring layer 110-1 and expose the first wiring layer 110-1, thereby forming the first interlayer insulating film 106-1 (FIG. 18).

[0044] (4) Lamination of Wiring Layers and Interlayer Insulating Films, and Formation of Protective Film Thereafter, by repeating the above-described process, the wiring layer 110 and the interlayer insulating film 106 are alternately laminated on the first interlayer insulating film 106-1. Briefly stated, by applying the above-described method for forming the first seed layer 112-1 and the second seed layer 114-2, the first seed layer 112-2 and the second seed layer 114-2 that constitute the second wiring layer 110-2 are sequentially formed on the first interlayer insulating film 106-1 and the wiring 116-1 exposed in the opening 106-1a of the first interlayer insulating film 106-1 (FIG. 19). Further, a resist mask 138 is formed on the second seed layer 114-2, and by supplying power to the first seed layer 112-2 and the second seed layer 114-2 in an electrolytic solution containing copper ions, the wiring 116-2 is formed (FIG. 20). Thereafter, the resist mask 138 is removed, and the wiring 116-2, the second seed layer 114-2, and the first seed layer 11^ are shaped by dry etching, thereby forming the second wiring layer 110-2 as shown in FIG. 21.

[0045] Thereafter, a second interlayer insulating film 106-2 is formed to cover the end portion of the second wiring layer 110-2 in the same manner as the first interlayer insulating film 106-1. Further, in the same manner as the second wiring layer 110-2, a third wiring layer 110-3 including a first seed layer 112-3, a second seed layer 114-3, and a wiring 116-3 is formed on the second interlayer insulating film 106-2 (FIG. 22). After this, a protective film 108 is formed (FIG. 23). The protective film 108 may also be formed by the same method as the interlayer insulating film 106.

[0046] (5) Peeling off the support substrate Next, the support substrate 130 is peeled off. Peeling is performed using a method called laser lift-off. Specifically, laser light is irradiated onto the substrate 102 through the support substrate 130 (see arrow in Figure 23). As the laser light, for example, laser light emitted from an excimer laser is used. The wavelength of the laser light is in the ultraviolet region, for example, 193 nm, 248 nm, 308 nm, or 351 nm. By irradiating with laser light, some of the polymer contained in the substrate 102 is decomposed, and as a result, the adhesive strength between the support substrate 130 and the substrate 102 is reduced. Subsequently, by physically peeling the support substrate 130 from the multiple wiring layers 110 and the multiple interlayer insulating films 106, the bottom surface 102b of the substrate 102 and the first wiring layer 110-1 are exposed, and the wiring substrate 100 shown in Figure 1 can be obtained. Note that the amount of decomposition of the substrate 102 can be adjusted by appropriately changing the conditions for laser light irradiation, for example, by adjusting the intensity of the laser light and the irradiation time. Therefore, by increasing the intensity and / or irradiation time of the laser light, for example, the thickness of the substrate 102 can be further reduced, and as a result, the wiring board 100 shown in Figure 6 can be manufactured.

[0047] Here, when the support substrate 130 is peeled off, the support substrate 130 comes into contact with the second seed layer 114-1 but not with the first seed layer 112-1 (see Figure 23). Since the titanium constituting the first seed layer 112-1 has high adhesion to the silicon oxide contained in the support substrate 130, if the first seed layer 112-1 is formed so as to come into contact with the support substrate 130, the high adhesion between the first seed layer 112-1 and the support substrate 130 is maintained even after laser irradiation. For this reason, a high adhesive force acts between the support substrate 130 and the first wiring layer 110-1 even after laser irradiation, making it difficult to peel off the support substrate 130. For example, when the support substrate 130 is peeled off, the first wiring layer 110-1 may be destroyed, and a part of it may remain on the support substrate 130.

[0048] On the other hand, in the above-described process, before the support substrate 130 is peeled off, the first seed layer 112-1 of the first wiring layer 110-1, which is the bottommost wiring layer, is formed to be separated from the support substrate 130, and the second seed layer 114-1, which contains or is substantially made of copper, is in contact with the support substrate 130. Compared to titanium, the adhesive strength between copper and silicon oxide is low. For this reason, in the method for manufacturing a wiring substrate according to the embodiment of the present invention, when peeling off the support substrate 130, the adhesive strength between the first wiring layer 110-1 and the support substrate 130 is low, and the support substrate 130 can be easily peeled off without damaging the wiring layer 110. This characteristic improves the manufacturing yield of the wiring substrate 100, making it possible to provide a low-cost and highly reliable wiring substrate.

[0049] (6) Modified Examples When manufacturing the wiring board 100 shown in Figures 2 and 3, the layout of the resist mask 134 (see Figure 11) can be changed. For example, when manufacturing the wiring board 100 shown in Figure 2, although not shown, the resist mask 134 can be formed so that the end of the resist mask 134 on the through-hole 102a side coincides with the side wall of the through-hole 102a in the vertical direction. When manufacturing the wiring board 100 shown in Figure 3, as shown in Figure 24, the resist mask 134 can be formed on the first seed layer 112-1 so as to partially protrude into the through-hole 102a. At this time, the length L of the through-hole 102a at the end face １ The length L of the protruding portion that overlaps with the through hole 102a of the resist mask 134. ２ The ratio is preferably greater than 0 and less than or equal to 0.2. Also, the length L ２Preferably, the thickness of the resist mask 134 is greater than the thickness of the first seed layer 112-1 on the side wall of the through hole 102a. By forming the resist mask 134 in this manner, it is possible to significantly reduce the area in contact between the first seed layer 112-1 and the support substrate 130 compared to the area in contact between the second seed layer 114-1 and the support substrate 130, and a certain degree of adhesion can be ensured between the first seed layer 112-1 and the support substrate 130. As a result, it is possible to prevent the contact between the first seed layer 112-1 and the support substrate 130 from having an adverse effect on the peeling of the support substrate 130, and also to prevent unintended peeling of the support substrate 130 during the manufacturing process of the wiring board 100. By performing dry etching in this state, the first seed layer 112-1 that covers at least a part of the side wall of the through hole 102a can be formed (Figure 25). The subsequent steps are the same as those described above, so their explanation is omitted.

[0050] When manufacturing the wiring board 100 shown in Figure 5, as shown in Figure 26, after forming through holes 102a, a first metal film 122 containing or substantially made of copper is formed on the inorganic insulating film 104 (or the substrate 102 if the inorganic insulating film 104 is not formed). The first metal film 122 is formed over almost the entire surface of the substrate 102 and the inorganic insulating film 104. Since the first metal film 122 is also formed inside the through holes 102a, the first metal film 122 is also formed on the side walls of the through holes 102a and on the surface where the support substrate 130 is exposed from the substrate 102. Since the first metal film 122 functions as a seed layer, its thickness can be selected from, for example, a range of 0.10 μm to 0.50 μm. After that, as shown in Figure 27, a resist mask 140 having an opening that exposes the through holes 102a is formed, and electroplating is performed. That is, the first metal film 122 is supplied with power in an electrolyte containing copper ions. As a result, a second metal film 124 containing or substantially made of copper is formed on the first metal film 122.

[0051] Subsequently, the resist mask 140 is removed, and the first metal film 122 and the second metal film 124 are formed by dry etching. Specifically, as shown in Figure 28, dry etching is performed on the first metal film 122 and the second metal film 124 until the inorganic insulating film 104 (or the substrate 102 if the inorganic insulating film 104 is not formed) is exposed. As a result, the thickness of the second metal film 124 is reduced, and the portion of the first metal film 122 that was exposed from the second metal film 124 can be removed. The remaining first metal film 122 and the second metal film 124 act as via metal 120. By forming via metal 120, contact between the first seed layer 112-1 and the support substrate 130 can be prevented.

[0052] The subsequent steps are the same as those described above. Briefly, a first seed layer 112-1 and a second seed layer 114-1 are formed to cover the via metal 120 and the inorganic insulating film 104, and a resist mask 132 having an opening in the region where the wiring 116 is to be formed is formed (Figure 29). In this state, power is supplied to the first seed layer 112-1 and the second seed layer 114-1 in an electrolyte containing copper ions, thereby forming the wiring 116-1 on the second seed layer 114-1 exposed from the resist mask 132. After that, the resist mask 132 is removed (Figure 30), and the wiring 116, the first seed layer 112-1, and the second seed layer 114-1 are wet-etched until the inorganic insulating film 104 (or the substrate 102 if the inorganic insulating film 104 is not formed) is exposed, thereby forming the first wiring layer 110-1 on the via metal 120 (Figure 31). The subsequent steps are the same as those described above, so the explanation is omitted.

[0053] As described above, in the manufacturing method of the wiring substrate 100 according to the embodiment of the present invention, the support substrate 130 is peeled off in a state where the first seed layer 112-1 of the first wiring layer 110-1, which is the bottommost wiring layer, does not come into contact with the support substrate 130, or in a state where the contact area with the support substrate 130 is smaller than that of the second seed layer 114-1. Furthermore, all or most of the portion of the first wiring layer 110-1 that comes into contact with the support substrate 130 becomes the second seed layer 114-1, which contains or is substantially made of copper. Therefore, when peeling off the support substrate 130, the contribution of the large adhesive force acting between titanium and the support substrate 130 can be reduced or substantially eliminated. As a result, due to the low adhesion between copper and the support substrate 130, the support substrate 130 can be easily peeled off without damaging the wiring layer 110 or the interlayer insulating film 106. Thus, by applying the embodiment of the present invention, it is possible to provide a wiring substrate at low cost.

[0054] Furthermore, in the wiring board 100, the inorganic insulating film 104 can be provided in contact with the substrate 102. Therefore, as described above, it is possible to prevent deformation of the wiring board 100 and the resulting damage to the wiring board 100 not only during manufacturing but also during use. This feature contributes to reducing the manufacturing cost of highly reliable wiring boards.

[0055] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on these embodiments, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0056] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention.

[0057] 100: Wiring board, 102: Substrate, 102a: Through hole, 102b: Bottom surface, 104: Inorganic insulating film, 105: Inorganic insulating film, 106: Interlayer insulating film, 106-1: First interlayer insulating film, 106-1a: Opening, 106-2: Second interlayer insulating film, 108: Protective film, 108a: Opening, 110: Wiring layer, 110-1: First wiring layer, 110-2: Second wiring layer, 110-3: Third wiring layer, 112: First seed layer, 112-1: First seed layer, 112-1a: Opening 112-2: First seed layer, 114: Second seed layer, 114-1: Second seed layer, 114-1a: Bottom surface, 114-2: Second seed layer, 116: Wiring, 116-1: Wiring, 116-2: Wiring, 116-3: Wiring, 120: Via metal, 122: First metal film, 124: Second metal film, 130: Support substrate, 132: Resist mask, 134: Resist mask, 136: Resist mask, 138: Resist mask, 140: Resist mask

Claims

1. A wiring substrate comprising a substrate containing a polymer and having through holes, and a plurality of wiring layers and a plurality of interlayer insulating films alternately laminated on the substrate, wherein the plurality of wiring layers are electrically connected to each other through a first opening provided in each of the plurality of interlayer insulating films, and each of the plurality of wiring layers has a first seed layer containing titanium, a second seed layer located on the first seed layer and containing copper, and wiring located on the second seed layer and containing copper, and the second seed layer in the lowest wiring layer of the plurality of wiring layers is exposed from the substrate through the through holes.

2. The wiring board according to claim 1, wherein the second seed layer of the lowest wiring layer covers the side wall of the through hole.

3. The wiring substrate according to claim 1, wherein the first seed layer of the lowest wiring layer has a second opening surrounding the through hole, and the substrate is exposed from the first seed layer of the lowest wiring layer at the second opening.

4. The wiring board according to claim 1, wherein the first seed layer of the lowest wiring layer is spaced apart from the side wall of the through hole.

5. The wiring board according to claim 1, wherein in the lowest wiring layer, the first seed layer covers the side wall of the through hole, and the second seed layer covers the side wall via the first seed layer.

6. The wiring board according to claim 1, wherein the second seed layer of the lowest wiring layer is surrounded by the first seed layer in the through hole.

7. The wiring board according to claim 1, wherein the second seed layer of the lowest wiring layer protrudes from the bottom surface of the substrate in the through hole.

8. The wiring board according to claim 1, further comprising via metal in contact with the side wall of the through hole, wherein the via metal is covered by the first seed layer of the lowest wiring layer.

9. The wiring substrate according to claim 1, further comprising an inorganic insulating film between the first seed layer of the bottommost wiring layer and the substrate, wherein the inorganic insulating film is exposed from the first seed layer of the bottommost wiring layer.

10. The wiring substrate according to claim 1, further comprising an inorganic insulating film beneath the substrate.

11. A method for manufacturing a wiring substrate, comprising: forming a substrate containing a polymer and having through holes on a support substrate; alternately laminating a plurality of wiring layers and a plurality of interlayer insulating films on the substrate; and peeling the substrate from the plurality of wiring layers and the plurality of interlayer insulating films, wherein the plurality of wiring layers are electrically connected to each other through a first opening provided in each of the plurality of interlayer insulating films; each of the plurality of wiring layers is formed by sequentially laminating a first seed layer containing titanium, a second seed layer containing copper, and wiring containing copper; and the second seed layer of the bottommost wiring layer among the plurality of wiring layers is formed to be exposed from the substrate through the through holes.

12. The manufacturing method according to claim 11, wherein the second seed layer of the lowest wiring layer is formed to cover the side wall of the through hole.

13. The manufacturing method according to claim 11, further comprising forming a second opening surrounding the through hole in the first seed layer before forming the second seed layer of the bottommost wiring layer, wherein the substrate is exposed from the first seed layer of the bottommost wiring layer at the second opening.

14. The manufacturing method according to claim 11, wherein the first seed layer of the lowest wiring layer is formed to be separated from the side wall of the through hole.

15. The manufacturing method according to claim 11, wherein the first seed layer of the bottommost wiring layer is formed to cover the side wall of the through hole, and the second seed layer of the bottommost wiring layer is formed to cover the side wall via the first seed layer of the bottommost wiring layer.

16. The manufacturing method according to claim 11, wherein the second seed layer of the lowest wiring layer is formed so as to be surrounded by the first seed layer in the through hole.

17. The manufacturing method according to claim 11, wherein the peeling of the substrate includes irradiating the substrate with laser light through the support substrate.

18. The manufacturing method according to claim 17, wherein the irradiation of the laser light is performed in such a way that a portion of the bottom surface of the substrate is disassembled, causing the second seed layer of the lowest wiring layer to protrude from the bottom surface of the substrate.

19. The manufacturing method according to claim 11, further comprising forming an inorganic insulating film on the substrate before forming the plurality of wiring layers and the plurality of interlayer insulating films, wherein the first seed layer of the bottommost wiring layer is formed such that the inorganic insulating film is exposed.

20. The manufacturing method according to claim 11, further comprising forming an inorganic insulating film on the support substrate before forming the substrate.

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