Storage device and method for assessing state of storage device

Abstract

Provided is a storage device comprising: a cell array unit that includes a plurality of memory cells arranged in a matrix; a reference unit that is provided within the cell array unit and that includes a first reference and a second reference; a sense amplifier that assesses the states of three of the memory cells by comparing the resistance values of the memory cells and the resistance value of the reference unit; and a switching unit that switches between connecting the first reference and the second reference as the reference unit to be connected to the sense amplifier.

Description

Memory device and method for determining state of memory device

[0001] The present disclosure relates to a memory device and a method for determining the state of a memory device.

[0002] A magnetoresistive random access memory (MRAM: Magnetoresistive Random Access Memory) using magnetoresistive elements is used as one of non-volatile memory devices in which the magnetization state of a ferromagnetic material inside the magnetoresistive element is maintained, so that the recorded data is retained even when the power is turned off. Further, the MRAM can also be used as a one-time programmable (OTP) memory device that can be written only once.

[0003] Japanese Patent Application Laid-Open No. 2009-16840, Japanese Patent Application Laid-Open No. 2009-211792

[0004] In a conventional memory device, although a detection circuit for detecting the resistance state of the magnetoresistive element of a memory cell is provided, for example, a circuit for detecting a failure of the memory cell is not provided. Therefore, although it has been considered to provide a circuit for detecting such a failure in the memory device, since it is necessary to provide a plurality of reference voltage generators and the like, the circuit scale has become large.

[0005] Therefore, the present disclosure proposes a memory device and a method for determining the state of a memory device that can detect three states of a memory cell without increasing the circuit scale.

[0006] According to the present disclosure, there is provided a memory device including a cell array unit including a plurality of memory cells arranged in a matrix, a reference unit provided in the cell array unit and including a first reference and a second reference, and a sense amplifier that determines three states of the memory cell by comparing a resistance value of the memory cell and a resistance value of the reference unit, and a switching unit that switches connections of the first reference and the second reference as the reference unit connected to the sense amplifier.

[0007] Furthermore, the present disclosure provides a method for determining the state of a storage device comprising a cell array portion including a plurality of memory cells arranged in a matrix, and a reference portion provided within the cell array portion including a first reference and a second reference, the method for determining the state of a storage device comprising switching the connection of the first reference and the second reference as the reference portion connected to a sense amplifier, and determining three states of the memory cells by comparing the resistance value of the memory cells with the resistance value of the reference portion using the sense amplifier.

[0008] This is a diagram showing an example configuration of the storage device 10 according to an embodiment of this disclosure. This is a diagram showing an example configuration of the memory cell 202 according to an embodiment of this disclosure. This is a diagram showing an example configuration of the main part of the storage device 10a according to a comparative example. This is an explanatory diagram for explaining the background of the embodiments of this disclosure. This is a diagram showing an example configuration of the main part of the storage device 10 according to the first embodiment of this disclosure. This is an explanatory diagram for explaining the operation of the first embodiment of this disclosure. This is a diagram (1) showing an example configuration of the main part of the storage device 10 according to the second embodiment of this disclosure. This is a diagram (2) showing an example configuration of the main part of the storage device 10 according to the second embodiment of this disclosure. This is a diagram (1) showing an example configuration of the main part of the storage device 10 according to a modified example of the second embodiment of this disclosure. This is a diagram (2) showing an example configuration of the main part of the storage device 10 according to a modified example of the second embodiment of this disclosure. This is a diagram showing an example configuration of the main part of the storage device 10 according to the third embodiment of this disclosure. This is a flowchart showing an example operation of the storage device 10 according to the fourth embodiment of this disclosure. This is a diagram showing an application example using the storage device 10 according to an embodiment of this disclosure.

[0009] Preferred embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configuration will be denoted by the same reference numeral to avoid redundant explanation. In addition, in this specification and drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding a different alphabet after the same reference numeral. However, if there is no particular need to distinguish each of multiple components having substantially the same or similar functional configurations, only the same reference numeral will be used.

[0010] Furthermore, in the following descriptions of circuits (electrical connections), unless otherwise specified, "electrically connected" or "connected" means connecting multiple elements so that electricity (signals) can conduct through them. In addition, "electrically connected" or "connected" in the following descriptions includes not only cases where multiple elements are directly and electrically connected, but also cases where they are indirectly and electrically connected through other elements.

[0011] In the embodiments described below, the case of application to an MRAM having a magnetoresistive element will be explained as an example, but the embodiments of the disclosure are not limited to application to an MRAM and can be applied to any memory device having a resistive switching element.

[0012] The explanation will proceed in the following order: 1. Example of a storage device configuration 2. Background 3. First embodiment 4. Second embodiment 5. Third embodiment 6. Fourth embodiment 7. Summary 8. Application examples 9. Supplementary information

[0013] <<1. Example of Storage Device Configuration>> First, an example of the configuration of the storage device 10 according to the embodiment of this disclosure will be described with reference to Figure 1. Figure 1 is a diagram showing an example of the configuration of the storage device 10 according to the embodiment of this disclosure.

[0014] The memory device 10 shown in Figure 1 is an example of a memory device that holds data according to the magnetization direction of a magnetic material, and has a memory cell array 200. The memory cell array 200 includes a plurality of memory cells 202 arranged in two dimensions. These memory cells 202 are each connected to a bit line BL, a source line SL, and a word line WL. For example, the plurality of word lines WL each extend along the left-right direction (row direction) in Figure 1, and the plurality of bit lines BL and the plurality of source lines SL each extend along the up-down direction (column direction) in Figure 1. These bit lines BL, source lines SL, and word lines WL each function as control lines.

[0015] Each memory cell 202 has a magnetoresistive element 11 and a selection element 12, as described later. As the magnetoresistive element 11, for example, a magnetoresistive element such as an MTJ (Magnetic Tunnel Junction) can be used. The selection element 12 is connected to one end of the magnetoresistive element 11 and is an element that controls the application of voltage, current, etc. to the magnetoresistive element 11. As the selection element 12, for example, various transistors can be used.

[0016] In addition to the memory cell array section 200, the storage device 10 includes an I / O (Input / Output) 21, a control circuit (writing section) 22, an address decoder 26, multiple bit line control circuits 27A, 27B, multiple source line control circuits 28A, 28B, a word line address decoder 29, multiple word line control circuits 30A, 30B, a sense amplifier circuit 31, and a reference cell array section 100.

[0017] In Figure 1, the memory cell array 200 and the reference cell array 100 are arranged so as to sandwich the sense amplifier circuit 31, etc. Bit line control circuits 27A, 27B, source line control circuits 28A, 28B, and word line control circuits 30A, 30B are provided to correspond to the memory cell array 200 and the reference cell array 100. In this embodiment of the disclosure, the memory cell array 200 and the reference cell array 100 are not limited to being arranged so as to sandwich the sense amplifier circuit 31, etc., but may be provided in close proximity to each other.

[0018] I / O 21 enables the exchange of commands related to reading and writing data, addresses of memory cells 202 and other data to be accessed, and data itself between the external circuitry of the storage device 10 (for example, the Central Processing Unit (CPU)) and the control circuit 22 of the storage device 10.

[0019] The control circuit 22 controls the writing and reading of data to the memory cell 202 in response to commands. Furthermore, in embodiments of this disclosure, the control circuit 22 controls the reference cell array 100 to obtain a reference resistor having various values ​​used for reading data from the memory cell 202. Specifically, the control circuit 22 can select a reference cell 102 from among a plurality of reference cells 102 in the reference cell array 100 to be referenced for reading the reference resistance value.

[0020] The address decoder 26 can obtain column addresses such as bit line BL and source line SL corresponding to the address received by the I / O 21 described above. The address decoder 26 has a column switch selection circuit 32. The column switch selection circuit 32 controls the bit line control circuits 27A, 27B and the source line control circuits 28A, 28B.

[0021] Each bit line control circuit 27A and 27B is connected to each bit line BL. These bit line control circuits 27A and 27B each select and control the bit line BL corresponding to the address of the address decoder 26.

[0022] Each source line control circuit 28A and 28B is connected to each source line SL. These source line control circuits 28A and 28B each select and control the source line SL corresponding to the address of the address decoder 26.

[0023] The word line address decoder 29 can obtain the address of the word line WL corresponding to the address received by the I / O 21 described above.

[0024] Each word line control circuit 30A and 30B is connected to each word line WL. These word line control circuits 30A and 30B each select and control the word line WL corresponding to the address of the word line address decoder 29.

[0025] The sense amplifier circuit 31 is connected to the source line SL via the respective source line control circuits 28A and 28B. This sense amplifier circuit 31 can detect data read from the memory cell 202, specifically the resistance value of the magnetoresistive element 11.

[0026] In detail, the sense amplifier circuit 31 has a plurality of sense amplifiers 300 (see Figure 3). Each sense amplifier 300 can be, for example, a sense amplifier that uses a reference voltage (reference current). Furthermore, each sense amplifier 300 is provided such that it bundles a predetermined number of columns consisting of a plurality of memory cells 202.

[0027] When reading data from each memory cell 202, the sense amplifier 300 detects the resistance state of the memory cell 202 (for example, a low resistance state or a high resistance state) based on the reference resistance value, which is the combined resistance value of each reference cell 102 in the reference cell array unit 100 described later. For example, the sense amplifier 300 refers to the reference voltage (reference current) based on the reference resistance value, compares the reference voltage with the voltage of the memory cell 202, and detects the resistance state of the memory cell 202 based on the comparison result. The sense amplifier 300 outputs data (for example, 0 or 1) corresponding to the read resistance state, i.e., a read voltage corresponding to the read data.

[0028] The reference cell array section 100, like the memory cell array section 200, includes a plurality of reference cells 102 arranged in a two-dimensional manner. These reference cells 102 are each connected to a bit line BL, a source line SL, and a word line WL. For example, the plurality of word lines WL each extend along the left-right direction (row direction) in Figure 1, and the plurality of bit lines BL and the plurality of source lines SL each extend along the up-down direction (column direction) in Figure 1. These bit lines BL, source lines SL, and word lines WL each function as control lines.

[0029] Each reference cell 102, like the memory cell 202, has a magnetoresistive element 11 and a selection element 12. For example, a magnetoresistive element such as an MTJ can be used as the magnetoresistive element 11. The selection element 12 is connected to one end of the magnetoresistive element 11 and controls the application of voltage, current, etc., to the magnetoresistive element 11. For example, various transistors can be used as the selection element 12.

[0030] Next, with reference to Figure 2, an example configuration of the memory cell 202 according to the present disclosure will be described. Figure 2 is a diagram showing an example configuration of the memory cell 202 according to the present disclosure.

[0031] As shown in Figure 2, the memory cell 202 has a magnetoresistive element 11 and a selection element 12. The magnetoresistive element 11 and the selection element 12 are connected in series between the bit line BL and the source line SL.

[0032] The magnetoresistive element 11 has a sandwich structure in which a non-magnetic insulating film (tunnel barrier film) is sandwiched between two magnetic layers (a fixed layer and a recording layer) made of a magnetic material film. This structure is called a magnetic tunnel junction (MTJ). Because the thickness of the insulating film is very thin, about a few nanometers, a tunnel current flows when a voltage is applied across both ends of the element. The magnitude of this tunnel current has the characteristic of depending on the relative angle of magnetization of the two magnetic layers, and this is called the tunnel magnetoresistance (TMR) effect. Furthermore, the magnetoresistive element 11 has an upper electrode and a lower electrode that sandwich the sandwich structure from above and below.

[0033] In MRAM, the magnetization of one of the two magnetic layers (the stationary layer) is fixed, while the magnetization direction of the other magnetic layer (the recording layer) is controlled. For example, methods for controlling the direction of magnetization include using spin transfer torque (STT), which involves directly applying current to the MTJ, and using voltage-based magnetic anisotropy control (VCMA).

[0034] By switching the resistance state (resistance value) of such a magnetoresistive element 11 between a low-resistance state (low resistance value) and a high-resistance state (high resistance value), data (for example, 0 or 1) is written to the memory cell 202. The low-resistance state is a state in which the magnetizations of the fixed layer and the recording layer are parallel to each other, and the high-resistance state is a state in which the magnetizations of the fixed layer and the recording layer are antiparallel.

[0035] Furthermore, the selection element 12 is, for example, a field-effect transistor (FET). One of the drain and source terminals of the selection element 12 is connected to the magnetoresistive element 11. The other of the drain and source terminals of the selection element 12 is connected to the source line SL. The gate terminal of the selection element 12 is connected to the word line WL. When a voltage signal from the word line WL is applied to the gate of the selection element 12, the selection element 12 turns on (the drain and source become conductive), connecting the magnetoresistive element 11 to the bit line BL and the source line SL, and applying voltage, current, etc. to the magnetoresistive element 11.

[0036] Furthermore, in the embodiments of this disclosure, the reference cell 102 of the reference cell array 100 also has a configuration similar to, for example, the memory cell 202 shown in Figure 2.

[0037] <<2. Background>> Next, with reference to Figures 3 and 4, the background to the present inventors' creation of the embodiments of this disclosure will be explained. Figure 3 is an example of the configuration of the main part of a comparative example of a storage device 10a, and in Figure 3, the bit line BL connected to the magnetoresistive element 11 is not shown. Figure 4 is an explanatory diagram for explaining the background of the embodiments of this disclosure. Here, the comparative example refers to a storage device 10a that the present inventors had been studying before creating the embodiments of this disclosure.

[0038] As explained earlier, MRAM using a magnetoresistive element 11 can be used as a non-volatile memory device that retains recorded data even when the power is turned off, because the magnetization state of the ferromagnetic material inside the magnetoresistive element 11 is maintained. Furthermore, as a non-volatile memory device, MRAM can also be used as an OTP memory device that can only be written to once by destroying (cutting) the memory cell 202 as a fuse, thereby creating a short-circuit or open state. Specifically, for example, by applying a first voltage to destroy only the non-magnetic film (tunnel barrier film) of the magnetoresistive element 11, the memory cell 202 can be put into a short-circuit state. Alternatively, for example, by applying a second voltage greater than the first voltage to destroy the upper and lower electrodes of the magnetoresistive element 11, the memory cell 202 can be put into an open state.

[0039] In the following explanation, if a memory cell 202 is destroyed and written to as an OTP memory element (fuse), the state of the memory cell 202 will be referred to as the "disconnected state." In other words, in the following explanation, the state of the memory cell 202 that has been written to as an OTP element will be referred to as the "disconnected state," regardless of whether it is in a short-circuited or open state.

[0040] Here, we assume that the memory cell 202 is used as an OTP memory element by being in an open state (disconnected state). In this assumption, for example, if the memory cell 202 in question is already short-circuited due to a manufacturing defect, it is not possible to apply voltage to open the memory cell 202, and therefore the memory cell 202 cannot be used as an OTP memory element (it cannot be written to as an OTP memory element). In other words, the memory cell 202 is a faulty element that does not function as an OTP memory element, and if such an element is included, the storage device 10 is considered faulty or defective.

[0041] Therefore, in the sorting test before shipment of the memory device 10, it is required to detect such a failure (product defect) and exclude the memory device 10 determined to be defective or perform some treatment. However, the OTP memory device 10a according to the comparative example did not have a function of detecting such a failure.

[0042] Specifically, as shown in FIG. 3, the memory device 10a according to the comparative example includes a sense amplifier 300, a reference cell array unit 100 electrically connected to the sense amplifier 300, and a memory cell array unit 200. In the comparative example, the sense amplifier 300 compares the resistance value (potential) of the target memory cell 202 with the reference resistance value (reference potential) of the reference cell 102 in the reference cell array unit 100. Then, in the comparative example, as shown in the upper part of FIG. 4, based on the comparison result of the resistance values, it is possible to detect (determine) whether the memory cell 202 is in a cut state (open state), an uncut state (non-open state) (L: low resistance state, H: high resistance state). However, in the comparative example, as shown in the upper part of FIG. 4, although it is possible to detect whether the memory cell 202 is in a cut state or an uncut state, it was not possible to detect the failure state. In other words, in the comparative example, although the cut state and the uncut state could be distinguished, the failure state could not be distinguished.

[0043] Therefore, it was considered to provide a dedicated circuit for detecting the failure state in the memory device 10a. When a dedicated circuit for detecting the failure state is provided, it is necessary to provide a plurality of reference voltage generators and a plurality of comparators in the memory device 10a. Therefore, it is inevitable that the circuit scale of the memory device 10a increases, leading to an increase in the manufacturing cost and power consumption of the memory device 10.

[0044] Therefore, in view of such a situation, the inventors of the present invention have created the embodiment of the present disclosure described below.

[0045] In an embodiment of the present disclosure, it is possible to detect three states (for example, a cut-off state, an uncut state, and a failure state) of the memory cell 202 without increasing the circuit scale of the memory device 10. Specifically, in an embodiment of the present disclosure, two different cell array regions are provided in the reference cell array unit 100, and the cell array region connected to the sense amplifier 300 is switched. By doing so, according to an embodiment of the present disclosure, for example, as shown in the lower part of FIG. 4, it is possible to detect (determine) whether the memory cell 202 is in any of the cut-off state, the uncut state, and the failure state. And, according to an embodiment of the present disclosure, three states of the memory cell 202 can be detected by adding a minimum mechanism, so the circuit scale is not increased. Further, by using such a memory device 10, in the sorting test before shipment of the memory device 10, it is possible to detect a failure (product defect), and exclude the memory device 10 determined to be a failure, or perform some treatment.

[0046] Hereinafter, the details of the embodiments of the present disclosure created by the present inventors will be sequentially described.

[0047] <<3. First Embodiment>> First, referring to FIGS. 5 and 6, the details of the first embodiment of the present disclosure will be described. FIG. 5 is a diagram showing a configuration example of a main part of the memory device 10 according to the present embodiment. In FIG. 5, the illustration of the bit line BL connected to the magnetoresistive element 11 is omitted. Further, FIG. 6 is an explanatory diagram for explaining the operation of the present embodiment.

[0048] The memory device 10 according to the present embodiment is, for example, an MRAM used as an OTP memory device. As shown in FIG. 5, the memory device 10 according to the present embodiment has a reference cell array unit 100 and a memory cell array unit 200. Further, in the reference cell array unit (reference unit) 100, a cell array region (first reference) 110 and a cell array region (second reference) 120 are provided.

[0049] Furthermore, the storage device 10 has a plurality of sense amplifiers 300. Each sense amplifier 300 can be connected to each memory cell 202 in the memory cell array section 200 and to one or more reference cells 102 in the cell array areas 110 and 120 of the reference cell array section 100 by a switch, which will be described later. The sense amplifier 300 can then be connected to the memory cell 202 and the reference cells 102 in the cell array areas 110 and 120 by switching the connection with the switch, and can detect the state of the memory cell 202.

[0050] In this embodiment, as shown in Figure 5, the cell array regions 110 and 120 are composed of a plurality of reference columns. Each of the plurality of reference columns has a plurality of reference cells 102 that constitute the column, a source line SL connected to one terminal of the plurality of reference cells 102, and a bit line BL (not shown) connected to the other terminal of the plurality of reference cells 102. Furthermore, each reference column has a column header switch 126 that connects the source line SL to the sense amplifier 300, and a column footer switch (not shown) connected to the bit line BL. The column header switch 126 and the column footer switch can be made of, for example, FETs. In the reference cell array section 100, a plurality of reference cells 102 located in the same row are connected to the same word line WL. Furthermore, in the reference cell array section 100, for example, the word line WL, the source line SL, and the bit line BL are arranged in a grid, and the plurality of reference cells 102 are arranged in a matrix. Each reference cell 102 is located at the intersection of the word line WL, the source line SL, and the bit line BL.

[0051] Furthermore, each reference cell 102 has a configuration similar to that of the memory cell 202 shown in Figure 2. In detail, the reference cell 102 has a magnetoresistive element 11 and a selection element 12 made of an FET or the like. The magnetoresistive element 11 and the selection element 12 are connected in series between the bit line BL and the source line SL. In this embodiment, at least a portion of the reference cell 102 may have a resistive element instead of the magnetoresistive element 11, or it may have another resistance change element.

[0052] Furthermore, in this embodiment, for example, the resistance value of a reference cell 102 in the cell array region 110 (or the combined resistance value of multiple reference cells 102) is different from the resistance value of a reference cell 102 in the cell array region 120 (or the combined resistance value of multiple reference cells 102). Moreover, in this embodiment, for example, the resistance value of a reference cell 102 in the cell array region 110 (or the combined resistance value of multiple reference cells 102) and the resistance value of a reference cell 102 in the cell array region 120 (or the combined resistance value of multiple reference cells 102) are different from the resistance value of a memory cell 202 in an undisconnected state (low resistance state, high resistance state).

[0053] Furthermore, as shown in Figure 5, the memory cell array 200 is composed of multiple memory columns. Each of the multiple memory columns has multiple memory cells 202 constituting the column, a source line SL connected to one terminal of the multiple memory cells 202, and a bit line BL (not shown) connected to the other terminal of the multiple memory cells 202. In addition, each memory column has a column header switch 126 that connects the source line SL to the sense amplifier 300, and a column footer switch (not shown) connected to the opposite side of the source line SL from the column header switch 126. The column header switch 126 and the column footer switch can be made of, for example, FETs. Also, in the memory cell array 200, multiple memory cells 202 located in the same row are connected to the same word line WL. In the memory cell array 200, for example, the word line WL, the source line SL, and the bit line BL are arranged in a grid, and the multiple memory cells 202 are arranged in a matrix. Each memory cell 202 is located at the intersection of the word line WL, the source line SL, and the bit line BL.

[0054] Furthermore, the storage device 10 according to this embodiment may have, for example, a redundant circuit (redundant circuit section) (not shown) including a cell configured similarly to the memory cell 202. This redundant circuit can be used, for example, as a replacement for a memory cell 202 that has been determined to be faulty.

[0055] In this embodiment, the control circuit (switching unit) 22 described above can switch the memory cell 202 and reference cell 102 connected to the sense amplifier 300 according to address information that specifies the memory cell 202 and reference cell 102 connected to the sense amplifier 300. In this embodiment, for example, when selecting a target memory cell 202, the column address is specified, which turns on the switch connected to the source line SL corresponding to the memory cell 202, thereby connecting the memory cell 202 to the sense amplifier 300.

[0056] Furthermore, in this embodiment, when detecting whether the memory cell 202 is in a disconnected or undisconnected state, a column address is specified, which turns on a switch connected to the source line SL corresponding to the reference cell 102 in the cell array area 110, thereby connecting the reference cell 102 to the sense amplifier 300. The sense amplifier 300 then compares the resistance value (potential) of the target memory cell 202 with the reference resistance value (reference potential) of the reference cell 102 in the cell array area 110. The storage device 10 can then detect (determine) whether the memory cell 202 is in a disconnected or undisconnected state based on the results of the resistance value comparison.

[0057] Furthermore, in this embodiment, when detecting whether the memory cell 202 is in a faulty state, the sense amplifier 300 can be connected to the reference cell 102 by specifying a column address and turning on a switch connected to the source line SL corresponding to the reference cell 102 in the cell array area 120. In addition, the sense amplifier 300 compares the resistance value (potential) of the target memory cell 202 with the reference resistance value (reference potential) of the reference cell 102 in the cell array area 120. The storage device 10 can then detect (determine) whether the memory cell 202 is in a faulty state based on the results of the resistance value comparison.

[0058] In this embodiment, when detecting whether the memory cell 202 is in a disconnected state or an undisconnected state, or when detecting whether the memory cell 202 is in a faulty state, the sense amplifier 300 may compare the resistance value of the memory cell 202 with the combined resistance value of the reference cell 102 in the cell array region 110 and the reference cell 102 in the cell array region 120.

[0059] Here, for example, when writing to an OTP memory element, we assume that the memory cell 202 is set to an open state (disconnected state), and the failure state of the memory cell 202 is set to a short state. In this case, the resistance value of the reference cell 102 in the cell array area 110 (or the combined resistance value of multiple reference cells 102) is set higher than the resistance value of the reference cell 102 in the cell array area 120 (or the combined resistance value of multiple reference cells 102). Specifically, the value of the reference resistance consisting of one or more reference cells 102 in the cell array area 110 is set to a value between the resistance value of the memory cell 202 in an open state (disconnected state) and the resistance value of the memory cell 202 in an open state (not disconnected state). Also, the value of the reference resistance consisting of one or more reference cells 102 in the cell array area 120 is set to a value between the resistance value of the memory cell 202 in a short state (failed state) and the resistance value of the memory cell 202 in an open state (not disconnected state). In such cases, as shown in the lower left section of Figure 6, it is possible to detect (determine) whether the memory cell 202 is in a disconnected state (open state), an undisconnected state (non-open state), or a faulty state (short circuit state) based on the results of the resistance value comparison.

[0060] Furthermore, in this embodiment, for example, when writing as an OTP memory element, the memory cell 202 may be set to a short-circuit state (disconnected state), and the fault state of the memory cell 202 may be set to an open state. In this case, the resistance value of the reference cell 102 in the cell array area 110 (or the combined resistance value of multiple reference cells 102) is set lower than the resistance value of the reference cell 102 in the cell array area 120 (or the combined resistance value of multiple reference cells 102). Specifically, the value of the reference resistance consisting of one or more reference cells 102 in the cell array area 110 is set to a value between the resistance value of the memory cell 202 in a short-circuit state (disconnected state) and the resistance value of the memory cell 202 in a non-short-circuit state (undisconnected state). Also, the value of the reference resistance consisting of one or more reference cells 102 in the cell array area 120 is set to a value between the resistance value of the memory cell 202 in an open state (failed state) and the resistance value of the memory cell 202 in a non-short-circuit state (undisconnected state). In such cases, as shown in the lower right section of Figure 6, it is possible to detect (determine) whether the memory cell 202 is in a disconnected state (short circuit), an unconnected state (non-short circuit), or a faulty state (open circuit), based on the results of the resistance value comparison.

[0061] In this embodiment, if a memory cell 202 is detected to be in a faulty state, the memory cell 202 may be removed from the array of elements used as a defective element, or it may be replaced by a redundant circuit provided in the storage device 10. Furthermore, in this embodiment, if a memory cell 202 is detected to be in a faulty state, the storage device 10 including the memory cell 202 may be removed from the shipment as a defective product.

[0062] As described above, in this embodiment, two cell array regions 110 and 120 are provided within the reference cell array section 100, and by switching between the cell array regions 110 and 120 connected to the sense amplifier 300, it is possible to detect whether the memory cell 202 is in a disconnected state, an undisconnected state, or a faulty state. Furthermore, in this embodiment, the sense amplifier 300 used to detect the disconnected state and the undisconnected state can also detect the faulty state. Therefore, according to this embodiment, the three states of the memory cell 202 can be detected without increasing the circuit size. Moreover, by using such a storage device 10, it is possible to detect faults (product defects) in the pre-shipment sorting test of the storage device 10, and to exclude the storage device 10 determined to be faulty, or to take some kind of action.

[0063] In this embodiment, the storage device 10 is not limited to the form shown in Figure 5, but can be transformed into various forms.

[0064] Furthermore, although this embodiment describes detecting three states of the memory cell 202: disconnected, not disconnected, and faulty, it is not limited to these three states. For example, three or more values ​​stored in the memory cell 202 may be detected as states.

[0065] <<4. Second Embodiment>> Next, the details of the second embodiment and modifications of the present disclosure will be described with reference to Figures 7A, 7B and 8A, 8B. Figures 7A and 7B are diagrams showing an example of the configuration of the main part of the storage device 10 according to this embodiment, and Figures 8A and 8B are diagrams showing an example of the configuration of the main part of the storage device 10 according to a modification of this embodiment. Note that in Figures 7A, 7B and 8A, 8B, the bit line BL connected to the magnetoresistive element 11 is not shown.

[0066] In this embodiment, variations in the connection of the reference cell 102 will be described.

[0067] In this embodiment, when detecting whether the memory cell 202 is in a disconnected state, an undisconnected state, or a faulty state, the control circuit (switching unit) 22 can switch the cell array region to which the sense amplifier 300 is connected according to the column address information. Specifically, as shown in Figures 7A and 7B, the reference cell 102 in the cell array region 110 and the reference cell 102 in the cell array region 120 are connected to different columns, i.e., different source lines SL. In this embodiment, by specifying the column address, the switch connected to the source line SL corresponding to the reference cell 102 in the cell array region 110 or the reference cell 102 in the cell array region 120 is turned on, and the reference cell 102 in the cell array region 110 or the reference cell 102 in the cell array region 120 can be connected to the sense amplifier 300. Therefore, in this embodiment, by switching in this way, the same sense amplifier 300 can not only detect whether the memory cell 202 is in a disconnected state or an undisconnected state, but also detect a faulty state. In Figures 7A and 7B, switches that are turned on are indicated by thick lines.

[0068] Furthermore, in a modified version of this embodiment, when detecting whether the memory cell 202 is in a disconnected state, an undisconnected state, or a faulty state, the control circuit (switching unit) 22 can switch the cell array region to which the sense amplifier 300 is connected according to the low address information. Specifically, as shown in Figures 8A and 8B, the reference cell 102 in cell array region 110 and the reference cell 102 in cell array region 120 are connected to different rows, i.e., different word lines WL. Specifically, in Figures 8A and 8B, the reference cell 102 in cell array region 110 is connected to word line RWL 10, and the reference cell 102 in cell array region 120 is connected to word line RWL 11. In this modified version, by specifying a low address, the reference cell 102 in cell array region 110 or the reference cell 102 in cell array region 120, which are connected to different word lines WL, can be connected to the sense amplifier 300. Therefore, in this modified example, by switching in this manner, the same sense amplifier 300 can not only detect whether the memory cell 202 is in a disconnected state or an undisconnected state, but also detect a fault condition. In Figures 8A and 8B, the selected word line WL is shown with a thick line.

[0069] <<5. Third Embodiment>> Next, the details of the third embodiment of the present disclosure will be described with reference to Figure 9. Figure 9 is an example of the configuration of the main part of the storage device 10 according to this embodiment. More specifically, the upper left section of Figure 9 shows an explanatory diagram illustrating the detection (determination) method, and the lower left section of Figure 9 shows an example of the configuration of the main part of the storage device 10. Furthermore, the right side of Figure 9 shows an example of the configuration of the reference cell 102 in the cell array area 110 and the reference cell 102 in the cell array area 120.

[0070] In this embodiment, variations in the configuration of the reference cell 102 will be described. Here, as shown in the upper left of Figure 9, for example, when writing as an OTP memory element, the memory cell 202 is set to an open state (disconnected state), and the fault state of the memory cell 202 is set to a short state.

[0071] In this embodiment, at least one of the multiple reference cells 102 in the cell array region 110 used to detect whether the memory cell 202 is in a disconnected state or an undisconnected state may be an open cell. As shown in the upper right panel of Figure 9, such an open cell is, for example, a cell that includes a disconnected section instead of a magnetoresistive element 11. More specifically, in this embodiment, the multiple reference cells 102 in the cell array region 110 may be, for example, a combination of one or more open cells and one or more normal cells (consisting of a magnetoresistive element 11 and a selection element 12 in series), as shown in the upper right panel of Figure 9. In this way, in this embodiment, the reference resistance of the cell array region 110 can be obtained to be a resistance value between the resistance value of the memory cell 202 in an open state (disconnected state) and the resistance value of the memory cell 202 in an undisconnected state.

[0072] Furthermore, in this embodiment, at least one of the multiple reference cells 102 in the cell array region 120 used to detect whether the memory cell 202 is in a faulty state may be a short cell. As shown in the lower right section of Figure 9, such a short cell is, for example, a cell that includes a short circuit instead of a magnetoresistive element 11. More specifically, in this embodiment, the multiple reference cells 102 in the cell array region 120 may be, for example, a combination of one or more short cells and one or more normal cells (consisting of a series connection between a magnetoresistive element 11 and a selection element 12), as shown in the lower right section of Figure 9. In this way, in this embodiment, the reference resistance of the cell array region 120 can be obtained to be between the resistance value of a memory cell 202 in a short-circuit state (faulty state) and the resistance value of a memory cell 202 in an open state (unconnected state).

[0073] Furthermore, this embodiment can also be applied, for example, when writing to the memory cell 202 as an OTP memory element, the memory cell 202 is set to a short state (disconnected state), and the fault state of the memory cell 202 is set to an open state. In this case, at least one of the multiple reference cells 102 in the cell array area 110 used to detect whether the memory cell 202 is in a disconnected state or an open state may be a short cell. Furthermore, at least one of the multiple reference cells 102 in the cell array area 120 used to detect whether the memory cell 202 is in a fault state may be an open cell.

[0074] In this embodiment, the storage device 10 is not limited to the form shown in Figure 9, but can be transformed into various forms.

[0075] <<6. Fourth Embodiment>> Next, with reference to Figure 10, the details of the fourth embodiment of the present disclosure will be described. Figure 10 is a flowchart showing an example of the operation of the storage device 10 according to this embodiment. In this embodiment, an example of a determination method for determining whether the memory cell 202 is in a disconnected state, an open state, or a faulty state will be described. Here, for example, when writing as an OTP storage element, the memory cell 202 is set to an open state (disconnected state), and the faulty state of the memory cell 202 is set to a short state.

[0076] More specifically, as shown in Figure 10, the detection method according to this embodiment includes a plurality of steps from step S101 to step S111. Each step of the determination method according to this embodiment will be described below.

[0077] First, it is determined whether the target memory cell 202 is in a faulty state (second state). Specifically, the storage device 10 selects a reference cell 102 in the cell array area 120 as a fault determination reference and connects the selected reference cell 102 to the sense amplifier 300. Furthermore, the sense amplifier 300 reads the resistance values ​​(specifically the potential) of the target memory cell 202 and the selected reference cell 102 (step S101). The sense amplifier 300 then compares the read resistance values ​​(step S102), and if the resistance value of the target memory cell 202 is lower than the resistance value of the selected reference cell 102, it determines that there is a "fault" (step S102: Yes) and proceeds to step S103. On the other hand, the sense amplifier 300 compares the read resistance values ​​(step S102), and if the resistance value of the target memory cell 202 is higher than the resistance value of the selected reference cell 102, it determines that there is "no fault" (step S102: No) and proceeds to step S104.

[0078] Next, if it is determined that there is a "malfunction," it is determined whether the memory cell 202 in question can be salvaged (step S103). If it is determined that it cannot be salvaged (step S103: Yes), the process proceeds to step S111. On the other hand, if it is determined that it can be salvaged (step S103: No), the process proceeds to step S104.

[0079] Next, it is determined whether the target memory cell 202 is in an "abnormal" state (first state). Specifically, the storage device 10 selects a reference cell 102 in the cell array area 110 as a normal operation reference and connects the selected reference cell 102 to the sense amplifier 300. Furthermore, the sense amplifier 300 reads the resistance values ​​(specifically the potential) of the target memory cell 202 and the selected reference cell 102 (step S104). The sense amplifier 300 then compares the read resistance values ​​(step S105), and if the resistance value of the target memory cell 202 is higher than the resistance value of the selected reference cell 102, it determines that there is an "abnormality" (disconnected state or fault state) (step S105: Yes), and proceeds to step S106. On the other hand, the sense amplifier 300 compares the read resistance values ​​(step S105) and, if the resistance value of the target memory cell 202 is lower than the resistance value of the selected reference cell 102, it determines that there is "no abnormality (normal)" (not disconnected) (step S105: No), and proceeds to step S107.

[0080] Next, if it is determined that there is an "abnormality" (disconnection or failure), it is determined whether the memory cell 202 in question can be recovered (step S106). If it is determined that it cannot be recovered (step S106: Yes), the process proceeds to step S111. On the other hand, if it is determined that it can be recovered (step S106: No), the process proceeds to step S107.

[0081] Next, it is determined whether the target memory cell 202 requires rescue (step S107). If rescue is deemed necessary (step S107: Yes), the process proceeds to step S108. On the other hand, if rescue is deemed unnecessary (step S107: No), the process proceeds to step S109.

[0082] Memory cells 202 that are determined to require rescue are rescued by being replaced by the redundant circuit described above (step S108), and the process proceeds to step S109. The target memory cells 202 are then determined to be good products that can be shipped (step S109), and are written to as OTP memory elements (step S110). Alternatively, the target memory cells 202 are determined to be defective products that cannot be shipped (step S111).

[0083] Furthermore, steps S101 to S111 are repeated for all memory cells 202.

[0084] Furthermore, the steps in the determination method according to this embodiment described above do not necessarily have to be processed in the order described. For example, the order of the steps may be changed as appropriate. Also, instead of being processed chronologically, the steps may be processed partially in parallel or individually. Moreover, the processing of each step does not necessarily have to follow the method described, and may also be processed by other functional units or by other methods.

[0085] <<7. Summary>> As described above, in each embodiment of this disclosure, the three states of the memory cell 202 can be detected (determined) without increasing the circuit size. Furthermore, by using such a storage device 10, it is possible to detect a failure (product defect) in the pre-shipment sorting test of the storage device 10, and to exclude the storage device 10 determined to be faulty, or to take some kind of action.

[0086] In the embodiments of this disclosure described above, the case of application to an MRAM having a magnetoresistive element 11 was explained as an example, but the embodiments of this disclosure are not limited to application to an MRAM, and can be applied to any storage device 10 having a resistive switching element. Furthermore, in the embodiments of this disclosure, when the memory cell 202 is written as an OTP storage element, the memory cell 202 may be in a low-resistance state including a short-circuit state, or in a high-resistance state including an open state.

[0087] Furthermore, although the embodiments of the present disclosure described above have been described as detecting three states of the memory cell 202: disconnected, not disconnected, and faulty, the embodiments of the present disclosure are not limited to detecting such three states. In the embodiments of the present disclosure, for example, three or more values ​​stored in the memory cell 202 may be detected as three states.

[0088] <<8. Application Examples>> Application examples of the storage device 10 according to each embodiment of the present disclosure described above will be explained with reference to Figure 11. Figure 11 is a diagram showing an application example using the storage device 10 according to the embodiment of the present disclosure.

[0089] The storage devices 10 according to each embodiment of the present disclosure described above can be implemented in various electronic devices that can be equipped with memory (storage unit), for example, as shown in Figure 11. For example, the storage devices 10 according to the embodiment of the present disclosure, as shown in Figure 11, include: "devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions"; "devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles"; and "devices that capture user gestures and perform device operations according to those gestures, such as TVs, refrigerators, and air conditioners." It can be used in appliances such as conditioners, medical and healthcare equipment such as endoscopes and devices that perform angiography using infrared light, security equipment such as surveillance cameras and cameras for person recognition, beauty equipment such as skin measuring devices that photograph skin and microscopes that photograph the scalp, sports equipment such as action cameras and wearable cameras for sports use, and agricultural equipment such as cameras for monitoring the condition of fields and crops.

[0090] <<9. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the attached drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person with ordinary skill in the art of the present disclosure may conceive of various modifications or alterations within the scope of the technical ideas described in the claims, and these will naturally also be understood to fall within the technical scope of the present disclosure.

[0091] Furthermore, the effects described herein are merely descriptive or illustrative and not limiting. In other words, the technology relating to this disclosure may produce other effects that will be apparent to those skilled in the art from the description herein, in addition to or in lieu of the effects described herein.

[0092] Furthermore, this technology can also take the following configurations: (1) A memory device comprising: a cell array section including a plurality of memory cells arranged in a matrix; a reference section provided in the cell array section including a first reference and a second reference; a sense amplifier that determines three states of the memory cell by comparing the resistance value of the memory cell with the resistance value of the reference section; and a switching section that switches the connection of the first reference and the second reference as the reference section connected to the sense amplifier. (2) The memory device according to (1) above, wherein the first and second references include reference cells made of transistors and resistive switching elements. (3) The memory device according to (2) above, wherein each memory cell and each reference cell are provided at the intersections of a plurality of bit lines and a plurality of word lines arranged in a grid. (4) The memory device according to (3) above, wherein the first reference and the second reference constitute different columns, and the switching section selects the reference section to connect to the sense amplifier based on the column address. (5) The storage device according to (3), wherein the first reference and the second reference are connected to different word lines, and the switching unit selects the reference unit to connect to the sense amplifier based on the low address. (6) The storage device according to any one of (2) to (5), wherein the first and second references include a plurality of reference cells. (7) The storage device according to (6), wherein at least one of the plurality of reference cells of the second reference includes a short circuit instead of the resistive element. (8) The storage device according to (6) or (7), wherein at least one of the plurality of reference cells of the second reference includes a break in the circuit instead of the resistive element. (9) The storage device according to any one of (2) to (8), wherein the resistive element is a magnetoresistive element. (10) The storage device according to any one of (1) to (9), wherein it is an OTP (One Time Programmable) storage device that can only be written to once.(11) The storage device according to (10), wherein the three states are disconnected, undisconnected, and faulty. (12) The storage device according to (11), further comprising a redundant circuit section that can be used as a replacement for a memory cell determined to be in a faulty state. (13) A method for determining the state of a storage device comprising: a cell array section including a plurality of memory cells arranged in a matrix; and a reference section provided in the cell array section including a first reference and a second reference, the method comprising: switching the connection of the first reference and the second reference as the reference section connected to a sense amplifier; and determining the three states of the memory cell by comparing the resistance value of the memory cell with the resistance value of the reference section using the sense amplifier. (14) A method for determining the state of a storage device according to (13), comprising: when determining a first state, comparing the resistance value of the memory cell with the resistance value of the first reference using the sense amplifier; and when determining a second state, comparing the resistance value of the memory cell with the resistance value of the second reference using the sense amplifier. (15) A method for determining the state of a storage device according to (13), comprising: when determining a first state, comparing the resistance value of the memory cell with the resistance value of the first reference using the sense amplifier; and when determining a second state, comparing the resistance value of the memory cell with the resistance values ​​of the first and second references using the sense amplifier. (16) A method for determining the state of a storage device according to any one of (13) to (15), wherein the storage device is an OTP (One Time Programmable) storage device that can only be written to once. (17) A method for determining the state of a storage device according to (16), wherein the three states are disconnected, undisconnected, and faulty. (18) A method for determining the state of a storage device according to (17), wherein the storage device further comprises a writing unit for writing data to memory cells, and further includes writing to memory cells that have not been determined to be faulty.(19) The method for determining the state of a storage device according to (17) or (18), further comprising a redundant circuit section that can be used as a substitute for a memory cell determined to be in a faulty state, and further comprising replacing the memory cell determined to be in a faulty state with the redundant circuit section when the memory cell is determined to be in a faulty state.

[0093] 10, 10a Memory device 11 Magnetoresistive element 12 Selection element 21 I / O 22 Control circuit 26 Address decoder 27A, 27B Bit line control circuit 28A, 28B Source line control circuit 29 Word line address decoder 30A, 30B Word line control circuit 31 Sense amplifier circuit 32 Column switch selection circuit 100 Reference cell array section 102 Reference cell 110, 120 Cell array area 200 Memory cell array section 202 Memory cell 300 Sense amplifier

Claims

1. A storage device comprising: a cell array section including a plurality of memory cells arranged in a matrix; a reference section provided within the cell array section including a first reference and a second reference; a sense amplifier that determines three states of the memory cells by comparing the resistance values ​​of the memory cells with the resistance values ​​of the reference section; and a switching section that switches the connection of the first reference and the second reference as the reference section connected to the sense amplifier.

2. The storage device according to claim 1, wherein the first and second references include a reference cell comprising a transistor and a resistive switching element.

3. The memory device according to claim 2, wherein each memory cell and each reference cell are located at the intersections of a plurality of bit lines and a plurality of word lines arranged in a grid.

4. The storage device according to claim 3, wherein the first reference and the second reference constitute different columns, and the switching unit selects the reference unit to connect to the sense amplifier based on the column address.

5. The storage device according to claim 3, wherein the first reference and the second reference are connected to different word lines, and the switching unit selects the reference unit to connect to the sense amplifier based on the low address.

6. The storage device according to claim 2, wherein the first and second references include a plurality of reference cells.

7. The storage device according to claim 6, wherein at least one of the plurality of reference cells having the second reference includes a short circuit instead of the resistance changing element.

8. The storage device according to claim 6, wherein at least one of the plurality of reference cells having the second reference includes a break in the resistivity element.

9. The memory device according to claim 2, wherein the resistance-changing element is a magnetoresistive element.

10. The storage device according to claim 1, which is an OTP (One Time Programmable) storage device that can only be written to once.

11. The storage device according to claim 10, wherein the three states are disconnected state, undisconnected state, and faulty state.

12. The storage device according to claim 11, further comprising a redundant circuit section that can be used as a replacement for a memory cell determined to be in a faulty state.

13. A method for determining the state of a storage device comprising: a cell array section including a plurality of memory cells arranged in a matrix; and a reference section provided within the cell array section including a first reference and a second reference, the method comprising: switching the connection of the first reference and the second reference as the reference section connected to a sense amplifier; and determining three states of the memory cell by comparing the resistance value of the memory cell with the resistance value of the reference section using the sense amplifier.

14. A method for determining the state of a storage device according to claim 13, comprising: comparing the resistance value of the memory cell with the resistance value of the first reference using the sense amplifier when determining the first state; and comparing the resistance value of the memory cell with the resistance value of the second reference using the sense amplifier when determining the second state.

15. A method for determining the state of a storage device according to claim 13, comprising: comparing the resistance value of the memory cell with the resistance value of the first reference using the sense amplifier when determining the first state; and comparing the resistance value of the memory cell with the resistance values ​​of the first and second references using the sense amplifier when determining the second state.

16. A method for determining the state of a storage device according to claim 13, wherein the storage device is an OTP (One Time Programmable) storage device that can only be written to once.

17. The method for determining the state of a storage device according to claim 16, wherein the three states are disconnected state, undisconnected state, and faulty state.

18. The method for determining the state of a storage device according to claim 17, further comprising a writing unit for writing data to memory cells, and further including writing to memory cells that have not been determined to be faulty.

19. The method for determining the state of a storage device according to claim 17, further comprising a redundant circuit section that can be used as a replacement for a memory cell determined to be in a faulty state, and further comprising replacing the memory cell determined to be in a faulty state with the redundant circuit section when the memory cell is determined to be in a faulty state.

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