Display device

Abstract

A display device comprising a plurality of substrates, a plurality of flexible printed substrates that connect neighboring substrates among the plurality of substrates, a plurality of pixel ICs, a plurality of display elements, and a driving circuit, wherein: the plurality of pixel ICs are connected in series; a clock signal input terminal and an image data input terminal of an initial-stage pixel IC among the plurality of pixel ICs connected in series are connected to the driving circuit, while a clock signal output terminal and an image data output terminal thereof are connected to a subsequent-stage pixel IC; and a clock signal output terminal and an image data output terminal of a final-stage pixel IC provided to one of the neighboring substrates are connected via one of the flexible printed substrates to the clock signal input terminal and the image data input terminal of the initial-stage pixel IC provided to the other of the neighboring substrates.

Description

Display device

[0001] The present invention relates to a display device.

[0002] Patent Documents 1 and 2 disclose a technique in which a pixel IC (represented as a pixel controller or a controller in Patent Documents 1 and 2) is connected to each of one or more pixels.

[0003] U.S. Patent No. 10,832,609 Japanese Patent Application Laid-Open No. 2014-63845

[0004] When a display device is used for interiors, signage, etc., display devices having various shapes and sizes are required. For this reason, it is necessary to increase the degree of freedom in the shape of the display device.

[0005] An object of the present disclosure is to provide a display device capable of improving the degree of freedom in shape.

[0006] A display device according to an aspect of the present disclosure includes a plurality of substrates, a plurality of flexible printed boards that connect adjacent substrates among the plurality of substrates, a plurality of pixel ICs provided on each of the plurality of substrates, a plurality of display elements provided on each of the plurality of substrates and provided corresponding to each of the plurality of pixel ICs, and a drive circuit. Each of the plurality of pixel ICs has a clock signal input terminal to which a clock signal is input, an image data input terminal to which image data is input, a clock signal output terminal that outputs the clock signal, an image data output terminal that outputs the image data, and a connection terminal connected to at least one of the display elements. The plurality of pixel ICs are connected in series. The clock signal input terminal and the image data input terminal of the first-stage pixel IC among the plurality of pixel ICs connected in series are connected to the drive circuit, the clock signal output terminal and the image data output terminal are connected to the next-stage pixel IC, and the clock signal output terminal and the image data output terminal of the last-stage pixel IC provided on one of the adjacent substrates are connected to the clock signal input terminal and the image data input terminal of the first-stage pixel IC provided on the other of the adjacent substrates via the flexible printed board.

[0007] A display device according to one aspect of the present disclosure comprises a plurality of substrates, a plurality of flexible printed circuit boards connecting adjacent substrates among the plurality of substrates, a plurality of first pixel ICs provided on each of the plurality of substrates, a plurality of display elements provided on each of the plurality of substrates and corresponding to each of the plurality of first pixel ICs, and a drive circuit, wherein each of the plurality of first pixel ICs has a clock signal input terminal into which a clock signal is input, an image data input terminal into which image data is input, a clock signal output terminal for outputting the clock signal, an image data output terminal for outputting the image data, and a connection terminal connected to at least one of the display elements, wherein the plurality of first pixel ICs are connected in series on each of the plurality of substrates, and the clock signal input terminal and the image data input terminal of the first stage first pixel IC among the plurality of first pixel ICs are connected to the drive circuit, and the clock signal and the image data are supplied from the drive circuit.

[0008] Figure 1 is a schematic plan view showing a display device according to the first embodiment. Figure 2 is an explanatory diagram for illustrating an example of use of the display device according to the first embodiment. Figure 3 is a schematic plan view showing an example of the configuration of the display device according to the first embodiment. Figure 4 is a schematic plan view showing an example of the configuration of a substrate. Figure 5 is a circuit diagram showing a driver IC, a plurality of pixel ICs, and a plurality of light-emitting elements. Figure 6 is a block diagram showing an example of the configuration of a pixel IC. Figure 7 is a timing chart showing a clock signal and image data in a pixel IC. Figure 8 is a schematic plan view showing an example of the configuration of a substrate of a display device according to a first modification of the first embodiment. Figure 9 is a cross-sectional view taken along IX-IX' in Figure 8. Figure 10 is a schematic plan view showing an example of the configuration of a display device according to a second modification of the first embodiment. Figure 11 is a schematic plan view showing an example of the configuration of a display device according to a third modification of the first embodiment. Figure 12 is a schematic plan view showing an example of the configuration of a display device according to the second embodiment. Figure 13 is a schematic plan view showing an example of the configuration of a display device according to a fourth modification of the second embodiment. Figure 14 is a schematic plan view showing an example of the configuration of a display device according to a fifth modification of the second embodiment. Figure 15 is a schematic plan view showing an example of the configuration of a display device according to a sixth modification of the second embodiment. Figure 16 is a schematic plan view showing an example of the configuration of a display device according to a seventh modification of the second embodiment.

[0009] The embodiments for implementing this disclosure will be described in detail with reference to the drawings. This disclosure is not limited to the embodiments described below. Furthermore, the components described below include those that can be easily conceived by a person skilled in the art, and those that are substantially the same. In addition, the components described below can be combined as appropriate. The disclosure is merely an example, and any modifications that a person skilled in the art can easily conceive while maintaining the spirit of this disclosure are naturally included within the scope of this disclosure. Furthermore, in order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but these are merely examples and do not limit the interpretation of this disclosure. Furthermore, in this disclosure and in each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0010] In this disclosure, when describing a manner in which one structure is placed on top of another structure, unless otherwise specified, the term "on top of" includes both cases: when one structure is placed directly on top of another structure so as to be in contact with it, and when another structure is placed above another structure via yet another structure.

[0011] (First Embodiment) Figure 1 is a schematic plan view showing a display device according to the first embodiment. In Figure 1, the display areas 23 of the substrate 21 are schematically shown with hatching to facilitate understanding.

[0012] As shown in Figure 1, the display device 1 of this embodiment has a plurality of elongated substrates 21 and a plurality of flexible printed circuit boards 22 connecting adjacent substrates 21. Each of the plurality of substrates 21 is a flexible circuit board. Note that each of the plurality of substrates 21 may be a rigid circuit board. Each substrate 21 has a plurality of display areas 23 provided along its longitudinal direction. The plurality of substrates 21 are arranged to form the display surface of the display device 1. The display surface of the display device 1 is composed of a plurality of display areas 23 arranged in a matrix.

[0013] More specifically, each of the multiple substrates 21 extends in a first direction Dx and is arranged in a second direction Dy. The display areas 23 are arranged in a matrix on the multiple substrates 21. That is, on one substrate 21, the multiple display areas 23 are arranged along the first direction Dx. Also, on two adjacent substrates 21 in the second direction Dy, the display areas 23 of one substrate 21 and the display areas 23 of the other substrate 21 are arranged to be adjacent in the second direction Dy.

[0014] In the following description, the first direction Dx is one direction in a plane parallel to the surface of the display surface (multiple display areas 23) of the display device 1. The second direction Dy is one direction in a plane parallel to the display surface of the display device 1 and is perpendicular to the first direction Dx. The second direction Dy may intersect the first direction Dx without being perpendicular to it. The third direction Dz is perpendicular to both the first direction Dx and the second direction Dy. The third direction Dz is the normal direction to the display surface of the display device 1. Furthermore, "plan view" refers to the positional relationship when viewed from a direction perpendicular to the display surface of the display device 1.

[0015] The flexible printed circuit board 22 is a deformable resin substrate. The flexible printed circuit board 22 connects two adjacent substrates 21 in the second direction Dy from among a plurality of substrates 21. More specifically, the plurality of flexible printed circuit boards 22 includes a first flexible printed circuit board 22A and a second flexible printed circuit board 22B. The first flexible printed circuit board 22A connects one end (right end in Figure 1) of each of the two adjacent substrates 21 in the first direction Dx. The second flexible printed circuit board 22B connects the other end (left end in Figure 1) of each of the two adjacent substrates 21 in the first direction Dx.

[0016] In the following explanation, if it is not necessary to distinguish between the first flexible printed circuit board 22A and the second flexible printed circuit board 22B, they will simply be referred to as the flexible printed circuit board 22.

[0017] Figure 2 is an explanatory diagram illustrating an example of use of the display device according to the first embodiment. As described above, two adjacent substrates 21 are connected by a plurality of deformable flexible printed circuit boards 22. As a result, the display device 1 can be transformed into various forms, as shown in Figure 2. For example, the plurality of substrates 21 may be arranged flat for display (First Use Example EX1). Alternatively, the plurality of substrates 21 may be arranged spaced apart from each other in the direction of arrow A by extending each of the flexible printed circuit boards 22 in the direction of arrow A (Second Use Example EX2).

[0018] Alternatively, the flexible printed circuit board 22 may be bent alternately for each adjacent board 21, thereby folding and arranging the boards 21 in a zigzag pattern (Third Example EX3). Alternatively, the flexible printed circuit board 22 may be curved in a curved shape, so that the boards 21 as a whole are arranged along an arc-shaped curved surface to form a curved panel (Fourth Example EX4).

[0019] As described above, the display device 1 of this embodiment is configured to have a plurality of substrates 21 provided with a plurality of display areas 23, and a plurality of flexible printed circuit boards 22 connecting two adjacent substrates 21. This allows the shape of the display surface of the display device 1, which is composed of a plurality of substrates 21, to be changed in various ways by deforming the plurality of flexible printed circuit boards 22. Furthermore, the dimensions and shape of the display surface of the display device 1 can be changed by varying the length of each substrate 21 along its longitudinal direction, or by varying the number of substrates 21. As a result, the display device 1 of this embodiment can improve the degree of freedom in the shape of the display surface and can be incorporated into various products with diverse shapes, such as interiors and signage.

[0020] Figure 1 shows an example where the display areas 23 of multiple substrates 21 are arranged in a 4x6 grid for clarity. However, it is not limited to this, and the display surface of the display device 1 may be 3x5 or less, or 5x7 or more. The display device 1 may have different numbers of multiple substrates 21. For example, the display device 1 may be configured with at least two substrates 21. Alternatively, the longitudinal lengths of the multiple substrates 21 may be different. In addition, although the display surface as a whole is formed by multiple substrates 21 (display areas 23), it is possible to form a display surface of an irregular shape, such as having an arc-shaped curved portion on part of the outer periphery.

[0021] Two flexible printed circuit boards 22 are provided between two adjacent circuit boards 21, but this is not limited to that. Three or more flexible printed circuit boards 22 may be provided between two adjacent circuit boards 21. Alternatively, one flexible printed circuit board 22 may be provided between two adjacent circuit boards 21.

[0022] As mentioned above, the multiple substrates 21 are not limited to being arranged in a planar configuration, but can also be arranged in a curved or zigzag pattern. In this case, the first direction Dx, the second direction Dy, and the third direction Dz indicate the respective directions of the multiple substrates 21. For the sake of ease of understanding, the following explanation will describe an example in which the multiple substrates 21 are arranged in a planar configuration.

[0023] Next, the system configuration of the display device 1 and the detailed configuration of the multiple substrates 21 and the multiple flexible printed circuit boards 22 will be described. Figure 3 is a schematic plan view showing an example of the configuration of the display device according to the first embodiment. As shown in Figure 3, the display device 1 includes a pixel IC 50 provided in the display area 23 of the substrate 21, wiring 14 connecting the pixel IC 50, and power supply wiring 19 supplying power to the pixel IC 50. Furthermore, the display device 1 includes a driver IC (Integrated Circuit) 11 and a host 101. The host 101 may be a host IC, a host CPU, etc.

[0024] The driver IC 11 (driving circuit) is a circuit that controls the display of multiple substrates 21 of the display device 1. The host 101 is a display control circuit that controls the driver IC 11. The driver IC 11 supplies a clock signal CK and image data DT (see Figure 5) to each of the multiple pixel ICs 50 on the substrate 21.

[0025] The driver IC 11 is connected to the host 101 and controls multiple pixel ICs 50 provided on multiple boards 21 based on control signals from the host 101. The display device 1 is not limited to having only one driver IC 11, but may have multiple driver ICs 11 depending on the number of boards 21. Furthermore, the driver IC 11 may be configured as a single circuit or as two or more circuits.

[0026] As shown in Figure 3, the multiple substrates 21 are arranged in the order of substrates 21-1, 21-2, 21-3, 21-4, ..., 21-32 in the second direction Dy. Substrate 21-1 is positioned closest to the driver IC 11. Substrate 21-32 is positioned furthest from the driver IC 11. In the following description, among the multiple substrates 21 arranged in the second direction Dy, substrate 21-1, which is closest to the driver IC 11, may be referred to as the first stage substrate 21, and substrate 21-32, which is furthest from the driver IC 11, may be referred to as the final stage substrate 21.

[0027] Multiple pixel ICs 50 are arranged along the longitudinal direction (first direction Dx) on each of the substrates 21 and connected in series via wiring 14. The number of multiple pixel ICs 50 arranged on one substrate 21 is, for example, 64. The total number of multiple pixel ICs 50 arranged on multiple substrates 21 is, for example, 64 × 32 = 2048.

[0028] However, the number of multiple circuit boards 21 and the number of multiple pixel ICs 50 arranged on one circuit board 21 are merely examples and can be appropriately changed depending on the configuration and application of the display device 1. The number of multiple circuit boards 21 may be 31 or less, or 33 or more. Also, the number of multiple pixel ICs 50 arranged on one circuit board 21 may be 63 or less, or 65 or more.

[0029] In Figure 3, the substrate 21 is shown schematically, and the light-emitting elements 3 in the display area 23, as well as the connection relationship between the pixel IC 50 and the light-emitting elements 3, are omitted. The detailed configuration of the display area 23 on the substrate 21 and the detailed configuration of the pixel IC 50 will be described later in Figure 4 and subsequent figures.

[0030] The wiring 14 is for supplying signals such as a clock signal CK and image data DT (see Figure 5) to multiple pixel ICs 50. Specifically, the wiring 14 includes a clock signal supply wiring 12 and an image data supply wiring 13 (see Figure 5). The power supply wiring 19 also includes a power potential supply wiring 17 and a reference potential supply wiring 18 (see Figure 5).

[0031] Of the multiple pixel ICs 50 connected in series on board 21-1, the first-stage pixel IC 50 (the rightmost pixel IC 50 in Figure 3) is electrically connected to the driver IC 11 via the first flexible printed circuit board 22A. Furthermore, of the multiple pixel ICs 50 connected in series on board 21-1, the final-stage pixel IC 50 (the leftmost pixel IC 50 in Figure 3) is electrically connected to the first-stage pixel IC 50 on board 21-2 (the leftmost pixel IC 50 in Figure 3) via the second flexible printed circuit board 22B.

[0032] Of the multiple pixel ICs 50 connected in series on board 21-2, the final stage pixel IC 50 (the rightmost pixel IC 50 in Figure 3) is electrically connected to the first stage pixel IC 50 (the rightmost pixel IC 50 in Figure 3) on board 21-3 via the first flexible printed circuit board 22A.

[0033] Similarly, multiple pixel ICs 50 connected in series on each of the multiple substrates 21 arranged in the second direction D are electrically connected to multiple pixel ICs 50 provided on the next substrate 21 by alternately passing through the first flexible printed circuit board 22A and the second flexible printed circuit board 22B.

[0034] As a whole, the wiring 14 connecting the multiple pixel ICs 50 across the multiple substrates 21 is arranged in a meander pattern. That is, in two adjacent substrates 21, the wiring 14 provided on one substrate 21 (the wiring 14 connected to the final stage pixel IC 50) is connected to the wiring 14 provided on the other substrate 21 (the wiring 14 connected to the first stage pixel IC 50) through either the first flexible printed circuit board 22A or the second flexible printed circuit board 22B. Furthermore, in the multiple substrates 21 arranged in the second direction Dy, the wiring 14 provided on each is connected along the second direction Dy, alternately passing through the first flexible printed circuit board 22A and the second flexible printed circuit board 22B. As a result, in this embodiment, the entirety of the multiple pixel ICs 50 provided on substrates 21-1 to 21-32 is connected in series in a meander pattern and connected to a single driver IC 11.

[0035] More specifically, the wiring 14 includes a first wiring 14a that extends in a first direction Dx and connects multiple pixel ICs 50, and a second wiring 14b that extends in a second direction Dy and connects two adjacent substrates 21. For example, multiple substrates 21-1, 21-2, and 21-3 arranged in the second direction Dy will be described. The second wiring 14b connected to the first-stage pixel IC 50 of substrate 21-1 is electrically connected to the driver IC 11 via a connection wiring 25 provided on the first flexible printed circuit board 22A.

[0036] The first wiring 14a connected to the final stage pixel IC 50 on substrate 21-1 is electrically connected to the second wiring 14b on the adjacent substrate 21-2 and the first wiring 14a connected to the first stage pixel IC 50 via the second wiring 14b and the connecting wiring 25 provided on the second flexible printed circuit board 22B.

[0037] The first wiring 14a connected to the final stage pixel IC 50 on board 21-2 is electrically connected to the second wiring 14b on the adjacent board 21-3 and the first wiring 14a connected to the first stage pixel IC 50 via the second wiring 14b and the connecting wiring 25 provided on the first flexible printed circuit board 22A. From board 21-4 to the final stage board 21-32, the wiring 14 is connected in a meander pattern along the second direction Dy, alternately passing through the first flexible printed circuit board 22A and the second flexible printed circuit board 22B.

[0038] The power supply wiring 19 includes a first power supply wiring 19a, a second power supply wiring 19b, and a third power supply wiring 19c. The first power supply wiring 19a is provided on one end (right end) of the first direction Dx of the plurality of substrates 21 and extends in the second direction Dy across the plurality of substrates 21. The first power supply wiring 19a provided on each of two adjacent substrates 21 is electrically connected via a connection wiring 26 provided on the first flexible printed circuit board 22A.

[0039] The second power supply wiring 19b is provided on the opposite side of the first power supply wiring 19a, that is, on the other end (left end) of the multiple substrates 21 in the first direction Dx, and extends in the second direction Dy across the multiple substrates 21. The second power supply wiring 19b provided on each of two adjacent substrates 21 is electrically connected via a connecting wiring 26 provided on the second flexible printed circuit board 22B. On each substrate 21, the multiple pixel ICs 50 are arranged between the first power supply wiring 19a and the second power supply wiring 19b in the first direction Dx.

[0040] The third power supply wiring 19c extends in the first direction Dx along the arrangement direction of the multiple pixel ICs 50 on each substrate 21. Although not shown in the figures, each of the multiple pixel ICs 50 is electrically connected to the third power supply wiring 19c. As a result, the multiple pixel ICs 50 provided on each of the multiple substrates 21 are supplied with power (power supply potential and reference potential, etc.) from the driver IC 11.

[0041] With the above configuration, the multiple pixel ICs 50 arranged on the multiple substrates 21 are connected in series via wiring 14, and the first-stage pixel IC 50 (the pixel IC 50 located at the right end of substrate 21-1 in Figure 3) is electrically connected to the driver IC 11. The image data DT transmitted from the driver IC 11 includes data to light up the multiple light-emitting elements 3, which are provided corresponding to each of the multiple pixel ICs 50 connected in series. Each pixel IC 50 controls a predetermined current to flow through each light-emitting element 3 (see Figure 4) connected to the pixel IC 50 based on the control signals (clock signal CK and image data DT) from the driver IC 11, causing the light-emitting elements 3 to emit light. As a result, the display device 1 can display an image on the display surface composed of the multiple substrates 21.

[0042] Further, as described above, the wirings 14 provided on each of the plurality of substrates 21 arranged in the second direction Dy are connected in a meander shape by alternately passing through the first flexible printed board 22A and the second flexible printed board 22B along the second direction Dy. Thereby, compared with a configuration in which the wiring 14 is folded back and connected in a meander shape within the substrate 21 (see, for example, FIG. 10), the length of the wiring 14 can be shortened, and an increase in resistance of the entire wiring 14 can be suppressed.

[0043] FIG. 4 is a plan view schematically showing a configuration example of the substrate. In FIG. 4, among the plurality of substrates 21, the configuration of one substrate 21 is shown, but the configurations of the other substrates 21 are the same.

[0044] As shown in FIG. 4, in the plurality of display areas 23 arranged on the substrate 21, pixel PX (a plurality of light emitting elements 3R, 3G, 3B) and a pixel IC50 for driving the plurality of light emitting elements 3R, 3G, 3B are arranged respectively. The plurality of light emitting elements 3R, 3G, 3B are arranged on the pixel IC50.

[0045] The light emitting elements 3R, 3G, 3B are display elements of the display device 1, and are self-emitting elements that emit red light, green light, and blue light respectively. The light emitting elements 3R, 3G, 3B are, for example, inorganic light emitting diodes (LEDs: Light Emitting Diodes). The light emitting elements 3R, 3G, 3B may be micro LEDs having a size of about 3 μm or more and 300 μm or less in plan view. The display device 1 including micro LEDs in each pixel PX is also called a micro LED display device.

[0046] In the following description, when it is not necessary to distinguish and describe the light emitting elements 3R, 3G, 3B, they are simply represented as the light emitting element 3. The plurality of light emitting elements 3 may emit four or more different colors of light. Also, in the example shown in FIG. 4, the plurality of light emitting elements 3R, 3G, 3B are arranged side by side in an L shape. However, the arrangement of the plurality of light emitting elements 3R, 3G, 3B is merely an example and is not limited thereto.

[0047] The pixel IC 50 is composed of, for example, a micro IC and is provided for each display area 23. Also, in one display area 23, one pixel IC 50 and one pixel PX (a plurality of light-emitting elements 3) connected thereto are arranged. In the example shown in FIG. 4, three light-emitting elements 3 are connected to one pixel IC 50.

[0048] On the substrate 21, the pixel IC 50 and the plurality of light-emitting elements 3 provided for each display area 23 are arranged along the first direction Dx. Also, the pixel ICs 50 provided in adjacent display areas 23 are serially connected by a wiring 14 provided in the non-display area 24. In other words, in the non-display area 24 of the substrate 21, no elements such as the light-emitting element 3 are provided, and only the wiring 14 connecting the display areas 23 is provided. The wiring 14 includes, for example, a clock signal supply wiring 12 and an image data supply wiring 13. The clock signal supply wiring 12 is a wiring for supplying a clock signal CK to a plurality of pixel ICs 50. The image data supply wiring 13 is a wiring for supplying image data DT to a plurality of pixel ICs 50.

[0049] The clock signal supply wiring 12 and the image data supply wiring 13 connecting between adjacent pixel ICs 50 are wavy. Specifically, the clock signal supply wiring 12 and the image data supply wiring 13 each extend in a wavy shape along the first direction Dx. Also, the clock signal supply wiring 12 and the image data supply wiring 13 are arranged adjacent to each other in the second direction Dy. In the present disclosure, "wavy" means a shape that changes direction and meanders as it progresses in a predetermined direction. The wavy shape includes a zigzag shape. Thereby, even when the substrate 21 is deformed, such as when the substrate 21 is stretched or contracted along the second direction Dy or when the substrate 21 is bent into a curved shape, the concentration of stress in the wiring 14 can be suppressed. Therefore, in the present embodiment, disconnection of the wiring 14 can be suppressed.

[0050] In Figure 4, for the sake of clarity, the wiring 14 includes a clock signal supply wiring 12 and an image data supply wiring 13. However, in addition to the wiring 14, the circuit board 21 is also provided with power supply wiring 19 (for example, a third power supply wiring 19c). That is, two wirings 14 connecting multiple pixel ICs 50 arranged in a first direction Dx are arranged in parallel, and the power supply wiring 19 is arranged along the multiple pixel ICs 50 arranged in the first direction Dx. The power supply wiring 19 is also formed in a wavy shape, similar to the wiring 14. However, it is not limited to this, and the wiring 14 and power supply wiring 19 may be arranged in a straight line.

[0051] Figure 4 shows a configuration in which one pixel IC 50 is connected to one pixel PX, but the configuration is not limited to this, and one pixel IC 50 may be connected to multiple pixel PXs (four or more light-emitting elements 3). Also, the configuration is not limited to multiple light-emitting elements 3 overlapping the pixel IC 50 in one display area 23, and multiple light-emitting elements 3 and the pixel IC 50 may be arranged adjacent to each other in a plan view.

[0052] As shown in Figure 4, the width Wsub of the substrate 21 (width in the second direction Dy) is, for example, about 1 mm to 15 mm. Alternatively, the width Wsub of the substrate 21 is, for example, 0.1 mm to 30 mm. The width Wsub of the substrate 21 can be appropriately set according to the respective sizes and arrangement of the pixel IC 50 and the light-emitting element 3.

[0053] Figure 5 is a circuit diagram showing a driver IC, multiple pixel ICs, and multiple light-emitting elements. As shown in Figure 5, the multiple pixel ICs 50 include a first pixel IC 50-1, a second pixel IC 50-2, and a third pixel IC 50-3 connected in series. The first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 are each provided corresponding to the display area 23.

[0054] In Figure 5, for the sake of clarity, three of the multiple pixel ICs 50 (display area 23) are shown, specifically those connected to the driver IC 11. Furthermore, in the following explanation, if it is not necessary to distinguish between the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3, they will simply be referred to as pixel IC 50. Similarly, if it is not necessary to distinguish between the clock signal supply lines 12-1, 12-2, 12-3, and 12-4, they will simply be referred to as clock signal supply line 12. And if it is not necessary to distinguish between the image data supply lines 13-1, 13-2, 13-3, and 13-4, they will simply be referred to as image data supply line 13.

[0055] Each of the multiple pixel ICs 50 has a clock signal input terminal 51, an image data input terminal 52, a clock signal output terminal 53, and an image data output terminal 54. A clock signal CK is input to the clock signal input terminal 51. Image data DT is input to the image data input terminal 52. A clock signal output terminal 53 outputs a clock signal CK. An image data output terminal 54 outputs image data DT.

[0056] In multiple adjacent pixel ICs 50, the clock signal output terminal 53 is connected to the clock signal input terminal 51, and the image data output terminal 54 is connected to the image data input terminal 52.

[0057] More specifically, the clock signal input terminal 51 of the first pixel IC 50-1 is connected to the driver IC 11 via the clock signal supply wiring 12-1. The image data input terminal 52 of the first pixel IC 50-1 is also connected to the driver IC 11 via the image data supply wiring 13-1. The first pixel IC 50-1 corresponds to the first-stage pixel IC 50 provided on the aforementioned substrate 21-1 (see Figure 3). Furthermore, the multiple clock signal supply wirings 12-1, 12-2, 12-3, and 12-4 are independently provided between two adjacent pixel ICs 50 in the first direction Dx (the longitudinal direction of the substrate 21). Similarly, the multiple image data supply wirings 13-1, 13-2, 13-3, and 13-4 are independently provided between two adjacent pixel ICs 50 in the first direction Dx (the longitudinal direction of the substrate 21).

[0058] The clock signal output terminal 53 of the first pixel IC 50-1 is connected to the clock signal input terminal 51 of the second pixel IC 50-2 via the clock signal supply wiring 12-2. The image data output terminal 54 of the first pixel IC 50-1 is connected to the image data input terminal 52 of the second pixel IC 50-2 via the image data supply wiring 13-2.

[0059] The clock signal output terminal 53 of the second pixel IC 50-2 is connected to the clock signal input terminal 51 of the third pixel IC 50-3 via the clock signal supply wiring 12-3. The image data output terminal 54 of the second pixel IC 50-2 is connected to the image data input terminal 52 of the third pixel IC 50-3 via the image data supply wiring 13-3.

[0060] In other words, the multiple clock signal supply lines 12 are provided between two adjacent pixel ICs 50, spaced apart from each other. Similarly, the multiple image data supply lines 13 are provided between two adjacent pixel ICs 50, spaced apart from each other. As a result, the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3, which are arranged in the first direction Dx, are connected in series.

[0061] Referring to Figures 4 and 5, on a single substrate 21, the clock signal output terminal 53 of a pixel IC 50 (for example, a first pixel IC 50-1) provided in one of two adjacent display areas 23 separated by a non-display area 24 is connected to the clock signal input terminal 51 of a pixel IC 50 (for example, a second pixel IC 50-2) provided in the other display area 23 via wiring 14 (for example, clock signal supply wiring 12-2) provided in the non-display area 24.

[0062] Furthermore, with reference to Figures 3 and 5, the connection between adjacent substrates 21 in the second direction Dy will be described in detail. The clock signal output terminal 53 and image data output terminal 54 of the final stage pixel IC 50 provided on one of the adjacent substrates 21 are connected via a flexible printed circuit board 22 (connection wiring 25) to the clock signal input terminal 51 and image data input terminal 52 of the first stage pixel IC 50 provided on the other substrate 21 of the adjacent substrates 21.

[0063] With this configuration, the clock signal CK output from the driver IC 11 is transmitted sequentially in series to the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 via the clock signal supply wiring 12. Similarly, the image data DT output from the driver IC 11 is transmitted sequentially in series to the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 via the image data supply wiring 13.

[0064] As a result, the display device 1 of this embodiment can increase the bandwidth (frequency) of the transmitted clock signal CK and image data DT compared to the case where multiple pixel ICs 50 are connected in parallel to a common clock signal supply line 12 and a common image data supply line 13. In other words, the display device 1 can suppress voltage fluctuations and delays of the clock signal CK and image data DT due to the wiring resistance of the clock signal supply line 12 and the image data supply line 13. This allows the phase relationship between the clock signal CK and the image data DT to be maintained.

[0065] Therefore, the display device 1 of this embodiment can achieve good display characteristics even when the number of display areas 23 (pixel ICs 50) connected in series is increased. For example, the display device 1 can achieve good display characteristics even when the number of multiple boards 21 connected via the flexible printed circuit board 22 is changed to increase the degree of freedom of the shape and area of ​​the display surface.

[0066] Each of the multiple pixel ICs 50 further has a power terminal 55, a reference potential terminal 56, and connection terminals 57, 58, and 59 (see Figure 6). The power terminal 55 is connected to the driver IC 11 via a power potential supply wiring 17. The power potential supply wiring 17 is wiring for supplying power potential to the multiple pixel ICs 50. As a result, the driver IC 11 supplies power potential to the multiple pixel ICs 50 through the power terminal 55 and the power potential supply wiring 17. The power potential supply wiring 17 is also connected to the anodes of the light-emitting elements 3 (3R, 3G, 3B). The driver IC 11 supplies power potential to the anodes of the light-emitting elements 3 (3R, 3G, 3B) through the power potential supply wiring 17.

[0067] Multiple pixel ICs 50 and multiple light-emitting elements 3 are connected in parallel to the power supply wiring 17. In other words, the power supply wiring 17 is provided in common to multiple display areas 23 (pixel ICs 50 and multiple light-emitting elements 3) which are arranged in a first direction Dx.

[0068] The reference potential terminal 56 is connected to the driver IC 11 via the reference potential supply wiring 18. The reference potential supply wiring 18 is wiring for supplying a reference potential to a plurality of pixel ICs 50. As a result, the driver IC 11 supplies a reference potential GND to the plurality of pixel ICs 50 through the reference potential terminal 56 and the reference potential supply wiring 18. The reference potential GND is, for example, the ground potential. However, it is not limited to this, and the reference potential GND may be a predetermined fixed potential different from the ground potential.

[0069] Multiple pixel ICs 50 are connected in parallel to the reference potential supply wiring 18. In other words, the reference potential supply wiring 18 is provided in common to multiple display areas 23 (pixel ICs 50 and multiple light-emitting elements 3) which are arranged in a first direction Dx.

[0070] The connection terminals 57, 58, and 59 are connected to the cathodes of the light-emitting elements 3R, 3G, and 3B, respectively. The cathodes of the light-emitting elements 3R, 3G, and 3B are connected to the reference potential GND via the drive transistor inside the light-emitting element drive circuit 68 (see Figure 6) of the pixel IC 50, as a result of the operation of the light-emitting element drive circuit 68. As a result, the light-emitting elements 3R, 3G, and 3B are driven in a forward bias and emit light.

[0071] Note that Figures 4 and 5 show an example where one pixel IC 50 is connected to one pixel PX (three light-emitting elements 3) for clarity. However, two or more pixel PXs, i.e., six or more light-emitting elements 3, may be connected to one pixel IC 50, and in this case, the number of connection terminals can be changed according to the number of light-emitting elements 3. One pixel IC 50 may be provided with six or more connection terminals.

[0072] Figure 6 is a block diagram showing an example of the configuration of a pixel IC. As shown in Figure 6, the pixel IC 50 includes buffer circuits 61 and 62, flip-flop circuits 63 and 64, control circuit 65, PWM control circuit 66, memory circuit 67, and light-emitting element driving circuit 68 (display element driving circuit).

[0073] The buffer circuit 61 is connected between the clock signal input terminal 51 and the clock signal output terminal 53. As a result, the clock signal CK input to the clock signal input terminal 51 of the pixel IC 50 is output from the clock signal output terminal 53 via the buffer circuit 61. The buffer circuit 61 corrects and outputs voltage fluctuations of the clock signal CK due to resistance in the clock signal supply wiring 12 and wiring within the pixel IC 50. As a result, even in a configuration where multiple pixel ICs 50 are connected in series, the clock signal CK is transmitted reliably to the final stage pixel IC 50 (the nth pixel IC 50-n).

[0074] The flip-flop circuit 63 is connected between the clock signal input terminal 51 and the image data input terminal 52 and the control circuit 65. The buffer circuit 62 and the flip-flop circuit 64 are connected in series between the control circuit 65 and the image data output terminal 54.

[0075] The flip-flop circuit 63 receives the clock signal CK from the clock signal input terminal 51 and the image data DT from the image data input terminal 52, and outputs the image data DT to the control circuit 65 at a timing corresponding to the clock signal CK.

[0076] The control circuit 65 controls the lighting of the light-emitting element 3 connected to the pixel IC 50 based on the image data DT input through the image data input terminal 52 and the flip-flop circuit 63. The control circuit 65 performs predetermined processing on the input image data DT and outputs it to the buffer circuit 62.

[0077] The buffer circuit 62 corrects and outputs the voltage fluctuations and delay time of the image data DT caused by resistance in the image data supply wiring 13 and wiring within the pixel IC 50. The delay time correction is adjusted so that the delay time of the data after predetermined processing of the image data DT does not become shorter than the delay time generated by the buffer circuit 61 provided for the clock signal CK.

[0078] The flip-flop circuit 64 receives a clock signal CK supplied from the clock signal input terminal 51 through the buffer circuit 61, and image data DT from the image data input terminal 52 via the flip-flop circuit 63, control circuit 65, and buffer circuit 62. The flip-flop circuit 64 outputs the image data DT to the image data output terminal 54 at a timing corresponding to the clock signal CK.

[0079] The control circuit 65 performs predetermined processing on the input image data DT and outputs it to the storage circuit 67, and controls the PWM control circuit 66 and the light-emitting element drive circuit 68 based on the input image data DT. The storage circuit 67 stores the image data DT input from the control circuit 65. The PWM control circuit 66 determines the illumination period of the multiple light-emitting elements 3 corresponding to the grayscale and generates a PWM control signal based on the image data DT acquired from the control circuit 65.

[0080] The light-emitting element driving circuit 68 drives a plurality of light-emitting elements 3 connected to the connection terminals 57, 58, and 59 of the pixel IC 50 based on a PWM control signal obtained from the PWM control circuit 66. Specifically, the light-emitting element driving circuit 68 may be configured to include a plurality of switch elements that switch the connection state between the cathode of the light-emitting element 3 and the reference potential terminal 56. For example, the light-emitting element driving circuit 68 may be configured to include a plurality of switch elements that switch between connection (on) and disconnection (off) between the cathode of the light-emitting element 3 and the reference potential GND based on a PWM control signal. Current flows to the light-emitting element 3 and it lights up during a predetermined period when the cathode of the light-emitting element 3 is connected to the reference potential GND. Also, the light-emitting element 3 turns off during the period when the cathode of the light-emitting element 3 is not connected to the reference potential GND. By making the lighting period and the off period different based on the PWM control signal, the light-emitting element 3 can express gradations according to the image data DT. As described above, the multiple light-emitting elements 3 are driven by PWM (Pulse Width Modulation) based on the image data DT acquired by the control circuit 65.

[0081] Figure 7 is a timing chart showing the clock signal and image data in a pixel IC. Figure 7 shows the clock signal CK(IN) input to the clock signal input terminal 51, the image data DT(IN) input to the image data input terminal 52, the clock signal CK(OUT) output from the clock signal output terminal 53, and the image data DT(OUT) output from the image data output terminal 54.

[0082] As shown in Figure 7, the clock signal CK(OUT) output from the clock signal output terminal 53 is slightly delayed relative to the clock signal CK(IN) due to the operation of the buffer circuit 61. For example, the delay of the clock signal CK(OUT) is the difference between time t2 and time t1 shown in Figure 7. This delay is very small and does not pose any practical problems.

[0083] The flip-flop circuits 63 and 64 output the image data DT at the timing of the rising (or falling) edge of the clock signal CK. In other words, the image data DT is output by each of the flip-flop circuits 63 and 64 with a 1-bit delay relative to the clock signal CK.

[0084] Specifically, as shown in Figure 7, the image data DT includes multiple image data DT(a), DT(b), DT(c), and DT(d). Note that image data DT(a), DT(b), DT(c), and DT(d) are shown schematically for clarity.

[0085] Focusing on image data DT(a) within the image data DT, image data DT(a) is input to the image data input terminal 52 after a predetermined time has elapsed from time t1, when the clock signal CK(IN) is input to the clock signal input terminal 51. In the first stage flip-flop circuit 63, image data DT(a) is output at the rising edge timing of the clock signal CK(IN) (time t3). In other words, image data DT(a) is delayed by 1 bit relative to the clock signal CK(IN).

[0086] In the second stage flip-flop circuit 64, the image data DT(a) is output at the rising edge timing (time t6) of the clock signal CK(OUT). As a result, when compared with the timing relationship between the input clock signal CK(IN) and the image data DT(IN), the image data DT(OUT) is output with a total delay of 2 bits relative to the clock signal CK(OUT).

[0087] As described above, in the pixel IC 50, buffer circuits 61, 62 and flip-flop circuits 63, 64 cause a predetermined bit (for example, 2 bits) delay between the image data DT(OUT) output from the image data output terminal 54 and the clock signal CK(OUT) output from the clock signal output terminal 53. However, the timing relationship (delay time) between the clock signal CK(OUT) and the image data DT(OUT) is substantially the same for each of the multiple pixel ICs 50. As a result, the display device 1 can display images well even in a configuration that does not synchronize horizontally (for example, without gate drive signals in an active matrix system).

[0088] Note that the configuration and operation of the pixel IC 50 shown in Figures 5 to 7 are merely examples and can be modified as appropriate.

[0089] (First Modification of the First Embodiment) Figure 8 is a schematic plan view showing an example of the substrate configuration of a display device according to the first modification of the first embodiment. Figure 9 is a cross-sectional view taken along IX-IX' in Figure 8. In the following description, the same reference numerals are used for components that are the same as those described in the above-described embodiments, and redundant descriptions are omitted.

[0090] As shown in Figure 8, in the display device 1A according to the first modification of the first embodiment, among the plurality of pixel ICs 50, a plurality of pixel PXs (light-emitting elements 3R, 3G, 3B) are connected to one pixel IC 50. That is, the display area 23 includes one pixel IC 50 and a plurality of pixel PXs (light-emitting elements 3R, 3G, 3B) connected to the pixel IC 50. The plurality of light-emitting elements 3 connected to one pixel IC 50 are arranged in a matrix.

[0091] In the example shown in Figure 8, the pixels PX connected to one pixel IC 50 are arranged in a 4x4 grid. If one pixel PX has three light-emitting elements 3R, 3G, and 3B, then 48 light-emitting elements 3 are connected to one pixel IC 50.

[0092] In this modified configuration, multiple pixel PXs (light-emitting elements 3R, 3G, 3B) are connected to a single pixel IC, allowing for higher resolution display compared to a configuration where one pixel PX is connected to one pixel IC 50. Furthermore, in this modified configuration, even if the number of pixel PXs increases, the number of pixel ICs 50 provided on the substrate 21 can be kept from increasing, thereby reducing the cost of the display device 1A. Note that the number and arrangement of pixel PXs (light-emitting elements 3) connected to a single pixel IC 50 are merely examples and can be changed as appropriate.

[0093] As shown in Figure 9, the multiple light-emitting elements 3 are mounted on a substrate 21 common to the pixel IC 50. The substrate 21 is a flexible or rigid substrate made of a resin material such as polyimide resin. A protective film 27 is provided to cover the multiple light-emitting elements 3 and the pixel IC 50. The protective film 27 is a film made of a light-transmitting resin material, such as OCA (Optically Clear Adhesive).

[0094] The substrate 21 is placed on the support member 28. The support member 28 is made of a deformable material, such as cloth or tape. This allows the support member 28 to support the substrate 21 in a deformable manner while improving its strength.

[0095] The support member 28 may be provided for each substrate 21, or multiple substrates 21 may be bonded together on a single support member 28. Alternatively, the support member 28 may be omitted.

[0096] (Second Modification of the First Embodiment) Figure 10 is a schematic plan view showing an example of the configuration of a display device according to a second modification of the first embodiment. As shown in Figure 10, in the display device 1B according to the second modification, the wiring 14 provided on each of the plurality of substrates 21 arranged in the second direction Dy is connected to each other through the first flexible printed circuit board 22A.

[0097] Specifically, the wiring 14 includes a first wiring 14a connecting multiple pixel ICs 50, a third wiring 14c extending along the first wiring 14a, and a second wiring 14b connecting the first wiring 14a and the third wiring 14c. For example, multiple substrates 21-1 and 21-2 arranged in the second direction D will be described. The second wiring 14b connected to the first-stage pixel IC 50 of substrate 21-1 is electrically connected to the driver IC 11 via a connecting wiring 25 provided on the first flexible printed circuit board 22A.

[0098] The second wiring 14b, connected to the final stage pixel IC 50 of substrate 21-1, is connected to the left end of the third wiring 14c. The third wiring 14c extends in the first direction Dx along the first wiring 14a. The right end of the third wiring 14c is electrically connected to the first stage pixel IC 50 of the adjacent substrate 21-2 via a connecting wiring 25 provided on the first flexible printed circuit board 22A.

[0099] The second wiring 14b, connected to the final stage pixel IC 50 of substrate 21-2, is connected to the left end of the third wiring 14c. The third wiring 14c extends in the first direction Dx along the first wiring 14a. The right end of the third wiring 14c is electrically connected to the first stage pixel IC 50 of the adjacent substrate 21-3 via a connecting wiring 25 provided on the first flexible printed circuit board 22A.

[0100] From board 21-3 to the final stage board 21-32, the wiring 14 is connected in a meander pattern along the second direction Dy through the first flexible printed circuit board 22A. The wiring 14 is not connected to the second flexible printed circuit board 22B. The second flexible printed circuit board 22B does not have connecting wiring 25 for connecting the wiring 14 to each other. However, the second flexible printed circuit board 22B may have connecting wiring 25 in the same way as the first flexible printed circuit board 22A.

[0101] In the second modified example, the wiring 14 is folded back and provided within each of the multiple substrates 21. In the multiple substrates 21 arranged in the second direction Dy, the wiring 14 provided on each of the multiple substrates 21 is connected to each other along the second direction Dy through either the first flexible printed circuit board 22A or the second flexible printed circuit board 22B. In the example shown in Figure 10, adjacent substrates 21 are connected only through the first flexible printed circuit board 22A of the two flexible printed circuit boards 22B.

[0102] This allows the wiring patterns 14 of each of the multiple substrates 21 to be the same. Furthermore, the connection configuration between adjacent substrates 21 and the flexible printed circuit board 22 can be made the same for each of the multiple substrates 21 arranged in the second direction Dy. Therefore, in the second modified example, the manufacturing cost of the multiple adjacent substrates 21, and the cost required for connecting and assembling the multiple substrates 21 can be reduced.

[0103] In Figure 10, a configuration was described in which the wiring 14 provided on each of the multiple substrates 21 arranged in the second direction Dy is connected to each other through the first flexible printed circuit board 22A, but the configuration is not limited to this. The wiring 14 provided on each of the multiple substrates 21 arranged in the second direction Dy may also be connected to each other through the second flexible printed circuit board 22B.

[0104] (Third Modification of the First Embodiment) Figure 11 is a schematic plan view showing an example of the configuration of a display device according to the third modification of the first embodiment. As shown in Figure 11, in the display device 1C according to the second modification, two rows of pixel ICs 50 are provided on each of the multiple substrates 21.

[0105] On a single substrate 21 (for example, substrate 21-1), the first wiring 14a connects multiple pixel ICs 50 arranged in the first direction Dx in the first row. The third wiring 14c connects multiple pixel ICs 50 arranged in the first direction Dx in the second row. The second wiring 14b connects the left ends of the first wiring 14a and the third wiring 14c. As a result, the pixel ICs 50 arranged in two rows on a single substrate 21 are connected in series by the first wiring 14a, the second wiring 14b, and the third wiring 14c, which are provided in a folded manner. Of the pixel ICs 50 connected in series on a single substrate 21 (for example, substrate 21-1), the pixel IC 50 located in the upper right corresponds to the first stage pixel IC 50, and the pixel IC 50 located in the lower right corresponds to the final stage pixel IC 50.

[0106] Furthermore, the connection configuration of the multiple substrates 21 is the same as in the second modified example described above. The wiring 14 provided on each of the multiple substrates 21 arranged in the second direction Dy is connected to each other through the first flexible printed circuit board 22A.

[0107] In this modified example, the number of pixel ICs 50 arranged in one row is the same as in the first embodiment (or second modified example) described above. That is, in this modified example, the number of multiple pixel ICs 50 arranged on one substrate 21 is greater than in the first embodiment (or second modified example) described above. The number of pixel ICs 50 arranged in one row is, for example, 64. The number of multiple pixel ICs 50 arranged on one substrate 21 is, for example, 128.

[0108] Therefore, in this modified example, when the total number of pixel ICs 50 is the same as in the first embodiment (or second modified example) described above, the number of substrates 21 can be reduced. For example, the number of substrates 21 in this modified example is 16. Therefore, in this modified example, manufacturing costs can be reduced. In addition, in this modified example, the total length of the wiring 14 can be shortened, and voltage fluctuations and delays in the clock signal CK and image data DT due to wiring resistance can be suppressed.

[0109] (Second Embodiment) Figure 12 is a schematic plan view showing an example of the configuration of a display device according to the second embodiment. As shown in Figure 12, the display device 1D according to the second embodiment has a plurality of first pixel ICs 71 arranged in a matrix on each of a plurality of substrates 21. The plurality of first pixel ICs 71 are arranged on one substrate 21 in a first direction Dx and a second direction Dy.

[0110] The circuit configuration of the first pixel IC 71 and the connection configuration between the multiple first pixel ICs 71 in this embodiment are the same as in the first embodiment described above (see Figures 4 to 6), and a repeated explanation will be omitted. Also, although not shown in Figure 12, multiple light-emitting elements 3 are connected to each of the multiple first pixel ICs 71. The configuration of the multiple first pixel ICs 71 and the multiple light-emitting elements 3 is also the same as in the first embodiment described above (see Figure 3 or Figure 8), and a repeated explanation will be omitted. Also, although the power supply wiring 19 is not shown in Figure 12, the power supply potential and reference potential GND are supplied to each of the multiple first pixel ICs 71 via the power supply wiring 19, similar to the first embodiment described above.

[0111] On one substrate 21, the number of first pixel ICs 71 arranged in the first direction Dx is, for example, 512. The number of first pixel ICs 71 arranged in the second direction Dy is, for example, 4. The total number of first pixel ICs 71 arranged in a matrix on one substrate 21 is 512 × 4 = 2048.

[0112] Each of the multiple substrates 21 extends in a first direction Dx and is arranged in a second direction Dy. The number of multiple substrates 21-1, 21-2, ..., 21-64 arranged in the second direction Dy is 64. That is, in the entire display device 1D, the number of first pixel ICs 71 is 512 × 4 × 64 = 131,072, and the number of light-emitting elements 3 (light-emitting elements 3R, 3G, 3B) is 131,072 × 3 = 393,216. In this embodiment, the display resolution can be increased compared to the first embodiment described above.

[0113] On a single substrate 21, multiple first pixel ICs 71 are connected in series in a meander configuration. That is, the wiring 15 (clock signal supply wiring 12 and image data supply wiring 13 (see Figure 5)) includes a first wiring 15a, a second wiring 15b, and a third wiring 15c.

[0114] The first wiring 15a extends in the first direction Dx and connects multiple first pixel ICs 71 arranged in the first direction Dx. Multiple first wirings 15a are arranged in the second direction Dy, corresponding to multiple first pixel ICs 71 in each row arranged in the second direction Dy. The second wiring 15b connects the left ends of multiple adjacent first wirings 15a in the second direction Dy. The third wiring 15c connects the right ends of multiple adjacent first wirings 15a in the second direction Dy. Along the second direction Dy, the second wiring 15b and the third wiring 15c alternately connect the first wirings 15a.

[0115] In the example shown in Figure 12, among the multiple first pixel ICs 71 arranged on a single substrate 21, the first pixel IC 71 located in the upper right corresponds to the first stage first pixel IC 71, and the first pixel IC 71 located in the lower right corresponds to the final stage first pixel IC 71.

[0116] In this embodiment, multiple wirings 15-1, 15-2, ..., 15-64 are provided corresponding to each of the multiple substrates 21-1, 21-2, ..., 21-64. In other words, multiple first pixel ICs 71 connected in series on each of the multiple substrates 21 are connected in parallel to the driver IC 11.

[0117] Multiple wirings 15-1, 15-2, ..., 15-64 are arranged in the first direction Dx at one end of the substrate 21 in the first direction Dx (the right end in Figure 12), and each extends in the second direction Dy. Of the multiple wirings 15, wirings 15-2, ..., 15-64 extend across multiple substrates 21 and multiple flexible printed circuit boards 22 arranged in the second direction Dy. Specifically, wiring 15-1 of the multiple wirings 15 is connected from the driver IC 11 to the first pixel IC 71 of the first stage provided on substrate 21-1 via a connection wiring 25 provided on the first flexible printed circuit board 22A.

[0118] Wiring 15-2 is connected from the driver IC 11 to the first pixel IC 71 of the first stage provided on board 21-2 via connection wiring 25 provided on board 21-1 and the first flexible printed circuit board 22A. Similarly, wirings 15-3 to 15-64 extend in the second direction Dy across multiple boards 21 and multiple first flexible printed circuit boards 22A, and are connected to the first pixel IC 71 of the first stage on the corresponding board 21.

[0119] On each of the multiple substrates 21, the first stage of the multiple first pixel ICs 71 has its clock signal input terminal 51 and image data input terminal 52 (see Figures 5 and 6) connected to the driver IC 11. As a result, the driver IC 11 supplies the clock signal CK and image data DT to the multiple first pixel ICs 71 provided on each of the multiple substrates 21. The driver IC 11 supplies the clock signal CK and image data DT to the multiple first pixel ICs 71 provided on each of the multiple substrates 21 arranged in the second direction Dy in a synchronized manner.

[0120] As described above, in the second embodiment, the display resolution can be increased by increasing the number of substrates 21 and the number of first pixel ICs 71 provided on each of the substrates 21. Furthermore, the multiple first pixel ICs 71 provided on each of the substrates 21 and connected in series can drive multiple light-emitting elements 3 based on the clock signal CK and image data DT supplied from the driver IC 11.

[0121] (Fourth Modification of the Second Embodiment) Figure 13 is a schematic plan view showing an example of the configuration of a display device according to the fourth modification of the second embodiment. As shown in Figure 13, the display device 1E according to the fourth modification of the second embodiment further has a second pixel IC 72 compared to the second embodiment described above.

[0122] Multiple second pixel ICs 72 are provided on each of the multiple substrates 21 and are arranged in the first direction Dx between flexible printed circuit boards 22 adjacent in the second direction Dy. Multiple second pixel ICs 72 are connected to each of the multiple wirings 15 that connect the substrates 21. When the number of substrates 21 is n, the number of wirings 15 is also n. The first stage substrate 21-1 has (n-1) second pixel ICs 72. The next stage substrate 21-2 has (n-2) second pixel ICs 72. On substrates 21-2, ..., 21-64, the further away from the driver IC 11, the fewer second pixel ICs 72 are arranged on a single substrate 21.

[0123] Furthermore, the second pixel IC 72 is not connected to the wiring 15-1 corresponding to the first stage board 21-1. Of the multiple first pixel ICs 71 arranged on the first stage board 21-1, the first pixel IC 71 of the first stage is connected to the driver IC 11 without going through the second pixel IC 72.

[0124] In boards 21-2 to 21-64, which are located further from the driver IC 11 than the first stage board 21-1, the first stage first pixel IC 71 of the multiple first pixel ICs 71 is connected to the driver IC 11 via a second pixel IC 72. More specifically, the first stage first pixel IC 71 located on board 21-2 is connected to the driver IC 11 via wiring 15-2 and one second pixel IC 72 located on board 21-1.

[0125] The first pixel IC 71 of the first stage, located on substrate 21-3 (not shown), is connected to the driver IC 11 via wiring 15-3 and two second pixel ICs 72 located on substrates 21-1 and 21-2.

[0126] Similarly, the first pixel IC 71 of the first stage, located on the nth stage board 21-n, is connected to the driver IC 11 via wiring 15-n and (n-1) second pixel ICs 72. The (n-1) second pixel ICs 72 corresponding to the nth stage board 21-n are located on boards 21-1 to 21-(n-1) respectively and are connected in series by wiring 15-n and multiple flexible printed circuit boards 22.

[0127] Furthermore, among the multiple wirings 15, wirings 15-2 to 15-64 connect adjacent first pixel ICs 71 and electrically connect the first stage first pixel IC 71 and the driver IC 11 via the second pixel IC 72. However, among the multiple wirings 15, wiring 15-1 connects adjacent first pixel ICs 71 and electrically connects the first stage first pixel IC 71 and the driver IC 11 without going through the second pixel IC 72. As a result, the clock signal CK and image data DT are supplied from the driver IC 11 to the multiple first pixel ICs 71 via the second pixel IC 72. Also, the second pixel IC 72 and dummy IC 72D are not placed on the final stage substrate 21-64.

[0128] The circuit configuration of the second pixel IC 72 is the same as that of the pixel IC 50 (see Figure 6) and the first pixel IC 71. The second pixel IC 72 corrects and outputs voltage fluctuations of the clock signal CK caused by resistors such as wiring 15 connecting multiple boards 21, using the buffer circuit 61 (see Figure 6) that the second pixel IC 72 has.

[0129] This makes it possible to suppress fluctuations in the waveform of the clock signal CK from the first stage board 21-1, which is closest to the driver IC 11, to the final stage board 21-64, which is furthest from the driver IC 11. Therefore, the display device 1E can display images well even when the display resolution is increased by increasing the number of boards 21 and the number of first pixel ICs 71 provided on each of the boards 21.

[0130] Furthermore, on board 21-2, multiple second pixel ICs 72 corresponding to the next stage board 21 and one dummy IC 72D are arranged. The dummy IC 72D is placed in the first direction Dx between the multiple second pixel ICs 72 and the multiple first pixel ICs 71. The dummy IC 72D has the same circuit configuration as the second pixel ICs 72 but is not connected to any other wiring. From board 21-2 to board 21-63, the number of second pixel ICs 72 decreases by one each time, and the number of dummy ICs 72D increases by one each time. That is, the total number of second pixel ICs 72 and dummy ICs 72D remains constant on each of the multiple boards 21. However, the final stage board 21-64 does not have any second pixel ICs 72 or dummy ICs 72D.

[0131] Furthermore, the second pixel IC 72 is not connected to the light-emitting element 3 (display element). In other words, the control circuit 65, PWM control circuit 66, memory circuit 67, and light-emitting element driving circuit 68 (see Figure 6) of the second pixel IC 72, which are related to driving the light-emitting element 3, are not in operation.

[0132] (Fifth Modification of the Second Embodiment) Figure 14 is a schematic plan view showing an example of the configuration of a display device according to the fifth modification of the second embodiment. As shown in Figure 14, in the display device 1F according to the fifth modification of the second embodiment, each of the plurality of first flexible printed circuit boards 22A has connecting wiring 25 that connects a plurality of adjacent boards 21, and the connecting wiring 25 extends in an oblique direction that is inclined with respect to the first direction Dx.

[0133] For example, regarding the wiring 15-2 corresponding to the board 21-2, the wiring 15-2 connected to the first pixel IC 71 of the first stage of board 21-2 is shifted to one side (right) of the first direction Dx through the connection wiring 25 of the first flexible printed circuit board 22A and is electrically connected to the wiring 15-2 provided on board 21-1. The wiring 15-2 provided on board 21-1 is further shifted to one side (right) of the first direction Dx through the connection wiring 25 of the first flexible printed circuit board 22A and is connected to the driver IC 11.

[0134] Thus, the wiring 15-n corresponding to the nth stage board 21-n shifts to one side (right) of the first direction Dx as it approaches the driver IC 11 in the second direction Dy, that is, as it passes through the connection wiring 25 of the first flexible printed circuit board 22A. In other words, the wiring 15-n shifts to the other side (left) of the first direction Dx as it moves away from the driver IC 11 in the second direction Dy, that is, as it passes through the connection wiring 25 of the first flexible printed circuit board 22A, as it approaches the multiple first pixel ICs 71, and connects to the first stage first pixel IC 71 on the nth stage board 21-n.

[0135] As a result, in this modified example, the wiring patterns on each of the multiple substrates 21 can be formed identically. In this modified example, the manufacturing cost of the substrates 21 can be reduced.

[0136] Similar to the fourth modification described above, the further a substrate 21 is located from the driver IC 11, the fewer second pixel ICs 72 are placed on a single substrate 21. Also, the further a substrate 21 is located from the driver IC 11, the more connection terminals 73 on which the second pixel ICs 72 are not mounted increase.

[0137] For example, on board 21-1, (n-1) second pixel ICs 72 are arranged, on board 21-2, (n-2) second pixel ICs 72 are arranged, and on the final stage board 21-2, the number of second pixel ICs 72 is 0. In the fifth modification, an example is shown where no second pixel ICs 72 are mounted on the connection terminal 73 on board 21, which is located away from the driver IC 11. However, as in the fourth modification, a dummy IC 72D may be provided.

[0138] (Sixth Modification of the Second Embodiment) Figure 15 is a schematic plan view showing an example of the configuration of a display device according to the sixth modification of the second embodiment. As shown in Figure 15, in the display device 1G according to the sixth modification of the second embodiment, the wiring 15 connected to the second pixel IC 72 extends in the second direction Dy and is arranged to be shifted in the first direction Dx.

[0139] More specifically, as described above, the multiple wirings 15 (wirings 15-2 to 15-64) are provided to electrically connect the first pixel IC 71 and the driver IC 11 via the second pixel IC 72. On each of the multiple substrates 21, the multiple wirings 15 include a portion that extends in the second direction Dy and connects to the second pixel IC 72, a portion that extends in the first direction Dx, and a portion that extends in the second direction Dy and connects to the first flexible printed circuit board 22A provided between the substrate 21 and the next stage substrate 21. The connecting wiring 25 provided on the first flexible printed circuit board 22A extends in the second direction Dy.

[0140] In the sixth modification, the wiring 15-n corresponding to the nth stage substrate 21-n shifts to the other side (left side) of the first direction Dx for each of the multiple substrates 21 as it moves away from the driver IC 11 in the second direction Dy. On the nth stage substrate 21-n, the wiring 15-n is located at the first pixel IC 71 of the first stage and is connected to the first pixel IC 71 of the first stage. As a result, in this modification, the wiring patterns on each of the multiple substrates 21 can be formed equally. Therefore, the manufacturing cost of the substrates 21 can be reduced in this modification.

[0141] (Seventh Modification of the Second Embodiment) Figure 16 is a schematic plan view showing an example of the configuration of a display device according to the seventh modification of the second embodiment. As shown in Figure 16, the display device 1H according to the seventh modification of the second embodiment has a plurality of driver ICs 11A, 11B, 11C, and 11D. The plurality of driver ICs 11A, 11B, 11C, and 11D are provided corresponding to the corners of the overall shape formed by the plurality of substrates 21.

[0142] Driver IC 11A is located in the upper right corner of the multiple boards 21. Driver IC 11B is located in the lower right corner of the multiple boards 21. Driver IC 11C is located in the upper left corner of the multiple boards 21. Driver IC 11D is located in the lower left corner of the multiple boards 21.

[0143] On each of the multiple substrates 21, a plurality of first pixel ICs 71 arranged on one side (right side) of the first direction Dx are designated as the first pixel IC group 71G-1. A plurality of first pixel ICs 71 arranged on the other side (left side) of the first direction Dx are designated as the second pixel IC group 71G-2. The number of first pixel ICs 71 in the first pixel IC group 71G-1 is, for example, 512 × 4 = 2028. The number of first pixel ICs 71 in the second pixel IC group 71G-2 is, for example, 512 × 4 = 2028.

[0144] Each of the multiple substrates 21 extends in a first direction Dx and is arranged in a second direction Dy. The number of multiple substrates 21-1, 21-2, ..., 21-128 arranged in the second direction Dy is 128.

[0145] Of the multiple substrates 21, the first pixel IC group 71G-1 located on substrates 21-1 to 21-64 is connected to the driver IC 11A located in the upper right via wiring 15. The first pixel IC group 71G-1 located on substrates 21-1 to 21-64 is supplied with a clock signal CK and image data DT from the driver IC 11A.

[0146] Of the multiple substrates 21, the first pixel IC group 71G-1 located on substrates 21-65 to 21-128 is connected to the driver IC 11B located in the lower right via wiring 15. The first pixel IC group 71G-1 located on substrates 21-65 to 21-128 is supplied with a clock signal CK and image data DT from the driver IC 11B.

[0147] Of the multiple substrates 21, the second pixel IC group 71G-2 located on substrates 21-1 to 21-64 is connected to the driver IC 11C located in the upper left via wiring 15. The second pixel IC group 71G-2 located on substrates 21-1 to 21-64 is supplied with a clock signal CK and image data DT from the driver IC 11C.

[0148] Of the multiple substrates 21, the second pixel IC group 71G-2 located on substrates 21-65 to 21-128 is connected to the driver IC 11D located in the lower left via wiring 15. The second pixel IC group 71G-2 located on substrates 21-65 to 21-128 is supplied with a clock signal CK and image data DT from the driver IC 11D.

[0149] In this modified example, the multiple driver ICs 11A, 11B, 11C, and 11D are controlled synchronously by the host 101 (see Figures 3, 12, etc.). As a result, the multiple first pixel ICs 71 and light-emitting elements 3 (not shown in Figure 16) connected to each of the driver ICs 11A, 11B, 11C, and 11D are driven to form a single display surface.

[0150] In this modified example, since it has multiple driver ICs 11A, 11B, 11C, and 11D, high-resolution display can be achieved.

[0151] In the seventh modified example, the connection configuration of the multiple driver ICs 11A, 11B, 11C, 11D, the multiple substrates 21, and the multiple flexible printed circuit boards 22 can be any of the second embodiment and the fourth to sixth modified examples described above.

[0152] In the embodiments and modifications described above, the configuration in which the multiple flexible printed circuit boards 22 are connected is described as connecting the long sides of the substrate 21 that extends in the first direction Dx, but this is not limited to this. The flexible printed circuit boards 22 may also be connected by connecting the short sides of the substrate 21 that extends in the first direction Dx.

[0153] For example, in the seventh modified example shown in Figure 16, two or more substrates 21 are arranged in the first direction Dx, and a first pixel IC group 71G-1 may be provided on one of the two substrates 21 adjacent to each other in the first direction Dx, and a second pixel IC group 71G-2 may be provided on the other substrate 21. In this case, the two substrates 21 adjacent to each other in the first direction Dx are connected by a flexible printed circuit board 22, and the two substrates 21 adjacent to each other in the second direction Dy may also be connected by a flexible printed circuit board 22.

[0154] While preferred embodiments of this disclosure have been described above, this disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of this disclosure. Any modifications made without departing from the spirit of this disclosure will naturally fall within the technical scope of this disclosure. At least one of various omissions, substitutions, and modifications of components can be made without departing from the gist of each embodiment and each modification described above.

[0155] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H Display device 3, 3B, 3G, 3R Light-emitting element 11, 11A, 11B, 11C, 11D Driver IC 12, 12-1, 12-2, 12-3, 12-4 Clock signal supply wiring 13, 13-1, 13-2, 13-3, 13-4 Image data supply wiring 14, 15 Wiring 17 Power supply potential supply wiring 18 Reference potential supply wiring 19 Power supply wiring 21 Board 22 Flexible printed circuit board 22A First flexible printed circuit board 22B Second flexible printed circuit board 25, 26 Connection wiring 50 Pixel IC 51 Clock signal input terminal 52 Image data input terminal 53 Clock signal output terminal 54 Image data output terminal 57, 58, 59 Connection terminals 71 First pixel IC 72 Second pixel IC 72D Dummy IC 73 Connection terminal 101 Host

Claims

1. The device comprises: a plurality of substrates; a plurality of flexible printed circuit boards connecting adjacent substrates among the plurality of substrates; a plurality of pixel ICs provided on each of the plurality of substrates; a plurality of display elements provided on each of the plurality of substrates and corresponding to each of the plurality of pixel ICs; and a drive circuit, wherein each of the plurality of pixel ICs has a clock signal input terminal into which a clock signal is input, an image data input terminal into which image data is input, a clock signal output terminal for outputting the clock signal, an image data output terminal for outputting the image data, and a connection terminal connected to at least one of the display elements, the plurality of pixel ICs are connected in series, the clock signal input terminal and the image data input terminal of the first stage pixel IC among the plurality of pixel ICs connected in series are connected to the drive circuit, and the clock signal output terminal and the image data output terminal are connected to the next stage pixel IC. A display device in which the clock signal output terminal and the image data output terminal of the final stage pixel IC provided on one of the adjacent substrates are connected via the flexible printed circuit board to the clock signal input terminal and the image data input terminal of the first stage pixel IC provided on the other of the adjacent substrates.

2. The display device according to claim 1, wherein each of the plurality of substrates extends in a first direction and is arranged in a second direction intersecting the first direction.

3. The display device according to claim 2, wherein the plurality of flexible printed circuit boards include a first flexible printed circuit board and a second flexible printed circuit board, and one end of each of the adjacent boards in the first direction is connected by the first flexible printed circuit board, and the other end in the first direction is connected by the second flexible printed circuit board.

4. The display device according to claim 3, wherein the plurality of substrates, arranged in the second direction, have a plurality of wirings connecting the plurality of pixel ICs, and the wirings provided on each of the plurality of substrates are connected to each other along the second direction, through either the first flexible printed circuit board or the second flexible printed circuit board.

5. The display device according to claim 3, having a plurality of wirings connecting the plurality of pixel ICs, wherein the plurality of substrates arranged in the second direction, the wirings provided on each of the plurality of substrates are connected along the second direction, alternately passing through the first flexible printed circuit board and the second flexible printed circuit board.

6. The display device according to claim 1, wherein the plurality of pixel ICs provided on each of the plurality of substrates are supplied with power from the drive circuit.

7. The display device according to claim 1, wherein the display element includes a plurality of self-luminous elements that emit red light, green light, and blue light.

8. The display device according to claim 1, wherein the image data transmitted from the drive circuit includes data for lighting up a plurality of display elements provided corresponding to each of the plurality of pixel ICs connected in series.

9. A display device comprising: a plurality of substrates; a plurality of flexible printed circuit boards connecting adjacent substrates among the plurality of substrates; a plurality of first pixel ICs provided on each of the plurality of substrates; a plurality of display elements provided on each of the plurality of substrates and corresponding to each of the plurality of first pixel ICs; and a drive circuit, wherein each of the plurality of first pixel ICs has a clock signal input terminal into which a clock signal is input, an image data input terminal into which image data is input, a clock signal output terminal for outputting the clock signal, an image data output terminal for outputting the image data, and a connection terminal connected to at least one of the display elements; the plurality of first pixel ICs are connected in series on each of the plurality of substrates; and on each of the plurality of substrates, the clock signal input terminal and the image data input terminal of the first stage first pixel IC among the plurality of first pixel ICs are connected to the drive circuit, and the clock signal and the image data are supplied from the drive circuit.

10. The display device according to claim 9, further comprising a second pixel IC disposed on at least one of the plurality of substrates, wherein when the substrate closest to the drive circuit is designated as the first stage substrate, in each of the plurality of substrates located further from the drive circuit than the first stage substrate, the first pixel IC of the plurality of first pixel ICs is connected to the drive circuit via the second pixel IC, and the clock signal and the image data are supplied to the plurality of first pixel ICs via the second pixel IC.

11. The display device according to claim 10, wherein the display element is not connected to the second pixel IC.

12. The display device according to claim 10, wherein the number of second pixel ICs arranged on one substrate is less for substrates that are located further away from the drive circuit.

13. The display device according to claim 9, wherein each of the plurality of substrates extends in a first direction and is arranged in a second direction perpendicular to the first direction, each of the plurality of flexible printed circuit boards has connecting wiring for connecting adjacent substrates, the connecting wiring extends in an oblique direction inclined with respect to the first direction, and the wiring patterns of each of the plurality of substrates are equivalent.

14. The display device according to claim 9, wherein each of the plurality of substrates extends in a first direction and is arranged in a second direction perpendicular to the first direction, each of the plurality of substrates has wiring for electrically connecting the first pixel IC and the drive circuit, the wiring extends in the second direction and is arranged to be shifted in the first direction on each of the plurality of substrates, and the wiring patterns on each of the plurality of substrates are the same.

15. The display device according to claim 9, wherein each of the plurality of substrates extends in a first direction and is arranged in a second direction intersecting the first direction.

16. The display device according to claim 9, wherein it has a plurality of drive circuits, each of the plurality of substrates extends in a first direction and is arranged in a second direction perpendicular to the first direction, and the plurality of drive circuits are provided corresponding to the corners of the overall shape formed by the plurality of substrates.

17. The display device according to claim 9, wherein the plurality of first pixel ICs provided on each of the plurality of substrates are supplied with power from the drive circuit.

18. The display device according to claim 9, wherein the display element includes a plurality of self-luminous elements that emit red light, green light, and blue light.

19. The display device according to claim 9, wherein the image data transmitted from the drive circuit includes data for lighting up a plurality of display elements provided corresponding to each of the plurality of first pixel ICs connected in series.

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