Method for manufacturing memory cube

Abstract

This method for manufacturing a memory cube in which a plurality of substrates on which memories are formed are stacked includes: dividing each of a first base material and a second base material, each including a first surface and a second surface opposite to the first surface and on which memories are formed, into a plurality of substrates; bonding two different substrates among the plurality of substrates to form one bonded chip; forming a plurality of bonded chips, and bonding the plurality of bonded chips to form a stacked chip; and forming electrodes electrically connected to a plurality of wirings exposed on a side surface. Each of the plurality of substrates includes a third surface, a fourth surface opposite to the third surface, a side surface in contact with an end of the third surface and an end of the fourth surface, and a plurality of wirings exposed on the side surface. The angle between the side surface and the third surface is less than 90 degrees.

Description

Memory cube manufacturing method

[0001] One embodiment of the present invention relates to a method for manufacturing a memory cube.

[0002] In recent years, the volume of data communication in electronic computers such as data centers has increased. This increase in data communication has also led to a sharp rise in the power consumption of electronic computers. For example, an electronic computer includes multiple logic chips and multiple memory chips electrically connected to those logic chips. Logic chips are, for example, integrated circuit (IC) chips on which logic circuits are mounted, while memory chips are semiconductor chips on which memory circuits are mounted. For instance, stacking logic chips and memory chips in a three-dimensional configuration shortens the distance between logic chips and memory chips, which is an effective solution for reducing the power consumption of electronic computers.

[0003] For example, Patent Documents 1 to 5 and Non-Patent Documents 1 to 3 disclose, as an example of a three-dimensional mounting method, a method for mounting a semiconductor module in which a structure (vertically stacked memory cube) made of multiple memory chips stacked so that the multiple memory chips are parallel to the substrate or logic chip is placed on the substrate or logic chip, or a method for mounting a semiconductor module in which a structure (horizontally stacked memory cube) made of multiple memory chips stacked so that the multiple memory chips are perpendicular to the substrate or logic chip is vertically mounted (standing upright) on the substrate or logic chip.

[0004] Japanese Patent Publication No. 3-501428, International Publication No. 2021 / 095083, International Publication No. 2021 / 199447, International Publication No. 2024 / 057707, International Publication No. 2024 / 135670, Japanese Patent Publication No. 2020-194936

[0005] A. Agnesina et al. , “A Novel 3D DRAM Memory Cube Architecture for Space Applications,” 2018 55th ACM / ESDA / IEEE Design Automation Conference (DAC), (USA) June 2018, p. 1-6. R. W. Johnson, “3-D Packaging: A Technology Review,” p. 1-70, June 23, 2005. https: / / nepp. nasa. gov / doculoads / EA7E7EA1-BD30-4DA4-BD615FEA1A7F5AE9 / 3D%20Packaging%20Report%20071805. pdfR. M. Lea et al. , “3-D Stacked Chip Packaging Solution for Miniaturized Massively Parallel Processing,” IEEE Trans. Adv Packag. , (USA), August 1999, Vol. 22, no. 3, p. 424-432K. Kim et al. , “Plasma dicing before grinding process for highly reliable singulation of low-profile and large die sizes in advanced packages,” Micro and Nano Systems Letters, (USA), November 2023, Vol. 11, no. 16

[0006] On the other hand, for example, when stacking multiple IC chips and semiconductor chips in a 3D mounting method, misalignment between chips may impair electrical connections between chips. Also, for example, when stacking multiple IC chips and semiconductor chips in a 3D mounting method, the time required for stacking accounts for a large proportion of the time required for 3D mounting, which may reduce the throughput of 3D mounting.

[0007] In view of these problems, one embodiment of the present invention aims to provide a method for manufacturing a memory cube that can suppress misalignment between multiple chips. Another embodiment of the present invention aims to provide a memory cube that can suppress the time required for stacking. Another embodiment of the present invention aims to provide a method for manufacturing a semiconductor module that can suppress misalignment between multiple chips. Another embodiment of the present invention aims to provide a semiconductor module that can suppress the time required for stacking.

[0008] A method for manufacturing a memory cube according to one embodiment of the present invention includes dividing a first substrate and a second substrate on which the memory is formed into a plurality of substrates, each including a first surface and a second surface opposite to the first surface; joining two different substrates from the plurality of substrates to form a single bonding chip; forming a plurality of the single bonding chips, joining the plurality of bonding chips to form a laminated chip; and forming electrodes that are electrically connected to a plurality of wirings exposed on the side surface, wherein each of the plurality of substrates includes a third surface, a fourth surface opposite to the third surface, the end of the third surface and the side surface in contact with the end of the fourth surface, and the plurality of wirings exposed on the side surface, and having a first adhesive film made of an organic resin as a base material on part or all of the bonding interface of the bonding chip and the laminated chip, the first adhesive film is separated from the wiring exposed on the side surface of the bonding chip and the laminated chip by molding.

[0009] The method may further include forming grooves on the second surface by plasma grooving before the division, and then forming an inorganic insulating film on the second surface and on the grooves.

[0010] The method may further include forming the inorganic insulating film, and then attaching the first adhesive film to the inorganic insulating film on the second surface to form the fourth surface.

[0011] The division may include grinding and polishing the first surface to form the third surface.

[0012] The process further includes subjecting the first adhesive film on the plurality of substrates to plasma activation or vacuum ultraviolet treatment before forming the bonding chip, and forming the bonding chip may include bonding the first adhesive films on two different substrates by thermocompression bonding.

[0013] The plurality of bonding chips include a first bonding chip and a second bonding chip, and forming the laminated chip may include applying a liquid to a third surface of the second substrate of the second bonding chip and bonding the third surface to which the liquid has been applied to the third surface of the first substrate of the first bonding chip by self-assembly.

[0014] Forming the laminated chip may involve, after joining the plurality of bonding chips by the self-assembly, applying a UV-curing resin between the third surface of the second substrate of the second bonding chip and the third surface of the first substrate of the first bonding chip.

[0015] Forming the laminated chip may include joining the plurality of bonding chips by the self-assembly method, and then applying the UV-curing resin to the corners of the joined plurality of bonding chips.

[0016] The method may further include forming grooves on the second surface by plasma grooving before the division, forming an inorganic insulating film on the second surface and on the grooves to form the fourth surface, and grinding and polishing the first surface after the inorganic insulating film has been formed.

[0017] The division may include forming the third surface by attaching an adhesive film to the ground and polished surface after grinding and polishing, oxidizing the ground and polished surface, and, after the oxidation, using a laser, expander, or plasma etching to divide the inorganic insulating film and the first adhesive film along the groove in a direction from the fourth surface toward the third surface.

[0018] Prior to forming the bonded chip, the third surface of one of the two distinct substrates and the fourth surface of the remaining substrate may be subjected to plasma activation or vacuum ultraviolet treatment, and forming the bonded chip may include low-temperature bonding with the third surface of the one substrate and the fourth surface of the remaining substrate facing each other.

[0019] Forming the aforementioned laminated chip may include joining the plurality of bonded chips in a vacuum or under a high-pressure atmosphere.

[0020] Forming the stacked chip may further include forming bumps on the bottom surface of the stacked chip.

[0021] The division may include grinding and polishing the first surface of the first substrate, attaching a second adhesive film to the ground and polished surface to form a third surface of the first substrate, oxidizing the ground and polished surface, using a laser, expander, or plasma etching to divide the inorganic insulating film and the adhesive film along the groove of the first substrate in a direction from the fourth surface toward the third surface, and grinding and polishing the first surface of the second substrate to form a third surface of the second substrate.

[0022] One of the two distinct substrates is divided using the first substrate and includes a fourth surface and a third surface including the second adhesive film, and the other of the two distinct substrates is divided using the second substrate and includes a fourth surface and a third surface from which the first surface has been ground and polished, and forming the bonding chip may include bonding the second adhesive film of the one substrate to the third surface of the other substrate by heat-pressing.

[0023] The plurality of bonding chips include a first bonding chip and a second bonding chip, and forming the laminated chip may include bonding the fourth surface of the remaining substrate of the second bonding chip to the fourth surface of one of the substrates of the first bonding chip using plasma activation.

[0024] Forming the stacked chip may include, after joining the plurality of bonding chips, sandwiching the joined plurality of bonding chips between two different third substrates on which the memory is not formed.

[0025] The plurality of bonding chips include a first bonding chip and a second bonding chip, and forming the laminated chip may include: placing the plurality of bonding chips in a jig that can vibrate and pressurize; vibrating the jig and pressing the plurality of bonding chips in a direction perpendicular to the third surface; applying UV-curing resin to three of the four corners of the bonded plurality of bonding chips that are separated from the jig; and applying the UV-curing resin between the fourth surface of the second substrate of the second bonding chip and the fourth surface of the first substrate of the first bonding chip.

[0026] A method for manufacturing a memory cube according to one embodiment of the present invention is a method for manufacturing a memory cube in which a plurality of substrates on which a memory is formed are stacked, and each of the plurality of substrates includes a first surface and a second surface opposite to the first surface, and the second surfaces of the first substrate and the second substrate on which the memory is formed are joined together; grinding and polishing the first surface of the second substrate to form a third surface; forming grooves on the third surface by plasma grooving, and then forming an inorganic film on the third surface and on the grooves; grinding and polishing the first surface of the first substrate to form a fourth surface and form a plurality of bonding chips; joining the plurality of bonding chips to form a stacked chip; and forming electrodes that are electrically connected to a plurality of wirings exposed on the side surface in contact with the end of the third surface and the end of the fourth surface, wherein each of the plurality of bonding chips includes the side surface, and the angle between the side surface and the fourth surface is less than 90 degrees.

[0027] The plurality of bonding chips include a first bonding chip and a second bonding chip, and forming the laminated chip may include: placing the plurality of bonding chips in a jig that can vibrate and pressurize; vibrating the jig and pressing the plurality of bonding chips in a direction perpendicular to the third surface; applying UV-curing resin to three of the four corners of the bonded plurality of bonding chips that are separated from the jig; and applying the UV-curing resin between the fourth surface of the second bonding chip and the fourth surface of the first bonding chip.

[0028] The first adhesive film may be formed using photolithography.

[0029] Dividing the inorganic insulating film and the first adhesive film along the groove in a direction from the fourth surface to the third surface using the laser, the expander, or the plasma etching may include any one of the following processes: a first process of scanning the laser along the groove; a second process of scanning the laser along the groove, dividing the inorganic insulating film along the groove in a direction from the fourth surface to the third surface, and etching the first adhesive film exposed in the groove in a direction from the fourth surface to the third surface using the plasma etching; and a third process of dividing the inorganic insulating film along the groove in a direction from the fourth surface to the third surface using dicing, and expanding by stretching the dicing tape attached to the first adhesive film to widen the spacing between the multiple substrates.

[0030] Dividing the inorganic insulating film and the second adhesive film along the groove of the first substrate in a direction from the fourth surface to the third surface using the laser, the expander, or the plasma etching may include any one of the following processes: a first process of scanning the laser along the groove; a second process of scanning the laser along the groove, dividing the inorganic insulating film along the groove in a direction from the fourth surface to the third surface; and etching the first adhesive film exposed in the groove in a direction from the fourth surface to the third surface using the plasma etching; and a third process of dividing the inorganic insulating film along the groove in a direction from the fourth surface to the third surface using dicing, and expanding by stretching a dicing tape attached to the second adhesive film to widen the spacing between the multiple substrates.

[0031] The UV-curing resin may be applied using a dispenser.

[0032] This is a perspective view showing the configuration of a memory cube according to the first embodiment of the present invention. This is an end view showing the cross-sectional structure of the end of the memory cube along the line A1-A2 shown in Figure 1. This is an end view showing the cross-sectional structure of the end of the memory cube along the line B1-B2 shown in Figure 1. This is a perspective view showing the configuration of an IC chip according to the first embodiment of the present invention. This is an end view showing the cross-sectional structure of the end of the IC chip along the line C1-C2 shown in Figure 3. This is a flowchart showing the manufacturing method of a memory cube according to the first embodiment of the present invention. This is a plan view showing the manufacturing method of a memory cube according to the first embodiment of the present invention. This is a plan view and end view showing the manufacturing method of a memory cube according to the first embodiment of the present invention. This is a plan view and end view showing the manufacturing method of a memory cube according to the first embodiment of the present invention. This is an end view showing the manufacturing method of a memory cube according to the first embodiment of the present invention. This is an end view showing the manufacturing method of a memory cube according to the first embodiment of the present invention. This is an end view showing the manufacturing method of a memory cube according to the first embodiment of the present invention. This is an end view showing the manufacturing method of a memory cube according to the first embodiment of the present invention. This is a perspective view showing the manufacturing method of a memory cube according to the first embodiment of the present invention. This is a perspective view showing a modified example of the manufacturing method of a memory cube according to the first embodiment of the present invention. This is a perspective view showing the configuration of a memory cube according to the second embodiment of the present invention. This is an end view showing the cross-sectional structure of the end of a memory cube along the line F1-F2 shown in Figure 16. This is an end view showing the cross-sectional structure of the end of a memory cube along the line G1-G2 shown in Figure 16. This is a perspective view showing the configuration of an IC chip according to the second embodiment of the present invention. This is an end view showing the cross-sectional structure of an IC chip along the line H1-H2 shown in Figure 18. This is a flowchart showing the manufacturing method of a memory cube according to the second embodiment of the present invention. This is a plan view and an end view showing the manufacturing method of a memory cube according to the second embodiment of the present invention. This is an end view showing the manufacturing method of a memory cube according to the second embodiment of the present invention. This is an end view showing the manufacturing method of a memory cube according to the second embodiment of the present invention. This is a perspective view showing the manufacturing method of a memory cube according to the second embodiment of the present invention.This is an end view showing a modified example of the memory cube according to the second embodiment of the present invention. This is an end view showing a modified example of the memory cube according to the second embodiment of the present invention. This is a perspective view showing the configuration of the memory cube according to the third embodiment of the present invention. This is an end view showing the end cross-sectional structure of the memory cube along the line J1-J2 shown in Figure 27. This is an end view showing the end cross-sectional structure of the memory cube along the line K1-K2 shown in Figure 27. This is a perspective view showing the configuration of the IC chip according to the third embodiment of the present invention. This is an end view showing the end cross-sectional structure of the IC chip along the line L1-L2 shown in Figure 29. This is a flowchart showing the manufacturing method of the memory cube according to the third embodiment of the present invention. This is an end view showing the manufacturing method of the memory cube according to the third embodiment of the present invention. This is an end view showing the manufacturing method of the memory cube according to the third embodiment of the present invention. This is an end view showing the manufacturing method of the memory cube according to the third embodiment of the present invention. This is an end view showing the manufacturing method of the memory cube according to the third embodiment of the present invention. This is a perspective view showing the manufacturing method of the memory cube according to the third embodiment of the present invention. This is a flowchart showing the manufacturing method of the memory cube according to the fourth embodiment of the present invention. This is a perspective view showing the manufacturing method of the memory cube according to the fourth embodiment of the present invention. This is a flowchart showing the manufacturing method of the memory cube according to the fifth embodiment of the present invention. This is a plan view and end view showing the manufacturing method of the memory cube according to the fifth embodiment of the present invention. This is an end view showing a method for manufacturing a memory cube according to the fifth embodiment of the present invention. This is an end view showing a method for manufacturing a memory cube according to the fifth embodiment of the present invention. This is an end view showing a method for manufacturing a memory cube according to the fifth embodiment of the present invention. This is a perspective view showing the configuration of a semiconductor module according to the sixth embodiment of the present invention. This is an end view showing the cross-sectional structure of the end of a semiconductor module along the N1-N2 line shown in Figure 45. This is a block diagram showing the configuration of a semiconductor module according to the sixth embodiment of the present invention. This is a perspective view showing a plurality of inductors included in a memory cube according to the sixth embodiment of the present invention and a plurality of inductors included in a first substrate. This is a block diagram showing the configuration of a stacked memory chip according to the sixth embodiment of the present invention.This is a perspective view showing the configuration of a semiconductor module according to the seventh embodiment of the present invention. This is a block diagram showing the configuration of a semiconductor module according to the seventh embodiment of the present invention. This is a block diagram showing the configuration of a memory cube and a redistribution layer according to the seventh embodiment of the present invention. This is an end view showing the end cross-sectional structure of an example of mounting a semiconductor module according to the seventh embodiment of the present invention. This is an end view showing the end cross-sectional structure of an example of mounting a semiconductor module according to the seventh embodiment of the present invention. This is an end view showing the end cross-sectional structure of an example of mounting a semiconductor module according to the seventh embodiment of the present invention. This is a perspective view showing the configuration of a semiconductor module according to the eighth embodiment of the present invention. This is an end view showing the end cross-sectional structure of a semiconductor module along the O1-O2 line shown in Figure 56. This is a block diagram showing the configuration of a semiconductor module according to the eighth embodiment of the present invention. This is an end view showing the end cross-sectional structure of an example of mounting a semiconductor module according to the eighth embodiment of the present invention. This is a flowchart showing a method for manufacturing a memory cube according to the ninth embodiment of the present invention. This is a flowchart showing a modified example of the method for manufacturing a memory cube according to the ninth embodiment of the present invention.

[0033] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described below. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals (or numerals followed by a, b, etc.), and detailed explanations may be omitted as appropriate. Furthermore, the letters "First," "Second," etc., attached to each element are convenient indicators used to distinguish each element and have no further meaning unless specifically explained.

[0034] In one embodiment of the present invention, when a certain member or region is "above (or below)" another member or region, unless otherwise specifically limited, this includes not only the case where it is directly above (or directly below) the other member or region, but also the case where it is above (or below) the other member or region, that is, it also includes the case where another component is included between them above (or below) the other member or region.

[0035] In one embodiment of the present invention, the first direction D1 intersects the second direction D2, and the third direction D3 intersects the first direction D1 and the second direction D2 (D1D2 plane).

[0036] In one embodiment of the present invention, when the notations "same", "identical", and "coincident" are used, the "same", "identical", and "coincident" may include errors within the design range. Also, in one embodiment of the present invention, when errors within the design range are included, the expressions "substantially the same", "substantially identical", and "substantially coincident" may be used.

[0037] [First Embodiment] The memory cube 100 according to the first embodiment will be described with reference to FIGS. 1 to 15. <​​​As shown in Figure 1, Figure 2A, or Figure 2B, the memory cube 100 includes a stacked memory chip 30, a side power supply wiring 162 and a side ground wiring 163 electrically connected to the stacked memory chip 30. The memory cube 100 also includes a first outermost surface (first surface 146) and a second outermost surface (second surface 148) opposite to the first outermost surface, which are the two outermost surfaces in the third direction D3; a third outermost surface (third surface 145) and a fourth outermost surface (fourth surface 147) parallel to the third direction D3 and the first direction D1 and the two outermost surfaces in the second direction D2; and a fifth outermost surface (fifth surface 142) and a sixth outermost surface (sixth surface 144) parallel to the third direction D3 and the second direction D2 and the two outermost surfaces in the first direction D1. The stacked memory chip 30 may be referred to as a stacked chip, and the side grounding wiring 163 and side power wiring 162 may be referred to as a wiring layer, conductive film, conductive layer, electrode, etc.

[0040] The stacked memory chip 30 includes a plurality of bonding chips 20. Each of the plurality of bonding chips 20 includes two IC chips 110 including a plurality of power supply wirings 164, a plurality of ground wirings 165, a plurality of signal transmission wirings 166 (see FIG. 49), and a plurality of inductors 172. The two IC chips 110 are bonded. That is, the stacked memory chip 30 includes a plurality of IC chips 110. Although details will be described later, for example, the stacked memory chip 30 includes an adhesive film 140 having an organic resin as a base material. The adhesive film 140 is provided between the plurality of bonding chips 20 and between the plurality of IC chips 110. That is, the adhesive film 140 is provided on a part or all of the interfaces between the plurality of bonding chips 20 and on the interfaces or all of the interfaces between the plurality of IC chips 110. Although details will be described later, for example, the two IC chips 110 include an IC chip 110n (see FIG. 10) and 110n+1 (see FIG. 10) arranged adjacent to the IC chip 110n. The plurality of IC chips 110 may simply be referred to as a plurality of substrates. When each of the plurality of IC chips 110 is not distinguished, the IC chip is expressed as the IC chip 110. When each of the plurality of IC chips 110 is distinguished, the IC chip is denoted as the IC chip 110n, the IC chip 110n+1, etc. Similarly to the IC chip 110, when each of the plurality of bonding chips 20 is not distinguished, the bonding chip is expressed as the bonding chip 20. When each of the plurality of bonding chips 20 is distinguished, the bonding chip is denoted as the bonding chip 20n, the bonding chip 20n+1, etc. The same applies to each surface of the IC chip 110 and each surface of the bonding chip 20.

[0041] Further, the stacked memory chip 30 includes a first outermost surface (first surface 46) and a second outermost surface (second surface 48) which are two outermost surfaces in the third direction D3, a third outermost surface (third surface 45) and a fourth outermost surface (fourth surface 47) which are two outermost surfaces in the second direction D2 parallel to the third direction D3 and the first direction D�, and a fifth outermost surface (fifth surface 42) and a sixth outermost surface (sixth surface 44) which are two outermost surfaces in the first direction D1 parallel to the third direction D3 and the second direction D2.

[0042] The first face 46, second face 48, third face 45, fourth face 47, fifth face 42, and sixth face 44 of the stacked memory chip 30 are parallel to the first face 146, second face 148, third face 145, fourth face 147, fifth face 142, and sixth face 144 of the memory cube 100. For example, the first face 46 is parallel to the first face 146, and the second face 48 is parallel to the second face 148. The third faces 45 to 6th faces 44 and the third faces 145 to 6th faces 144 are also parallel to their respective faces, similar to the first face 46 and the first face 146, and the second face 48 and the second face 248. Also, the first face 146 is the same face as the first face 46. The first face 146 and the first face 46 are sometimes referred to as the bottom face.

[0043] As shown in Figure 1 or Figure 2A, the multiple power wirings 164 are exposed on the third surface 45 and the fourth surface 47 and are electrically connected to the side power wirings 162. The side power wirings 162 are in contact with the third surface 45 and the fourth surface 47 and are provided on top of the third surface 45 and the fourth surface 47. The side power wirings 162 are also in contact with the third surface 145 and the fourth surface 147. Furthermore, as shown in Figure 1, since the multiple power wirings 164 are electrically connected to the side power wirings 162, the multiple power wirings 164 do not overlap with the adhesive film 140 and are provided at a distance from the adhesive film 140. The adhesive film 140 is molded so as not to overlap with the multiple power wirings 164 and to be provided at a distance from the multiple power wirings 164.

[0044] As shown in Figure 1, Figure 2A, or Figure 2B, the multiple grounding wires 165 are exposed on the second surface 48 and electrically connected to the side grounding wires 163. The side grounding wires 163 are in contact with the second surface 48 and are provided on the second surface 48. The side grounding wires 163 are also in contact with the second surface 148. Also, similar to the multiple power supply wires 164, as shown in Figure 1, the multiple grounding wires 165 are electrically connected to the side grounding wires 163, so the multiple grounding wires 165 do not overlap with the adhesive film 140 and are provided at a distance from the adhesive film 140. Similar to the multiple power supply wires 164, the adhesive film 140 is molded so that it does not overlap with the multiple grounding wires 165 and is provided at a distance from the multiple grounding wires 165.

[0045] As shown in Figure 2A or Figure 2B, the multiple inductors 172 are arranged parallel to the first surface 46 for each IC chip 110 and spaced away from the first surface 46, and are arranged in a line along the second direction D2 for each IC chip 110. The inductors 172 may be provided across multiple IC chips 110, across one IC chip 110 and the redistribution layer 800 (see Figure 50), or across multiple IC chips 110 and the redistribution layer 800.

[0046] The side power wiring 162 has the function of supplying power voltage to multiple power wirings 164, and the side ground wiring 163 has the function of supplying ground voltage to multiple ground wirings 165. For example, the power voltage is voltage VDD, and the ground voltage is voltage VSS. For example, voltage VDD is a power voltage such as 1V or 3V, and voltage VSS is a ground voltage such as 0V. For example, the side power wiring 162 and the side ground wiring 163 are electrically connected to an external device (not shown). That is, the power voltage and ground voltage are supplied to the stacked memory chip 30 via the external device, the side power wiring 162, and the side ground wiring 163.

[0047] As shown in Figure 3 or Figure 4, the IC chip 110 includes a first surface 102 parallel to the second direction D2 and the third direction D3, a second surface 104 (21st surface 109) opposite to the first surface 102 with respect to the first direction D1, a first side surface 106 perpendicular to the first surface 102 and the second surface 104, a second side surface 105 adjacent to the first side surface 106, a third side surface 108 adjacent to the second side surface 105, a fourth side surface 107 adjacent to the third side surface 108 and the first side surface 106, a transistor layer 130, and a wiring layer 150. The first surface 102 is the surface opposite to the surface on which the wiring layer 150 is arranged relative to the transistor layer 130, and the second surface 104 (21st surface 109) is the surface opposite to the surface on which the transistor layer 130 is arranged relative to the wiring layer 150.

[0048] The third side surface 108 is in contact with the end of the first surface 102 and the end of the second surface 104 (21st surface 109), and has an inclined portion. Similarly to the third side surface 108, the second side surface 105 and the fourth side surface 107 are in contact with the end of the first surface 102 and the end of the second surface 104 (21st surface 109), and have inclined portions (see the end view showing the end cross-sectional structure of the memory cube along line B3-B4 in Figure 1, the end view showing the end cross-sectional structure of the memory cube along line B5-B6 in Figure 1, Figure 10, etc.).

[0049] For example, the angle between the first surface 102 and the third side surface 108 is angle α. Similarly, the angle between the second surface 104 and the third side surface 108, and the angle between the first surface 102 and the second side surface 105, and the angle between the first surface 102 and the fourth side surface 107 are also angles α. Angle α is greater than 0 degrees and less than 90 degrees.

[0050] In the example shown in Figure 4, the grounding wire 165 is exposed from the third side surface 108, and the power supply wire 164 is exposed from the second side surface 105 and the fourth side surface 107. The grounding wire 165 may be exposed from the second side surface 105 and the fourth side surface 107, and the power supply wire 164 may be exposed from the third side surface 108.

[0051] For example, the memory cube 100 includes bonding chips 20 joined so that their 21st faces 109 face each other, the first face 102 of the IC chip 110 corresponds to the 5th face 42 or the 6th face 44 of the stacked memory chip 30, the first side 106 of the IC chip 110 corresponds to the first face 46 of the stacked memory chip 30, the third side 108 of the IC chip 110 corresponds to the 2nd face 48 of the stacked memory chip 30, the second side 105 of the IC chip 110 corresponds to either the 4th face 47 or the 3rd face 45 of the stacked memory chip 30, and the 4th side 107 of the IC chip 110 corresponds to the remaining one of the 4th face 47 or the 3rd face 45 of the stacked memory chip 30. Note that depending on the configuration of the stacked memory chip 30 or bonding chip 20 included in the memory cube 100, the faces of the IC chip 110 corresponding to each face of the IC chip 110 may change. The first side 106 may be referred to as the bottom face, similar to the first face 146 and the first face 46.

[0052] As described above, for example, as shown in the end view showing the end cross-sectional structure of the memory cube along line B3-B4 in Figure 1, and the end view showing the end cross-sectional structure of the memory cube along line B5-B6 in Figure 1, the memory cube 100 includes a side grounding wire 163 that is in contact with the grounding wire 165 exposed on the third side surface 108 which has an inclined portion, and a side power supply wire 162 that is in contact with the power supply wire 164 exposed on the second side surface 105 which has an inclined portion and the fourth side surface 107 which has an inclined portion. That is, the grounding wire 165 and the power supply wire 164 are covered by the side grounding wire 163 and the side power supply wire 162, and the side grounding wire 163 and the side power supply wire 162 can fill each side surface which has an inclined portion. Although not shown in the diagram, similar to the third surface 145 and third surface 45 along the B3-B4 line in Figure 1, the power supply wiring 164 and grounding wiring 165 exposed on the inclined portion corresponding to the fourth surface 147 and fourth surface 47 are in contact with and covered by the side power supply wiring 162 and side grounding wiring 163.

[0053] Therefore, even if the positions of two IC chips 110 within the bonding chip 20 are misaligned, or if the positions of adjacent bonding chips 20 are misaligned, the power supply and grounding wires of each IC chip are electrically connected to the side grounding wires 163 and side power supply wires 162 embedded on each side, so that the electrical connection between chips is not impaired. Furthermore, as will be described in detail later, the manufacturing method of the memory cube 100 (stacked memory chip 30) includes a method that makes it relatively easy to align adjacent bonding chips 20, and the time required for stacking can be reduced.

[0054] [1-2. Overview of IC Chip 110] Next, an overview of the IC chip 110 will be described with reference to Figures 3 and 4. Configurations identical or similar to those described in Figures 1 to 4 in "1-1. Overview of Memory Cube 100" will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 4 may be omitted.

[0055] As explained in "1-1. Overview of Memory Cube 100", for example, the grounding wire 165 is exposed on the third side surface 108 which has an inclined portion, and the power supply wire 164 is exposed on the second side surface 105 which has an inclined portion and the fourth side surface 107 which has an inclined portion.

[0056] Furthermore, the multiple inductors 172 are provided so as to be spaced apart from the first side surface 106 and are arranged in a line along the second direction D2.

[0057] For example, the transistor layer 130 includes a substrate 173, an element isolation region 174, an activation region 175, a transistor 176, an insulating layer 177, and part of the wiring 178. For example, the substrate 173 is a Si substrate or Si-wafer, and is referred to as a semiconductor substrate. Through electrodes (not shown) that penetrate the substrate 173 and the element isolation region 174 may be provided.

[0058] For example, the wiring layer 150 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the wiring layer 150 includes a portion of wiring 178, insulating layer 179, wiring 180, insulating layer 181, insulating layer 182, and wiring 183. Wiring 183 may be a through electrode.

[0059] For example, wiring 178 is provided through the insulating layer 177 and is electrically connected to the source or drain of transistor 176. For example, wiring 180 is provided through the insulating layer 179 and is electrically connected to wiring 178. For example, multiple power supply wirings 164, multiple grounding wirings 165, multiple signal transmission wirings 166 (see Figure 49), and multiple inductors 172 are formed using wiring 183, wiring 180, or a portion of wiring 178. Each circuit within the memory cube 100 is formed using wiring 178, wiring 180, wiring 183, and transistor 176.

[0060] [1-3. Method for Manufacturing Memory Cube 100] The method for manufacturing the memory cube 100 will be described with reference to Figures 5 to 15. Figure 5 is a flowchart of the method for manufacturing the memory cube 100. Figure 6 is a plan view showing the first base material 50a in the method for manufacturing the memory cube 100. Figure 7 is a plan view showing step 102 (S102) in the method for manufacturing the memory cube 100, and an end view showing the end cross-sectional structure of the first base material 50a along the line E1-E2. Figure 8 is a plan view showing steps 104 (S104) and 106 (S106) in the method for manufacturing the memory cube 100, and an end view showing the end cross-sectional structure of the first base material 50a along the line E1-E2. Figure 9 is an end view showing the end cross-sectional structure of the first base material 50a along the line E1-E2 in steps 108 (S108) and 110 (S110) in the method for manufacturing the memory cube 100. Figure 10 is an end view showing the end cross-sectional structure of the IC chip 110 and bonded chip 20 in step 112 (S112) and step 114 (S114) of the manufacturing method of the memory cube 100. Figure 11 is an end view showing the end cross-sectional structure of the IC chip 110 and bonded chip 20 in step 116 (S116) of the manufacturing method of the memory cube 100. Figure 12 is an end view showing the end cross-sectional structure of the IC chip 110 and bonded chip 20 in step 118 (S118) of the manufacturing method of the memory cube 100. Figure 13 is an end view showing the end cross-sectional structure of the IC chip 110, bonded chip 20 and stacked memory chip 30 in step 120 (S120) of the manufacturing method of the memory cube 100. Figure 14 is a perspective view showing the stacked memory chip 30 in step 122 (S122) of the manufacturing method of the memory cube 100. Figure 15 is a perspective view showing a modified example of S122 in the manufacturing method of the memory cube 100. Figures 7 to 9 are enlarged views of the IC chip area 54. Configurations identical or similar to those in Figures 1 to 4 will be explained as necessary, and explanations of identical or similar configurations to those in Figures 1 to 4 may be omitted.

[0061] As shown in Figure 5, the manufacturing method of the memory cube 100 includes steps S102 to S122. Furthermore, the manufacturing method of the memory cube 100 also includes, as an example, joining and stacking eight IC chips 110 to form a stacked memory chip 30. The number of stacked IC chips 110 is not limited to eight (eight chips, eight layers), but may be 16 layers, 32 layers, 64 layers, or 128 layers. Also, the number of stacked IC chips 110 may be 2 ｎ The number of layers (where n is a non-negative integer) is not limited to 30 layers, 60 layers, etc. The number of layers of the IC chip 110 can be appropriately selected based on the specifications and application of the memory cube 100, within the limits of not departing from the manufacturing method of the memory cube 100.

[0062] When the manufacturing method for the memory cube 100 is started, the first substrate 50a is prepared. For example, as shown in Figure 6, the first surface 101b of the first substrate 50a overlaps with the peripheral region 52 and the IC chip region 54. The IC chip region 54 overlaps with and includes a plurality of IC chips 110 and grooves 56. The peripheral region 52 is the region surrounding the IC chip region 54.

[0063] Step S102 is a step in which grooves 56 that demarcate each of the multiple IC chips 110 are formed using plasma grooving. For example, plasma grooving is a processing method that uses plasma-enhanced etching gas to remove areas of the substrate to be diced. For example, the grooves 56 of the first substrate 50a shown in Figure 7 are formed by plasma grooving. The grooves 56 are formed in the insulating layer 185 included in the wiring layer 150, the insulating layer 184 included in the transistor layer 130, and the substrate 173. For example, the ends of the wiring 183 are exposed in the grooves 56. For the sake of easier understanding of the manufacturing method, the insulating layer 184 includes the element isolation region 174 and the insulating layer 177, and the insulating layer 185 includes the insulating layer 179, the insulating layer 181, and the insulating layer 182, making the drawing easier to read. For example, the process using plasma grooving in each embodiment may be processed by combining plasma grooving and laser grooving.

[0064] Step S104 is the step of forming an insulating film 155 on the second surface 101a and on the groove 56. As shown in Figure 8, the insulating film 155 is formed on the upper surface of the insulating layer 185, the side surface of the insulating layer 185 exposed by the groove 56, the side surface of the wiring 183, the side surface of the insulating layer 184, and the side surface of the substrate 173. For example, the insulating film 155 is formed using a CVD apparatus. In addition, the insulating film 155 in each embodiment may include an inorganic insulating film such as SiN or SiON. The exposed surface of the IC chip 110 is protected by the insulating film 155 formed in S104. CVD apparatus, SiN, SiON, etc., are commonly used in semiconductor manufacturing processes. The manufacturing method of the memory cube 100 can reduce manufacturing costs without using special equipment and manufacturing processes, and can protect the exposed surface of the IC chip 110. As a result, the manufacturing method of the memory cube 100 can suppress the intrusion of contaminants from the exposed surface of the IC chip 110, and can manufacture a high-quality memory cube 100.

[0065] S106 is the step of forming the adhesive film 140. As shown in Figure 8, the adhesive film 140 is formed on the insulating film 155 on the second surface 101a and on a portion of the insulating film 155 in the groove 56. The adhesive film 140 is an organic film containing an adhesive organic resin, and the adhesive film 140 is attached to the insulating film 155 on the second surface 101a and to a portion of the insulating film 155 in the groove 56. For example, the adhesive film 140 is a negative-type photosensitive resin. For example, the adhesive film 140 may be referred to as an organic resin, an organic film, or a first resin. Since S106 is the step of forming the adhesive film 140, the first substrate 50a is not separated into multiple IC chips 110 at the S106 stage, but as a result, the adhesive film 140 is provided on a portion or all of the interface between the multiple bonding chips 20 and on the interface between the multiple IC chips 110 or all of it. For example, the adhesive film 140 is molded so that it does not overlap with the multiple power wirings 164 exposed on the third surface 45 and the fourth surface 47, and is provided at a distance from the multiple power wirings 164. Similarly to the multiple power wirings 164, the adhesive film 140 is molded so that it does not overlap with the multiple grounding wires 165 exposed on the second surface 48, and is provided at a distance from the multiple grounding wires 165.

[0066] Step S108 is a step in which grooves 57 are formed by photolithography. As shown in STEP 108 of Figure 9, a portion of the adhesive film 140, a portion of the insulating film 155 on the second surface 101a, and the adhesive film 140 and insulating film 155 in the grooves 56 are removed by photolithography, and grooves 57 are formed. That is, by photolithography, a portion of the adhesive film 140, a portion of the insulating film 155 on the second surface 101a, and the adhesive film 140 and insulating film 155 in the grooves 56 are patterned, and grooves 57 are also patterned. As a result, a portion of the adhesive film 140, a portion of the insulating film 155 on the second surface 101a, and the adhesive film 140 and insulating film 155 in the grooves 56 are formed. Also, as shown in STEP 108 of Figure 9, grooves 57 are formed so as to surround the 21st surface 109 of the multiple IC chips 110. The groove 57 is necessary for dividing the first substrate 50a, described later, and forming multiple IC chips 110. For example, the groove 57 may be referred to as a dicing street. For example, in the manufacturing method of the memory cube 100, by using a negative-type photosensitive resin as the adhesive film 140, the insulating film 155 in the groove 56 and the residue in the groove 56 can be removed. As a result, the manufacturing method of the memory cube 100 can suppress contamination of the IC chip 110 by residue, disconnection of wiring, etc. The 21st surface 109 may be referred to as the 4th surface.

[0067] Step S110 is a step in which the first surface 101b of the first substrate 50a is polished to separate the first substrate 50a into multiple IC chips 110. As shown in STEP 110 of Figure 9, the first surface 101b (substrate 173) is polished to form the first surface 102n and the first surface 102n+1, and the thickness THI2 of the first substrate 50a becomes thickness THI. As a result, the first substrate 50a is separated into multiple IC chips 110. As shown in STEP 110 of Figure 9 and in Figure 4, thickness THI is the thickness of the IC chip 110. For example, thickness THI is 20 μm or more and 1 mm or less. Also, for example, a CMP apparatus can be used for polishing. The first surface 102 may be referred to as the third surface. For example, polishing in each embodiment may include grinding and may be referred to as grinding and polishing.

[0068] Step S112 is a step in which the adhesive film 140 on the multiple individualized IC chips 110 is subjected to plasma activation or vacuum ultraviolet (VUV) treatment. As shown in STEP 112 of Figure 10, the adhesive film 140 of two different IC chips 110n and the adhesive film 140 of IC chip 110n+1 are subjected to plasma activation or VUV treatment. The surfaces of IC chips 110n and IC chip 110n+1 are modified and cleaned by S112. For example, plasma activation is O ２ It is fine to use N ２ It is fine to use H ２ You may also use the following. Also, for example, VUV processing is O ３ You may also use [this].

[0069] Step S114 is a step in which two different IC chips 110 from a plurality of IC chips 110 are joined together to form a single joined chip 20. As shown in STEP 114 of Figure 10, the adhesive films 140 of two different IC chips 110n and the adhesive film 140 of IC chip 110n+1 are joined by thermocompression bonding to form a joined chip 20n. At this time, the 21st face 109n+1 of IC chip 110n+1 is joined to the 21st face 109n of IC chip 110n. For example, a method for manufacturing a memory cube 100 includes using an apparatus capable of joining a plurality of IC chips 110 and forming a stacked memory chip 30. This apparatus may be referred to as a bonder.

[0070] For example, stacking (joining) two different IC chips 110 so that their 21st faces 109 (2nd face 104) on the wiring layer 150 side face each other is referred to as an F2F junction (Face to Face Fusion). Also, for example, stacking (joining) two different IC chips 110 so that their 1st faces 102 (1st face 101b) on the substrate 173 side included in their transistor layers 130 face each other is referred to as a B2B junction (Back to Back Fusion). Furthermore, for example, stacking (joining) two different IC chips 110 such that the 21st surface 109 (2nd surface 104) on the wiring layer 150 side and the 1st surface 102 (1st surface 101b) on the substrate 173 side included in the transistor layer 130 face each other is referred to as F2B joining (Face to Back Fusion). For example, techniques such as welding (fusion bonding, FB), silicon direct bonding (SDB), and thermal compression bonding (TCB) can be used to stack (join) two different IC chips 110.

[0071] For example, step S114 shown in Figure 10 is a step of thermal bonding two different IC chips 110 by F2F bonding. By using thermal bonding for F2F bonding, the thermal warping of the two IC chips 110 can be canceled out. Also, at this time, since the two IC chips 110 are protected by the adhesive film 140 between them, it is possible to suppress the resin from seeping into the wiring 183.

[0072] Step S116 is the step of applying liquid 60 to the bonding chips 20 to bond multiple bonding chips 20 and form a stacked memory chip 30. For example, as shown in Figure 11, four bonding chips 20n, 20n+1, 20n+2, and 20n+3 are bonded, that is, eight IC chips 110 are bonded. Liquid 60 is applied to the first surface 102n+3 of IC chip 110n+3 of bonding chip 20n+1, and the first surface 102n+3 of bonding chip 20n+1 is bonded to the first surface 102n of IC chip 110n of bonding chip 20n. Similar to bonding chip 20n, liquid 60 is applied to the first surface 102n+5 of IC chip 110n+5 of bonding chip 20n+2, and the first surface 102n+5 of bonding chip 20n+2 is bonded to the first surface 102n+2 of IC chip 110n+2 of bonding chip 20n+1. Also, liquid 60 is applied to the first surface 102n+7 of IC chip 110n+7 of bonding chip 20n+3, and the first surface 102n+7 of bonding chip 20n+3 is bonded to the first surface 102n+4 of IC chip 110n+4 of bonding chip 20n+2.

[0073] For example, the liquid 60 may be water, pure water, glycerin, acetone, alcohol, or mixtures thereof, or it may be SOG (Spin On Glass) material, etc.

[0074] Step S116 uses the surface tension of the liquid 60 to join two different bonding chips 20 by self-alignment. As a result, the manufacturing method of the memory cube 100 can join two adjacent bonding chips 20 at a higher speed than bonding methods that do not perform self-alignment. Furthermore, by repeatedly applying the liquid 60 to adjacent bonding chips 20 and joining other bonding chips 20, multiple bonding chips 20 can be aligned and joined. At this time, since the liquid 60 remains between adjacent bonding chips 20, Step S116 can form a temporarily joined stacked memory chip 30.

[0075] For example, the device for applying the liquid 60 in S116 may be a dispenser. Furthermore, it is preferable to apply the liquid 60 to the center of the bonding tip 20 so that it does not overflow from the bonding tip 20. For example, the liquid 60 is applied so as not to spread around the bonding tip 20, covering no more than 80% of the area of ​​the first surface 102 of the bonding tip 20.

[0076] Furthermore, for example, the formation of the stacked memory chip 30 in S116 may be done by forming the stacked memory chip 30 one by one, or by forming multiple stacked memory chips 30 together. For example, forming multiple stacked memory chips 30 together may include arranging and forming multiple stacked memory chips 30 on a Si substrate, and batch processing may be used. When forming multiple stacked memory chips 30 together, the liquid 60 is applied to each of the stacked memory chips 30 one by one.

[0077] Step S118 is a step to inspect the multiple bonded chips 20 (stacked memory chip 30) that were temporarily bonded in S116. For example, as shown in Figure 12, the liquid 60 dries and the four bonded chips 20n, 20n+1, 20n+2, and 20n+3 are bonded together to form a stacked memory chip 30. If the inspection determines that the positions of the bonded chips 20 are aligned and that the stacked memory chip 30 is formed (OK in S118), the process in S120 is executed. Also, since each bonded chip 20 is separable, if the inspection determines that the positions of the bonded chips 20 are misaligned (NG in S118), each bonded chip 20 can be separated and the process can be returned to S116 to re-bond each bonded chip 20.

[0078] For example, in S118, the multiple bonded chips 20 (stacked memory chips 30) that were temporarily bonded in S116 are transported from the bonder to an inspectionable device located outside the bonder. The inspectionable device may also have a function for drying the multiple bonded chips 20 (stacked memory chips 30). For example, the temporarily bonded stacked memory chips 30 are transported using a robotic arm. The robotic arm is a device capable of slowly accelerating and moving the temporarily bonded stacked memory chips 30, and then slowly decelerating and stopping them. The acceleration of the robotic arm when transporting the temporarily bonded stacked memory chips 30 is limited to a predetermined range. For example, the acceleration is 0.1 mm / s². ２ 100mm / s or more ２ The following applies:

[0079] Furthermore, for example, S118 may include air-drying the multiple temporarily bonded bonded chips 20 (stacked memory chips 30), heating and drying, or heating and drying in a vacuum or high-pressure atmosphere. Also, for example, the temperature inside the apparatus during drying may be around 60 degrees Celsius. For example, processing the multiple temporarily bonded bonded chips 20 (stacked memory chips 30) in a vacuum or high-pressure atmosphere reduces voids within the multiple bonded chips 20 (stacked memory chips 30).

[0080] The manufacturing method for the memory cube 100 shows an example in which four bonding chips 20 are bonded, but the manufacturing method for the memory cube 100 may involve bonding five or more bonding chips 20. When bonding a larger number of bonding chips 20 to form a stacked memory chip 30, the manufacturing methods S116 and S118 may be repeated. That is, bonding by self-alignment, drying, inspection, and re-bonding may be repeated.

[0081] S120 is a step in which an organic film 65 is applied between adjacent bonding chips 20 in the stacked memory chip 30 formed in S118, and the organic film 65 is cured by UV irradiation. For example, as shown in Figure 13, the organic film 65 is applied between the first surface 102n of IC chip 110n+3 of bonding chip 20n+1 and the first surface 102n+3 of IC chip 110n of bonding chip 20n. Also, the organic film 65 is applied between the first surface 102n+5 of IC chip 110n+5 of bonding chip 20n+2 and the first surface 102n+2 of IC chip 110n+2 of bonding chip 20n+1. Furthermore, the organic film 65 is applied between the first surface 102n+7 of IC chip 110n+7 of bonding chip 20n+3 and the first surface 102n+4 of IC chip 110n+4 of bonding chip 20n+2. Furthermore, UV light can be irradiated onto the stacked memory chip 30 to cure the organic film 65 and fix each bonding chip 20 of the stacked memory chip 30. For example, the organic film 65 in each embodiment is a UV-curable resin that hardens upon UV irradiation. Also, for example, the apparatus for applying the UV-curable resin in each embodiment may be a dispenser, and the UV-curable resin may be applied and patterned using the dispenser.

[0082] In step S120, the organic film 65 is applied between adjacent bonding chips 20, and the stacked memory chip 30 is irradiated with UV light, thereby heating and holding the stacked memory chip 30 and accelerating the curing of the organic film 65. In other words, step S120 includes forming the organic film 65.

[0083] For example, if there is a gap between adjacent bonding chips 20, during electrode formation in S122 described later, the solvent may penetrate the stacked memory chip 30 through the gap, causing stacking defects. Also, as mentioned above, each of the multiple IC chips 110 has its own unique curvature, so as the number of stacked bonding chips 20 (IC chips 110) increases, the stress on the multiple bonding chips 20 accumulates because each IC chip 110 has its own unique curvature. As a result, in manufacturing methods that do not apply the manufacturing method of the memory cube 100, which is one embodiment of the present invention, there is a risk that the memory cube may be damaged. Furthermore, if multiple bonding chips 20 are heat-pressed together using an adhesive, depending on the thickness of the adhesive, it may not only affect the long-term reliability of the memory cube but also cause the memory cube to be damaged.

[0084] On the other hand, since the manufacturing method of the memory cube 100 includes S120, the manufacturing method of the memory cube 100 can ensure insulation between adjacent bonding chips 20, minimize the thickness of the organic film 65, and suppress defects caused by solvents. Furthermore, the manufacturing method of the memory cube 100 includes S116, which allows the stacked memory chip 30 to be formed by self-alignment. As a result, since the manufacturing method of the memory cube 100 includes S116 to S120, it is possible to relieve stress on multiple bonding chips 20 and suppress defects caused by stress.

[0085] S122 is a step in which electrodes (for example, side power wiring 162, side ground wiring 163, etc.) are electrically connected to a plurality of wirings (for example, power wiring 164, ground wiring 165, etc.) exposed on the second side surface 105, the third side surface 108, and the fourth side surface 107. For example, as shown in Figure 14, the conductive film 160 is formed on the sixth surface 44, second surface 48, third surface 45, fourth surface 47, and fifth surface 42 of the stacked memory chip 30, excluding the first surface 46 (bottom surface) which includes the organic film 65 formed in S120. The surfaces of the formed conductive film 160 become the sixth surface 144, second surface 148, third surface 145, fourth surface 147, and fifth surface 142 of the stacked memory chip 30. For example, the conductive film 160 is patterned using photolithography or laser ablation to form the side power wiring 162 and side ground wiring 163 shown in Figure 1, Figure 2A, or Figure 2B.

[0086] For example, step S122 is a step that can be simplified depending on the equipment used.

[0087] Furthermore, for example, the conductive film 160 is formed using electroplating (plating method) so as to be in contact with the multiple power supply wirings 164 and grounding wirings 165 exposed on each side, as well as in contact with a part of the substrate 173, a part of the insulating layer 184, and a part of the insulating layer 185. Also, the side power supply wirings 162 and side grounding wirings 163 are formed so as to be in contact with a part of the substrate 173, a part of the insulating layer 184, and a part of the insulating layer 185.

[0088] Furthermore, for example, the material forming the conductive film 160 includes Cu, Ti, and Au, and Cu, Ti, and Au are layered in this order from the side closest to each surface toward the side furthest from each surface. For example, the thickness of the conductive film 160 is 20 μm or more and 30 μm or less. However, the material forming the conductive film 160 and the thickness of the conductive film 160 are not limited to the materials and thicknesses shown herein. The material forming the conductive film 160 and the thickness of the conductive film 160 can be appropriately selected according to the specifications and application of the memory cube 100.

[0089] For example, the manufacturing method of the memory cube 100 allows for the formation of a thick conductive film 160 on each surface of the stacked memory chip 30 using a plating method, and each surface of the stacked memory chip 30 is protected from external damage and the intrusion of impurities by the thick conductive film 160. The manufacturing method of the memory cube 100 allows for the formation of the outermost surface of the memory cube 100 with Au, which suppresses electrode corrosion.

[0090] [1-4. Modified Methods] Next, an overview of modified methods for manufacturing the memory cube 100 will be described with reference to Figure 15. Figure 15 is a perspective view showing modified methods for manufacturing the memory cube 100. Configurations identical or similar to those in Figures 1 to 14 will be described as necessary, and descriptions of identical or similar configurations to those in Figures 1 to 14 may be omitted.

[0091] A modified version of the manufacturing method for the memory cube 100 is a manufacturing method in which S120 in the manufacturing method of the memory cube 100 includes applying an organic film 65 to the four corners 39 of the stacked memory chip 30 formed in S118. For example, applying the organic film 65 to the four corners 39 is performed before applying the organic film 65 between adjacent bonding chips 20.

[0092] In other words, in a modified example of the manufacturing method of the memory cube 100, step S120 involves applying an organic film 65 to the four corners 39 of the stacked memory chip 30 formed in S118, then applying the organic film 65 between adjacent bonding chips 20, and curing the organic film 65 by UV irradiation.

[0093] As shown in Figure 15, the four corners 39 are the parts where the first surface 46, the third surface 45, part of the fifth surface 42 and part of the sixth surface 44 meet, the parts where the third surface 45, the second surface 48, part of the fifth surface 42 and part of the sixth surface 44 meet, the parts where the second surface 48, the fourth surface 47, part of the fifth surface 42 and part of the sixth surface 44 meet, and the parts where the fourth surface 47, the first surface 46, part of the fifth surface 42 and part of the sixth surface 44 meet.

[0094] In a modified method for manufacturing the memory cube 100, UV light is irradiated onto the stacked memory chip 30 to cure the organic film 65, and the corners of each bonding chip 20 and the spaces between the bonding chips 20 of the stacked memory chip 30 can be fixed. Therefore, the modified method for manufacturing the memory cube 100 makes it possible to fix the stacked memory chip 30 more firmly, and it is possible to suppress the penetration of solvent into the stacked memory chip 30 not only from the gaps but also from the corners 39 during electrode formation in S122.

[0095] [Second Embodiment] The memory cube 100A according to the second embodiment will be described with reference to Figures 16 to 26B. Configurations identical or similar to those in Figures 1 to 15 will be described as necessary, and descriptions of identical or similar configurations to those in Figures 1 to 15 may be omitted.

[0096] [2-1. Overview of Memory Cube 100A] First, an overview of the memory cube 100A will be explained with reference to Figures 16 to 19. Figure 16 is a perspective view showing the configuration of the memory cube 100A. Figure 17A is an end view showing the end cross-sectional structure of the memory cube 100A along F1-F2 shown in Figure 16. Figure 17B is an end view showing the end cross-sectional structure of the memory cube 100A along G1-G2 shown in Figure 16. Figure 18 is a perspective view showing the configuration of the IC chip 110A. Figure 19 is an end view showing the end cross-sectional structure of the IC chip 110A along the line H1-H2 shown in Figure 18. Note that in the perspective view shown in Figure 18, the inclined portion shown in Figure 19 is omitted, and the figure is simplified.

[0097] As shown in Figure 16, Figure 17A, or Figure 17B, the memory cube 100A includes a stacked memory chip 30A, a side power supply wiring 162 and a side ground wiring 163 electrically connected to the stacked memory chip 30A. The stacked memory chip 30A includes two IC chips 110A, each containing a plurality of power supply wirings 164, a plurality of ground wirings 165, and a plurality of signal transmission wirings 166.

[0098] Memory cube 100A differs from memory cube 100 in at least the configurations (1) to (5) shown below. Configuration (1) The first face 146A, second face 148A, third face 145A, fourth face 147A, fifth face 142A and sixth face 144A of memory cube 100A are the faces that replace the first face 146, second face 148, third face 145, fourth face 147, fifth face 142 and sixth face 144 of memory cube 100. Configuration (2) The first face 46A, second face 48A, third face 45A, fourth face 47A, fifth face 42A and sixth face 44A of stacked memory chip 30A are the faces that replace the first face 46, second face 48, third face 45, fourth face 47, fifth face 42 and sixth face 44 of memory cube 100. Configuration (3) The first surface 102A, the second surface 104A (21st surface 109A), the first side surface 106A, the second side surface 105A, the third side surface 108A, and the fourth side surface 107A of the IC chip 110A are surfaces that replace the first surface 102, the second surface 104 (21st surface 109), the first side surface 106, the second side surface 105, the third side surface 108, and the fourth side surface 107 of the IC chip 110. Configuration (4) Power supply wiring 164, ground wiring 165, and signal transmission wiring 166 may be exposed from the first side surface 106A, and a plurality of inductors 172 may be provided at a distance from the first side surface 106A. When the power supply wiring 164, grounding wiring 165, and signal transmission wiring 166 are exposed from the first side surface 106A, the bump 167 is provided so as to be in contact with the exposed power supply wiring 164, grounding wiring 165, and signal transmission wiring 166. Configuration (5) The method for manufacturing the memory cube 100A (see Figures 20 to 26B) includes attaching an adhesive film 70 to a first substrate 50a (see Figure 6) and oxidizing the first substrate 50a, separating the first substrate 50a into a plurality of IC chips using a laser, expand or plasma etching, joining a plurality of IC chips 110A in a vacuum or high-pressure atmosphere to form a stacked memory chip 30A, and forming the side grounding wiring 163 so as to be in contact with the corners 38 and 39.

[0099] Configurations other than configurations (1) to (5) in Memory Cube 100A, and configurations other than those related to configurations (1) to (5), are the same as those in Memory Cube 100. Therefore, when describing Memory Cube 100A, configurations identical or similar to those in Memory Cube 100 will be described as necessary, and descriptions of identical or similar configurations may be omitted.

[0100] Multiple IC chips 110A may simply be referred to as multiple circuit boards. If the individual IC chips 110A are not distinguishable, the IC chip is referred to as IC chip 110A. If the individual IC chips 110A are distinguishable, the IC chip is referred to as IC chip 110An, IC chip 110An+1, etc. The same applies to each side of the IC chip 110A.

[0101] Furthermore, in the memory cube 100A, similar to the end view showing the end cross-sectional structure of the memory cube along line B3-B4 in Figure 1, and the end view showing the end cross-sectional structure of the memory cube along line B5-B6 in Figure 1, the power wiring 164 and ground wiring 165 exposed on the corresponding inclined portion are in contact with and covered by the side power wiring 162 and side ground wiring 163. Also, similar to the third surface 145 and third surface 45 along line B3-B4 in Figure 1, the power wiring 164 and ground wiring 165 exposed on the inclined portion corresponding to the fourth surface 147 and fourth surface 47 are in contact with and covered by the side power wiring 162 and side ground wiring 163.

[0102] [2-2. Overview of IC Chip 110A] Next, an overview of IC chip 110A will be described with reference to Figures 18 and 19. Configurations identical or similar to those in Figures 1 to 19 will be described as necessary, and descriptions of identical or similar configurations may be omitted.

[0103] An insulating film 155 is provided on the second surface 104. The 21st surface 109A is the surface opposite to the side where the insulating film 155 is in contact with the second surface 104. As will be described in detail later, the 11th surface 101c is the surface formed by polishing the first surface 101b of the first substrate 50a. An adhesive film 70 is provided on the 11th surface 101c. The first surface 102A is the surface opposite to the side where the adhesive film 70 is in contact with the 11th surface 101c. For example, the adhesive film 70 is a die attach film (DAF).

[0104] The third side surface 108A, like the third side surface 108, is in contact with the end of the first surface 102A and the end of the second surface 104A (21st surface 109A), and has an inclined portion. Similar to the third side surface 108A, the second side surface 105A and the fourth side surface 107A are in contact with the end of the first surface 102A and the end of the second surface 104A (21st surface 109A), and have an inclined portion (see Figure 23).

[0105] For example, the angle between the 11th face 101c and the 3rd side surface 108A is an alternate interior angle with the angle between the 1st face 102A and the 3rd side surface 108A. The angle between the 11th face 101c (1st face 102A) and the 3rd side surface 108A is angle α. Similarly, the angle between the 11th face 101c (1st face 102A) and the 2nd side surface 105A, and the angle between the 11th face 101c (1st face 102A) and the 4th side surface 107A are angles α. Angle α is greater than 0 degrees and less than 90 degrees.

[0106] In the example shown in Figure 19, the grounding wire 165 is exposed from the third side surface 108A which has an inclined portion, while the power supply wire 164 is exposed from the second side surface 105A which has an inclined portion and the fourth side surface 107A which has an inclined portion. The grounding wire 165 may be exposed from the second side surface 105A which has an inclined portion and the fourth side surface 107A which has an inclined portion, and the power supply wire 164 may be exposed from the third side surface 108A which has an inclined portion.

[0107] The transistor layer 130 and wiring layer 150 in the IC chip 110A have the same configuration as the transistor layer 130 and wiring layer 150 in the IC chip 110.

[0108] [2-3. Method for Manufacturing Memory Cube 100A] The method for manufacturing the memory cube 100A will be described with reference to Figures 16, 17A, and 17B, and Figures 20 to 26B. Figure 20 is a flowchart showing the method for manufacturing the memory cube 100A. Figure 21 is a plan view showing steps 202 (S202) and 204 (S204) of the method for manufacturing the memory cube 100A, and an end view showing the end cross-sectional structure of the first base material 50a along the line I1-I2. Figure 22 is an end view showing the end cross-sectional structure of the first base material 50a along the line I1-I2 shown in Figure 21 during steps 206 (S206), 208 (S208), and 210 (S210) of the method for manufacturing the memory cube 100A. Figure 23 is an end view showing the end cross-sectional structure of the IC chip 110A to be joined in steps 212 (S212) and 214 (S214) of the manufacturing method of the memory cube 100A. Figure 24 is an end view showing the end cross-sectional structure of the stacked memory chip 30A in step 218 (S218) following step 216 (S216) of the manufacturing method of the memory cube 100A. Figure 25 is a perspective view showing the memory cube 100A in step 220 (S220) or step 222 (S222) of the manufacturing method of the memory cube 100A. Figures 21 and 22 are enlarged views of the IC chip area 54. Configurations identical or similar to those in Figures 1 to 19 will be described as necessary, and descriptions of identical or similar configurations in Figures 1 to 19 may be omitted.

[0109] As shown in Figure 20, the method for manufacturing the memory cube 100A includes steps S202 to S222. Furthermore, the method for manufacturing the memory cube 100A, similar to the method for manufacturing the memory cube 100, includes, as an example, joining and stacking eight IC chips 110A to form a stacked memory chip 30A. The number of stacked IC chips 110A is not limited to eight (eight chips, eight layers), but may be 16 layers, 32 layers, 64 layers, or 128 layers. Also, the number of stacked IC chips 110A may be 2 ｎInstead of the (n is an integer greater than or equal to 0) layer, it may be 30 layers, 60 layers, etc. The number of stacked layers of the IC chip 110A can be appropriately selected based on the specifications, applications, etc. of the memory cube 100A, as long as it does not deviate from the manufacturing method of the memory cube 100A.

[0110] When the manufacturing method of the memory cube 100A is started, the first base material 50a (see FIG. 6) is prepared.

[0111] S202 and S204 are the same as S102 and S104, and detailed descriptions here are omitted. S204 is a step of forming the insulating film 155 on the second surface 101a and on the groove 56, and is a step of forming the 21st surface 109A. For example, as shown in FIG. 21, the insulating film 155 is formed on the second surface 101a and on the groove 56. More specifically, the insulating film 155 is formed on the upper surface of the insulating layer 185, the side surface of the insulating layer 185 exposed by the groove 56, the side surface of the wiring 183, the side surface of the insulating layer 184, and the side surface of the substrate 173. The surface of the insulating film 155 opposite to the surface in contact with the second surface 101a (second surface 104A) is the 21st surface 109A. The 21st surface 109A may be referred to as the fourth surface.

[0112] S206 is a step of grinding and polishing the first surface 101b to form the 11th surface 101c. As shown in STEP206 of FIG. 22, the first surface 101b (substrate 173) is ground and polished, the 11th surface 101c is formed, and the thickness THI4 of the first base material 50a in S204 becomes the thickness THI5. For example, grinding and polishing can use a CMP device. The first surface 102A may be referred to as the third surface.

[0113] S208 is a step of attaching the adhesive film 70 to the 11th surface 101c to form the first surface 102A and oxidizing the first base material 50a. As shown in STEP208 of FIG. 22, the adhesive film 70 is attached to the 11th surface 101c. At this time, the surface of the first base material 50a, that is, the 11th surface 101c is oxidized. For example, the oxidation treatment may be performed using an aqueous solution such as hydrogen peroxide water, ozone water, etc., O ２ Plasma, O ３The process may be carried out using plasma, such as a plasma, and an oxide film such as SiN or SiON may be formed. For example, the manufacturing method of the memory cube 100A includes an oxidation treatment, which suppresses contamination by metals and the like from the first surface 102A side of the first substrate 50a. The adhesive film 70 may be referred to as an adhesive film.

[0114] Step S210 is a step in which the insulating film 155 and the adhesive film 70 are separated (cut) along the groove 56 using a laser, expander, or plasma etching, in the direction from the 21st surface 109A to the 1st surface 102A, thereby dividing the first substrate 50a attached to the dicing tape 71 into a plurality of IC chips 110A. Specifically, step S210 includes any one of the first process, the second process, and the third process, or a combination of the first process, the second process, and the third process. For example, the first process may include all or part of attaching the first substrate 50a to the dicing tape 71, scanning the groove 56 with a laser to separate (cut) the insulating film 155 and the adhesive film 70 in the direction from the 21st surface 109A to the 1st surface 102A, and consequently separating the first substrate 50a attached to the dicing tape 71 into a plurality of IC chips 110A. Furthermore, for example, the second process may include all or part of the following: attaching the first substrate 50a to the dicing tape 71; scanning the groove 56 with a laser to divide (cut) the insulating film 155 in the direction from the 21st surface 109A to the first surface 102A; etching the adhesive film 70 exposed in the groove 56 in the direction from the 21st surface 109A to the first surface 102A using plasma etching; and consequently, framing the first substrate 50a attached to the dicing tape 71 into a plurality of IC chips 110A. Furthermore, for example, the third process may include all or part of the following: attaching the first substrate 50a to the dicing tape 71; using dicing to separate (cut) the insulating film 155 and the adhesive film 70 along the groove 56 in the direction from the 21st surface 109A to the first surface 102A; stretching the dicing tape 71 to widen the spacing between the multiple IC chips 110A (expanding); and separating the multiple IC chips 110A into individual pieces by expanding. As a result, as shown in STEP 210 of Figure 22, the insulating film 155 formed in the groove 56 is removed, and the side surface of the insulating film 155, the side surface of the insulating layer 185, the side surface of the wiring 183, the side surface of the insulating layer 184, the side surface of the substrate 173, the side surface of the adhesive film 70, and a part of the dicing tape 71 are exposed, and a groove 58 is formed.In other words, the sides of the insulating film 155, the insulating layer 185, the wiring 183, the insulating layer 184, the substrate 173, and the adhesive film 70 are formed. At this time, the grooves 58 are the second side surface 105A and the fourth side surface 107A of the individualized IC chips 110An and 110An+1. At this time, the shape of the adhesive film 70 includes inclined portions similar to the substrate 173 and is the same shape as the outer shape of the IC chip 110A in a plan view. For example, the thickness THI3 of the IC chip 110A is 20 μm or more and 1 mm or less.

[0115] Step S212 is a step in which two different IC chips 110An and 110An+1 are selected from a plurality of individualized IC chips 110A, and the adhesive film 70 of IC chip 110An (first surface 102An) and the insulating film 155 of IC chip 110An+1 (21st surface 109An+1) are subjected to plasma activation or vacuum ultraviolet (VUV) treatment. As shown in STEP 212 of Figure 23, the adhesive film 70 of two different IC chips 110An and the insulating film 155 of IC chip 110An+1 are subjected to plasma activation or VUV treatment. The surfaces of IC chip 110An and IC chip 110An+1 are modified and cleaned by S212. As a result, the surfaces of IC chip 110An and IC chip 110An+1 are activated, and the tackiness (adhesion, bonding) between IC chip 110An and IC chip 110An+1 is improved. For example, plasma activation is O ２ It is fine to use N ２ It is fine to use H ２ You may also use the following. Also, for example, VUV processing is O ３ You may also use [this].

[0116] Step S214 is a step in which multiple individual IC chips 110A are stacked and temporarily joined. As shown in the example of temporarily joining two IC chips 110 facing each other in STEP 214 of Figure 23, two different IC chips (the adhesive film 70 of 110An and the insulating film 155 of IC chip 110An+1) are temporarily joined at a low temperature. In reality, as shown in Figure 24, multiple IC chips 110 are temporarily joined at a low temperature. At this time, the 21st face 109An+1 of IC chip 110An+1 is joined to the 1st face 102An of IC chip 110An, the 21st face 109An+2 of IC chip 110An+2 is joined to the 1st face 102An+1 of IC chip 110An+1, the 21st face 109An+3 of IC chip 110An+3 is joined to the 1st face 102An+2 of IC chip 110An+2, and the 21st face 109An+4 of IC chip 110An+4 is joined to IC The first face 102An+3 of chip 110An+3 is bonded to the first face 102An+3 of IC chip 110An+5, the 21st face 109An+5 of IC chip 110An+4 is bonded to the first face 102An+4 of IC chip 110An+4, the 21st face 109An+6 of IC chip 110An+6 is bonded to the first face 102An+5 of IC chip 110An+5, and the 21st face 109An+7 of IC chip 110An+7 is bonded to the first face 102An+6 of IC chip 110An+6.

[0117] For example, step S214 shown in Figure 23 is a step of temporarily joining two different IC chips 110A at a low temperature by F2B bonding. Since the manufacturing method of the memory cube 100A includes temporarily joining multiple IC chips 110A at a low temperature, it is possible to suppress the flow of the resin of the adhesive film 70 at high temperatures and to suppress the flow of the resin to each side of the IC chip 110A and contamination of each side of the IC chip 110A.

[0118] Furthermore, for example, S214 may include joining two different IC chips 110A together to form one joined chip, similar to S114 and S116, forming multiple such joined chips, joining the multiple joined chips together to form a stacked memory chip 30A, forming the stacked memory chips 30A one by one, or forming multiple stacked memory chips 30A together. For example, forming multiple stacked memory chips 30A together may include arranging and forming multiple stacked memory chips 30A on a Si substrate, and batch processing may be used.

[0119] Step S216 is a step to inspect the multiple temporarily joined IC chips 110A. If the inspection determines that the positions of the multiple IC chips 110A are aligned (OK in S216), the process in S218 is executed. Also, since the multiple IC chips 110A are temporarily joined at a low temperature, they can be separated. If the inspection determines that the positions of the multiple IC chips 110A are misaligned (NG in S216), the multiple IC chips 110A can be separated, and the process returns to S214 to temporarily join the multiple IC chips 110A again at a low temperature.

[0120] Step S218 is a step in which a plurality of temporarily bonded IC chips 110A are permanently bonded in a vacuum or under a high-pressure atmosphere (under high pressure) to form a stacked memory chip 30A. For example, step S218 does not include the step of applying pressure. Since the manufacturing method of the memory cube 100A includes step S218, in which temporary bonding is performed in a vacuum or under a high-pressure atmosphere, gaps and voids between the plurality of IC chips 110A can be suppressed. As a result, the manufacturing method of the memory cube 100A can suppress the penetration of solvent into the stacked memory chip 30A from the gaps or voids during electrode formation in step S220, which will be described later, and stacking defects can be suppressed. Furthermore, since the manufacturing method of the memory cube 100A does not include the step of applying pressure, misalignment of the plurality of temporarily bonded IC chips 110A due to pressure can be suppressed.

[0121] Furthermore, the manufacturing method of the memory cube 100A may include a step of inspecting the stacked memory chip 30A after S218. For example, gaps or voids may be discovered during the inspection of the stacked memory chip 30A. In that case, the manufacturing method of the memory cube 100A may include repairing the gaps or voids in the stacked memory chip 30A by applying a UV-curable resin to the stacked memory chip 30A and UV curing the UV-curable resin.

[0122] S220 is a step in which electrodes (for example, side power wiring 162, side ground wiring 163, etc.) are electrically connected to a plurality of wirings (for example, power wiring 164, ground wiring 165, etc.) exposed on the second side surface 105A, third side surface 108A, and fourth side surface 107A of the stacked memory chip 30A formed in S218. For example, as shown in Figure 25, a conductive film 160 is formed on the sixth surface 44, second surface 48, third surface 45, fourth surface 47, and fifth surface 42 of the stacked memory chip 30A formed in S218, excluding the first surface 46 (bottom surface). The surfaces of the formed conductive film 160 become the sixth surface 144A, second surface 148A, third surface 145A, fourth surface 147A, and fifth surface 142A of the stacked memory chip 30A. For example, the conductive film 160 is patterned using photolithography or laser ablation to form the side power wiring 162 and side ground wiring 163 shown in Figure 16, Figure 17A, or Figure 17B.

[0123] For example, S220 is a step that can be simplified depending on the equipment used.

[0124] For example, as shown in Figure 25, the conductive film 160 is formed using electroplating (plating method) so as to be in contact with the corners 38 and 39, the multiple power supply wirings 164 and grounding wirings 165 exposed on each side, and also in contact with a part of the substrate 173, a part of the insulating layer 184, and a part of the insulating layer 185. The conductive film 160 is also formed on the sixth surface 44A, the second surface 48A, and the fifth surface 42A, including the corners 38 and 39, as well as on the corners 38 and 39 of the third surface 45A that are separated from the area where the side power supply wirings 162 are formed, and on the corners 38 and 39 of the fourth surface 47A that are separated from the area where the side power supply wirings 162 are formed. The side power supply wirings 162 and side grounding wirings 163 are formed so as to be in contact with a part of the substrate 173, a part of the insulating layer 184, and a part of the insulating layer 185.

[0125] Furthermore, for example, the material forming the conductive film 160 includes Cu, Ti, and Au, and Cu, Ti, and Au are layered in this order from the side closest to each surface toward the side furthest from each surface. For example, the thickness of the conductive film 160 is 20 μm or more and 30 μm or less. However, the material forming the conductive film 160 and the thickness of the conductive film 160 are not limited to the materials and thicknesses shown herein. The material forming the conductive film 160 and the thickness of the conductive film 160 can be appropriately selected according to the specifications and application of the memory cube 100A.

[0126] For example, the manufacturing method of the memory cube 100A allows for the formation of a thick conductive film 160 on the corners 38 and 39 of the stacked memory chip 30A, as well as on each surface including the corners 38 and 39, using a plating method. Each surface of the stacked memory chip 30A is protected by the thick conductive film 160 from external damage to the chip surface, chipping of the corners, and intrusion of impurities. Furthermore, the manufacturing method of the memory cube 100A allows for the outermost surface of the memory cube 100A to be formed of Au, thereby suppressing electrode corrosion.

[0127] Step S222 is the step of forming a bump 167 that is electrically connected to a plurality of wires (for example, power supply wires 164, grounding wires 165, signal transmission wires 166, etc.) exposed on the first side surface 106 (first surface 46, first surface 146). For example, as shown in Figures 17A and 17B, the bump 167 is formed to contact and cover the power supply wires 164, grounding wires 165, and signal transmission wires 166, respectively.

[0128] The manufacturing method of the memory cube 100A allows for the protection of all surfaces except the bottom surface using a thick conductive film 160 according to S220, and the protection of the bottom surface using bumps 167 according to S222. Therefore, each surface of the stacked memory chip 30A is protected by the thick conductive film 16 or bumps 167 from external damage to the chip surface, chipping of corners, and intrusion of impurities.

[0129] [2-4. Modified Methods] Next, an overview of modified methods for manufacturing the memory cube 100A will be described with reference to Figures 26A and 26B. Figures 26A and 26B are end views showing the end cross-sectional structure of modified methods for manufacturing the memory cube 100A. Configurations identical or similar to those in Figures 1 to 25 will be described as necessary, and descriptions of identical or similar configurations may be omitted.

[0130] A modified example of the manufacturing method for the memory cube 100A is an example in which the memory cube 100A includes a plurality of inductors 172.

[0131] As shown in Figure 26A or Figure 26B, the multiple inductors 172 are arranged parallel to the first surface 46A (first surface 146A, first side surface 106A) for each IC chip 110A and spaced away from the first surface 46A, and are arranged in a line along the second direction D2 for each IC chip 110A. The inductors 172 may be provided across multiple IC chips 110A, across one IC chip 110A and the redistribution layer 800 (see Figure 20), or across multiple IC chips 110A and the redistribution layer 800.

[0132] If the memory cube 100A includes a plurality of inductors 172, the bump 167 does not need to be formed on the first surface 46A (first surface 146A, first side surface 106A). For example, a modified method for manufacturing the memory cube 100A is one in which S222 does not include the step of forming the bump 167 on the first surface 46A (first surface 146A, first side surface 106A), but S222 includes the step of forming an insulating layer 49 (see Figures 26A and 26B) on the first surface 46A (first surface 146A, first side surface 106A).

[0133] For example, the insulating layer 49 is formed using a CVD apparatus, similar to the insulating film 155. Furthermore, the insulating layer 49 may also contain an inorganic insulating film such as SiN or SiON, similar to the insulating film 155.

[0134] A modified method for manufacturing the memory cube 100A is to protect the surfaces other than the bottom surface using a thick conductive film 160 according to S220, and to protect the bottom surface using an insulating layer 49 according to S222. Thus, each surface of the stacked memory chip 30A is protected by the thick conductive film 16 or bumps 167 from external damage to the chip surface, chipping of corners, and intrusion of impurities.

[0135] Furthermore, in the manufacturing method of the memory cube 100A, S120 may be performed between S218 and S220.

[0136] Furthermore, the method for manufacturing the memory cube 100 may also include, after S120, a step of forming an insulating layer 49 (see Figures 26A and 26B) on the first surface 46A (first surface 146A, first side surface 106A), similar to a modified example of the method for manufacturing the memory cube 100A.

[0137] Furthermore, the memory cube 100 may not include the multiple inductors 172, but may include power supply wiring 164, grounding wiring 165, and signal transmission wiring 166 exposed on the first surface 46A (first surface 146A, first side surface 106A). In this case, the manufacturing method of the memory cube 100 may be the same as the manufacturing method of the memory cube 100A, with S220 and S222 being performed after S120.

[0138] [Third Embodiment] The memory cube 100B according to the third embodiment will be described with reference to Figures 27 to 36B. Configurations identical or similar to those in Figures 1 to 26 will be described as necessary, and descriptions of identical or similar configurations to those in Figures 1 to 26 may be omitted.

[0139] [3-1. Overview of Memory Cube 100B] First, an overview of Memory Cube 100B will be explained with reference to Figures 27 to 30. Figure 27 is a perspective view showing the configuration of Memory Cube 100B. Figure 28A is an end view showing the end cross-sectional structure of Memory Cube 100B along J1-J2 shown in Figure 27. Figure 28B is an end view showing the end cross-sectional structure of Memory Cube 100B along K1-K2 shown in Figure 27. Figure 29 is a perspective view showing the configuration of IC Chip 110B. Figure 30 is an end view showing the end cross-sectional structure of IC Chip 110B along the line L1-L2 shown in Figure 29. Note that in the perspective view shown in Figure 29, the inclined portion shown in Figure 30 is omitted, and the figure is simplified.

[0140] As shown in Figure 27, Figure 28A, or Figure 28B, the memory cube 100B includes a stacked memory chip 30B, a side power supply wiring 162 and a side ground wiring 163 electrically connected to the stacked memory chip 30B. The stacked memory chip 30B includes a plurality of junction chips 20B. Each of the plurality of junction chips 20B includes two IC chips 110B, each containing a plurality of power supply wirings 164, a plurality of ground wirings 165, and a plurality of signal transmission wirings 166.

[0141] Memory cube 100B differs from memory cube 100 in at least the configurations (6) to (10) shown below. Configuration (6) The first face 146B, second face 148B, third face 145B, fourth face 147B, fifth face 142B and sixth face 144B of memory cube 100B are the faces that replace the first face 146, second face 148, third face 145, fourth face 147, fifth face 142 and sixth face 144 of memory cube 100. Configuration (7) The first face 46B, second face 48B, third face 45B, fourth face 47B, fifth face 42B and sixth face 44B of stacked memory chip 30B are the faces that replace the first face 46, second face 48, third face 45, fourth face 47, fifth face 42 and sixth face 44 of memory cube 100. Configuration (8) The first surface 102B, the second surface 104B (21st surface 109B), the first side surface 106B, the second side surface 105B, the third side surface 108B, and the fourth side surface 107B of the IC chip 110B are surfaces that replace the first surface 102, the second surface 104 (21st surface 109), the first side surface 106, the second side surface 105, the third side surface 108, and the fourth side surface 107 of the IC chip 110. Configuration (9) Power supply wiring 164, ground wiring 165, and signal transmission wiring 166 may be exposed from the first side surface 106B, and a plurality of inductors 172 may be provided at a distance from the first side surface 106B. When the power supply wiring 164, grounding wiring 165, and signal transmission wiring 166 are exposed from the first side surface 106B, the bump 167 is provided so as to be in contact with the exposed power supply wiring 164, grounding wiring 165, and signal transmission wiring 166. Configuration (10) The method for manufacturing the memory cube 100B (see Figures 31 to 36B) includes attaching an adhesive film 70 to a first substrate 50a (see Figure 6) and oxidizing the first substrate 50a, separating the first substrate 50a into a plurality of IC chips 110B using a laser, expand or plasma etching, joining a plurality of different IC chips 110 to form a plurality of bonded chips 20B by B2B bonding using plasma activation, sandwiching the joined plurality of bonded chips 20B with a dummy chip 72, forming a stacked memory chip 30B, and forming the side grounding wiring 163 so as to be in contact with the corners 38 and 39.For example, multiple IC chips 110 that are different from each other are IC chips 110B and IC chips 110 formed using a second substrate 50b which has a configuration similar to that of the first substrate 50a.

[0142] Configurations of Memory Cube 100B other than configurations (6) to (10) and configurations other than those related to configurations (6) to (10) are the same as those of Memory Cube 100. Also, parts of configurations (9) and (10) of Memory Cube 100B are the same as those of Memory Cube 100A. Therefore, when explaining Memory Cube 100B, configurations that are the same as or similar to those of Memory Cube 100 and Memory Cube 100A will be explained as necessary, and explanations of configurations that are the same as or similar to those of Memory Cube 100 and Memory Cube 100A may be omitted.

[0143] Multiple IC chips 110B may simply be referred to as multiple substrates. If the multiple IC chips 110B are not distinguishable, the IC chip is referred to as IC chip 110B. If the multiple IC chips 110B are distinguishable, the IC chip is referred to as IC chip 110Bn, IC chip 110Bn+1, etc. Similarly, if the multiple bonded chips 20B are not distinguishable, the bonded chip is referred to as bonded chip 20B. If the multiple bonded chips 20B are distinguishable, the bonded chip is referred to as bonded chip 20Bn, bonded chip 20Bn+1, etc. The same applies to each side of IC chip 110B and each side of bonded chip 20B.

[0144] Furthermore, in the memory cube 100B, similar to the end view showing the end cross-sectional structure of the memory cube along line B3-B4 in Figure 1, and the end view showing the end cross-sectional structure of the memory cube along line B5-B6 in Figure 1, the power wiring 164 and ground wiring 165 exposed on the corresponding inclined portion are in contact with and covered by the side power wiring 162 and side ground wiring 163. Also, similar to the third surface 145 and third surface 45 along line B3-B4 in Figure 1, the power wiring 164 and ground wiring 165 exposed on the inclined portion corresponding to the fourth surface 147 and fourth surface 47 are in contact with and covered by the side power wiring 162 and side ground wiring 163.

[0145] [3-2. Overview of IC Chip 110B] Next, an overview of IC chip 110B will be described with reference to Figures 29 and 30. Configurations identical or similar to those in Figures 1 to 30 will be described as necessary, and descriptions of identical or similar configurations may be omitted.

[0146] An insulating film 155 is provided on the second surface 104B. An adhesive film 140 is provided on the insulating film 155. The 21st surface 109B is the surface opposite to the side where the adhesive film 140 is in contact with the second surface 104B. As will be described in detail later, the 11th surface 101d is the surface formed by polishing the first surface 101b of the first substrate 50a. An adhesive film 70 is provided on the 11th surface 101d. The first surface 102B is the surface opposite to the side where the adhesive film 70 is in contact with the 11th surface 101d.

[0147] The third side surface 108B, like the third side surfaces 108 and 108A, is in contact with the end of the first surface 102B and the end of the second surface 104B (21st surface 109B) and has an inclined portion. Similar to the third side surface 108B, the second side surface 105B and the fourth side surface 107B are in contact with the end of the first surface 102B and the end of the second surface 104B (21st surface 109B) and have an inclined portion (see Figure 33).

[0148] For example, the angle between the 11th face 101d and the 3rd side surface 108B is an alternate interior angle with the angle between the 1st face 102B and the 3rd side surface 108B. The angle between the 11th face 101d (1st face 102B) and the 3rd side surface 108B is angle α. Similarly, the angle between the 11th face 101d (1st face 102B) and the 2nd side surface 105B, and the angle between the 11th face 101d (1st face 102B) and the 4th side surface 107B are angles α (see, for example, Figure 33). Angle α is greater than 0 degrees and less than 90 degrees.

[0149] In the example shown in Figure 30, the grounding wire 165 is exposed from the third side surface 108B which has an inclined portion, while the power supply wire 164 is exposed from the second side surface 105B which has an inclined portion and the fourth side surface 107B which has an inclined portion. The grounding wire 165 may be exposed from the second side surface 105B which has an inclined portion and the fourth side surface 107B which has an inclined portion, and the power supply wire 164 may be exposed from the third side surface 108B which has an inclined portion.

[0150] The transistor layer 130 and wiring layer 150 in the IC chip 110B have the same configuration as the transistor layer 130 and wiring layer 150 in the IC chip 110.

[0151] [3-3. Method for Manufacturing Memory Cube 100B] The method for manufacturing the memory cube 100B will be described with reference to Figures 6 to 9, Figure 27, Figure 28A and Figure 28B, and Figures 31 to 36B. Figure 31 is a flowchart of the method for manufacturing the memory cube 100B. Figures 6 to 8 are plan views showing steps 302 (S302), 304 (S304), and 306 (S306) of the method for manufacturing the memory cube 100B, and end views showing the end cross-sectional structure of the first base material 50a along the line E1-E2. STEP 108 in Figure 9 is an end view showing the end cross-sectional structure of the first base material 50a along the line E1-E2 in step 308 (S308) of the method for manufacturing the memory cube 100B. Figure 9, STEP 110, is an end view showing the end cross-sectional structure of the first substrate 50a along the E1-E2 line in step 310 (S310) of the manufacturing method of the memory cube 100B. Figure 32 is an end view showing the end cross-sectional structure of the first substrate 50a along the E1-E2 line in steps 310 (S310), 312 (S312), and 314 (S314) of the manufacturing method of the memory cube 100B. Figure 33 is an end view showing the end cross-sectional structure in step 316 (S316) of the manufacturing method of the memory cube 100B. Figure 34 is an end view showing the end cross-sectional structure of the multiple bonded chips 20B in step 318 (S318) of the manufacturing method of the memory cube 100B. Figure 35 is an end view showing the end cross-sectional structure of the stacked memory chip 30B in step 318 (S318) of the manufacturing method of the memory cube 100B. For example, Figure 36 is a perspective view showing the stacked memory chip 30B in step 320 (S320) of the manufacturing method of the memory cube 100B, Figure 27 is a perspective view showing the stacked memory chip 30B in step 322 (S322) of the manufacturing method of the memory cube 100B, and Figures 28A and 28B are end views showing the cross-sectional structure of the end of the stacked memory chip 30B in step 322 (S322) of the manufacturing method of the memory cube 100B. Also, Figures 6 to 9 and Figure 32 include enlarged views of the IC chip area 54. Configurations identical or similar to those in Figures 1 to 30 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 30 may be omitted.

[0152] As shown in Figure 31, the manufacturing method of the memory cube 100B includes steps S302 to S322. Furthermore, the manufacturing method of the memory cube 100B, similar to the manufacturing methods of the memory cubes 100 and 100A, includes, as an example, joining and stacking eight IC chips 110B to form a stacked memory chip 30B. The number of stacked IC chips 110B is not limited to eight (eight chips, eight layers), but may be 16 layers, 32 layers, 64 layers, or even 128 layers. Also, the number of stacked IC chips 110B is not 2n (where n is a non-negative integer), but may be 30 layers, 60 layers, etc. The number of stacked IC chips 110B can be appropriately selected based on the specifications and application of the memory cube 100B, within the limits of the manufacturing method of the memory cube 100B.

[0153] When the manufacturing method for the memory cube 100B is started, the first substrate 50a (see Figure 6) is prepared.

[0154] Steps S302, S304, S306, and S308 are the same as steps S102, S104, S106, and S108, and a detailed explanation is omitted here. Note that steps S302, S304, S306, and S308 refer to STEP 108 in Figures 6 to 9, similar to steps S102, S104, S106, and S108.

[0155] Step S310 is the step of grinding and polishing the first surface 101b to form the eleventh surface 101d. As shown in STEP 310 of Figure 32, the first surface 101b (substrate 173) is ground and polished to form the eleventh surface 101d, and the thickness THI2 of the first substrate 50a in S310 becomes thickness THI7. For example, grinding and polishing can be performed using a CMP apparatus.

[0156] Step S312 is the same as S208, and is a step in which the adhesive film 70 is attached to the 11th surface 101d to form the first surface 102B, and the first substrate 50a is oxidized. As shown in STEP 312 of Figure 32, the adhesive film 70 is attached to the 11th surface 101d. At this time, the surface of the first substrate 50a, i.e., the 11th surface 101d, is oxidized.

[0157] Step S314 is similar to S210, and is a step in which the insulating film 155 and the adhesive film 70 are separated (cut) along the groove 57 using a laser, expander, or plasma etching in the direction from the 21st surface 109B to the 1st surface 102B, thereby dividing the first substrate 50a attached to the dicing tape 71 into multiple IC chips 110B. As shown in STEP 314 of Figure 32, the insulating film 155 formed in the groove 57 is removed, and the sides of the insulating film 155, the sides of the insulating layer 185, the sides of the wiring 183, the sides of the insulating layer 184, the sides of the substrate 173, the sides of the adhesive film 70, and a part of the dicing tape 71 are exposed, and a groove 58 is formed. That is, similar to S210, the sides of the insulating film 155, the sides of the insulating layer 185, the sides of the wiring 183, the sides of the insulating layer 184, the sides of the substrate 173, and the sides of the adhesive film 70 are formed. The grooves 58 are the second side surface 105B and the fourth side surface 107B of the individualized IC chips 110Bn and 110Bn+1. At this time, the shape of the adhesive film 70 includes inclined portions, similar to the substrate 173, and is the same shape as the outer shape of the IC chip 110B in a plan view. For example, the thickness THI6 of the IC chip 110B is 20 μm or more and 1 mm or less.

[0158] Step S316 is a step in which two different IC chips 110 from a plurality of individualized IC chips 110 are joined together to form a single joined chip 20B. Specifically, Step S316 is a step in which two different IC chips 110 are thermally joined by B2B bonding to form a joined chip 20B. For example, as shown in Figure 33, of the two different IC chips 110, one is an IC chip 110n formed using a second substrate 50b which has a similar configuration to the first substrate 50a. The other is an IC chip 110Bn. The adhesive film 70 (first surface 102Bn) of the IC chip 110Bn and the substrate 173 (first surface 102n) of the IC chip 110n are joined by thermocompression bonding to form a joined chip 20Bn.

[0159] For example, S316, like S114, can cancel out the thermal warping of the two IC chips 110 by thermal bonding.

[0160] Step S318 is a step in which the spaces between multiple bonding chips 20B are bonded by plasma activation, and the multiple bonding chips 20B are sandwiched between two dummy chips 72 by plasma activation to form a stacked memory chip 30B. For example, as shown in Figure 34, four bonding chips 20Bn, 20Bn+1, 20Bn+2, and 20Bn+3, as well as a dummy chip 72, are bonded. That is, eight IC chips 110 (four IC chips 110 and four IC chips 110B) and two dummy chips 72 are bonded. More specifically, as shown in Figure 34, one dummy chip 72 and the 21st face 109n of the bonding chip 20Bn are plasma activated, the 21st face 109Bn of the bonding chip 20Bn and the 21st face 109n+1 of the bonding chip 20Bn+1 are plasma activated, the 21st face 109Bn+1 of the bonding chip 20Bn+1 and the 21st face 109n+2 of the bonding chip 20Bn+2 are plasma activated, the 21st face 109Bn+2 of the bonding chip 20Bn+2 and the 21st face 109n+3 of the bonding chip 20Bn+3 are plasma activated, and the 21st face 109Bn+3 of the bonding chip 20Bn+3 and the other dummy chip 72 are plasma activated, and the four bonding chips and the two dummy chips 72 are bonded together to form a stacked memory chip 30B as shown in Figure 35.

[0161] For example, the dummy chip 72 does not include the wiring layer 150 and transistors. For example, the dummy chip 72 is a Si substrate or Si-wafer without memory formed on it. Also, the plasma activation in S318 can be performed in the same way as in S212 and produce the same effect.

[0162] Furthermore, for example, S318 may involve forming one stacked memory chip 30B at a time, similar to S114 and S116, or it may involve forming multiple stacked memory chips 30B together. For example, forming multiple stacked memory chips 30B together may include arranging and forming multiple stacked memory chips 30B on a Si substrate, and batch processing may be used.

[0163] S320 is a step in which electrodes (for example, side power wiring 162, side ground wiring 163, etc.) are electrically connected to a plurality of wirings (for example, power wiring 164, ground wiring 165, etc.) exposed on the second side surface 105B, third side surface 108B, and fourth side surface 107B of the stacked memory chip 30B formed in S318. For example, as shown in Figure 36, the conductive film 160 is formed on the sixth surface 44B, second surface 48B, third surface 45B, fourth surface 47B, and fifth surface 42B of the stacked memory chip 30B formed in S318, excluding the first surface 46B (bottom surface). The surface of the formed conductive film 160 becomes the sixth surface 144B, second surface 148B, third surface 145B, fourth surface 147B, and fifth surface 142B of the stacked memory chip 30B. For example, the conductive film 160 is patterned using photolithography or laser ablation to form the side power wiring 162 and side ground wiring 163 shown in Figure 27, Figure 28A, or Figure 28B.

[0164] One of the two dummy chips 72 is in contact with the fifth surface 142B and is located on the outermost edge of the memory cube 100B in the first direction D1, including its outermost surface. The other of the two dummy chips 72 is in contact with the sixth surface 144B and is located on the outermost edge of the memory cube 100B in the first direction D1, including its outermost surface.

[0165] For example, S320 is a step that can be simplified depending on the equipment used.

[0166] For example, as shown in Figure 36, the conductive film 160 is formed using electroplating (plating method), similar to S220, so as to be in contact with the corners 38 and 39, the multiple power supply wirings 164 and grounding wirings 165 exposed on each side, and also in contact with a part of the substrate 173, a part of the insulating layer 184, and a part of the insulating layer 185. In addition, the conductive film 160 is formed on the sixth surface 44B, the second surface 48B, and the fifth surface 42B, including the corners 38 and 39, similar to S220, as well as on the corners 38 and 39 of the third surface 45B that are separated from the area where the side power supply wirings 162 are formed, and on the corners 38 and 39 of the fourth surface 47B that are separated from the area where the side power supply wirings 162 are formed. The side power supply wirings 162 and side grounding wirings 163 are formed so as to be in contact with a part of the substrate 173, a part of the insulating layer 184, and a part of the insulating layer 185.

[0167] Furthermore, for example, the conductive film 160 contains the same material as S220 and is laminated in the same manner. The manufacturing method of the memory cube 100B allows for the formation of a thick conductive film 160 on the corners 38 and 39 of the laminated memory chip 30B, as well as on each surface including the corners 38 and 39, using a plating method, and achieves the same effects as the manufacturing method of the memory cube 100A.

[0168] S322 is a step similar to S222 in which a bump 167 is formed that is electrically connected to a plurality of wires (for example, power supply wires 164, grounding wires 165, signal transmission wires 166, etc.) exposed on the first side surface 106B (first surface 46B, first surface 146B). For example, as shown in Figures 28A and 28B, the bump 167 is formed to contact and cover the power supply wires 164, grounding wires 165, and signal transmission wires 166, respectively.

[0169] The manufacturing method of the memory cube 100B allows for the protection of surfaces other than the bottom surface using a thick conductive film 160 in step S320, and the protection of the bottom surface using bumps 167 in step S322. Therefore, the manufacturing method of the memory cube 100B has the same effects as the manufacturing method of the memory cube 100A.

[0170] Furthermore, the manufacturing method for the memory cube 100B may be the same as that described in "3-4. Modified Examples".

[0171] [Fourth Embodiment] A method for manufacturing the memory cube 100 according to the fourth embodiment will be described with reference to Figures 37 to 39. Figure 37 is a flowchart showing the method for manufacturing the memory cube 100 according to the fourth embodiment. Figure 38 is a perspective view showing steps 416 (S416) and 418 (S418) of the method for manufacturing the memory cube 100 according to the fourth embodiment. Figure 39 is a perspective view showing step 420 (S420) of the method for manufacturing the memory cube 100 according to the fourth embodiment. Configurations identical or similar to those in Figures 1 to 36 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 36 may be omitted.

[0172] The manufacturing method of the memory cube 100 according to the fourth embodiment differs from the manufacturing method of the memory cube 100 according to the first embodiment in at least the configurations (11) to (13) shown below. Configuration (11) Using a vibrating and pressurizing jig 850, the multiple bonding chips 20 are mechanically aligned and bonded together by vibration and pressurization to form a stacked memory chip 30. Configuration (12) The multiple bonding chips 20 are aligned and bonded together, and an organic film 65 is applied to corners 39a, 39b and 39c of the four corners 39 to fix the positions of the multiple bonding chips 20. Configuration (13) The organic film 65 is applied to the remaining corner 39d of the four corners 39 and between each bonding chip 20 to form a stacked memory chip 30.

[0173] The configurations of the memory cube 100 according to the fourth embodiment, other than configurations (11) to (13) and configurations other than those related to configurations (11) to (13), are the same as those of the memory cube 100 according to the first embodiment. Therefore, when describing the memory cube 100 according to the fourth embodiment, configurations that are the same as or similar to the memory cube 100 and the manufacturing method of the memory cube 100 according to the first embodiment will be described as necessary, and descriptions of configurations that are the same as or similar to the memory cube 100 and the manufacturing method of the memory cube 100 according to the first embodiment may be omitted.

[0174] As shown in Figure 37, the manufacturing method of the memory cube 100 according to the fourth embodiment includes steps S402 to S424. Furthermore, the manufacturing method of the memory cube 100 according to the fourth embodiment, similar to the manufacturing method of the memory cube 100 according to the first embodiment, includes, for example, joining and stacking eight IC chips 110 to form a stacked memory chip 30. Also, similar to the manufacturing method of the memory cube 100 according to the first embodiment, the number of stacked IC chips 110 can be appropriately selected based on the specifications and applications of the memory cube 100 according to the fourth embodiment, within the limits of the manufacturing method of the memory cube 100 according to the fourth embodiment.

[0175] When the manufacturing method for the memory cube 100 according to the fourth embodiment is started, the first substrate 50a (see Figure 6) is prepared.

[0176] Steps 402 (S402), 404 (S404), 406 (S406), 408 (S408), 410 (S410), 412 (S412), and 414 (S414) are the same as S102, S104, S106, S108, S110, S112, and S114, and a detailed explanation is omitted here. Also, part of step 422 (S422) and step 424 (S424) are the same as S120 and S122, and a detailed explanation is omitted here.

[0177] S416 is executed after S414. S416 is a step in which multiple bonding tips 20 are placed in a jig 850 that can be vibrated and pressurized. For example, as shown in Figure 38, four bonding tips 20n, 20n+1, 20n+2 and 20n+3 are placed (arranged) in the jig 850.

[0178] The jig 850 includes three reference surfaces 80a, 80b, and 80c. Multiple bonding tips 20 are pressed against the three reference surfaces 80a, 80b, and 80c and installed (positioned) in the jig 850.

[0179] Step S418 is a step in which multiple bonding chips 20 and a jig 850 are vibrated, and multiple bonding chips 20 are pressed along a first direction D1 perpendicular to the first surface 102, thereby aligning and bonding the multiple bonding chips 20 to form a stacked memory chip 30. For example, as shown in Figure 38, S418 includes vibrating four bonding chips 20 and a jig 850 from side to side along a second direction D2. For example, in this case, S418 includes applying light pressure (pressure) along the first direction D1 perpendicular to the first surface 102n+6 of the bonding chips 20n+3 to the extent that the positions of the four bonding chips 20 can be moved by the vibration. Note that the four bonding chips 20 and the jig 850 may be vibrated not only along the second direction D2, but also along the first direction D1 and the third direction D3, to the extent that the bonding chips 20 are not damaged.

[0180] As a result, the manufacturing method of the memory cube 100 according to the fourth embodiment allows for mechanical alignment between the multiple bonding chips 20, so that the ends and corners 39d of the surfaces of the multiple bonding chips 20 that contact the jig 850 can be aligned (adjusted). For example, as shown in Figure 38, the surfaces of the multiple bonding chips 20 that contact the jig 850 are the second side surface 105 (third surface 45), the third side surface 108 (second surface 48), and so on.

[0181] Step S420 is the step of applying an organic film 65 to three of the four corners 39a, 39b, and 39c of the stacked memory chip 30 formed in S418. In the manufacturing method of the memory cube 100 according to the fourth embodiment, step S420 allows the three corners of the stacked memory chip 30 to be secured using the organic film 65 and the position of the stacked memory chip 30 to be fixed.

[0182] Step S422 is a step in which an organic film 65 is applied to the remaining corner 39d of the four corners 39 and between each bonding chip 20, and the organic film 65 is cured by UV irradiation to form a stacked memory chip 30. In the manufacturing method of the memory cube 100 according to the fourth embodiment, the position of the stacked memory chip 30 can be fixed more firmly by step S422.

[0183] [Fifth Embodiment] A method for manufacturing the memory cube 100 according to the fifth embodiment will be described with reference to Figures 40 to 44. Figure 40 is a flowchart showing the method for manufacturing the memory cube 100 according to the fifth embodiment. Figure 41 is a plan view showing step 502 (S502) in the method for manufacturing the memory cube 100 according to the fifth embodiment, and an end view showing the end cross-sectional structure of the first substrate 50a along the line M1-M2. Note that the plan view shown in Figure 41 is an enlarged plan view of the IC chip area 54 of the first substrate 50a in the method for manufacturing the memory cube 100 according to the fifth embodiment. Figure 42 is an end view showing the end cross-sectional structures of the first substrate 50a and the second substrate 50b along the line M1-M2 showing step 502 (S502) in the method for manufacturing the memory cube 100 according to the fifth embodiment. Figure 43 is an end view showing the end cross-sectional structures of steps 504 (S504), 506 (S506), and 508 (S508) in the method for manufacturing the memory cube 100 according to the fifth embodiment. Figure 44 is an end view showing the cross-sectional structure of the end of the bonded chip 20Cn and 20Cn+1 in step 510 (S510) of the manufacturing method of the memory cube 100. Also, parts of Figures 41 to 44 are enlarged views of the IC chip area 54. Configurations identical or similar to those in Figures 1 to 39 will be described as necessary, and descriptions of identical or similar configurations in Figures 1 to 39 may be omitted.

[0184] The manufacturing method of the memory cube 100 according to the fifth embodiment differs from the manufacturing method of the memory cube 100 according to the fourth embodiment in at least the configurations (14) to (17) shown below. Configuration (14): A first substrate 50a and a second substrate 50b having the same configuration as the first substrate 50a are fusion-bonded to form a bonded substrate. Configuration (15): The first surface 101b of the second substrate 50b is polished to form a third surface 756. Configuration (16): Grooves 758 are formed by plasma grooving, and an insulating film 155 is formed in the grooves 758. Configuration (17): The first surface 101b of the first substrate 50a is polished to separate the bonded substrate of the first substrate 50a and the second substrate 50b into a plurality of bonded chips 20C.

[0185] The configurations of the memory cube 100 according to the fifth embodiment, other than configurations (14) to (17) and configurations other than those related to configurations (14) to (17), are the same as those of the memory cube 100 according to the fourth embodiment. Therefore, when describing the memory cube 100 according to the fifth embodiment, configurations that are the same as or similar to the memory cube 100 and the manufacturing method of the memory cube 100 according to the fourth embodiment will be described as necessary, and the description of configurations that are the same as or similar to the memory cube 100 and the manufacturing method of the memory cube 100 according to the fourth embodiment may be omitted.

[0186] As shown in Figure 40, the method for manufacturing the memory cube 100 according to the fifth embodiment includes steps S502 to S520. Furthermore, the method for manufacturing the memory cube 100 according to the fifth embodiment, similar to the method for manufacturing the memory cube 100 according to the fourth embodiment, includes, as an example, bonding and stacking eight IC chips 110C (four bonding chips 20C) to form a stacked memory chip 30. Also, similar to the method for manufacturing the memory cube 100 according to the first embodiment, the number of stacked IC chips 110C (bonding chips 20C) can be appropriately selected based on the specifications and applications of the memory cube 100 according to the fifth embodiment, within the limits of the method for manufacturing the memory cube 100 according to the fifth embodiment.

[0187] When the manufacturing method for the memory cube 100 according to the fifth embodiment is started, a first substrate 50a (see Figure 6) and a second substrate 50b having the same configuration as the first substrate 50a are prepared.

[0188] As shown in Figure 6 or Figure 41, the first substrate 50a includes an IC chip region 54, and the IC chip region 54 includes a separation region 754. The separation region 754 is a region for separating a plurality of joined substrates (joined substrates). For example, when a joined substrate is separated, the separated joined substrate includes a plurality of joined chips 20C, and one of the plurality of joined chips 20C includes two (two) IC chips 110C. The configuration of the IC chip 110C is the same as the configuration of the IC chip 110, and a description of the IC chip 110C is omitted here.

[0189] Step S502 is a step in which two prepared substrates (a first substrate 50a and a second substrate 50b) are fusion-bonded to form a single bonded substrate. For example, as shown in the end view of the IC chip region 54 enlarged along the M1-M2 line of the first substrate 50a and the second substrate 50b, the second surface 101a of the first substrate 50a and the second surface 101a of the second substrate 50b are F2F-bonded by fusion bonding.

[0190] Step S504 includes grinding and polishing the first surface 101b (substrate 173) of the second substrate 50b of the bonding substrate to form a third surface 756. Specifically, as shown in STEP 504 of Figure 43, the third surface 756 is formed, and the thickness of the bonding substrate THI9 becomes a thickness THI10, thus thinning the bonding substrate.

[0191] Step S506 is a step in which grooves 758 are formed by plasma grooving to demarcate each of the multiple bonding chips 20C in the divided region 754. Plasma grooving is the same as the method described in "1-3. Method for Manufacturing Memory Cube 100". For example, as shown in STEP 406 of Figure 43, grooves 758 in the bonding substrate between the first substrate 50a and the second substrate 50b are formed by plasma grooving. The grooves 758 are formed in the insulating layer 185 included in the wiring layer 150, the wiring 183, the insulating layer 184 included in the transistor layer 130, and the substrate 173. For example, the ends of the wiring 183 are exposed in the grooves 758.

[0192] Step S508 is the step of forming the insulating film 155 on the third surface 756 and on the groove 758. As shown in STEP 508 of Figure 43, the insulating film 155 is formed on the upper surface of the substrate 173 of the second base material 50b, the upper surface of the insulating layer 185, the side surface of the substrate 173 of the second base material 50b exposed by the groove 758, the side surface of the insulating layer 184, the side surface of the insulating layer 185 and the side surface of the wiring 183, and the side surface of the insulating layer 185, the side surface of the wiring 183, the side surface of the insulating layer 184 and the side surface of the substrate 173 of the first base material 50a exposed by the groove 758. The surface opposite to the third surface 756 in contact with the insulating film 155 is the 31st surface 760. The insulating film 155 is formed using the same apparatus and materials as described in "1-3. Method for Manufacturing Memory Cube 100".

[0193] Step S510 is a step in which the bonding substrate is ground and polished, and the bonding substrate is divided into multiple bonding chips 20C, thereby forming multiple bonding chips 20C. Specifically, as shown in Figure 44, the first surface 101b of the first substrate 50a is ground and polished to form a fourth surface 762 (762n, 762n+1). At this time, the bonding substrate is divided into multiple bonding chips 20C, including bonding chips 20Cn and 20Cn+1. For example, grinding and polishing are performed using a CMP device.

[0194] For example, the bonded chip 20Cn has sides similar to those of the IC chip 110. Specifically, the second side surface 105C is in contact with the end of the 31st surface 760n and the end of the 4th surface 762n and has an inclined portion. Similarly to the second side surface 105C, the third side surface 108C (not shown) and the fourth side surface 107C are in contact with the end of the 31st surface 760n and the end of the 4th surface 762n and have inclined portions.

[0195] For example, the angle between the fourth surface 762n and the second side surface 105C is angle α. Similarly, the angle between the second side surface 105C and the fourth surface 762n, and the angle between the fourth surface 762n and the third side surface 108C, and the angle between the fourth surface 762n and the fourth side surface 107 are also angles α. Angle α is greater than 0 degrees and less than 90 degrees.

[0196] Steps 512 (S512), 514 (S514), 516 (S516), 518 (S518), and 520 (S520) are the same as steps S416, S418, S420, S422, and S42, and a detailed explanation of them is omitted here. Steps 512 (S512), 514 (S514), 516 (S516), 518 (S518), and 520 (S520) are performed using the bonded chip 20C.

[0197] The memory cube 100 and the method for manufacturing the memory cube 100 according to the fifth embodiment have the same effects and advantages as the memory cube 100 and the method for manufacturing the memory cube 100 according to the fourth embodiment.

[0198] [Sixth Embodiment] As one example of the application of the memory cubes 100, 100A, and 100B, a semiconductor module 10 according to the sixth embodiment will be described with reference to Figures 45 to 49. Configurations identical or similar to those in Figures 1 to 44 will be described as necessary, and descriptions of identical or similar configurations to those in Figures 1 to 44 may be omitted.

[0199] [6-1. Overview of Semiconductor Module 10] First, an overview of the semiconductor module 10 will be described with reference to Figures 45 and 46. Figure 45 is a perspective view showing the configuration of the semiconductor module 10. Figure 46 is an end view showing the cross-sectional structure of the end of the semiconductor module 10 along N1-N2 shown in Figure 45.

[0200] As shown in Figures 45 and 46, the semiconductor module 10 includes a memory cube 100, a first substrate 300, a logic chip 200, and an adhesive layer 400. The semiconductor module 10 may also include a bump layer 500 and a substrate 600. For example, the first substrate 300 may be referred to as the first semiconductor chip, and the logic chip 200 may be referred to as the second semiconductor chip. The semiconductor module 10 may include a memory cube 100A or 100B instead of the memory cube 100. In this case, the memory cube 100A or 100B may be appropriately adjusted to be applicable to the configuration of the semiconductor module 10.

[0201] The memory cube 100 includes an inductor layer 170 containing a plurality of inductors 172. To facilitate understanding of the semiconductor module 10, the illustrations in Figure 46 are simplified, including the IC chip 110, junction chip 20, stacked memory chip 30, each side of the stacked memory chip 30, power supply wiring 164, ground wiring 165, side power supply wiring 162, side ground wiring 163, etc., as shown in Figures 1, 2A, or 2B.

[0202] The first surface 146 is the bottom surface of the memory cube 100 and is the surface that contacts the adhesive layer 400. The first surface 146 is also positioned to face the first surface 302 of the first substrate 300, and the memory cube 100 is placed on the first surface 302 of the first substrate 300.

[0203] The first substrate 300 includes an inductor layer 370 containing a plurality of inductors 372, a first surface 302, and a second surface 304. The first surface 302 and the second surface 304 are surfaces parallel to the first direction D1 and the second direction D2. The second surface 304 is positioned to face the first surface 202 of the logic chip 200 and is also in contact with the first surface 202 of the logic chip 200. The first surface 302 is in contact with the adhesive layer 400 and is positioned to face the first surface 146 of the memory cube 100.

[0204] Furthermore, the first substrate 300 is a semiconductor chip having a configuration similar to that of the IC chip 110. For example, the first substrate 300 includes an inductor layer 370, and the inductor layer 370 includes a wiring layer 150 (see Figure 3). The inductor layer 370 is provided on the first surface 302 side, and the multiple inductors 372 are arranged in a matrix along the first direction D1 and the second direction D2 parallel to the first surface 302 (see Figure 4), and are also arranged at a distance from the first surface 302.

[0205] The logic chip 200 includes a first surface 202 and a second surface 204. The first surface 202 and the second surface 204 are surfaces parallel to the first direction D1 and the second direction D2. As described above, the first surface 202 is positioned facing the second surface 304 of the first substrate 300, and the logic chip 200 is stacked (bonded) to the second surface 304 of the first substrate 300. Furthermore, the logic chip 200 is a semiconductor chip that includes a configuration similar to that of the IC chip 110. For example, the logic chip 200 includes a wiring layer 150 (see Figure 3), and the wiring of the wiring layer 150 is used as electrodes to electrically connect to the bumps 51 included in the bump layer 500.

[0206] The first substrate 300 and the logic chip 200 may be a single IC chip. That is, a single IC chip may be a chip in which the configuration of the first substrate 300 and the configuration of the logic chip 200 are integrated, and may have the functions of both the first substrate 300 and the logic chip 200.

[0207] As described above, the adhesive layer 400 is placed between the memory cube 100 and the first substrate 300 to bond the memory cube 100 and the first substrate 300. The adhesive layer 400 may be an adhesive containing, for example, an epoxy resin or an acrylic polymer, a die bonding film (DBF) containing an epoxy resin or an acrylic polymer, or an adhesive film such as a die attach film.

[0208] The substrate 600 includes a multilayer wiring structure (not shown) in which wiring and insulating layers are alternately stacked, a first surface 602, and a second surface 604. For example, the multilayer wiring structure includes electrodes 62 exposed on the first surface 602. The electrodes 62 are electrically connected to the bumps 51, and the semiconductor module 10 is electrically connected to the substrate 600. For example, the semiconductor module 10 is connected to an external substrate and external circuits via the substrate 600, and various control signals and power supply voltages are supplied to the semiconductor module 10 from the external substrate and external circuits.

[0209] [6-2. Functional Block Configuration of Semiconductor Module 10] Next, the functional block configuration of the semiconductor module 10 will be described with reference to Figure 47. Figure 47 is a block diagram showing the functional block configuration of the semiconductor module 10. Configurations identical or similar to those in Figures 1 to 46 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 46 may be omitted.

[0210] As explained in "6-1. Overview of Semiconductor Module 10", the semiconductor module 10 includes a memory cube 100, a first substrate 300, and a logic chip 200.

[0211] The memory cube 100 includes a plurality of magnetic field coupled chip interfaces (Through Chip Interface-IO, TCI-IO) 112 and a plurality of memory modules 111. The plurality of TCI-IOs 112 are electrically connected to the memory modules 111. For example, the memory cube 100 includes functions for storing received data and transmitting stored data.

[0212] The TCI-IO112 includes multiple inductors 172, a transmit / receive circuit 114, and a parallel / series conversion circuit 113. The inductors 172 are electrically connected to the transmit / receive circuit 114 using terminals A and B. The transmit / receive circuit 114 is electrically connected to the parallel / series conversion circuit 113. The parallel / series conversion circuit 113 is electrically connected to the memory module 111.

[0213] The inductor 172 has the function of communicating with the inductor 372 of the first substrate 300 via contactless inductor communication.

[0214] For example, the transmitting / receiving circuit 114 has the function of amplifying the signal (e.g., control signal and data signal) received by the inductor 172, and the function of removing noise from the received signal (e.g., control signal and data signal). Also, for example, the transmitting / receiving circuit 114 has the function of transmitting the desired signal (e.g., control signal and data signal) converted using the parallel-to-series conversion circuit 113 onto radio waves. The signal received by the inductor 172 includes a number of parallel signals from the inductor 172. The desired signal includes a number of parallel signals from the memory module 111.

[0215] For example, in step 1, the parallel-to-serial conversion circuit 113 converts multiple parallel signals from the first board 300 into a series signal. The series signal is transmitted at high speed using a single signal path (wiring). In step 2, just before the memory module 111, the parallel-to-serial conversion circuit 113 converts the series signal back into multiple parallel signals, and then transmits the multiple parallel signals to the memory module 111. For example, when transmitting signals (e.g., control signals and data signals) from the memory module 111 to the first board 300, the parallel-to-serial conversion circuit 113 executes step 1 after step 2. The parallel-to-serial conversion circuit 113 is sometimes referred to as a SerDes circuit (Serialize and Deserialize Circuit).

[0216] For example, the memory module 111 includes a plurality of memory cell arrays 115 (see Figure 49). The memory module 111 includes functions for generating a plurality of parallel signals to transmit, and for controlling a plurality of parallel signals received and storing them in the memory cell arrays 115.

[0217] The first substrate 300 includes a plurality of TCI-IO 312s. The plurality of TCI-IO 312s are electrically connected to the TCI-IO control module 311.

[0218] The TCI-IO 312 includes multiple inductors 372, a transceiver circuit 314, and a parallel-to-series conversion circuit 313. The inductors 372 are electrically connected to the transceiver circuit 314 using terminals C and D. The transceiver circuit 314 is electrically connected to the parallel-to-series conversion circuit 313. For example, the parallel-to-series conversion circuit 313 is electrically connected to the TCI-IO control module 311.

[0219] The configuration and functions of the inductor 372, the transmitting / receiving circuit 314, and the parallel / series conversion circuit 313 are the same as those of the inductor 172, the transmitting / receiving circuit 114, and the parallel / series conversion circuit 113.

[0220] The logic chip 200 includes a logic module 211. The logic chip 200 may include multiple logic modules 211. The logic modules 211 are electrically connected to the TCI-IO control module 311.

[0221] For example, the logic chip 200 may include a plurality of DRAM interfaces (Dynamic Random Access Memory (DRAM) I / O) (not shown) and a plurality of external I / O (not shown).

[0222] The logic module 211 has functions for controlling the transmission of signals (data) to the TCI-IO control module 311, or the reception of signals (data) from the TCI-IO control module 311. The logic module 211 also has a function for driving the memory module 111 within the IC chip 110. Furthermore, the logic module 211 receives voltages such as VDD and VSS from an external circuit, receives a control program stored in the DRAM module from the DRAM module, and executes the processing of the control program. For example, the logic module 211 may include an arithmetic circuit such as a CPU (Central Processing Unit) and transmit signals to drive the memory module 111 via the TCI-IO 312.

[0223] For example, DRAMIO is electrically connected to a DRAM module (not shown) electrically connected on the substrate 600 and has the function of transmitting and receiving signals between the DRAM module and the logic chip 200. For example, external I / O is electrically connected to an external circuit (not shown, for example, a power supply circuit) between the logic chip 200 and an external circuit (not shown, for example, a power supply circuit) and has the function of transmitting and receiving signals between the external circuit and the logic chip 200.

[0224] [6-3. Overview of Inductor Communication] Next, an overview of inductor communication will be explained with reference to Figure 48. Figure 48 is a perspective view showing a plurality of inductors 172 included in the memory cube 100 and a plurality of inductors 372 included in the first substrate 300, and is a perspective view showing the configuration of inductors 172 and inductors 372. Configurations identical or similar to those in Figures 1 to 47 will be explained as necessary, and explanations of configurations identical or similar to those in Figures 1 to 47 may be omitted.

[0225] Each of the multiple inductors 172 includes terminal A, terminal B, a first portion 172a, a second portion 172b, a third portion 172c, a fourth portion 172e, and a fifth portion 172d.

[0226] The fifth portion 172d extends in the second direction D2, with one end of the fifth portion 172d electrically connected to terminal A, and the other end of the fifth portion 172d electrically connected to one end of the fourth portion 172e. The fourth portion 172e extends in the third direction D3, with the other end of the fourth portion 172e electrically connected to one end of the first portion 172a. The first portion 172a extends in the second direction D2, with the other end of the first portion 172a electrically connected to one end of the second portion 172b. The second portion 172b extends in the third direction D3, with the other end of the second portion 172b electrically connected to one end of the third portion 172c. The third portion 172c extends in the second direction D2, with the other end of the third portion 172c electrically connected to terminal B.

[0227] The multiple inductors 372 included in the first substrate 300 are arranged in a matrix along the first direction D1 and the second direction D2. Each of the multiple inductors 372 includes terminal C, terminal D, a first portion 372a, a second portion 372b, a third portion 372c, a fourth portion 372e, and a fifth portion 372d.

[0228] The fifth portion 372d extends in the second direction D2, with one end of the fifth portion 372d electrically connected to terminal C, and the other end of the fifth portion 372d electrically connected to one end of the fourth portion 372e. The fourth portion 372e extends in the first direction D1, with the other end of the fourth portion 372e electrically connected to one end of the first portion 372a. The first portion 372a extends in the second direction D2, with the other end of the first portion 372a electrically connected to one end of the second portion 372b. The second portion 372b extends in the first direction D1, with the other end of the second portion 372b electrically connected to one end of the third portion 372c. The third portion 372c extends in the second direction D2, with the other end of the third portion 372c electrically connected to terminal D.

[0229] Since the IC chips 110n and 110n+1 are positioned perpendicular to the first substrate 300, the inductor 172 is positioned opposite the inductor 372 at a 90-degree angle. When viewed from the third direction D3 in a plane parallel to the first direction D1 and the second direction D2, the first portion 172a of the inductor 172 and the first portion 372a of the inductor 372 overlap and are positioned parallel to each other. Among the multiple inductors 172 and multiple inductors 372, one inductor 172 and one inductor 372 that are facing each other are magnetically coupled, enabling one-to-one contactless communication between the inductors. For example, the communication between inductors due to magnetic field coupling is referred to as inductor communication, signal communication, data communication, etc.

[0230] For example, inductors 172 and 372 are positioned facing each other at a 90-degree angle, enabling one-to-one communication through magnetic field coupling. In the example shown in Figure 48, the magnetic field is generated by the first portion 172a of inductor 172 and the first portion 272a of inductor 372. More specifically, effective inductor communication is performed by the first portion 172a of inductor 172 and the first portion 372a of inductor 372. The first portion 172a primarily functions to communicate with the first portion 372a. The second portion 172b, third portion 172c, fourth portion 172e, and fifth portion 172d of inductor 172, excluding the first portion 172a, primarily function to supply current to the first portion 172a. Similar to inductor 172, the second portion 372b, third portion 372c, fourth portion 372e, and fifth portion 372d of inductor 372, excluding the first portion 372a, primarily function to supply current to the first portion 372a. Note that the magnetic field shown in Figure 5 is an example, and the magnetic field actually generated is not limited to the magnetic field shown in Figure 48.

[0231] Inductor 372 has the same configuration and function as inductor 172. In semiconductor module 10, viewing a plane parallel to the second direction D2 and the third direction D3 from the first direction D1 may be referred to as a front view, and viewing a plane parallel to the first direction D1 and the second direction from the third direction D3 may be referred to as a plan view.

[0232] Furthermore, when the inductor 172 is provided across multiple IC chips 110, the first portion 172a, second portion 172b, third portion 172c, fourth portion 172e, and fifth portion 172d of the inductor 172 are provided parallel to and opposite the first portion 372a, second portion 372b, third portion 372c, fourth portion 372e, and fifth portion 372d of the inductor 372.

[0233] As explained above, the memory cube 100 can transmit and receive signals using non-contact inductor communication, rather than transmitting and receiving signals via a signal path that is routed over a long distance using wiring, through electrodes, and bumps between the first substrate 300 and the memory cube 100.

[0234] As a result, the manufacturing process of the semiconductor module 10 can suppress long-distance wiring using wiring, through electrodes, and bumps, thereby reducing manufacturing costs and preventing a decrease in manufacturing yield. Furthermore, the semiconductor module 10 can suppress long-distance wiring using wiring, through electrodes, and bumps, thereby suppressing resistance and parasitic capacitance caused by wiring. Consequently, inductor communication using the semiconductor module 10 can suppress the power consumption of the semiconductor module 10.

[0235] [6-4. Functional Block Configuration of the Stacked Memory Chip 30] Next, the functional block configuration of the stacked memory chip 30 will be described with reference to Figure 49. Figure 49 is a block diagram showing the functional block configuration of the stacked memory chip 30. Configurations identical or similar to those in Figures 1 to 48 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 48 may be omitted.

[0236] The stacked memory chip 30 includes a plurality of memory modules 111. Each of the plurality of memory modules 111 includes a memory cell array 115. The plurality of memory modules 111 are electrically connected to a plurality of power lines 164, a plurality of ground lines 165, and a plurality of signal transmission lines 166.

[0237] For example, multiple signal transmission lines 166 are electrically connected to the TCI-IO 112. The multiple signal transmission lines 166 are connected to the first board 300 and an external circuit (not shown) by inductor communication, and signals including control signals such as address signals and enable signals, and data for controlling the IC chip 110 are supplied from the first board 300 and the external circuit.

[0238] The memory cell array 115 includes a plurality of memory cells (not shown in the figure). Each of the plurality of memory cell arrays 115 is, for example, an SRAM (Static Random Access Memory), and each of the plurality of memory cells is an SRAM cell. The SRAM, SRAM cell, and memory module 111 for the SRAM can employ technologies used in the field of SRAM. Therefore, a detailed explanation is omitted here. Note that the plurality of memory cell arrays 115 and the plurality of memory cells may be memory cell arrays and memory cells other than SRAM.

[0239] [Seventh Embodiment] As one example of the application of the memory cubes 100, 100A, and 100B, semiconductor modules 10A to 10C according to the seventh embodiment will be described with reference to Figures 50 to 55. Configurations identical or similar to those in Figures 1 to 50 will be described as necessary, and descriptions of identical or similar configurations may be omitted.

[0240] [7-1. Overview of Semiconductor Module 10A] An overview of the semiconductor module 10A will be described with reference to Figure 50. Figure 50 is a perspective view showing the configuration of the semiconductor module 10A. Configurations identical or similar to those in Figures 1 to 49 will be described as necessary, and descriptions of identical or similar configurations to those in Figures 1 to 49 may be omitted.

[0241] The semiconductor module 10A includes a memory cube 100A, a logic chip 700, and a redistribution layer 800. For example, the memory cube 100A, the logic chip 700, and the redistribution layer 800 constitute a structure 25. The semiconductor module 10A may include a substrate 600 and a bump layer 500. The logic chip 700 may be referred to as a second semiconductor chip. As will be described in detail later, the structure 25 may include elements other than the memory cube 100A, the logic chip 700, and the redistribution layer 800. The semiconductor module 10A may include a memory cube 100 or 100B instead of the memory cube 100A. In this case, the memory cube 100 or 100B may be appropriately adjusted to be applicable to the configuration of the semiconductor module 10A.

[0242] To facilitate understanding of the semiconductor module 10, Figure 50 simplifies the illustration of the IC chip 110, bonding chip 20, stacked memory chip 30, each side of the stacked memory chip 30, power supply wiring 164, grounding wiring 165, signal transmission wiring 166, side power supply wiring 162, side grounding wiring 163, etc., as shown in Figures 16, 17A, 17B, or 18.

[0243] The first face 146A of the memory cube 100A is the outermost face on which the logic chip 700 is placed. To facilitate understanding of the semiconductor module 10A, the illustrations of the IC chip 110A, junction chip 20A, stacked memory chip 30A, each face of the stacked memory chip 30A, power wiring 164, ground wiring 165, side power wiring 162, side ground wiring 163, etc., of the memory cube 100A described in the "Second Embodiment" have been simplified. In the semiconductor module 10A, the power wiring 164, ground wiring 165, and signal transmission wiring 166 are electrically connected to the redistribution layer 800 instead of the bumps 167.

[0244] For example, the logic chip 700 includes a first surface 702 and a second surface 704 parallel to a first direction D1 and a second direction D2 intersecting the first direction D1, a wiring layer 750, and a transistor layer 730. The first surface 702 is the surface on which the rewiring layer 800 is placed, and the second surface 704 is the surface on which the substrate 600 is placed. The wiring layer 750 and the transistor layer 730 are stacked in a third direction D3 parallel to the first surface 702 and the second surface 704. The substrate 773 is positioned below the third direction D3 (towards the second surface 704), and the wiring layer 750 is stacked above the substrate 773 (towards the first surface 702) with respect to the third direction D3. For example, the substrate 773 (second surface 704) of the logic chip 700 is placed on the substrate 600, and the logic chip 700 is face-up mounted on the substrate 600.

[0245] The logic chip 700 has the same configuration as the IC chip 110. The transistor layer 730 and wiring layer 750, including the substrate 773, in the logic chip 700 correspond to the transistor layer 130 and wiring layer 150, including the substrate 173, in the IC chip 110. Furthermore, the logic chip 700 includes multiple transistors formed in the same manner as transistor 176 (see Figure 4), and includes multiple logic circuits configured using multiple transistors, and can drive the memory cube 100A using multiple logic circuits.

[0246] The redistribution layer 800 is positioned between the first face 146A of the memory cube 100A and the first face 702 of the logic chip 700, and is directly connected to the memory cube 100A. The redistribution layer 800 has the function of electrically connecting the memory cube 100A and the logic chip 700.

[0247] Furthermore, for example, the redistribution layer 800 is a fan-in type redistribution layer. A fan-in type is a type of mounting in which, in a chip that includes a plurality of input / output terminals arranged in an array on the surface of the chip, a group of wires electrically connected to the chip is routed from the outside of the chip toward the plurality of input / output terminals on the inside. As shown in Figure 50, the fan-in type includes the group of wires being electrically connected to the input / output terminals in such a way that they taper inward from the periphery (outside) of the chip. Also, for example, although not shown in the figure, in a plan view, the fan-in type includes the group of wires being electrically connected to the input / output terminals in such a way that they taper inward from the periphery (outside) of the chip.

[0248] The substrate 600 includes a configuration similar to that described in "6-1. Overview of the Semiconductor Module 10". The substrate 600 has the function of connecting the memory cube 100A and logic chip 700, etc., to an external substrate and external circuits, etc.

[0249] For example, the substrate 600 may be a printed circuit board capable of high-density interconnection (HDI). Also, as shown in Figure 53, for example, the substrate 600 includes wiring layers 606, 608, 610, and 612. The wiring layers 606, 608, 610, and 612 are arranged parallel to the first direction D1 and the second direction D2 and are stacked in this order along the third direction D3. The plurality of wiring layers 606, 608, 610, and 612 include a plurality of wires 607, a plurality of wires 609, a plurality of wires 611, and a plurality of wires 613. For example, wire 607 is electrically connected to wire 609, wire 609 is electrically connected to wire 611, and wire 611 is electrically connected to wire 613.

[0250] The bump layer 500 includes a configuration similar to that described in "6-1. Overview of the Semiconductor Module 10". The bump layer 500 has the function of connecting the substrate 600 on which the memory cube 100A and logic chip 700 are mounted to an external substrate and external circuits.

[0251] The memory cube 100A has lengths MCBX, MCBY, and MCBZ along the first direction D1, the second direction D2, and the third direction D3. The redistribution layer 800 has lengths MCBX and MCBY along the first direction D1 and the second direction D2. The length of the redistribution layer 800 in the third direction D3 is arbitrary. The logic chip 700 has lengths LCX and LCY along the first direction D1 and the second direction D2. The length of the logic chip 700 in the third direction D3 is arbitrary. Length MCBX is longer than length LCX, and length MCBY is longer than length LCY. That is, the size of the memory cube 100A is larger than the size of the logic chip 700.

[0252] [7-2. Functional Block Configuration of Semiconductor Module 10A] Next, the functional block configuration of semiconductor module 10A will be described with reference to Figure 51. Figure 51 is a block diagram showing the functional block configuration of semiconductor module 10A. Configurations identical or similar to those in Figures 1 to 50 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 50 may be omitted.

[0253] As explained in "7-1. Overview of Semiconductor Module 10A", the semiconductor module 10A includes a memory cube 100A, a redistribution layer 800, and a logic chip 700.

[0254] The memory cube 100A includes a plurality of TCI-IO 112s, a plurality of memory modules 111s, and a portion of a plurality of inductors 172. The plurality of TCI-IO 112s are electrically connected to the memory modules 111s. For example, the memory cube 100A includes functions for storing received data and transmitting stored data.

[0255] The TCI-IO112 includes multiple inductors 172, a transmit / receive circuit 114, and a parallel / series conversion circuit 113. The inductors 172 are electrically connected to the transmit / receive circuit 114 using terminals A and B. The transmit / receive circuit 114 is electrically connected to the parallel / series conversion circuit 113. The parallel / series conversion circuit 113 is electrically connected to the memory module 111.

[0256] The redistribution layer 800 includes a portion of a plurality of inductors 172. The inductors 172 have the function of non-contact inductor communication with the inductors 372 of the logic chip 700.

[0257] The memory module 111, the transmitting / receiving circuit 114, the parallel / series conversion circuit 113, and the inductor 172 have the same configuration as the memory module 111, transmitting / receiving circuit 114, parallel / series conversion circuit 113, and inductor 172 described in "Sixth Embodiment," and a detailed description of the memory module 111, transmitting / receiving circuit 114, parallel / series conversion circuit 113, and inductor 172 is omitted here.

[0258] The logic chip 700 includes a plurality of TCI-IO 312s, a TCI-IO control module 311, and a logic module 211. The plurality of TCI-IO 312s are electrically connected to the TCI-IO control module 311, and the TCI-IO control module 311 is electrically connected to the logic module 211.

[0259] The TCI-IO 312 includes multiple inductors 372, a transceiver circuit 314, and a parallel-to-series conversion circuit 313. The inductors 372 are electrically connected to the transceiver circuit 314 using terminals C and D. The transceiver circuit 314 is electrically connected to the parallel-to-series conversion circuit 313. For example, the parallel-to-series conversion circuit 313 is electrically connected to the TCI-IO control module 311.

[0260] The configuration and functions of the logic chip 700, inductor 372, transmitting / receiving circuit 314, and parallel / series conversion circuit 313 are the same as those of the logic chip 200, inductor 172, transmitting / receiving circuit 114, and parallel / series conversion circuit 113 described in "Sixth Embodiment," and therefore a detailed explanation of the logic chip 700, inductor 372, transmitting / receiving circuit 314, and parallel / series conversion circuit 313 is omitted here.

[0261] [7-3. Functional Block Configuration of Memory Cube 100A and Redistribution Layer 800] Next, the functional block configuration of the memory cube 100A and the redistribution layer 800 will be described with reference to Figure 52. Figure 52 is a block diagram showing the functional block configuration of the memory cube 100A and the redistribution layer 800. Configurations identical or similar to those in Figures 1 to 51 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 51 may be omitted.

[0262] The memory cube 100A includes a plurality of memory modules 111. Each of the plurality of memory modules 111 includes a memory cell array 115. The plurality of memory modules 111 are electrically connected to a plurality of power lines 164, a plurality of ground lines 165, and a plurality of signal transmission lines 166.

[0263] For example, the rewiring layer 800 includes a side power supply wiring 862, a side grounding wiring 863, and a side signal transmission wiring 867. The side power supply wiring 862 is electrically connected to the power supply wiring 164, the side grounding wiring 863 is electrically connected to the grounding wiring 165, and the side signal transmission wiring 867 is electrically connected to the signal transmission wiring 166. The side power supply wiring 862, the side grounding wiring 863, and the side signal transmission wiring 867 may also be electrically connected to the logic chip 700, and the side signal transmission wiring 867 may be electrically connected to the inductor 172.

[0264] For example, multiple signal transmission lines 166 are connected to side signal transmission lines 867 included in the redistribution layer 800 and electrically connected to the TCI-IO 112. For example, the side signal transmission lines 867 are electrically connected to an inductor 172. The TCI-IO 112 is connected to the logic chip 700 and external circuits (not shown) by inductor communication, and signals including control signals such as address signals and enable signals for controlling the IC chip 110, as well as data, are supplied to the TCI-IO 112 from the logic chip 700 and external circuits.

[0265] The memory cell array 115 includes a configuration similar to that of the memory cell array 115 described in the "Sixth Embodiment".

[0266] [7-4. Mounting Example of Semiconductor Module 10A] Mounting examples of semiconductor module 10A will be described with reference to Figure 53. Figure 53 is an end view showing the end cross-sectional structure of the mounting example of semiconductor module 10A. Configurations that are the same as or similar to those in Figures 1 to 52 will not be explained here.

[0267] For example, the side signal transmission wiring 867 included in the redistribution layer 800 may be electrically connected to the inductor 172, or may include the inductor 172. For example, the side power wiring 862 and the side ground wiring 863 included in the redistribution layer 800 are each electrically connected to the bump 420.

[0268] The adhesive layer 400 is placed between the second surface 804 of the redistribution layer 800 and the first surface 702 of the logic chip 700, and adheres the memory cube 100A and the redistribution layer 800 to the logic chip 700. The adhesive layer 400 includes a configuration similar to that described in "6-1. Overview of Semiconductor Module 10".

[0269] For example, as described in "7-1. Overview of Semiconductor Module 10A," the logic chip 700 includes multiple inductors 372 along with multiple wirings (not shown) included in the wiring layer 750. The logic chip 700 also includes multiple through-electrodes 792 and multiple electrode pads 791. The multiple wirings and multiple inductors 372 are provided, for example, in the same process. Each of the multiple wirings and multiple inductors 372 is electrically connected to an electrode pad 791 using the through-electrode 792. Each of the multiple electrode pads 791 is electrically connected to a corresponding bump 793.

[0270] The substrate 773 (second face 704) of the logic chip 700 is placed on the cavity substrate 630, and the logic chip 700 is face-up mounted on the cavity substrate 630. For example, a mounting structure in which the wiring layer 750 (first face 702) of the logic chip 700 is placed on the cavity substrate 630, and the stacking direction of the logic chip 700 (the direction in which the wiring layer 750 is stacked from the substrate 773) is downward in the third direction D3, is referred to as face-down mounting.

[0271] The cavity substrate 630 includes a cavity portion 632, which may be referred to as a recess. The cavity substrate 630 can absorb the height of the portion containing the adhesive layer 400 and the logic chip 700, which are arranged convexly on the memory cube 100, with the cavity portion 632. Furthermore, the cavity substrate 630 includes the same configuration as the substrate 600. That is, the cavity substrate 630 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked.

[0272] The bump layer 500 includes a plurality of bumps 502 and is electrically connected to a plurality of wirings 613 included in the cavity substrate 630, and also includes the function of connecting the cavity substrate 630 to an external substrate and an external circuit.

[0273] The structure 25 (memory cube 100A, redistribution layer 800, adhesive layer 400, and logic chip 700) is electrically connected to the cavity substrate 630 using a plurality of bumps 420 and a plurality of bumps 793. The structure 25 and the cavity substrate 630 are fixed to each other using UF material 422. Specifically, the structure 25 is electrically connected to the wiring 607 exposed in the cavity portion 632 using a plurality of bumps 420, and is also electrically connected to the wiring 607 exposed on the first surface 602 using a plurality of bumps 793. In addition, a portion of the redistribution layer 800, the adhesive layer 400, the logic chip 700, the plurality of bumps 793, the plurality of bumps 420, the cavity portion 632, and a portion of the first surface 602 of the cavity substrate 630 are fixed using underfill (UF) material 422.

[0274] Furthermore, for example, the power supply voltage VDD, voltage VSS, and various signals are supplied to the logic chip 700 from an external circuit (not shown) via the cavity substrate 630, bumps 793, and electrode pads 791. Also, the power supply voltage VDD, voltage VSS, and various signals are supplied to the memory cube 100 from an external circuit (not shown) via the cavity substrate 630, bumps 420, and redistribution layer 800. Multiple power supply lines 164 and multiple ground lines 165 are electrically connected to an external circuit, for example, using the cavity substrate 630, bumps 420, and redistribution layer 800, and the power supply voltage VDD and voltage VSS are supplied from the external circuit. Furthermore, multiple signal transmission lines 166 are electrically connected to an external circuit (not shown), for example, using the cavity substrate 630, bumps 420, and redistribution layer 800, and some signals for controlling the IC chip 110 may be supplied from the external circuit.

[0275] Furthermore, for example, the semiconductor module 10A includes conductive film 445-1, conductive film 445-2, conductive film 446, conductive film 447, and a power supply unit 900. The semiconductor module 10AF uses the power supply unit 900 to supply power to, for example, the memory cube 100A.

[0276] As an example, conductive film 445-2 is formed on the side grounding wiring 163 of the fifth surface 142A (see, for example, Figure 16), and conductive film 445-1 is formed on the side grounding wiring 163 of the sixth surface 144A (see, for example, Figure 16). Conductive film 446 is formed on conductive film 445-1, and conductive film 447 is formed on conductive film 445-2. Conductive films 445-1 and 445-2, and conductive films 446 and 447 are formed, as an example, using electroplating (plating method). Conductive films 445-1 and 445-2 include a conductor made of metal, for example, a conductor containing copper, silver, nickel, etc. Conductive films 446 and 447 include a conductor made of metal, for example, a conductor containing gold, tin, nickel, etc.

[0277] As an example, the conductive film 445 is formed on the fifth surface 142A and the sixth surface 144A using electroplating (plating method). The conductive film 445 contains a conductor made of metal, for example, a conductor containing copper, silver, nickel, etc.

[0278] The power supply unit 900 includes a support unit 901 which contains a plurality of pogo pins 902. The support unit 901 has the function of supporting the plurality of pogo pins 902. For example, each of the plurality of pogo pins 902 is a connector consisting of a terminal portion, a cylindrical member connected to the terminal portion, and an elastic member inserted through the cylindrical member. The power supply unit 900 may also be referred to as a pogo pin crimping mechanism.

[0279] The power supply unit 900 presses each of the multiple pogo pins 902 against the conductive film 446 and the conductive film 447, and connects each of the multiple pogo pins 902 to the conductive film 446 and the conductive film 447. For example, each of the multiple pogo pins 902 is pressed against a metal film or the like and comes into contact with the metal film. At this time, each of the multiple pogo pins 902 comes into contact with the metal film due to the expansion and contraction of the elastic member.

[0280] As a result, the power supply unit 900 can supply voltage (for example, power supply voltage VDD and voltage VSS) to a plurality of pogo pins 902 from an external source, and supply voltage to the memory cube 100A via the plurality of pogo pins 902. Therefore, by including the power supply unit 900 in the semiconductor module 10A, the semiconductor module 10A can enhance the supplied voltage. As a result, large fluctuations in the internal voltage of the semiconductor module 10A are suppressed, and the internal voltage of the semiconductor module 10A becomes stable, enabling good communication.

[0281] The semiconductor module 10A is implemented as described above. The manufacturing method for the memory cube 100A and the redistribution layer 800 included in the semiconductor module 10A allows for the formation of wiring on the side surface using a simpler process than the manufacturing method that uses a complex process to form each wiring while maintaining alignment. Furthermore, since the semiconductor module 10A includes wiring (side wiring) formed on the side surface of the memory cube 100A, the memory cube 100A, the fan-in type redistribution layer 800, and the cavity substrate 630 can be electrically connected. The semiconductor module 10A includes a configuration in which the memory cube 100A is vertically mounted on the logic chip 700, and from a configuration in which multiple IC chips 110 and logic chips 700 are stacked in parallel, the distance between each IC chip 110 and logic chip 700 can be kept close and constant. By using the semiconductor module 10A, it is possible to realize a memory with low power consumption and large capacity.

[0282] Furthermore, the semiconductor module 10A includes the functions and configuration described above, and the memory cube 100A and the logic chip 700 can communicate contactlessly using inductor communication. The semiconductor module 10A includes a configuration that uses contactless inductor communication, and since the load associated with the wiring resistance and parasitic capacitance between the IC chip 110 and the logic chip 700 is suppressed, the power consumption of the semiconductor module 10A can be further reduced.

[0283] Furthermore, the semiconductor module 10A includes wiring (side wiring) formed on the memory cube 100A and the redistribution layer 800, electrode pads 791, bumps 420 and 793, and UF material 422, enabling electrical connection and fixation of the structure 25 and the cavity substrate 630 to each other. In other words, the design flexibility of the memory cube 100 is improved based on the wiring (side wiring) formed on the memory cube 100A and the redistribution layer 800 using the semiconductor module 10A, and mounting on the cavity substrate 630 becomes possible.

[0284] Although the semiconductor module 10A is shown as an example in which the logic chip 700 is mounted face-up on the cavity substrate 630, the mounting method of the logic chip 700 is not limited to face-up mounting. For example, even if the redistribution layer 800 (inductor 172) and the inductor 372 are separated, inductor communication between inductor 172 and inductor 372 is possible as long as the distance between inductor 172 and inductor 372 along the third direction D3 is constant. In other words, the constant distance is any distance at which inductor communication between inductor 172 and inductor 372 is possible. In this case, the logic chip 700 may be mounted face-down.

[0285] [7-5. Implementation Examples of Semiconductor Module 10B] Implementation examples of semiconductor module 10B will be described with reference to Figure 54. Figure 54 is an end view showing the end cross-sectional structure of the implementation example of semiconductor module 10B. Configurations that are the same as or similar to those in Figures 1 to 53 will not be explained here.

[0286] As shown in Figure 54, the semiconductor module 10B includes a configuration in which the power supply unit 900 in the semiconductor module 10A shown in Figure 53 is replaced by an L-shaped member 910. As an example, the semiconductor module 10B includes conductive films 445-1, 445-2, 447, and 446, similar to the semiconductor module 10A. The L-shaped member 910 includes a conductor made of metal, for example, a conductor containing copper. The semiconductor module 10B may include a memory cube 100 or 100B instead of a memory cube 100A. In this case, the memory cube 100 or 100B may be appropriately adjusted to be applicable to the configuration of the semiconductor module 10B.

[0287] The L-shaped member 910 is connected to the conductive film 446 and the conductive film 447. As a result, the semiconductor module 10AG includes a configuration in which voltage (for example, power supply voltage VDD and voltage VSS) is supplied from the outside to the multiple L-shaped members 910, and the memory cube 100A is supplied with voltage via the multiple L-shaped members 910.

[0288] [7-6. Mounting Examples of Semiconductor Module 10C] Mounting examples of semiconductor module 10C will be described with reference to Figure 55. Figure 55 is an end view showing the end cross-sectional structure of the mounting example of semiconductor module 10C. Configurations that are the same as or similar to those in Figures 1 to 53 will not be explained here.

[0289] As shown in Figure 55, the semiconductor module 10C includes a configuration in which the power supply unit 900 in the semiconductor module 10A shown in Figure 53 is replaced with a flexible substrate 920. The semiconductor module 10C includes conductive films 445-1, 445-2, 447, and 446, similar to the semiconductor module 10A. The semiconductor module 10C may include memory cube 100 or 100B instead of memory cube 100A. In this case, memory cube 100 or 100B may be appropriately adjusted to be applicable to the configuration of the semiconductor module 10C.

[0290] The flexible substrate 920 is connected to the conductive films 446 and 447. As a result, the semiconductor module 10C includes a configuration in which voltage (e.g., power supply voltage VDD and voltage VSS) is supplied to the flexible substrate 720 from an external source, and the memory cube 100A is supplied with voltage via the flexible substrate 720.

[0291] [Eighth Embodiment] As one example of the application of the memory cubes 100, 100A, and 100B, semiconductor modules 10D and 10E according to the eighth embodiment will be described with reference to Figures 56 to 59. Configurations identical or similar to those in Figures 1 to 55 will be described as necessary, and descriptions of identical or similar configurations may be omitted.

[0292] [8-1. Overview of Semiconductor Module 10D] First, an overview of the semiconductor module 10D will be described with reference to Figures 56 and 57. Figure 56 is a perspective view showing the configuration of the semiconductor module 10D. Figure 57 is an end view showing the cross-sectional structure of the end of the semiconductor module 10D along O1-O2 shown in Figure 56.

[0293] As shown in Figures 56 and 57, the semiconductor module 10D includes a memory cube 100C, a frame 1000, and a first substrate 300. The semiconductor module 10D may also include an insulating film 85 and an insulating film 1002, and may also include a thermal conductive sheet 1100 (see Figure 59) and a metal film 1200 (see Figure 59).

[0294] A frame 1000 is provided on the first surface 302 of the first substrate 300, and a memory cube 100C is provided on the first substrate 300 so that it can be attached to and detached from the frame 1000. Alternatively, for example, a semiconductor module 10D may be mounted on a mother board (not shown) by a plurality of bumps (not shown). As a result, for example, if a memory cube 100C malfunctions, the memory cube 100C can be removed from the semiconductor module 10D and a non-malfunctioning memory cube 100C can be installed. In other words, the semiconductor module 10D has a configuration that allows for the replacement of the memory cube 100C.

[0295] Furthermore, the memory cube 100C includes an IC chip 110 which includes a memory cell array 115 (see Figure 49) contained in the memory module 111 (see Figure 58), and functions as a storage device. In addition, the memory cube 100C includes an inductor 172, the first substrate 300 includes an inductor 372, and the inductor 172 can communicate with the inductor 372 via contactless inductor communication. That is, the memory cube 100C can send and receive signals (e.g., data) to and store (remember) signals using contactless inductor communication with the first substrate 300, rather than sending and receiving signals via a signal path that is routed over a long distance using wiring, through electrodes, and bumps.

[0296] As a result, the semiconductor module 10D includes a configuration in which the memory cube 100C can be attached and detached, enabling long-term use. Furthermore, the manufacturing process of the semiconductor module 10D can suppress processes that involve routing wires, through electrodes, and bumps over long distances. Therefore, the semiconductor module 10D can reduce manufacturing costs while maintaining reliability without compromising long-term reliability.

[0297] [8-2. Configuration of Memory Cube 100C] As shown in Figures 56 and 57, the memory cube 100C has the same configuration as the memory cube 100 described in the "First Embodiment," and also includes structures 90 and 90A that are in contact with the stacked memory chip 30. The configuration similar to that of the memory cube 100 will be described as necessary, and the description of the configuration similar to that of the memory cube 100 will be omitted.

[0298] For example, a portion of the first surface 146C is the first surface 46, and the portion of the first surface 146C that is not in contact with the structure 90A is the first surface 46.

[0299] The structure 90 is provided in contact with a part of the third surface 45 other than the third surface 45 to which the side power wiring 162 is in contact, in contact with a part of the fourth surface 47 other than the fourth surface 47 to which the side power wiring 162 is in contact, and in contact with a part of the fifth surface 42 and the sixth surface 44. Furthermore, the structure 90 is provided in contact with the second surface 48 other than the second surface 48 to which the side grounding wiring 163 is in contact. For example, the structure 90 is provided so as to cover the corners where the second surface 48, the third surface 45 and the fifth surface 42 are in contact, a part of the fifth surface 42, and the corners where the second surface 48, the fifth surface 42 and the fourth surface 47 are in contact. Although not shown in the diagram, the structure 90 is provided to cover the corner where the fourth surface 47 and the sixth surface 44 meet, a part of the sixth surface 44, and the corner where the second surface 48, the sixth surface 44, and the third surface 45 meet.

[0300] For example, as shown in Figure 56 or Figure 57, the structure 90A includes a second inclined portion 86 and is provided in contact with the third surface 45 other than the third surface 45 to which the side power wiring 162 covered by the structure 90 is in contact, in contact with the fourth surface 47 other than the fourth surface 47 to which the side power wiring 162 covered by the structure 90 is in contact, and in contact with the fifth surface 42 and the sixth surface 44 other than a part of the fifth surface 42 and the sixth surface 44 covered by the structure 90.

[0301] For example, in the end view shown in Figure 56, structures 90 and 90A are separated, but on the third surface 145C side with respect to the second direction D2, structures 90 and 90A are in contact (not shown). Also, although not shown, structure 90 is in contact with the third surface 145C and the fourth surface 147C, and is uniformly provided on the third surface 145C and the fourth surface 147C.

[0302] Structures 90 and 90A cover and contact the surface of the stacked memory chip 30 that does not have side wiring (e.g., side ground wiring 163 and side power wiring 162). For example, structures 90 and 90A include a sealing material. For example, the side power wiring 162 shown in Figure 57 is divided into three sections along the third direction D3. Structures 90 are provided between the side power wiring 162, and the three divided side power wiring 162 are spaced apart from each other. For example, the sealing material includes a resin material such as epoxy, a curing agent, a filler, and additives. Structures 90 and 90A have the function of suppressing moisture absorption and intrusion of impurities into the stacked memory chip 30, as well as protecting it from physical impact. Structure 90A is fitted into the frame 1000 and functions as a member for fixing the memory cube 100C to the frame 1000 and the first substrate 300. Structure 90A may also contain metal.

[0303] The memory cube 100C is fitted into the frame 1000 and placed on the first surface 302 of the first substrate 300. The memory cube 100C is fitted into the frame 1000 such that the second inclined portion 86 is parallel to the first inclined portion 87 of the frame 1000. The angle between the first surface 302 and the second inclined portion 86 is angle β.

[0304] For example, the angle β is designed such that the length (width) of the first surface 146C along the first direction D1 is ±2 μm. Both ends of the length of the first surface 146C correspond to the ends of the second inclined portion 86, and the angle β on one end of the second inclined portion 86 is designed to be ±1 μm of the length of the first surface 146C. In other words, for example, the positional accuracy of the memory cube 100C may be expressed as ±2 μm with respect to the length (width) of the frame 1000 along the first direction D1, or the positional accuracy of the memory cube 100C may be expressed as ±1 μm with respect to one end of the length (width) of the frame 1000.

[0305] [8-3. Structure of Frame 1000] As shown in Figures 56 and 57, the frame 1000 includes a first inclined portion 87 and is in contact with and provided on the first surface 302 of the first substrate 300.

[0306] For example, in the end view shown in Figure 57, the frame 1000 is trapezoidal in shape, and the length of the side touching the first surface 302 is longer than the side opposite to the first surface 302 in the third direction D3. Also, the angle β between the first surface 302 and the first inclined portion 87 is the same as the angle β between the first surface 302 and the second inclined portion 86. Furthermore, the first inclined portion 87 and the second inclined portion 86 may have shapes that interlock with each other. For example, the first inclined portion 87 may include a structure that is recessed from bottom to top along the third direction D3, and the second inclined portion 86 may include a structure that is recessed from top to bottom along the third direction D3, and the first inclined portion 87 may be configured to interlock with the second inclined portion 86.

[0307] The frame 1000 has the function of fitting the memory cube 100C and fixing the memory cube 100C onto the first substrate 300. In other words, the frame 1000 is configured to allow the memory cube 100C to be attached and to allow the memory cube 100C to be removed.

[0308] [8-4. Configuration of the First Substrate 300] As shown in Figure 57, the first substrate 300 includes at least a plurality of inductors 372, a control circuit capable of controlling the plurality of inductors 372 (see, for example, the TCI-IO control module 311 shown in Figure 58), and a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the first substrate 300 includes a first surface 302, a second surface 304, and a plurality of wiring layers 326, 328, 330, 332, and 334. The wiring layers 326, 328, 330, 332, and 334 are arranged parallel to the first direction D1 and the second direction D2, and are stacked in this order from the side closest to the first surface 302 along the third direction D3. The plurality of wiring layers 326 include wiring 327 and inductors 372. Multiple wiring layers 328, 330, 332, and 334 include multiple wires 329, multiple wires 331, multiple wires 333, and multiple wires 335. Wire 327 and inductor 372 are electrically connected to wire 329, wire 329 is electrically connected to wire 331, wire 331 is electrically connected to wire 333, and wire 333 is electrically connected to wire 335. The illustration of the insulating layer, which is alternately laminated with the wiring, is omitted in Figure 57.

[0309] Furthermore, the number of layers in the multilayer wiring structure of the first substrate 300 is not limited to five. The number of layers in the multilayer wiring structure of the first substrate 300 can be changed as appropriate based on the application or specifications of the semiconductor module 10D.

[0310] Furthermore, for example, the wiring 335 may be exposed on the second surface 304 and function as an electrode. The wiring 335 of the semiconductor module 10D may be electrically connected to a motherboard (not shown) by bumps (not shown) or the like. For example, the motherboard may be a board on which the semiconductor module 10D, a CPU (Central Processing Unit) that includes multiple arithmetic circuits and is capable of arithmetic processing, and a GPU (Graphics Processing Unit) that includes multiple arithmetic circuits and is capable of image processing or video processing are mounted. The semiconductor module 10 may include a CPU that includes multiple arithmetic circuits and is capable of arithmetic processing, or a GPU that includes multiple arithmetic circuits and is capable of image processing or video processing.

[0311] The first substrate 300 has the function of fixing and supporting the frame 1000 and the memory cube 100C, and the function of communicating with the memory cube 100C via an inductor. The first substrate 300 may also have the function of connecting the memory cube 100C to an external device or the like.

[0312] [8-5. Other Configurations] As described in "8-1. Overview of Semiconductor Module 10D", the semiconductor module 10D may include an insulating film 85 and an insulating film 1002.

[0313] For example, the insulating film 85 is provided so as to be in contact with the first surface 146C. For example, the first surface 146C is an important surface for the memory cube 100C to communicate with the first substrate 300 via an inductor, and the insulating film 85 has the function of coating the first surface 146C and protecting the first surface 146C. The insulating film 85 also has the function of preventing the memory cube 100C from coming into contact with the first substrate 300 and insulating the memory cube 100C from the first substrate 300. The insulating film 85 may also be provided so as to be in contact with the second inclined portion 86.

[0314] For example, the insulating film 1002 is in contact with the first inclined portion 87, the first surface 302, the second inclined portion 86, and the insulating film 85, and is provided between the first inclined portion 87 and the first surface 302 and the second inclined portion 86 and the insulating film 85. The insulating film 1002 has the function of preventing the memory cube 100C from coming into contact with the first substrate 300 and insulating the memory cube 100C from the first substrate 300.

[0315] For example, the insulating film 85 and the insulating film 1002 may be resins, and the resins may be fluororesins such as Teflon (registered trademark).

[0316] The semiconductor module 10D includes, for example, both the insulating film 85 and the insulating film 1002. The memory cube 100C and the first substrate 300 only need to be configured to be insulated from each other and detachable from each other, and the semiconductor module 10D may include either the insulating film 85 or the insulating film 1002.

[0317] Furthermore, as explained in "8-1. Overview of Semiconductor Module 10D," the semiconductor module 10D may also include a thermal conductive sheet 1100 (see Figure 59) and a metal film 1200 (see Figure 59). The thermal conductive sheet 1100 or the metal film 1200 may function as a heat spreader, or may function as a heat spreader. For example, the thermal conductive sheet 1100 and the metal film 1200 have the function of releasing the heat generated by the semiconductor module 10D to the outside of the semiconductor module 10D.

[0318] [8-6. Functional Block Configuration of Semiconductor Module 10D] Next, the functional block configuration of semiconductor module 10D will be described with reference to Figures 56 to 58. Figure 58 is a block diagram showing the functional block configuration of semiconductor module 10D. Configurations identical or similar to those in Figures 1 to 57 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 57 may be omitted.

[0319] As described in "8-1. Overview of Semiconductor Module 10D", the semiconductor module 10D includes a memory cube 100C and a first substrate 300.

[0320] As shown in Figure 58, the memory cube 100C includes a TCI-IO 112 and a plurality of memory modules 111. The plurality of TCI-IO 112s are electrically connected to the memory modules 111.

[0321] The TCI-IO112 includes an inductor 172 (for example, a second inductor), a transceiver circuit 114, and a parallel-to-series conversion circuit 113. The inductor 172 is electrically connected to the transceiver circuit 114 using terminals A and B. The transceiver circuit 114 is electrically connected to the parallel-to-series conversion circuit 113. The parallel-to-series conversion circuit 113 is electrically connected to the memory module 111.

[0322] The inductor 172 has the function of communicating with the inductor 372 (for example, the first inductor) of the first substrate 300 via contactless inductor communication.

[0323] The memory module 111, the transmitting / receiving circuit 114, the parallel / series conversion circuit 113, and the inductor 172 have the same configuration as the memory module 111, transmitting / receiving circuit 114, parallel / series conversion circuit 113, and inductor 172 described in "Sixth Embodiment," and a detailed description of the memory module 111, transmitting / receiving circuit 114, parallel / series conversion circuit 113, and inductor 172 is omitted here.

[0324] The first substrate 300 includes a plurality of TCI-IO 312s and a plurality of TCI-IO control modules 311. The plurality of TCI-IO 312s are electrically connected to the plurality of TCI-IO control modules 311.

[0325] The TCI-IO 312 includes an inductor 372, a transmit / receive circuit 314, and a parallel-to-series conversion circuit 313. The inductor 372 is electrically connected to the transmit / receive circuit 314 using terminals C and D. The transmit / receive circuit 314 is electrically connected to the parallel-to-series conversion circuit 313. For example, the parallel-to-series conversion circuit 313 is electrically connected to the TCI-IO control module 311.

[0326] The configuration and functions of inductor 372, transmitting / receiving circuit 314, and parallel / series conversion circuit 313 are the same as those of inductor 172, transmitting / receiving circuit 114, and parallel / series conversion circuit 113. A detailed explanation of the configuration and functions of inductor 372, transmitting / receiving circuit 314, and parallel / series conversion circuit 313 is omitted here.

[0327] [8-7. Configuration of Semiconductor Module 10E] The configuration of the semiconductor module 10E will be described with reference to Figure 59. Figure 59 is an enlarged end view of a part of the end cross-sectional structure of the semiconductor module 10E. Configurations identical or similar to those in Figures 1 to 58 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 58 may be omitted.

[0328] The semiconductor module 10E differs from the semiconductor module 10D in at least the configuration (18) shown below. Configuration (18) The semiconductor module 10E includes a plurality of memory cubes 100C (e.g., memory cubes 100CA and 100CB), a plurality of frames (e.g., frames 1000A and 1000B) from which the plurality of cube chips can be attached and detached, a plurality of inductors 372 corresponding to each of the plurality of cube chips, a power supply unit 900, a thermal conductive sheet 1100 and a metal film 1200.

[0329] The configuration of semiconductor module 10E, other than configuration (18), is the same as that of semiconductor module 10D. Therefore, when describing semiconductor module 10E, configurations that are the same as or similar to those of semiconductor module 10D will be described as necessary, and descriptions of configurations that are the same as or similar to those of semiconductor module 10D may be omitted.

[0330] For example, the configurations of memory cubes 100CA and 100CB are the same as those of memory cube 100C, the configurations of frame bodies 1000A and 1000B are the same as those of frame body 1000, and the configurations of the multiple inductors 372 corresponding to each of the multiple cube chips are the same as those of the inductors 372 of semiconductor module 10. In addition, the configuration of the second substrate 300A other than the configuration shown in configuration (18) of semiconductor module 10E is the same as that of the first substrate 300. In Figure 59, reference numerals for identical components are omitted, and configurations similar to those of semiconductor module 10D are described as necessary. Also, insulating films 85 and 1002 are omitted.

[0331] Memory cube 100CA is fitted to the frame 1000A in a manner that allows for attachment and removal, and is provided on the second substrate 300A (first surface 302A). Memory cube 100CB is fitted to the frame 1000B in a manner that allows for attachment and removal, and is provided on the second substrate 300A (first surface 302A).

[0332] The power supply unit 900 has the same configuration and function as described in "7-4. Implementation Example of Semiconductor Module 10A," and a detailed explanation is omitted here.

[0333] The power supply unit 900 is provided between the fourth face 147C of the memory cube 100CA and the third face 145C of the memory cube 100CB, and on the third face 145C of the memory cube 100CA and the fourth face 147C of the memory cube 100CB. The power supply unit 900 connects the side power wiring 162 of the memory cubes 100CA and 100CB electrically by crimping each of the multiple pogo pins 902 to them. As a result, the power supply unit 900 can supply the power voltage VDD to the memory cubes 100CA and 100CB from an external device (external circuit) outside the semiconductor module 10E via the multiple pogo pins 902.

[0334] The metal film 1200 is provided so as to be in contact with the second surfaces 148C of the memory cubes 100CA and 100CB. As a result, the metal film 1200 is electrically connected to the side grounding wiring 163 of the memory cubes 100CA and 100CB. The thermal conductive sheet 1100 is electrically connected to the metal film 1200 which is electrically connected to the memory cubes 100CA and 100CB. As a result, the thermal conductive sheet 1100 can supply a grounding voltage to the memory cubes 100CA and 100CB from an external device outside the semiconductor module 10E via the metal film 1200.

[0335] The thermal conductive sheet 1100 and the metal film 1200 have the function of supplying voltage to the memory cubes 100CA and 100CB, and the function of releasing the heat generated by the semiconductor module 10E to the outside of the semiconductor module 10E. A heat sink may be placed on the thermal conductive sheet 1100 and the metal film 1200.

[0336] For example, if the second circuit board 300A, memory cube 100CA, or 100CB generate heat due to their operation, the circuit boards or chips may warp, potentially causing the circuits to malfunction.

[0337] On the other hand, the memory cubes 100CA and 100CB are attached to the frames 1000A and 1000B. Even if the second substrate 300A warps due to heat from crimping or heat generated by each substrate or chip, the memory cubes 100CA and 100CB will only shift slightly from their initial mounting positions on the second substrate 300A in accordance with the warping of the second substrate 300A. Therefore, the memory cubes 100CA and 100CB will not be detached from the frame 1000A or frame 1000B due to heat from crimping or heat generated by each substrate or chip.

[0338] Furthermore, each of the multiple pogo pins 902 maintains an electrically connected state to the memory cube 100CA or 100CB due to the expansion and contraction of the elastic member. In other words, power supply to the memory cubes 100CA and 100CB is maintained.

[0339] Furthermore, the positional misalignment between the multiple inductors 172 and the multiple inductors 372 is minimal, and inductor communication between the multiple inductors 172 and the multiple inductors 372 is also possible.

[0340] Therefore, the semiconductor module 10E can release heat or heat generation to the outside of the semiconductor module 10E, thereby suppressing malfunctions caused by heat or heat generation, and suppressing the effects of deformation of the semiconductor module 10E's structure. As a result, the semiconductor module 10E has excellent long-term reliability.

[0341] [Ninth Embodiment] As one method of manufacturing the memory cubes 100, 100A, and 100B, a method of manufacturing the memory cube according to the ninth embodiment will be described with reference to Figures 60 and 61. Configurations identical or similar to those in Figures 1 to 59 will be described as necessary, and descriptions of identical or similar configurations may be omitted. Figures 60 and 61 are flowcharts illustrating the method of manufacturing the memory cube. For example, the method of manufacturing the memory cube according to the ninth embodiment is similar to a part of the method of manufacturing the memory cube 100 according to the first embodiment, and will be described with reference to a part of the method of manufacturing the memory cube 100 according to the first embodiment. Also, for example, the method of manufacturing the memory cube according to the ninth embodiment is similar to a part of the manufacturing method according to the first to fifth embodiments, and will be described with reference to a part of the manufacturing method according to the first to fifth embodiments.

[0342] [9-1. Method for Manufacturing a Memory Cube According to the Ninth Embodiment] As shown in Figure 60, the method for manufacturing a memory cube according to the ninth embodiment includes steps 902 (S902), 906 (S906), 908 (S908), 910 (S910), 912 (S912), 914 (S914), 916 (S916), 918 (S918), 920 (S920), 922 (S922), and 924 (S924). Furthermore, the number of IC chips stacked according to the ninth embodiment can be appropriately selected based on the specifications and application of the memory cube, etc., without departing from the method for manufacturing a memory cube according to the ninth embodiment, similar to the first to eighth embodiments.

[0343] When the manufacturing method of the memory cube according to the ninth embodiment is started, for example, a first substrate 50a (see Figure 6) is prepared in the same manner as in the manufacturing method of the memory cube according to the first embodiment.

[0344] For example, S902, S906, and S908 are the same as S102, S106, and S108, respectively, and refer to STEP 108 in Figures 6, 7, 8, and 9. For example, configurations (19) to (21) shown below are different from STEP 108 in Figures 6, 7, 8, and 9.

[0345] Configuration (19) For example, S902 is a step similar to S102, and includes using plasma grooving to expose the ends of the wiring 183 shown in STEP 108 of Figures 7 to 9 (e.g., side electrodes), and suppressing the exposure of the substrate 173 by leaving a small portion of the insulating layer 184 shown in STEP 108 of Figures 7 to 9. Configuration (20) For example, S906 is a step similar to S106, and the organic film in S906 corresponds to the adhesive film 140 shown in Figure 8. Configuration (21) For example, S908 is a step similar to S108. As explained in Configuration (19), a small portion of the insulating layer 184 is left, and the exposure of the substrate 173 is suppressed. That is, the groove 57 in step STEP 108 of Figure 9 does not reach the substrate 173, but is formed up to partway up the insulating layer 184.

[0346] S910 is the step of bonding the substrate formed up to S908 to the support substrate. For example, an adhesive film is applied to the exposed surface and a part of the groove 57 of the substrate formed up to S908, and then it is bonded to the support substrate. The support substrate can be any substrate that can withstand the grinding and polishing in the following S912. For example, it may be a Si substrate, Si-wafer, or a glass substrate.

[0347] Step S912 is a step in which the first surface 101b side of the substrate 173 on the support substrate formed in S910 and to which the base material is bonded is ground and polished to thin the substrate 173 of the base material. At this time, for example, step S912 in the manufacturing method of the memory cube according to the ninth embodiment can be explained by referring to STEP 110 in Figure 9. STEP 110 in Figure 9 shows that the groove 57 reaches the substrate 173, indicating that the base material is pieced into individual IC chips 110. However, step S912 in the manufacturing method of the memory cube according to the ninth embodiment includes processing the base material to which the groove 57 has been formed up to the middle of the insulating layer 184 in S908, and therefore includes thinning the substrate 173, so in S912 the base material is not pieced into individual IC chips 110.

[0348] Step S914 is a step in which grooves are formed on the back side (the side of the thinned substrate 173) of the substrate formed up to S912, using plasma grooving similar to that in S902, to demarcate each of the multiple IC chips 110. At this time, the grooves formed on the back side of the substrate penetrate the substrate 173 and face the grooves 57 via the insulating layer 184. That is, a small amount of the insulating layer 184 remains between the grooves formed on the back side of the substrate and the grooves 57.

[0349] Step S916 is the step of forming an inorganic insulating film on the substrate formed up to S914. Specifically, the inorganic insulating film is formed so as to be in contact with the grooves formed on the back side of the substrate and the back side of the substrate formed up to S912 (the thinned substrate 173) where the grooves are not formed. The inorganic insulating film is also formed on the edges and sides of the substrate formed up to S912. For example, the inorganic insulating film is formed using a CVD apparatus. For example, the inorganic insulating film is made of SiN, SiON, SiCN, SiO ２ It may include one layer of any of the following inorganic insulating films: SiN, SiON, SiCN, SiO ２ The film may be a laminated film of multiple layers of inorganic insulating films such as the above. For example, the grooves formed on the back side of the substrate, and the back side of the substrate formed up to S912 where the grooves are not formed (the thinned substrate 173), are covered with the inorganic insulating film. This prevents contamination of the substrate by the diffusion of exposed metal, and ensures the long-term reliability of the individualized IC chips 110 and memory cubes 100.

[0350] Step S918 includes attaching the substrate bonded to the support substrate formed up to S916 to the dicing tape, and peeling off the substrate bonded to the dicing tape from the support substrate and cleaning. For example, the cleaning in S918 may include not only cleaning the substrate bonded to the dicing tape, but also etching the thin, remaining insulating layer 184 using a cleaning solution diluted with the solution used in wet etching, or by dry etching.

[0351] S920 is a step of using an expander to separate the material into multiple IC chips 110. Specifically, S920 is a step of using an expander to stretch the dicing tape to widen the grooves and groove 57 formed on the back side of the substrate, thereby separating (cutting) the inorganic insulating film formed in S916 and the slightly remaining insulating layer 184 along the grooves and groove 57 formed on the back side of the substrate, thereby separating the first substrate 50a attached to the dicing tape into multiple IC chips 110. If the thin, slightly remaining insulating layer 184 is etched in S918, S920 includes using an expander to separate (cut) the inorganic insulating film formed in S916 along the grooves and groove 57 formed on the back side of the substrate, thereby separating the first substrate 50a attached to the dicing tape into multiple IC chips 110.

[0352] Step S922 is a step of joining two different IC chips 110 from a plurality of individualized IC chips 110 to form a single joined chip. It is also a step of joining a plurality of joined chips to form a stacked memory chip. For example, S922 may include the steps of forming a joined chip to forming a stacked memory chip in the manufacturing method according to the first to fifth embodiments. The manufacturing method of the memory cube according to the ninth embodiment may include forming a stacked memory chip using the steps of forming a joined chip to forming a stacked memory chip in the manufacturing method according to the first to fifth embodiments, without departing from the manufacturing method of the memory cube according to the ninth embodiment.

[0353] S924 is a step of forming electrodes (e.g., side power wiring 162, side ground wiring 163, etc.) that are electrically connected to a plurality of wirings (e.g., power wiring 164, ground wiring 165, signal transmission wiring 166, etc.) exposed on each side of the stacked memory chip formed in S922 in the manufacturing method of the ninth embodiment. For example, S924 may include a step of forming electrodes in the manufacturing methods of the first to fifth embodiments, similar to S922. The manufacturing method of the memory cube according to the ninth embodiment may include forming electrodes (e.g., side power wiring 162, side ground wiring 163, etc.) that are electrically connected to a plurality of wirings (e.g., power wiring 164, ground wiring 165, signal transmission wiring 166, etc.) exposed on each side of the stacked memory chip, using the step of forming electrodes in the manufacturing methods of the first to fifth embodiments, without departing from the manufacturing method of the memory cube according to the ninth embodiment.

[0354] For example, in conventional IC chip stacking methods, when grooving from either the front or back surface of a substrate and stacking IC chips, the adhesive film used to bond the IC chips together may leak onto the sides of the IC chips. Also, in conventional IC chip stacking methods, when the substrate is divided into multiple IC chips, an insulating film may be formed. In either case, as in the present invention, if wiring or electrodes are exposed on the sides of the IC chip, the wiring or electrodes may be contaminated by the adhesive film exposed from the IC chip, and the wiring or electrodes on the sides may be contaminated by the insulating film. As a result, connection failures occur in IC chips and stacked memory chips formed using conventional IC chip stacking methods, and the long-term reliability of the IC chips and stacked IC chips is reduced.

[0355] On the other hand, the memory cube according to the ninth embodiment includes an IC chip 110 and a plurality of wirings exposed on each side of the stacked memory chip (for example, power wiring 164, ground wiring 165, signal transmission wiring 166, etc.), which are used to electrically connect to adjacent memory cubes or IC chips. Furthermore, the manufacturing method of the memory cube according to the ninth embodiment allows the substrate to be divided into multiple IC chips by plasma grooving the front and back surfaces of the substrate separately. In this case, even if the adhesive film overflows onto the sides, the overflowed adhesive film is removed by processing using photolithography, and the insulating film formed on the sides is removed by plasma grooving from the front and back surfaces. As a result, the manufacturing method of the memory cube according to the ninth embodiment can protect the electrodes and wiring exposed on the sides from contamination such as insulating films, thus ensuring long-term reliability for the memory cube according to the ninth embodiment.

[0356] [9-2. Modified Method of Manufacturing a Memory Cube According to the Ninth Embodiment] As shown in Figure 61, a modified method of manufacturing a memory cube according to the ninth embodiment includes steps 902a (S902a), S906, S908, 910a (S910a), S912 to S918, 920a (S920a), S922, and S924. Steps S906, S908, S912 to S918, S922, and S924 in the modified method of manufacturing a memory cube according to the ninth embodiment are the same as steps S906, S908, S912 to S918, S922, and S924 in the method of manufacturing a memory cube according to the ninth embodiment, and their explanation is omitted here.

[0357] For example, S902a is a step similar to S902, and includes using plasma grooving to expose the ends (e.g., side electrodes) of the wiring 183 shown in STEP 108 of Figures 7 to 9, and removing the insulating layer 184 using the substrate 173 shown in STEP 108 of Figures 7 to 9 as an etching stopper. That is, S902a includes using plasma grooving to expose a portion of the substrate 173.

[0358] S910a includes the step of bonding the substrate formed up to S908 to a support substrate, and includes the step of covering the exposed ends of the wiring 183 (e.g., side electrodes) with an adhesive film. The substrate formed up to S908 is bonded to the support substrate using an adhesive film. As with S910, the support substrate can be any substrate that can withstand grinding and polishing in S912.

[0359] S920a is a step in which the substrate is divided into multiple IC chips 110 using an expander. Specifically, since the insulating layer 184 is removed in S902a, S920a is a step in which the inorganic insulating film formed in S916 is divided (cut) along the grooves formed on the back side of the substrate and groove 57 using an expander, and the first substrate 50a attached to the dicing tape is divided into multiple IC chips 110.

[0360] As described above, the modified method for manufacturing the memory cube according to the ninth embodiment includes the same steps as the method for manufacturing the memory cube according to the ninth embodiment and provides the same effects and advantages as the method for manufacturing the memory cube according to the ninth embodiment.

[0361] The various configurations of the memory cube and semiconductor module exemplified as embodiments of the present invention can be combined as appropriate, as long as they do not contradict each other, and technical matters common to each embodiment are included in each embodiment even if not explicitly stated. Furthermore, the scope of the present invention also includes the memory cube and semiconductor module disclosed in this specification and drawings, with additions, deletions, or design changes to components, or additions, omissions, or changes to processes, as these are based on the memory cube and semiconductor module disclosed in this specification and drawings and are modified by those skilled in the art, as long as they retain the essence of the present invention.

[0362] Any effects or benefits other than those brought about by the embodiments disclosed herein are to be understood to be brought about by the present invention if they are clear from the description herein or can be easily predicted by a person skilled in the art.

[0363] (Note) The present invention is not limited to the embodiments described above, and can be modified as appropriate without departing from the spirit of the invention. For example, one embodiment of the present invention may have the following configuration.

[0364] (Note 1) A method for manufacturing a memory cube in which a plurality of substrates on which memory is formed are stacked, comprising: a first surface, a second surface opposite to the first surface, a first insulating film, and a substrate, wherein the first substrate on which memory is formed is plasma-grooved to form a first groove, the second surface of the first substrate on which memory is formed is plasma-grooved to form a second groove, the first substrate is divided into the plurality of substrates, two different substrates from the plurality of substrates are joined to form a single bonded chip, a plurality of the single bonded chips are formed, the plurality of bonded chips are joined to form a stacked chip, and electrodes are formed that are electrically connected to a plurality of wirings exposed on the side surface, wherein each of the plurality of substrates comprises: a third surface, a fourth surface opposite to the third surface, the side surface in contact with the end of the third surface and the end of the fourth surface, and the plurality of wirings exposed on the side surface.

[0365] (Note 2) The method for manufacturing a memory cube according to Note 1, further comprising bonding the first substrate to a support substrate after forming the first groove.

[0366] (Note 3) The method for manufacturing a memory cube according to Note 2, further comprising forming an insulating film on the second surface and on the groove.

[0367] (Appendix 4) The method for manufacturing a memory cube according to Appendix 3, further comprising forming the insulating film, and then attaching an adhesive film to the insulating film on the second surface to form the fourth surface.

[0368] (Note 5) A method for manufacturing a memory cube according to Note 4, comprising bonding the first substrate to the support substrate, and then polishing the substrate on the first surface side to thin it.

[0369] (Note 6) The method for manufacturing a memory cube according to Note 5, further comprising forming a third insulating film so as to be in contact with the second groove and the thinned substrate after forming the second groove.

[0370] (Note 7) A method for manufacturing a memory cube according to Note 6, comprising: attaching the first substrate on which the third insulating film is formed to a dicing tape after the third insulating film is formed; peeling the support substrate from the first substrate on which the third insulating film is formed; and cleaning the first substrate on which the third insulating film is formed, which has been attached to the dicing tape.

[0371] (Note 8) A method for manufacturing a memory cube according to Note 7, comprising stretching the dicing tape to widen the first groove and the second groove, and expanding the first insulating film and the third insulating film along the first groove and the second groove.

[0372] (Note 9) The method for manufacturing a memory cube according to Note 8, wherein forming the first groove by plasma grooving the second surface is to form the first groove in the first insulating film provided on the substrate and the substrate is not exposed.

[0373] (Note 10) The method for manufacturing a memory cube according to Note 7, wherein cleaning the first substrate includes removing the first insulating film.

[0374] (Note 11) A method for manufacturing a memory cube according to Note 10, comprising stretching the dicing tape to widen the first groove and the second groove, and expanding the third insulating film along the first groove and the second groove.

[0375] (Note 12) The method for manufacturing a memory cube according to Note 7, wherein forming the first groove by plasma grooving the second surface is to form the first groove in the first insulating film provided on the substrate and expose a part of the substrate.

[0376] (Note 13) The method for manufacturing a memory cube according to Note 12, wherein bonding the first substrate to the support substrate includes covering the plurality of wirings exposed on the side surface with an adhesive film and bonding the first substrate and the support substrate with the adhesive film.

[0377] (Note 14) A method for manufacturing a memory cube according to Note 13, comprising stretching the dicing tape to widen the first groove and the second groove, and expanding the third insulating film along the first groove and the second groove.

[0378] (Note 15) A method for manufacturing a memory cube according to Note 14, comprising stretching the dicing tape to widen the first groove and the second groove, and expanding the third insulating film along the first groove and the second groove.

[0379] 10: Semiconductor module, 10A: Semiconductor module, 10AF: Semiconductor module, 10AG: Semiconductor module, 10B: Semiconductor module, 10C: Semiconductor module, 10D: Semiconductor module, 10E: Semiconductor module, 20: Bonded chip, 20A: Bonded chip, 20B: Bonded chip, 20Bn: Bonded chip, 20C: Bonded chip, 20Cn: Bonded chip, 20n: Bonded chip, 25: Structure, 30: Stacked memory chip, 30A: Stacked memory chip, 30B: Stacked memory chip, 38: Corner, 39: Corner, 39a: Corner, 39b: Corner, 39 c: corner, 39d: corner, 42: fifth surface, 42A: fifth surface, 42B: fifth surface, 44: sixth surface, 44A: sixth surface, 44B: sixth surface, 45: third surface, 45A: third surface, 45B: third surface, 46: first surface, 46A: first surface, 46B: first surface, 47: fourth surface, 47A: fourth surface, 47B: fourth surface, 48: second surface, 48A: second surface, 48B: second surface, 49: insulating layer, 50a: first substrate, 50b: second substrate, 51: bump, 52: peripheral area, 54: IC chip area, 56: groove, 57: groove, 58: groove, 60: liquid, 62: electrode, 65: organic film, 70: adhesive film, 71: die Single tape, 72: Dummy chip, 80a: Reference surface, 80b: Reference surface, 80c: Reference surface, 85: Insulating film, 86: Second inclined section, 87: First inclined section, 90: Structure, 90A: Structure, 100: Memory cube, 100A: Memory cube, 100B: Memory cube, 100C: Memory cube, 100C: Cube chip, 100CA: Memory cube, 100CB: Memory cube, 101a: Second face, 101b: First face, 101c: Eleventh face, 101d: Eleventh face, 102: First face, 102A: First face, 102An: First face, 102B: First face, 10 2Bn: first surface, 102n: first surface, 104: second surface, 104A: second surface, 104B: second surface, 105: second side, 105A: second side, 105B: Second side surface, 105C: Second side surface, 106: First side surface, 106A: First side surface, 106B: First side surface, 107: Fourth side surface, 107A: Fourth side, 107B: Fourth side, 107C: Fourth side, 108: Third side, 108A: Third side, 108B: Third side, 108C: Third side surface, 109: 21st surface, 109A: 21st surface, 109An: 21st surface, 109B: 21st surface, 109Bn: 21st surface, 109n: 21st surface,110: IC chip, 110A: IC chip, 110An: IC chip, 110B: IC chip, 110Bn: IC chip, 110C: IC chip, 110n: IC chip, 111: Memory module, 112: TCI-IO, 113: Parallel-to-serial conversion circuit, 114: Transceiver circuit, 115: Memory cell array, 130: Transistor layer, 140: Adhesive film, 142: Fifth surface, 142A: Fifth surface, 142B: Fifth surface, 144: Sixth surface, 144A: Sixth surface, 144B: Sixth surface, 145: Third surface, 145A: Third surface, 145B: Third surface, 145C: Third surface, 146: Surface 1, 146A: Surface 1, 146B: Surface 1, 146C: Surface 1, 147: Surface 4, 147A: Surface 4, 147B: Surface 4, 147C: Surface 4, 148: Surface 2, 148A: Surface 2, 148B: Surface 2, 148C: Surface 2, 150: Wiring layer, 155: Insulating film, 160: Conductive film, 162: Side power wiring, 163: Side ground wiring, 164: Power wiring, 165: Ground wiring, 166: Signal transmission wiring, 167: Bump, 170: Inductor layer, 172: Inductor, 172a: Part 1, 172b: Part 2, 172c: Part 3, 172d: Part 5, 172e: Part 4, 173: Substrate, 174: Element isolation region, 175: Activation region, 176: Transistor, 177: Insulating layer, 178: Wiring, 179: Insulating layer, 180: Wiring, 181: Insulating layer, 182: Insulating layer, 183: Wiring, 184: Insulating layer, 185: Insulating layer, 200: Logic chip, 202: First surface, 204: Second surface, 211: Logic module, 272: Inductor, 272a: Part 1, 300: First substrate, 300A: Second substrate, 302: First surface, 302A: First surface, 304: Second surface, 311: TCI-IO control module, 312: TCI-IO, 313: Parallel-to-series conversion circuit, 314: Transceiver circuit, 326: Wiring layer, 327: Wiring, 328: Wiring layer, 329: Wiring, 330: Wiring layer, 331: Wiring, 332: Wiring layer, 333: Wiring, 334: Wiring layer, 335: Wiring, 370: Inductor layer, 372: Inductor, 372a: First part, 372b: Second part, 372c: Third part, 372d: Fifth part, 372e: Fourth part, 400: Adhesive layer, 404: Second surface, 420: Bump, 422: UF material, 445: Conductive film, 445-1: Conductive film, 445-2: Conductive film, 446: Conductive film, 447: Conductive film, 500: Bump layer,502: Bump, 600: Substrate, 602: First surface, 604: Second surface, 606: Wiring layer, 607: Wiring, 608: Wiring layer, 609: Wiring, 610: Wiring layer, 611: Wiring, 612: Wiring layer, 613: Wiring, 630: Cavity substrate, 632: Cavity area, 700: Logic chip, 702: First surface, 704: Second surface, 720: Flexible substrate, 730: Transistor layer, 750: Wiring layer, 754: Divided region, 756: Third surface, 758: Groove, 760: 31st surface, 760n: 31st Surface, 762: Fourth surface, 762n: Fourth surface, 773: Substrate, 791: Electrode pad, 792: Through electrode, 793: Bump, 800: Redistribution layer, 804: Second surface, 850: Jig, 862: Side power wiring, 863: Side ground wiring, 867: Side signal transmission wiring, 900: Power supply unit, 901: Support unit, 902: Pogo pin, 910: Letter-shaped member, 920: Flexible substrate, 1000: Frame, 1000A: Frame, 1000B: Frame, 1002: Insulating film, 1100: Thermal conductive sheet, 1200: Metal film,

Claims

1. A method for manufacturing a memory cube in which a plurality of substrates on which memory is formed are stacked, comprising: dividing a first substrate and a second substrate on which the memory is formed into a plurality of substrates, each including a first surface and a second surface opposite to the first surface; joining two different substrates from the plurality of substrates to form a single bonding chip; forming a plurality of the single bonding chips, joining the plurality of bonding chips to form a stacked chip; and forming electrodes that are electrically connected to a plurality of wirings exposed on the side surface, wherein each of the plurality of substrates includes a third surface, a fourth surface opposite to the third surface, the end of the third surface and the side surface in contact with the end of the fourth surface, and the plurality of wirings exposed on the side surface, and having a first adhesive film made of an organic resin as a base material on part or all of the bonding interface between the bonding chip and the stacked chip, wherein the first adhesive film is separated from the wiring exposed on the side surface of the bonding chip and the stacked chip by molding.

2. The method for manufacturing a memory cube according to claim 1, further comprising forming grooves on the second surface by plasma grooving before the division, and then forming an inorganic insulating film on the second surface and on the grooves.

3. The method for manufacturing a memory cube according to claim 2, further comprising forming the inorganic insulating film, and then attaching the first adhesive film to the inorganic insulating film on the second surface to form the fourth surface.

4. The method for manufacturing a memory cube according to claim 3, wherein the division includes grinding and polishing the first surface to form the third surface.

5. The method for manufacturing a memory cube according to claim 4, further comprising: plasma activation or vacuum ultraviolet treatment of the first adhesive film on the plurality of substrates before forming the bonding chip, wherein forming the bonding chip includes bonding the first adhesive films on two different substrates by thermocompression bonding.

6. The method for manufacturing a memory cube according to claim 1, wherein the plurality of bonding chips include a first bonding chip and a second bonding chip, and forming the laminated chip includes applying a liquid to a third surface of the second substrate of the second bonding chip and bonding the third surface to which the liquid has been applied and the fourth surface of the first substrate of the first bonding chip by self-assembly.

7. The method for manufacturing a memory cube according to claim 6, wherein forming the laminated chip includes, after joining the plurality of bonding chips by the self-assembly, applying a UV-curing resin between the third surface of the second substrate of the second bonding chip and the third surface of the first substrate of the first bonding chip.

8. The method for manufacturing a memory cube according to claim 7, wherein forming the laminated chip includes joining the plurality of bonding chips by the self-assembly method, and then applying the UV-curing resin to the corners of the joined plurality of bonding chips.

9. A method for manufacturing a memory cube according to claim 1, further comprising: forming grooves on the second surface by plasma grooving before the division; forming an inorganic insulating film on the second surface and on the grooves to form the fourth surface; and grinding and polishing the first surface after the inorganic insulating film has been formed.

10. The method for manufacturing a memory cube according to claim 9, wherein the division comprises: applying the first adhesive film to the ground and polished surface after grinding and polishing to form the third surface; oxidizing the ground and polished surface; and, after the oxidation, using a laser, expander, or plasma etching, dividing the inorganic insulating film and the first adhesive film along the groove in a direction toward the fourth surface and toward the third surface.

11. The method for manufacturing a memory cube according to claim 10, wherein, prior to forming the bonded chip, the third surface of one of the two distinct substrates and the fourth surface of the remaining substrate are subjected to plasma activation or vacuum ultraviolet treatment, and the formation of the bonded chip includes low-temperature bonding with the third surface of the one substrate and the fourth surface of the remaining substrate facing each other.

12. The method for manufacturing a memory cube according to claim 11, wherein forming the stacked chips includes joining the plurality of bonding chips in a vacuum or a high-pressure atmosphere.

13. The method for manufacturing a memory cube according to claim 9, wherein forming the stacked chip further comprises forming a bump on the bottom surface of the stacked chip.

14. The method for manufacturing a memory cube according to claim 3, wherein the division comprises grinding and polishing a first surface of the first substrate; attaching a second adhesive film to the ground and polished surface to form a third surface of the first substrate; oxidizing the ground and polished surface; using a laser, expander, or plasma etching to divide the inorganic insulating film and the second adhesive film along the groove of the first substrate in a direction from the fourth surface toward the third surface; and grinding and polishing the first surface of the second substrate to form a third surface of the second substrate.

15. A method for manufacturing a memory cube according to claim 14, wherein one of the two distinct substrates is divided using the first substrate and includes a fourth surface and a third surface including the second adhesive film, the other of the two distinct substrates is divided using the second substrate and includes a third surface having the fourth surface and the first surface ground and polished, and forming the bonded chip involves bonding the second adhesive film of the one substrate to the third surface of the other substrate by thermocompression bonding.

16. The method for manufacturing a memory cube according to claim 15, wherein the plurality of bonding chips include a first bonding chip and a second bonding chip, and forming the stacked chip involves bonding the fourth surface of the remaining substrate of the second bonding chip to the fourth surface of one of the substrates of the first bonding chip using plasma activation.

17. The method for manufacturing a memory cube according to claim 16, wherein forming the stacked chip includes, after joining the plurality of bonding chips, sandwiching the joined plurality of bonding chips between three different third substrates on which the memory is not formed.

18. The method for manufacturing a memory cube according to claim 5, wherein the plurality of bonding chips include a first bonding chip and a second bonding chip, and forming the laminated chip includes: placing the plurality of bonding chips in a jig that can vibrate and pressurize; vibrating the jig and pressurizing the plurality of bonding chips in a direction perpendicular to the third surface; applying UV-curing resin to three of the four corners of the bonded plurality of bonding chips that are separated from the jig; and applying the UV-curing resin between the fourth surface of the second substrate of the second bonding chip and the fourth surface of the first substrate of the first bonding chip.

19. A method for manufacturing a memory cube in which a plurality of substrates on which memory is formed are stacked, comprising: joining the second surfaces of a first substrate and a second substrate on which the memory is formed, which include a first surface and a second surface opposite to the first surface; grinding and polishing the first surface of the second substrate to form a third surface; forming grooves on the third surface by plasma grooving, and then forming an inorganic film on the third surface and on the grooves; grinding and polishing the first surface of the first substrate to form a fourth surface and to form a plurality of bonding chips; joining the plurality of bonding chips to form a stacked chip; and forming electrodes that are electrically connected to a plurality of wirings exposed on the end of the third surface and the side surface in contact with the end of the fourth surface, wherein each of the plurality of bonding chips includes the side surface, and the angle between the side surface and the fourth surface is less than 90 degrees.

20. The method for manufacturing a memory cube according to claim 19, wherein the plurality of bonding chips include a first bonding chip and a second bonding chip, and forming the laminated chip includes: placing the plurality of bonding chips in a jig that can vibrate and pressurize; vibrating the jig and pressurizing the plurality of bonding chips in a direction perpendicular to the third surface; applying UV-curing resin to three of the four corners of the bonded plurality of bonding chips that are separated from the jig; and applying the UV-curing resin between the fourth surface of the second bonding chip and the fourth surface of the first bonding chip.

21. The method for manufacturing a memory cube according to claim 1, wherein the first adhesive film is formed using photolithography.

22. The method for manufacturing a memory cube according to claim 10, wherein separating the inorganic insulating film and the first adhesive film along the groove in a direction from the fourth surface to the third surface using the laser, the expander, or the plasma etching comprises any one of the following: a first process of scanning the laser along the groove; a second process of scanning the laser along the groove, separating the inorganic insulating film along the groove in a direction from the fourth surface to the third surface; and etching the first adhesive film exposed in the groove in a direction from the fourth surface to the third surface using the plasma etching; and a third process of separating the inorganic insulating film along the groove in a direction from the fourth surface to the third surface using dicing, and expanding by stretching a dicing tape attached to the first adhesive film to widen the spacing between a plurality of substrates.

23. The method for manufacturing a memory cube according to claim 14, wherein separating the inorganic insulating film and the second adhesive film along the groove of the first substrate in a direction toward the fourth surface to the third surface using the laser, the expander, or the plasma etching comprises any one of the following processes: a first process of scanning the laser along the groove; a second process of scanning the laser along the groove, separating the inorganic insulating film along the groove in a direction toward the fourth surface to the third surface; and etching the first adhesive film exposed in the groove in a direction toward the fourth surface to the third surface using the plasma etching; and a third process of separating the inorganic insulating film along the groove in a direction toward the fourth surface to the third surface using dicing, and expanding by stretching a dicing tape attached to the second adhesive film to widen the spacing between a plurality of substrates.

24. The method for manufacturing a memory cube according to any one of claims 7, 8, and 18, wherein the UV-curing resin is applied using a dispenser.

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