Airgap source / drain for tensile channel strain

Abstract

Gate-all-around (GAA) transistor devices and methods for forming GAA transistor devices are provided. The method includes forming a sacrificial capping layer over a source / drain cavity, the source / drain cavity defined by a pair of opposing sidewalls, the sidewalls each defined by alternating pairs of a first semiconductor layer and a second semiconductor layer, the sacrificial capping layer defining an air gap in between the opposing sidewalls and at least a portion of the sacrificial capping layer covers the air gap. The method further includes performing a replacement metal gate process and removing the sacrificial capping layer to expose the source / drain cavity, wherein the sacrificial capping layer keeps the source / drain cavity free from deposition during the replacement metal gate process.

Description

PATENTAttorney Docket No.: 44025376WO01AIRGAP SOURCE / DRAIN FOR TENSILE CHANNEL STRAIN BACKGROUNDField

[0001] Implementations of the present disclosure generally relate to semiconductor devices and methods for forming semiconductor devices. More specifically, the present disclosure relates to gate-all-around (GAA) transistor devices and methods for forming GAA transistor devices.Description of the Related Art

[0002] The electronics industry is experiencing an ever-increasing demand for smaller and faster electronic devices, which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). These goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thus improving production efficiency and lowering associated costs. However, such miniaturization has introduced greater complexity into the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.

[0003] Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device is the gate-all-around transistor (GAA). In a GAA device, all side surfaces of the channel region are surrounded by the gate electrode, which allows for fuller depletion in the channel region and results in less short-channel effects due to a steeper sub-threshold current swing and smaller drain induced barrier lowering (DIBL).

[0004] As transistor dimensions are scaled down to smaller technology nodes, there is a need for further improvements in GAA design and manufacturing.PATENTAttorney Docket No.: 44025376WO01SUMMARY

[0005] Implementations of the present disclosure generally relate to semiconductor devices and methods for forming semiconductor devices. More specifically, the present disclosure relates to gate-all-around (GAA) transistor devices and methods for forming GAA transistor devices.

[0006] In one or more implementations which can be combined with other implementations, a method of forming a semiconductor device is provided. The method includes forming a sacrificial capping layer over a source / drain cavity, the source / drain cavity defined by a pair of opposing sidewalls, the sidewalls each defined by alternating pairs of a first semiconductor layer and a second semiconductor layer, the sacrificial capping layer defining an air gap in between the opposing sidewalls and at least a portion of the sacrificial capping layer covers the air gap. The method further includes performing a replacement metal gate process and removing the sacrificial capping layer to expose the source / drain cavity, wherein the sacrificial capping layer keeps the source / drain cavity free from deposition during the replacement metal gate process.

[0007] Implementations may include one or more of the following. A source / drain material is formed in the source / drain cavity after removing the sacrificial capping layer. Each sidewall is further defined by a dummy gate structure formed over the alternating pairs of the first semiconductor layer and the second semiconductor layer. The sacrificial capping layer has a first thickness along a top surface of the dummy gate structure and a second thickness along the sidewalls, the first thickness being greater than the second thickness. The sacrificial capping layer is a silicon-containing low-k dielectric material. The silicon-containing low-k dielectric material is silicon oxide, silicon carbonitride, or a combination thereof. Forming the sacrificial capping layer is performed by a plasma enhanced chemical vapor deposition process. The replacement metal gate process includes removing the first semiconductor layers to form recesses between the second semiconductor layers and filling the recesses with a metal gate material.

[0008] In one or more implementations which can be combined with other implementations, a method of forming a semiconductor device is provided. ThePATENTAttorney Docket No.: 44025376WO01method includes forming a sacrificial capping layer over a source / drain cavity, the source / drain cavity defined by a pair of opposing sidewalls, the sidewalls each defined by a dummy gate formed over alternating pairs of a first semiconductor layer and a second semiconductor layer, the sacrificial capping layer coating a top surface of the dummy gate and the sidewalls, the sacrificial capping layer defining an air gap in between the opposing sidewalls and at least a portion of the sacrificial capping layer covers the air gap. The method further includes removing the sacrificial capping layer coating the top surface of the dummy gate; selectively removing the dummy gate and the first semiconductor layers; performing a replacement metal gate process; removing the sacrificial capping layer to expose the source / drain cavity; and forming an epitaxial source / drain material in the source / drain cavity.

[0009] Implementations may include one or more of the following. The sacrificial capping layer keeps the source / drain cavity free from deposition during the replacement metal gate process. A portion of the first semiconductor layer is removed to form a sidewall recess prior to forming the sacrificial capping layer. An inner spacer is formed in the sidewall recess. The sacrificial capping layer fills the sidewall recess. Removing the sacrificial capping layer to expose the source / drain cavity forms an inner spacer in the sidewall recesses. The sacrificial capping layer is a silicon-containing low-k dielectric material. The silicon-containing low-k dielectric material is silicon oxide, silicon carbonitride, or a combination thereof.

[0010] In one or more implementations which can be combined with other implementations, a method of forming a semiconductor device is provided. The method includes forming a first fin structure and a second fin structure on a substrate, wherein the first fin structure and the second fin structure each include alternating pairs of a first semiconductor layer and a second semiconductor layer, opposing sidewalls of the first fin structure and the second fin structure defining a source / drain cavity in between the first fin structure and the second fin structure. The method further includes forming a sacrificial capping layer over the source / drain cavity, the source / drain cavity defined by a pair of opposing sidewalls, the sacrificial capping layer coating a top surface of the first fin structure, a top surface of the second fin structure and the sidewalls defining the source / drain cavity, the sacrificial capping layer definingPATENTAttorney Docket No.: 44025376WO01an air gap in between the opposing sidewalls and at least a portion of the sacrificial capping layer covers the air gap. The method further includes removing the first semiconductor layers to form recesses between the second semiconductor layers; filling the recesses with a metal gate material; removing the sacrificial capping layer to expose the source / drain cavity after filling the recesses with the metal gate material; and forming an epitaxial source / drain material in the source / drain cavity.

[0011] Implementations may include one or more of the following. The sacrificial capping layer is a silicon-containing low-k dielectric material. The sacrificial capping layer has a first thickness along the top surface of the first fin structure and the top surface of the second fin structure, and a second thickness along the sidewalls, the first thickness being greater than the second thickness. The first semiconductor layer is silicon germanium, the second semiconductor layer is silicon, and the sacrificial capping layer is silicon oxide.

[0012] In another aspect, a non-transitory computer readable medium has stored thereon instructions, which, when executed by a processor, causes the process to perform operations of the above apparatus and / or method.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.

[0014] FIG. 1 illustrates one example, of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view in accordance with one or more implementations of the present disclosure.

[0015] FIG. 2 illustrates one example of a flow chart of a method of forming a nano-FET structure in accordance with one or more implementations of the present disclosure.PATENTAttorney Docket No.: 44025376WO01

[0016] FIGS. 3A-3J illustrate schematic views of various stages of forming a nano-FET structure in accordance with one or more implementations of the present disclosure.

[0017] FIG. 4 illustrates a plan view of a cluster tool in accordance with one or more implementations of the present disclosure.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0019] Implementations of the present disclosure generally relate to semiconductor devices and methods for forming semiconductor devices. More specifically, the present disclosure relates to GAA transistor devices and methods for forming GAA transistor devices.

[0020] Scaling down of silicon metal oxide semiconductor (MOS) devices has become a major challenge in the semiconductor industry. One problem with the scaling of conventional planar devices is the short channel effects, which start to dominate over device performance. One solution to this problem came with the introduction of multi-gate devices with three-dimensional architecture, such as fin-based semiconductor devices or FinFETs and GAA devices. Due to their three-dimensional architecture with either the gate being wrapped around a thin semiconductor fin for FINFET or the gate electrode surrounding all side surfaces of the channel region for GAA, improved gate control (and thus less short channel effects) over the channel could be achieved by using multiple gates.

[0021] The introduction of these multi-gate devices has led to additional challenges. For example, horizontal GAA (hGAA) devices typically lack nMOS strain. An initial tensile strain in the nMOS channel, which is beneficial for device performance, is typically present. However, the introduction of nMOS source drainPATENTAttorney Docket No.: 44025376WO01(S / D) epitaxial material will fill up the trench and reduce tensile strain, resulting in loss of device performance.

[0022] In one or more implementations of the present disclosure, the replacement metal gate (RMG) process is performed prior to deposition of the epitaxial source / drain material, for example, while the source / drain cavity is empty and protected by a sacrificial capping layer. Thus, the tensile strain in the channel can be conserved by the RMG metals and the strain will be present even after epitaxial growth of the source / drain material. In addition, the sacrificial capping layer is removable without damaging the underlying structure.

[0023] The implementations described herein are applicable to nanostructure fieldeffect transistors (nano-FET) including vertically stacked lateral nanowires (NW) / nanosheets (NS) Gate-AII-Around (GAA) FET devices.

[0024] FIG. 1 illustrates one example of a nanostructure field-effect transistor (nano-FET) 100 in a three-dimensional view in accordance with one or more implementations of the present disclosure. The nano-FET 100 includes nanostructures 120, for example, nanosheets, nanowire, or the like, formed over fin structures 130 on a substrate 110, for example, a semiconductor substrate, wherein the nanostructures 120 act as channel regions for the nano-FET. The nanostructure 120 may include p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions 140 are disposed between adjacent fin structures 130, which may protrude above and from between neighboring isolation regions 140. Although the isolation regions 140 are described / illustrated as being separate from the substrate 110, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of the fin structures 130 are illustrated as being single, continuous materials with the substrate 110, the bottom portion of the fin structures 130 and / or the substrate 110 may include a single material or a plurality of materials. In this context, the fin structures 130 refer to the portion extending between the neighboring isolation regions 140.PATENTAttorney Docket No.: 44025376WO01

[0025] Gate dielectric layers 160 are over top surfaces of the fin structures 130 and along top surfaces, sidewalls, and bottom surfaces of the nanostructures 120. Gate electrodes 170 are over the gate dielectric layers 160. Epitaxial source / drain regions 150 are disposed on the fin structures 130 on opposing sides of the gate dielectric layers 160 and the gate electrodes 170. Source / drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context.

[0026] Some implementations discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other implementations, a gate-first process may be used. Also, some implementations contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs).

[0027] FIG. 2 illustrates an exemplary flow chart of a method 200 of forming a nano-FET structure in accordance with one or more implementations of the present disclosure. FIGS. 3A-3J illustrate schematic views of various stages of forming a nano-FET structure in accordance with one or more implementations of the present disclosure. With reference to FIGS. 3A-3J, schematic views of some implementations of a nano-FET structure at various stages of manufacture are provided to illustrate the method of FIG. 2. Although FIGS. 3A-3J are described in relation to the method 200, it will be appreciated that the structures disclosed in FIGS. 3A-3J are not limited to the method 200 but instead may stand alone as structures independent of the method 200. Similarly, although the method 200 is described in relation to FIGS. 3A-3J, it will be appreciated that the method 200 is not limited to the structures disclosed in FIGS.3A-3J but instead may stand alone independent of the structures disclosed in FIGS.3A-3J. The method 200 may be used to form portions of the nano-FET 100 depicted in FIG. 1.

[0028] Referring to FIG. 3A, at operation 210 a semiconductor device structure 300 having a source / drain cavity 308 is provided. The semiconductor device structure 300 may be or be part of a multi-gate device with three-dimensional architecture, such as fin-based semiconductor devices including nano-FETs and gate-all-around (GAA) transistor devices. The semiconductor device structure 300 includes a first semiconductor region 302 also referred to as a first fin structure and a second semiconductor region 304 also referred to as a second fin structure formed on aPATENTAttorney Docket No.: 44025376WO01substrate 306. The first semiconductor region 302 and the second semiconductor region 304 are separated by a feature, such as the source / drain cavity 308, which exposes the substrate 306. In one or more implementations, as is shown in FIG. 3A, a portion of the source / drain cavity 308 extends into the substrate 306.

[0029] As shown in FIG. 3A, the first semiconductor region 302 and the second semiconductor region 304 each include a plurality of alternating semiconductor layers 309. The plurality of alternating semiconductor layers 309 include first semiconductor layers 310A-C and second semiconductor layers 312A-C that are alternately and repeatedly stacked on the substrate 306. Although the example shown in FIG. 3A shows three pairs, each pair including the first semiconductor layer 310A-C and the second semiconductor layer 312A-C, the number of pairs may be varied based on different process needs with or without the first semiconductor layers 310A-C and the second semiconductor layers 312A-C being needed. The first semiconductor layers 310A-C are formed of a first material having etch selectivity to a second material of which the second semiconductor layers 312A-C are formed, for example, an etch rate of the first material is higher than an etch rate of the second material. The etch selectivity, a ratio of the etch rate of the first material to the etch rate of the second material, is between about 10:1 to 200:1. Example combinations of the first material and the second material include silicon-germanium (SiGe)Zsilicon (Si), silicongermanium (SiGe) / germanium (Ge), and germanium tin (GeSn)Zsilicon (Si). In one or more implementations, which can be combined with other implementations, the first semiconductor layers 310A-C are or include SiGe and the second semiconductor layers 312A-C are or include silicon, for example, crystalline silicon. The second semiconductor layers 312A-C may serve as channels having a width of between several nanometers and several tens of nanometers. The first semiconductor layers 310A-C and the second semiconductor layers 312A-C can be nanostructures, for example, nanowires or nanosheets.

[0030] The first semiconductor layers 310A-C and the second semiconductor layers 312A-C may be formed using any suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the source / drain cavity 308 is formed by a patterning technique,PATENTAttorney Docket No.: 44025376WO01such as lithography followed by an etch or ashing process. The first semiconductor layers 310A-C and the second semiconductor layers 312A-C may each have thickness of between about 1 nm and about 15 nm, for example, about 10 nm. The selective etching of the first semiconductor layers 310A-C may be performed by any appropriate etching process, such as a dry plasma etching process.

[0031] The semiconductor device structure 300 further includes a dummy gate structure 320 formed over at least a portion of each of the first semiconductor region 302 and the second semiconductor region 304. The dummy gate structure 320 includes a dummy gate 322. The dummy gate 322 may be a conductive or nonconductive material and may be selected from amorphous silicon, doped or undoped polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), silicon oxide, metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate 322 may be formed using any suitable techniques such as physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), CVD, ALD, or the like. The dummy gate 322 includes a top surface 322t, which defines a top surface of the semiconductor device structure 300.

[0032] The dummy gate structure 320 may further include a dummy gate dielectric layer 324 formed on or over the alternating semiconductor layers 309, for example, on or over the first semiconductor layer 310C. The dummy gate 322 is formed on or over the dummy gate dielectric layer 324 with the dummy gate dielectric layer 324 formed in between the alternating semiconductor layers 309 and the dummy gate 322 such that the dummy gate dielectric layer 324 separates the dummy gate 322 from the alternating semiconductor layers 309. The dummy gate dielectric layer 324 protects the underlying alternating semiconductor layers 309 during subsequent removal of the dummy gate 322. The dummy gate dielectric layer 324 may be formed of any suitable oxide, for example, silicon oxycarbonitride, silicon oxide, silicon oxynitride, or the like, using any suitable techniques such as thermal oxidation, or deposited by PECVD, CVD, ALD, or the like.

[0033] The dummy gate structure 320 may further include one or more spacers 326. The spacer 326 may function as a spacer for forming self-aligned source / drain regions. The spacer 326 may be formed along the sidewalls of the dummy gate 322PATENTAttorney Docket No.: 44025376WO01and the dummy gate dielectric layer 324. The spacer 326 may be formed of silicon oxycarbonitride, silicon oxide, silicon nitride, silicon oxynitride, or the like, using any suitable techniques such as thermal oxidation, or deposited by PECVD, CVD, ALD, or the like.

[0034] The substrate 306 has a frontside 306f (also referred to as a front surface) and a backside 306b opposite the frontside 306f. The substrate 306 may be a material such as crystalline silicon (e.g., Si<100> or Si<111 >), silicon oxide, strained silicon, silicon-germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. In one or more implementations, which can be combined with other implementations, the substrate 306 is or includes crystalline silicon.

[0035] The source / drain cavity 308 is defined by a pair of opposing sidewalls 308s and a bottom surface 308b. The sidewalls 308s may be defined by the dummy gate structure 320 and the alternating pairs of the first semiconductor layers 310A-C and the second semiconductor layers 312A-C. The bottom surface 308b of the source / drain cavity 308 is defined by the substrate 306.

[0036] Referring to FIG. 3B, at operation 220, an inner cavity recess process may be performed. As shown in FIG. 3B, portions of the sidewalls 308s of the plurality of alternating semiconductor layers 309 formed of the first semiconductor layers 310A-C exposed by the source / drain cavity 308 are etched to form sidewall recesses 330A-C along the sidewalls 308s. Although sidewalls of the first semiconductor layers 310A-C in the sidewall recesses 330A-C are illustrated as being straight in FIG. 3B, the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. In one or more implementations in which the first semiconductor layers 310A-C include, for example, SiGe, and the second semiconductor layers 312A-C include, for example, Si or SiC, a wet etch process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch the sidewalls of the first semiconductor layersPATENTAttorney Docket No.: 44025376WO01

[0037] Referring to FIG. 3C, at operation 230, inner spacer layers are formed. As shown in FIG. 3C, first inner spacers 332A-C are formed in the sidewall recess 330A-C. The first inner spacers 332A-C may be formed by depositing an inner spacer layer (not separately illustrated) over the structure illustrated in FIG. 3B. The first inner spacers 332A-C function as isolation features between subsequently formed source / drain regions and a gate structure. As will be discussed in greater detail below, source / drain regions will be formed in the source / drain cavity 308, while the first semiconductor layers 310A-C in the n-type region and in the p-type region (not shown) will be replaced with corresponding gate structures.

[0038] The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may be or include a material such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may then be anisotropically etched to form the first inner spacers 332A-C. Although outer sidewalls of the first inner spacers 332A-C are illustrated as being flush with sidewalls of the second semiconductor layers 312A-C in the n-type region shown in FIG. 3C and in the p-type region (not shown), the outer sidewalls of the first inner spacers 332A-C may extend beyond or be recessed from sidewalls of the second semiconductor layers 312A-C and / or the first inner spacers 332A-C, respectively.

[0039] Moreover, although the outer sidewalls of the first inner spacers 332A-C are illustrated as being straight in FIG. 3C, the outer sidewalls of the first inner spacers 332A-C may be concave or convex. The inner spacer layer may be etched by an anisotropic etching process, such as reactive ion etching (RIE) or the like. The first inner spacers 332A-C may be used to prevent damage to the subsequently formed source / drain region, for example, the source / drain region 380 discussed below with respect to FIG. 3 J , by subsequent etching processes, such as etching processes used to form gate structures.

[0040] The first inner spacers 332A-C may be formed of dielectric material, such as silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN). In one or more implementations, the first inner spacersPATENTAttorney Docket No.: 44025376WO01332A-C are formed from the same material as the spacer 326. For example, both the first inner spacers 332A-C and the spacer 326 are formed from silicon oxycarbonitride. In one or more other implementations, the first inner spacers 332A-C are formed from a material that is different from the material of the spacer 326.

[0041] Referring to FIG. 3D, at operation 240, a sacrificial capping layer 340 is formed over or on the semiconductor device structure 300 such that the opening of the source / drain cavity 308 is blocked while maintaining an air gap 342 within the source / drain cavity. The air gap 342 is not just an open air space in a trench but is a space that is enclosed on the sides / bottom / top by the sacrificial capping layer 340. The sacrificial capping layer 340 protects the source / drain cavity 308 by keeping the source / drain cavity 308 free from deposition during the subsequent replacement metal gate (RMG) process performed at operation 250. As shown in FIG. 3D, the sacrificial capping layer 340 coats the top surface 322t of the dummy gate 322, the sidewalls 308s and optionally the bottom surface 308b. The sacrificial capping layer 340 defines the air gap 342 between the opposing sidewalls 308s and the sacrificial capping layer 340. The sacrificial capping layer 340 forms a thicker layer along the top surface 322t while forming a thinner layer which coats the sidewalls 308s and optionally the bottom surface 308b within the source / drain cavity 308, which define the air gap 342. The sacrificial capping layer 340 and the air gap enable the tensile strain in the channel to be conserved by the RMG metals, and the strain will be present even after epitaxial growth of the source / drain region 380 within the source / drain cavity 308.

[0042] The sacrificial capping layer 340 is formed by a pinch-off deposition process meaning that the deposition conditions including process gas flow rates are selected such that the top portion of the source / drain cavity 308 closes-off before the source / drain cavity 308 fills with the sacrificial capping material, which leaves the air gap 342 within the source / drain cavity 308. The pinch-off deposition process provides sufficient reactants at the surface of the semiconductor device structure 300 to have uniform deposition across the surface of the semiconductor device structure 300 while ensuring that the reaction happens primarily at the top of the source / drain cavity 308. This allows the deposition to be thicker at the top of the source / drain cavity 308, resulting in a pinch-off, which forms the air gap 342 within the source / drain cavity 308.PATENTAttorney Docket No.: 44025376WO01

[0043] The sacrificial capping layer 340 may be formed of a low-k dielectric material. Any suitable low-k dielectric material which provides protection for the source / drain cavity 308 while meeting selective etching characteristics may be used. The low-k dielectric material is typically compatible with ease of the metal gate processing and ease of subsequent removal with no damage to the structure. The low-k dielectric material can be a silicon-containing low-k dielectric material having a k-value less than about 3.5. Examples of suitable low-k dielectric materials include silicon-containing low-k dielectric materials such as silicon oxide, for example, SiO2, silanol, for example, SiOH, silicon oxycarbonitrides, for example, SiOCN, and silicon carbonitrides, for example, SiCNH or SiCN. In one or more implementations, the sacrificial capping layer 340 is or includes silicon carbon nitride, such as that available under the trade name BLOk® available commercially from Applied Materials.

[0044] The low-k dielectric material of the sacrificial capping layer 340 may be formed using any suitable pinch-off deposition techniques, for example, CVD or PECVD techniques. In one or more implementations, deposition of the low-k dielectric material includes providing one or more silicon-containing precursors. The silicon-containing precursors can include silicon-and-nitrogen containing precursors, silicon-and-hydrogen containing precursors, silicon-and-nitrogen-and-hydrogen containing precursors, silicon-and-carbon-and-hydrogen containing precursors, or a combination thereof. The one or more silicon-containing precursors can be a silane-containing precursor, a silylamine precursor, an organosilicon precursor, or a combination thereof. In one or more implementations, the silane-containing precursor is silane, disilane, trisilane, tetrasilane, higher order silanes, substituted silanes, or a combination thereof, among others. In one or more implementations, the silylamine precursor is trisilylamine (N(SiH3)3), disilylamine (HN(SiH3)2), silylamine (H2N(SiH3), or a combination thereof, among others. In one or more implementations, the organosilicon precursor is dimethylsilane, trimethylsilane, tetramethylsilane, diethylsilane, tetramethylorthosilicate (TMOS), tetraethylorthosilicate (TEOS), octamethyltrisiloxane (OMTS), octamethylcyclotetrasiloxane (OMCTS), tetramethylcyclotetrasiloxane (TOMCATS), DMDMOS, DEMS, methyl triethoxysilane (MTES), phenyldimethylsilane, and phenylsilane, or a combination thereof, among others. The low-k dielectric material can be deposited using an RF plasma, where thePATENTAttorney Docket No.: 44025376WO01RF power is in a range from about 50 Watts to about 500 Watts. The process chamber can be maintained at a temperature in a range from about 25 degrees Celsius to about 400 degrees Celsius. The silicon-containing precursor can be mixed with a reaction precursor to create a deposition gas. The reaction precursor can be an inert gas such as argon or helium, an oxidizing gas, such as 02, a nitrogen containing gas, such as nitrogen or ammonia, or a combination thereof.

[0045] The silicon-containing precursor may be mixed with a carrier gas before or during its introduction to the deposition chamber. A carrier gas may be an inactive gas that does not unduly interfere with the formation of the oxide film on the substrate. Examples of carrier gases include helium, hydrogen, neon, argon, and nitrogen, among other gases.

[0046] An oxygen-containing precursor may also be introduced to the substrate containing reaction chamber. The oxygen containing precursor may include atomic oxygen remotely generated outside the deposition chamber. The atomic oxygen may be generated by the dissociation of a precursor such as molecular oxygen (O2), ozone (O3), a nitrogen-oxygen compound (e.g., NO, NO2, N2O, etc.), a hydrogen-oxygen compound (e.g., H2O, H2O2, etc.), a carbon-oxygen compound (e.g., CO, CO2, etc.), as well as other oxygen containing precursors and combinations of precursors.

[0047] One or more of the precursors can be activated to deposit a carbon containing material from the deposition gas. The deposition gas mixture or components thereof can be activated using power sources capable of forming ionized and radical species from the reactant gas mixture. In one example, the power source is an RF power source. The RF power source can produce a plasma from one or more of the precursors which comprise the deposition gas. The RF power can be maintained at between 50 W and 500 W for a 300 mm diameter substrate. During the deposition process, the process chamber can be maintained at a temperature of between about 25 degrees Celsius and 400 degrees Celsius.

[0048] Referring to FIG. 3E, in an alternate implementation, the sacrificial capping layer 340 also fills the inner cavity 330A-C. Thus, the sacrificial capping layer 340 also forms the first inner spacer 332A-C upon removal of the sacrificial capping layer 340.PATENTAttorney Docket No.: 44025376WO01In implementations where the sacrificial capping layer 340 forms the first inner spacer 332A-C, operation 230 of the method 200 is not performed. For example, the inner cavity recess process of operation 220 is performed as shown in FIG. 3B followed by the formation of the sacrificial capping layer 340 which also fills the inner cavity 330A-C at operation 240 as is shown in FIG. 3E.

[0049] Referring to FIG. 3F, at operation 250, the sacrificial capping layer 340 is planarized. Any suitable planarization process may be used. The planarization process may be a chemical mechanical polishing (CMP) process or an etchback process. In one or more implementations, the planarization process of operation 250 exposes the top surface 322t of the dummy gate 322 allowing for subsequent removal of the dummy gate 322.

[0050] Referring to FIG. 3G, at operation 260, the dummy gate 322 and the first semiconductor layers 310A-C are selectively removed from the semiconductor device structure 300. The dummy gate 322 and the first semiconductor layers 31 OA-c can be removed using a wet selective etch process or a dry selective etch process. The dummy gate 322 is removed to form a first recess 360. In one or more implementations, in which the dummy gate 322 is polysilicon, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NF OH), or the like may be used to remove the dummy gate 322. The first semiconductor layer 310A-C are selectively removed to form recesses 362A-C which expose the first inner spacers 332A-C. In one or more implementations, in which the first semiconductor layer 310A-C includes SiGe and the second semiconductor layers 312A-C include Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove first semiconductor layer 310A-C in the n-type region. In one or more implementations, in which the second semiconductor layer 312A-C includes SiGe and the first semiconductor layers 310A-C includes Si or SiC, hydrogen fluoride, another fluoride-based etchant, or the like may be used to remove the first semiconductor layer 310A-C. In one or more implementations, the dummy gate dielectric layer 324 is selectively removed during operation 260 to expose the top surface of the second semiconductor layer 312C.PATENTAttorney Docket No.: 44025376WO01

[0051] Referring to FIG. 3H, at operation 270, the replacement gate metals are deposited in order to form the metal gate stack. As shown in FIG. 3H, gate dielectric layers 370 and gate electrodes 372 are formed for the replacement gates. The gate dielectric layers 370 are deposited conformally in the first recess 360. In the n-type region, the gate dielectric layers 370 may be formed on top surfaces and sidewalls of the semiconductor device structure 300, on top surfaces, sidewalls, and bottom surfaces of the second semiconductor layers 312A-C, and sidewalls of the first inner spacers 332A-C exposed by the second recesses 362A-C.

[0052] In one or more implementations, the gate dielectric layers 370 include one or more dielectric layers, such as an oxide, a metal oxide, the like, or a combination thereof. For example, in some implementations, the gate dielectrics include a silicon oxide layer and a metal oxide layer formed over the silicon oxide layer. In some implementations, the gate dielectric layers 370 include a high-k dielectric material, and in these implementations, the gate dielectric layers 370 may have a k-value greater than about 7.0, and may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or a combination thereof. The structure of the gate dielectric layers 370 may be the same or different in the n-type region and the p-type region. The formation methods of the gate dielectric layers 370 may include molecular-beam deposition (MBD), ALD, PECVD, and the like.

[0053] The gate electrodes 372 are deposited over the gate dielectric layers 370, respectively, and fill the remaining portions of the first recess 360 and the second recesses 362A-C. In one or more implementations, the gate electrodes 372 includes a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although single layer gate electrodes 372 are illustrated in FIG. 3H, the gate electrodes 372 may include any number of liner layers, any number of work function tuning layers, and a fill material. Any combination of the layers which make up the gate electrodes 372 may be deposited in the n-type region between adjacent ones of the second semiconductor layers 312A-C and between the second semiconductor layers 312A-C and the substrate 306.PATENTAttorney Docket No.: 44025376WO01

[0054] The formation of the gate dielectric layers 370 in the n-type region and the p-type region may occur simultaneously such that the gate dielectric layers 370 in each region are formed from the same materials, and the formation of the gate electrodes 372 may occur simultaneously such that the gate electrodes 372 in each region are formed from the same materials. In some implementations, the gate dielectric layers 370 in each region may be formed by distinct processes, such that the gate dielectric layers 370 may be different materials and / or have a different number of layers, and / or the gate electrodes 372 in each region may be formed by distinct processes, such that the gate electrodes 372 may be different materials and / or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.

[0055] After the filling of the first recess 360, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers 370 and the material of the gate electrodes 372. The remaining portions of material of the gate electrodes 372 and the gate dielectric layers 370 thus form replacement gate structures of the resulting nano-FETs. The gate electrodes 372 and the gate dielectric layers 370 may be collectively referred to as “gate structures.”

[0056] In one or more implementations, the gate structure filling the first recess 360 (including the gate dielectric layers 370 and the corresponding overlying gate electrodes 372) is recessed, so that a recess is formed directly over the gate structure and between opposing portions of the one or more spacers 326. A gate mask 374 including one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, and optionally followed by a planarization process to remove excess portions of the dielectric material. The formation methods of the gate mask 374 may include molecular-beam deposition (MBD), ALD, PECVD, and the like.

[0057] In one or more implementations, the gate structure filling the second recesses 362A-C (including the gate dielectric layers 370 and the corresponding overlying gate electrodes 372) is recessed, so that sidewall recesses are formed along the side of the gate structure formed in the second recesses 362A-C and between opposing portions of the second semiconductor layers 312A-C which are formedPATENTAttorney Docket No.: 44025376WO01adjacent to each other. As shown in FIG. 3H, first outer spacers 376A-C are formed in the sidewall recesses. The first outer spacers 376A-C may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The first outer spacers 376A-C may include a material such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. In one or more implementations, the first outer spacers 376A-C are formed from the same material as the first inner spacers 332A-C.

[0058] Referring to FIG. 3I, at operation 280, the sacrificial capping layer 340 is removed to expose the source / drain cavity 308. Removing the sacrificial capping layer 340 exposes the sidewalls 308s and the bottom surface 308b of the source / drain cavity 308. Any removal process suitable form removed the sacrificial capping layer 340 without damaging the semiconductor device structure 300 may be used. The sacrificial capping layer 340 can be removed using a wet selective etch process or a dry selective etch process. Any suitable selective etch process may be used. In one or more implementations, a selective wet etch process is used and includes diluted HF and / or SC1 chemistries.

[0059] Referring to FIG. 3J, at operation 290, a source / drain region 380 is formed in the source / drain cavity 308. The source / drain region 380 fills the source / drain cavity 308 in between the first semiconductor region 302 and the second semiconductor region 304. In at least one implementation, as shown in FIG. 3J, the source / drain region 380 contacts the sidewalls 308s of the first and second semiconductor regions 302, 304 including the first inner spacers 332A-C and the second semiconductor layers 312A-C.

[0060] The source / drain region 380 may be formed via an epitaxial deposition process. The use of an epitaxially grown material in the source / drain region 380 allows the source / drain region 380 to exert stress in the channel regions. The materials used for the source / drain region 380 may be varied for the n-type and p-type nano-FETs, such that one type of material is used for the n-type nano-FETs to exert a tensile stress in the channel region and another type of material for the p-type nano-FETs to exert a compressive stress. For example, SiP or SiC may be used to form n-type nano-FETsPATENTAttorney Docket No.: 44025376WO01and SiGe or Ge may be used to form p-type nano-FETs. However, any suitable material may be used. The source / drain region 380 may be doped either through an implanting process to implant appropriate dopants, or by in-situ doping as the material is grown. In some implementations, the source / drain region 380 is formed of SiC or SiP doped with phosphorus (P) to form an n-type nano-FET device. In other implementations, the source / drain region 380 is formed of SiGe or Ge doped with boron (B) to form a p-type nano-FET device.

[0061] In one or more implementations where the source / drain region 380 includes an Si P film, the Si P films is formed at a pressure in a range from about 200 Torr to about 400 Torr by flowing dichlorosilane and phosphine gases for the deposition process followed by an etchback process using for example, HCI, to achieve selectivity. The deposition and etchback processes may be cycled to form the source / drain region 380.

[0062] FIG. 4 illustrates a plan view of a cluster tool 400 in accordance with one or more implementations of the present disclosure. The cluster tool 400 may be used to perform various operations of the method 200. The cluster tool 400 features at least one material deposition chamber, for example, a plasma-enhanced chemical vapor deposition (PECVD) chamber and optionally an epitaxial deposition chamber. The epitaxial deposition chamber may be a plasma-enhanced epitaxial deposition chamber. One example of the cluster tool 400 is the CENTURA® EPI system available from Applied Materials, Inc., of Santa Clara, California. Cluster tools manufactured by others may be used as well. A transfer robot 404 of any convenient type is disposed in a transfer chamber 402 of the cluster tool 400. A load-lock 406, with two load-lock chambers 406A, 406B is coupled to the transfer chamber 402. A plurality of processing chambers 408, 410, 412, 414, and 416 are also coupled to the transfer chamber 402. In at least one aspect, the plurality of processing chambers 408, 410, 412, 414, and 416 includes at least one of a pre-clean chamber, a material deposition chamber such as an epitaxial deposition chamber, a plasma-enhanced chemical vapor deposition chamber, and a thermal processing chamber, such as an anneal, degas, or oxidation chamber.PATENTAttorney Docket No.: 44025376WO01

[0063] Processing chamber 408 may be a pre-clean chamber configured to clean the substrate prior to material deposition of materials, for example, a sacrificial capping layer, a source / drain material, or a superlattice structure. The pre-clean chamber may be configured to perform the Applied Materials SICON I™ Pre-clean process. Processing chamber 410 and / or 414 may be a material deposition chamber such as an epitaxial deposition chamber capable of performing an epitaxial growth process or a plasma-enhanced chemical vapor deposition process. Processing chamber 412 and / or 416 may be an additional material deposition chamber or a thermal treatment chamber capable of performing a thermal treatment process.

[0064] A system controller 457 is in communication with the transfer robot 404, and the plurality of processing chambers 408, 410, 412, 414, and 416. The system controller 457 can be any suitable component that can control the processing chambers and robots. For example, the system controller 457 can be a computer including a central processing unit (CPU) 492, memory 494, inputs / outputs 496, suitable circuits 498, and storage.

[0065] Processes, for example, one or more of operations 210-290, may generally be stored in the memory of the system controller 457 as a software routine that, when executed by the processor, causes the process chamber to perform processes of the present disclosure. The software routine may be stored and / or executed by a second processor (not shown) that is remotely located from the hardware being controlled by the processor. Some or all of the method of the present disclosure may also be performed in hardware. As such, the process may be implemented in software and executed using a computer system, in hardware as, for example, an application specific integrated circuit or other type of hardware embodiment, or as a combination of software and hardware. The software routine, when executed by the processor, transforms the general-purpose computer into a specific purpose computer (controller) that controls the chamber operation such that the processes are performed.

[0066] In at least one implementation, the system controller 457 has a configuration to control the epitaxial growth chamber to grow epitaxial materials, for example, one or more of the first semiconductor layers 310A-C, the second semiconductor layers 312A-C, and the source / drain region 380.PATENTAttorney Docket No.: 44025376WO01

[0067] The cluster tool 400 may be used to perform at least portions of the method 200 described above. During processing, a substrate that is to be processed may arrive at the cluster tool 400 in a pod (not shown). The substrate is transferred from the pod to the vacuum compatible load-lock chambers 406A, 406B by the factory interface robot (not shown). The substrate is then picked by the transfer robot 404 in the transfer chamber 402, which is generally kept in a vacuum state. The transfer robot 404 then loads the substrate into the processing chamber 408 for cleaning. The transfer robot 404 then picks up the substrate from the processing chamber 408 and loads the substrate into the processing chamber 410 or 414, whichever is available, for epitaxial deposition. Epitaxial materials as described may be grown on the cleaned substrate in the processing chamber 410 or 414. The transfer robot 404 then picks up the substrate from the processing chamber 410 or 414 and transfers the substrate into the processing chamber 412 or 416, which are thermal processing chambers, whichever is available. The epitaxial materials may then be exposed to a rapid heating / cooling process. The transfer robot 404 then picks the substrate from the processing chamber 412 or 416 and transfers the substrate to processing chamber 414 for deposition of additional materials over the epitaxial materials.

[0068] The previously described implementations of the present disclosure have many advantages. In one or more implementations of the present disclosure, the replacement metal gate (RMG) process is performed prior to deposition of the epitaxial source / drain material, for example, while the source / drain cavity is empty and protected by a sacrificial capping layer. Thus, the tensile strain in the channel can be conserved by the RMG metals and the strain will be present even after epitaxial growth of the source / drain material. In addition, the sacrificial capping layer is removable without damaging the underlying structure. However, the present disclosure does not necessitate that all the advantageous features and all the advantages need to be incorporated into every implementation of the present disclosure.

[0069] In the Summary and in the Detailed Description, and the claims, and in the accompanying drawings, reference is made to particular features (including method operations) of the present disclosure. It is to be understood that the disclosure in this specification includes all possible combinations of such particular features. ForPATENTAttorney Docket No.: 44025376WO01example, where a particular feature is disclosed in the context of a particular aspect or implementation of the present disclosure, or a particular claim, that feature can also be used, to the extent possible in combination with and / or in the context of other particular aspects and implementations of the present disclosure, and in the present disclosure generally.

[0070] Implementations and all of the functional operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structural means disclosed in this specification and structural equivalents thereof, or in combinations of them. Implementations described herein can be implemented as one or more non-transitory computer program products, i.e., one or more computer programs tangibly embodied in a machine readable storage device, for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple processors or computers.

[0071] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0072] The term "data processing apparatus" encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer.PATENTAttorney Docket No.: 44025376WO01

[0073] Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0074] The term “comprises,” “including,” and “having” and grammatical equivalents thereof are used herein to mean that other components, ingredients, operations, etc. are optionally present. For example, an article “comprising” (or “which comprises”) components A, B, and C can consist of (i.e. , contain only) components A, B, and C, or can contain not only components A, B, and C but also one or more other components. In addition, whenever a composition, an element or a group of elements is preceded with the transitional phrase “comprising” or grammatical equivalents thereof, it is understood that it is contemplated that the same composition or group of elements may be preceded with transitional phrases “consisting essentially of,” “consisting of,” “selected from the group of consisting of,” or “is” preceding the recitation of the composition, element, or elements and vice versa.

[0075] Where reference is made herein to a method comprising two or more defined operations, the defined operations can be carried out in any order or simultaneously (except where the context excludes that possibility), and the method can include one or more other operations which are carried out before any of the defined operations, between two of the defined operations, or after all of the defined operations (except where the context excludes that possibility).

[0076] When introducing elements of the present disclosure or exemplary aspects or implementation(s) thereof, the articles “a,” “an,” “the” and “said” are intended to mean that there are one or more of the elements.

[0077] While the foregoing is directed to implementations of the present disclosure, other and further implementations of the disclosure may be devised without departingPATENTAttorney Docket No.: 44025376WO01from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

PATENTAttorney Docket No.: 44025376WO01What is claimed is:

1. A method of forming a semiconductor device, comprising:forming a sacrificial capping layer over a source / drain cavity, the source / drain cavity defined by a pair of opposing sidewalls, the sidewalls each defined by alternating pairs of a first semiconductor layer and a second semiconductor layer, the sacrificial capping layer defining an air gap in between the opposing sidewalls and at least a portion of the sacrificial capping layer covers the air gap;performing a replacement metal gate process; andremoving the sacrificial capping layer to expose the source / drain cavity, wherein the sacrificial capping layer keeps the source / drain cavity free from deposition during the replacement metal gate process.

2. The method of claim 1 , further comprising:forming a source / drain material in the source / drain cavity after removing the sacrificial capping layer.

3. The method of claim 1, wherein each sidewall is further defined by a dummy gate structure formed over the alternating pairs of the first semiconductor layer and the second semiconductor layer.

4. The method of claim 3, wherein the sacrificial capping layer has a first thickness along a top surface of the dummy gate structure and a second thickness along the sidewalls, the first thickness being greater than the second thickness.

5. The method of claim 1, wherein the sacrificial capping layer is a silicon-containing low-k dielectric material.

6. The method of claim 5, wherein the silicon-containing low-k dielectric material is silicon oxide, silicon carbonitride, or a combination thereof.

7. The method of claim 1, wherein forming the sacrificial capping layer is performed by a plasma enhanced chemical vapor deposition process.PATENTAttorney Docket No.: 44025376WO018. The method of claim 1 , wherein the replacement metal gate process comprises:removing the first semiconductor layers to form recesses between the second semiconductor layers; andfilling the recesses with a metal gate material.

9. A method of forming a semiconductor device, comprising:forming a sacrificial capping layer over a source / drain cavity, the source / drain cavity defined by a pair of opposing sidewalls, the sidewalls each defined by a dummy gate formed over alternating pairs of a first semiconductor layer and a second semiconductor layer, the sacrificial capping layer coating a top surface of the dummy gate and the sidewalls, the sacrificial capping layer defining an air gap in between the opposing sidewalls and at least a portion of the sacrificial capping layer covers the air gap;removing the sacrificial capping layer coating the top surface of the dummy gate;selectively removing the dummy gate and the first semiconductor layers; performing a replacement metal gate process;removing the sacrificial capping layer to expose the source / drain cavity; and forming an epitaxial source / drain material in the source / drain cavity.

10. The method of claim 9, wherein the sacrificial capping layer keeps the source / drain cavity free from deposition during the replacement metal gate process.

11. The method of claim 9, further comprising:removing a portion of the first semiconductor layer forming a sidewall recess prior to forming the sacrificial capping layer.

12. The method of claim 11, further comprising forming an inner spacer in the sidewall recess.PATENTAttorney Docket No.: 44025376WO0113. The method of claim 11, wherein the sacrificial capping layer fills the sidewall recess.

14. The method of claim 13, wherein removing the sacrificial capping layer to expose the source / drain cavity forms an inner spacer in the sidewall recesses.

15. The method of claim 9, wherein the sacrificial capping layer is a silicon-containing low-k dielectric material.

16. The method of claim 15, wherein the silicon-containing low-k dielectric material is silicon oxide, silicon carbonitride, or a combination thereof.

17. A method of forming a semiconductor device, comprising:forming a first fin structure and a second fin structure on a substrate, wherein the first fin structure and the second fin structure each comprise alternating pairs of a first semiconductor layer and a second semiconductor layer, opposing sidewalls of the first fin structure and the second fin structure defining a source / drain cavity in between the first fin structure and the second fin structure;forming a sacrificial capping layer over the source / drain cavity, the source / drain cavity defined by a pair of opposing sidewalls, the sacrificial capping layer coating a top surface of the first fin structure, a top surface of the second fin structure and the sidewalls defining the source / drain cavity, the sacrificial capping layer defining an air gap in between the opposing sidewalls and at least a portion of the sacrificial capping layer covers the air gap;removing the first semiconductor layers to form recesses between the second semiconductor layers;filling the recesses with a metal gate material;removing the sacrificial capping layer to expose the source / drain cavity after filling the recesses with the metal gate material; andforming an epitaxial source / drain material in the source / drain cavity.PATENTAttorney Docket No.: 44025376WO0118. The method of claim 17, wherein the sacrificial capping layer is a silicon-containing low-k dielectric material.

19. The method of claim 17, wherein the sacrificial capping layer has a first thickness along the top surface of the first fin structure and the top surface of the second fin structure, and a second thickness along the sidewalls, the first thickness being greater than the second thickness.

20. The method of claim 17, wherein the first semiconductor layer is silicon germanium, the second semiconductor layer is silicon, and the sacrificial capping layer is silicon oxide.

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