Transistor, semiconductor device and manufacturing method therefor, and electronic device

Abstract

A transistor, a semiconductor device and a manufacturing method therefor, and an electronic device, which relate to the technical field of semiconductors. The transistor comprises: a first electrode (P1) and a second electrode (P2), which are located on a substrate (10); a first semiconductor layer (C1), which is located between the first electrode (P1) and the second electrode (P2); a first gate insulating layer (21); and a first gate electrode (G1), wherein the first electrode (P1) and the second electrode (P2) are spaced apart from each other in a column direction parallel to the substrate (10); the first gate electrode (G1) extends in a row direction parallel to the substrate (10), and the first gate electrode (G1) comprises sidewalls, which extend in the row direction, and a first end surface and a second end surface, which are spaced apart from each other in the row direction; the first electrode (P1) and the second electrode (P2) are located on the sidewalls of the first gate electrode (G1); the first end surface is used for connecting to a word line (WL); and the second end surface and the sidewalls, on which the first electrode (P1) and the second electrode (P2) are arranged, are surrounded by the first semiconductor layer (C1).

Description

Transistors, semiconductor devices and their manufacturing methods, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 2025100722078, filed on January 16, 2025, entitled "Transistor, Semiconductor Device and Method of Manufacturing Thereof, Electronic Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more particularly to a transistor, a semiconductor device, a method for manufacturing the same, and an electronic device. Background Technology

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0004] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0006] This application provides a transistor, which includes: a first electrode and a second electrode located on a substrate, a first semiconductor layer located between the first electrode and the second electrode, a first gate insulating layer, and a first gate electrode;

[0007] The first electrode and the second electrode are spaced apart in a column direction parallel to the substrate;

[0008] The first gate electrode extends along a row direction parallel to the substrate. The first gate electrode includes a sidewall extending along the row direction and a first end face and a second end face spaced apart in the row direction. The first electrode and the second electrode are located on the sidewall of the first gate electrode. The first end face is used to connect with a word line. The second end face and the sidewall on which the first electrode and the second electrode are disposed are surrounded by the first semiconductor layer.

[0009] In some embodiments of this application, the first semiconductor layer includes a first wall, a second wall, and a third wall located between the first wall and the second wall; the first wall and the second wall both extend along the row direction, and the third wall extends along the column direction;

[0010] The first wall, the second wall, and the third wall all surround the first gate electrode;

[0011] The first electrode is located on the first wall, and the second electrode is located on the second wall.

[0012] In some embodiments of this application, the sidewalls of the first gate electrode include opposing first and second sidewalls, as well as opposing third and fourth sidewalls;

[0013] The first wall surrounds the first sidewall, and the second wall surrounds the second sidewall; the first semiconductor layer is exposed to the third and fourth sidewalls.

[0014] In some embodiments of this application, the transistor further includes a second gate electrode located on the side of the second end face away from the first end face, the first semiconductor layer being located between the second gate electrode and the first gate electrode, and a second gate insulating layer being present between the first semiconductor layer and the second gate electrode.

[0015] This application also provides a semiconductor device, the semiconductor device comprising: a plurality of memory cells located on a substrate; the plurality of memory cells being located on different layers and spaced apart along a direction perpendicular to the substrate;

[0016] The storage unit includes a read transistor and a write transistor; the read transistor is the transistor described above.

[0017] In some embodiments of this application, the semiconductor device further includes a read word line, a read bit line, a write word line, and a write bit line; the read word line is connected to a first end face of the first gate electrode, the read bit line is connected to the second electrode, and both the write word line and the write bit line are connected to the write transistor;

[0018] Both the read line and the write line extend along the column direction; both the read bit line and the write bit line extend in a direction perpendicular to the substrate.

[0019] In some embodiments of this application, the write transistor includes a third electrode and a fourth electrode, a second semiconductor layer located between the third electrode and the fourth electrode, a third gate insulating layer, and a third gate electrode;

[0020] Both the second semiconductor layer and the third gate electrode extend along the row direction, and the second semiconductor layer at least partially surrounds the third gate electrode;

[0021] The third gate electrode is connected to the write word line; the fourth electrode is connected to the write bit line.

[0022] In some embodiments of this application, at least a portion of the sidewalls of the second semiconductor layer are surrounded by an etch barrier layer; and / or,

[0023] At least a portion of the sidewalls of the writing line are surrounded by an etched barrier layer.

[0024] In some embodiments of this application, the second semiconductor layer is a cylindrical structure closed at one end and open at the other end, and the third gate electrode extends into the interior of the cylindrical structure of the second semiconductor layer through the opening.

[0025] In some embodiments of this application, the storage unit further includes a storage node, which is connected to the read transistor and the write transistor, respectively;

[0026] The storage node and the third electrode are integrated into one unit.

[0027] In some embodiments of this application, the write bit line includes a first sub-write bit line and a second sub-write bit line, wherein one end of the first sub-write bit line and the second sub-write bit line are connected and the other end is spaced apart;

[0028] One end of the first sub-write bit line and the second sub-write bit line, which are spaced apart, is connected to the sidewall of the second semiconductor layer.

[0029] In some embodiments of this application, the read word line is connected to the first gate electrode of a column of memory cells spaced apart along the column direction; and / or,

[0030] The read bit line is connected to the second electrode of a plurality of memory cells spaced apart along a direction perpendicular to the substrate; and / or,

[0031] The write lines are connected to the third gate electrodes of a column of memory cells spaced apart along the column direction; and / or,

[0032] The write bit line is connected to the fourth electrode of a plurality of memory cells spaced apart along a direction perpendicular to the substrate; and / or,

[0033] The second electrode and the read line are integrally formed; and / or,

[0034] The fourth electrode and the write bit line are an integral structure.

[0035] This application also provides a method for manufacturing a semiconductor device, the method comprising:

[0036] An insulating layer and a sacrificial layer are alternately formed sequentially on a substrate to obtain a stacked structure;

[0037] In the stacked structure, a plurality of isolation holes are formed extending in a direction toward the substrate; the plurality of isolation holes are spaced apart in a column direction parallel to the substrate; the isolation holes include read regions and write regions distributed in a row direction parallel to the substrate;

[0038] An etch barrier layer and a first isolation layer are sequentially formed within the isolation hole;

[0039] Remove the sacrificial layer surrounding the read tube area to obtain a first channel groove located between two adjacent isolation holes;

[0040] A first semiconductor layer, a first gate insulating layer, and a first gate electrode are sequentially formed within the first channel trench;

[0041] The etching barrier layer and the first isolation layer of the read tube region are etched to form a first through-hole that penetrates the read tube region. Two adjacent first through-holes expose the two sidewalls of the first semiconductor layer distributed along the column direction.

[0042] A first electrode and a second electrode are respectively formed in two adjacent first through holes, located on the two sidewalls of the same first semiconductor layer distributed along the column direction;

[0043] Remove the insulating layer located on the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, exposing the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate;

[0044] Remove the exposed areas of the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate.

[0045] In some embodiments of this application, removing the sacrificial layer surrounding the read tube region to obtain a first channel groove located between two adjacent isolation holes includes:

[0046] The stacked structure located on the side of the read region away from the write region is etched along the direction toward the substrate to form a first trench that penetrates the stacked structure and extends along the column direction, the first trench exposing each of the sacrificial layers of the stacked structure;

[0047] The exposed sacrificial layers are laterally etched within the first trench to obtain the first channel trench and read word line trench located between two adjacent insulating layers; the first channel trench is located between two adjacent isolation holes, and the read word line trench is located on the side of the read tube area away from the write tube area and extends along the column direction.

[0048] In some embodiments of this application, the step of sequentially forming a first semiconductor layer, a first gate insulating layer, and a first gate electrode within the first channel trench includes:

[0049] A first semiconductor layer and a first gate insulating layer are sequentially formed in each of the first trenches, covering one end face of the read region away from the write region. The first semiconductor layers in each of the first trenches are connected to each other, and the first gate insulating layers in each of the first trenches are connected to each other.

[0050] Remove at least a portion of the first semiconductor layer and the first gate insulating layer located on the end face of the read tube region away from the write tube region, and disconnect the first semiconductor layer and the first gate insulating layer located in different first channel trenches;

[0051] The first gate electrode is formed in each of the first channel slots and the reading line is formed in the reading line slot, which is connected to the first gate electrode;

[0052] The first trench is filled with insulating material.

[0053] In some embodiments of this application, forming first and second electrodes on the sidewalls of the same first semiconductor layer distributed along the column direction within two adjacent first vias includes:

[0054] A first electrode layer is formed on the sidewall of the first through hole, and a second isolation layer is filled inside the first through hole;

[0055] The first isolation layer on both sides of the first via distributed along the row direction is etched along the direction toward the substrate, and a first opening penetrating the read tube region in the direction toward the substrate is formed on both sides of the first via distributed along the row direction, and the first opening exposes the first electrode layer.

[0056] The exposed first electrode layer is etched within the first opening, dividing the first electrode layer within the same first via into two portions located on the sidewalls of two adjacent first semiconductor layers. One portion of the first electrode layer includes a plurality of first electrodes distributed and connected along a direction perpendicular to the substrate, and the other portion of the first electrode layer includes a plurality of second electrodes distributed and connected along a direction perpendicular to the substrate. The first electrode and the second electrode formed by the first electrode layer within the same first via are each part of the read transistor of two adjacent memory cells. The plurality of connected second electrodes form a read bit line.

[0057] Fill the first opening with insulating material.

[0058] In some embodiments of this application, removing the insulating layer located on the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, thereby exposing the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, includes:

[0059] Remove the insulating material from the first trench to expose the first trench, thus exposing the insulating layer.

[0060] Laterally etch the exposed insulating layer within the first trench to remove the insulating layer surrounding the read tube region and the insulating layer located on the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, thereby exposing the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate.

[0061] In some embodiments of this application, the manufacturing method further includes: after forming the first isolation layer within the isolation hole, and before removing the sacrificial layer surrounding the read tube region,

[0062] The etching barrier layer and the first isolation layer of the write tube region are etched to form a second via through the write tube region. The second via penetrates the etching barrier layer in the column direction.

[0063] A second electrode layer is formed on the sidewall of the second through hole, and a second isolation layer is filled inside the second through hole;

[0064] The etching barrier layer and the first isolation layer on both sides of the second via distributed along the row direction are etched along the direction toward the substrate. Second openings penetrating the write tube region in the direction toward the substrate are formed on both sides of the second via distributed along the row direction. The second openings expose the second electrode layer.

[0065] The exposed second electrode layer is etched within the second opening, dividing the second electrode layer within the same second via into two parts distributed along the column direction. One part of the second electrode layer is a first sub-write bit line, and the other part of the second electrode layer is a second sub-write bit line. The first sub-write bit line and the second sub-write bit line formed by the second electrode layer within the same second via are each part of the write bit line of two adjacent memory cells. The second sub-write bit line includes a plurality of fourth electrodes distributed and connected along a direction perpendicular to the substrate.

[0066] In some embodiments of this application, the manufacturing method further includes: after removing exposed areas from the upper and lower surfaces of the first semiconductor layer distributed along a direction perpendicular to the substrate,

[0067] The stacked structure located on the side of the write region away from the read region is etched along the direction toward the substrate to form a second trench that penetrates the stacked structure and extends along the column direction, the second trench exposing each of the sacrificial layers of the stacked structure;

[0068] Laterally etch each of the exposed sacrificial layers in the second trench to obtain a second channel trench and a write line trench located between two adjacent insulating layers; the second channel trench is located between two adjacent isolation holes, and the second channel trench exposes the first semiconductor layer; the write line trench is located on the side of the write tube region away from the read tube region and extends along the column direction;

[0069] A second insulating layer and a second gate electrode are sequentially formed at one end of the second channel groove near the read tube area;

[0070] A second semiconductor layer, a third gate insulating layer, and a third gate electrode are sequentially formed in the remaining region of the second trench.

[0071] Writing lines are formed in the writing line groove, and insulating material is filled into the second groove.

[0072] In some embodiments of this application, the step of sequentially forming a second insulating layer and a second gate electrode at one end of the second channel trench near the read region includes:

[0073] A second gate insulating layer and a second gate electrode are sequentially formed in each of the second channel trenches, covering one end face of the write tube region away from the read tube region. The second insulating layers in each of the second channel trenches are connected to each other, and the second gate electrodes in each of the second channel trenches are connected to each other.

[0074] The second gate insulating layer and the second gate electrode in the second channel trench are etched back to disconnect the second gate insulating layer and the second gate electrode located in different second channel trenches.

[0075] In some embodiments of this application, the step of sequentially forming a second semiconductor layer, a third gate insulating layer, and a third gate electrode in the remaining region of the second trench includes:

[0076] A second semiconductor layer, a third gate insulating layer, and a third gate electrode are sequentially formed in each of the second channel trenches, covering one end face of the write region away from the read region. The second semiconductor layers in each of the second channel trenches are connected to each other, the third gate insulating layers in each of the second channel trenches are connected to each other, and the third gate electrodes in each of the second channel trenches are connected to each other.

[0077] At least a portion of the second semiconductor layer, the third gate insulating layer, and the third gate electrode located on the end face of the write region away from the read region are removed, and the second semiconductor layer, the third gate insulating layer, and the third gate electrode located in different second channel trenches are disconnected.

[0078] This application also provides an electronic device, which includes the transistor or semiconductor device described above, or a semiconductor device obtained by the manufacturing method described above.

[0079] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0080] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0081] Overview of the attached figures

[0082] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0083] Figure 1A is a three-dimensional structural schematic diagram of a transistor according to an exemplary embodiment of this application;

[0084] Figure 1B is a cross-sectional view of the transistor shown in Figure 1A on a section parallel to the substrate;

[0085] Figure 2A is a three-dimensional structural diagram of a memory cell of a semiconductor device according to an exemplary embodiment of this application;

[0086] Figure 2B is a top view of the semiconductor device shown in Figure 2A;

[0087] Figure 2C is a schematic diagram of the longitudinal section of the semiconductor device shown in Figure 2A on the section aa' perpendicular to the substrate;

[0088] Figure 2D is a schematic diagram of the longitudinal section of the semiconductor device shown in Figure 2A on the section perpendicular to the substrate bb'.

[0089] Figure 2E is a schematic diagram of the longitudinal section of the semiconductor device shown in Figure 2A on the cc' section perpendicular to the substrate;

[0090] Figure 2F is a schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in Figure 2A on the dd' section perpendicular to the substrate;

[0091] Figure 3 is a process flow diagram of a semiconductor device manufacturing method according to an exemplary embodiment of this application;

[0092] Figure 4A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after forming a stacked structure;

[0093] Figure 4B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 4A on the section aa' perpendicular to the substrate;

[0094] Figure 4C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 4A on the cc' section perpendicular to the substrate;

[0095] Figure 5A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the isolation hole is filled with a first isolation layer;

[0096] Figure 5B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 5A on the section perpendicular to the substrate bb'.

[0097] Figure 5C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 5A on the cc' section perpendicular to the substrate;

[0098] Figure 6A is a top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application, after the second isolation layer is filled into the first through-hole;

[0099] Figure 6B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 6A on the section perpendicular to the substrate bb'.

[0100] Figure 6C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 6A on the dd' section perpendicular to the substrate;

[0101] Figure 7A is a top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application, after the second opening and the second through hole are filled with a second isolation layer;

[0102] Figure 7B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 7A on the section perpendicular to the substrate bb'.

[0103] Figure 8A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after the formation of a first channel trench;

[0104] Figure 8B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 8A on the section aa' perpendicular to the substrate;

[0105] Figure 8C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 8A on the section perpendicular to the substrate bb'.

[0106] Figure 8D is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 8A on the cc' section perpendicular to the substrate;

[0107] Figure 9A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after forming the readout lines;

[0108] Figure 9B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 9A on the section aa' perpendicular to the substrate;

[0109] Figure 9C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 9A on the section perpendicular to the substrate bb'.

[0110] Figure 9D is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 9A on the cc' section perpendicular to the substrate;

[0111] Figure 10A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after the formation of the first electrode layer;

[0112] Figure 10B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 10A on the section perpendicular to the substrate bb'.

[0113] Figure 10C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 10A on the cc' section perpendicular to the substrate;

[0114] Figure 11A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after forming read lines;

[0115] Figure 11B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 11A on the section perpendicular to the substrate bb'.

[0116] Figure 12A is a top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application, after exposing the upper and lower surfaces of the first semiconductor layer;

[0117] Figure 12B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 12A on the section aa' perpendicular to the substrate;

[0118] Figure 12C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 12A on the section perpendicular to the substrate bb'.

[0119] Figure 12D is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 12A on the cc' section perpendicular to the substrate;

[0120] Figure 13A is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application after removing the exposed area of ​​the first semiconductor layer, on a section perpendicular to the substrate aa'.

[0121] Figure 13B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 13A on the cc' section perpendicular to the substrate;

[0122] Figure 14A is a top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application, after exposing the upper and lower surfaces of the first semiconductor layer;

[0123] Figure 14B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 14A on the section perpendicular to the substrate aa'.

[0124] Figure 14C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 14A on the section perpendicular to the substrate bb'.

[0125] Figure 14D is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 14A on the cc' section perpendicular to the substrate;

[0126] Figure 15A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after forming a second channel trench writing line groove;

[0127] Figure 15B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 15A on the section perpendicular to the substrate aa'.

[0128] Figure 15C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 15A on the section perpendicular to the substrate bb'.

[0129] Figure 15D is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 15A on the dd' section perpendicular to the substrate.

[0130] Detailed Explanation

[0131] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0132] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0133] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0134] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0135] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0136] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0137] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0138] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0139] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0140] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0141] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the drawings.

[0142] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.

[0143] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0144] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0145] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0146] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0147] In this application, "film" and "layer" can be interchanged. For example, "semiconductor layer" can sometimes be replaced with "semiconductor film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0148] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0149] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functional circuits are already distributed. The devices involved in the inventive construction of the embodiments of this application are disposed on the main surface of the support structure.

[0150] In this application, the spacing distribution can be understood as a separate, independent distribution. This spacing can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors can be modified to achieve insulation, thus creating an electrical gap between the two channels.

[0151] This application provides a transistor. FIG1A is a three-dimensional structural schematic diagram of a transistor according to an exemplary embodiment of this application; FIG1B is a cross-sectional view of the transistor shown in FIG1A on a section parallel to the substrate.

[0152] As shown in Figures 1A and 1B, the transistor includes: a first electrode P1 and a second electrode P2 located on a substrate, a first semiconductor layer C1 located between the first electrode P1 and the second electrode P2, a first gate insulating layer 21, and a first gate electrode G1.

[0153] The first electrode P1 and the second electrode P2 are spaced apart in a column direction parallel to the substrate;

[0154] The first gate electrode G1 extends along a row direction parallel to the substrate. The first gate electrode G1 includes a sidewall extending along the row direction and a first end face and a second end face spaced apart in the row direction. The first electrode P1 and the second electrode P2 are located on the sidewall of the first gate electrode G1. The first end face is used to connect with the word line WL. The second end face and the sidewall on which the first electrode P1 and the second electrode P2 are disposed are surrounded by a first semiconductor layer C1.

[0155] The transistors in this embodiment have a simple manufacturing process. The gate length of the first gate electrode can be adjusted by adjusting the extension length of the sidewall of the first semiconductor layer C1, and the gate width of the first gate electrode can be adjusted by adjusting the distance between the sidewalls of the first semiconductor layer C1. The gate length and gate width of the first gate electrode are easy to control.

[0156] In this application, the row direction intersects the column direction; for example, the row direction and the column direction can be perpendicular to each other. For example, the row direction can be the X direction as shown in Figure 1B; the column direction can be the Y direction as shown in Figure 1B.

[0157] In some embodiments of this application, as shown in Figures 1A and 1B, the first semiconductor layer C1 includes a first wall C11, a second wall C12, and a third wall C13 located between the first wall C11 and the second wall C12; the first wall C11 and the second wall C12 both extend along the row direction, and the third wall C13 extends along the column direction.

[0158] The first wall C11, the second wall C12 and the third wall C13 all surround the first gate electrode G1;

[0159] The first electrode P1 is located on the first wall C11, and the second electrode P2 is located on the second wall C12.

[0160] The first semiconductor layer C1 of the transistor in this embodiment adopts a three-sided structure composed of a first wall C11, a second wall C12 and a third wall C13, instead of a ring gate or ring channel structure, which can reduce the difficulty of the process and improve the uniformity of the device structure.

[0161] In some embodiments of this application, as shown in FIG1A and FIG1B, the sidewalls of the first gate electrode G1 include opposing first sidewalls G11 and second sidewalls G12, as well as opposing third sidewalls G13 and fourth sidewalls G14.

[0162] The first wall C11 surrounds the first sidewall G11, and the second wall C12 surrounds the second sidewall G12; the first semiconductor layer C1 exposes the third sidewall G13 and the fourth sidewall G14.

[0163] In some embodiments of this application, as shown in FIG1A and FIG1B, the transistor further includes a second gate electrode G2, which is located on the side of the second end face away from the first end face, and a first semiconductor layer C1 is located between the second gate electrode G2 and the first gate electrode G1, and a second gate insulating layer 22 is provided between the first semiconductor layer C1 and the second gate electrode G2.

[0164] This application also provides a semiconductor device. Figure 2A is a three-dimensional structural schematic diagram of a memory cell of a semiconductor device according to an exemplary embodiment of this application; Figure 2B is a top view of the semiconductor device shown in Figure 2A; Figure 2C is a longitudinal cross-sectional schematic diagram of the semiconductor device shown in Figure 2A on the aa' section perpendicular to the substrate; Figure 2D is a longitudinal cross-sectional schematic diagram of the semiconductor device shown in Figure 2A on the bb' section perpendicular to the substrate; Figure 2E is a longitudinal cross-sectional schematic diagram of the semiconductor device shown in Figure 2A on the cc' section perpendicular to the substrate; Figure 2F is a longitudinal cross-sectional schematic diagram of the semiconductor device shown in Figure 2A on the dd' section perpendicular to the substrate.

[0165] As shown in Figures 2A to 2F, the semiconductor device includes: a plurality of memory cells located on a substrate 10; the plurality of memory cells are located in different layers and are spaced apart along a direction perpendicular to the substrate 10;

[0166] The storage unit includes a read transistor RTR and a write transistor WTR; the read transistor RTR is a transistor as described above.

[0167] The semiconductor device in this application adopts a 3D three-dimensional structure, which can integrate more memory cells in a limited area, resulting in high storage density.

[0168] In some embodiments of this application, the semiconductor device further includes a read word line RWL, a read bit line RBL, a write word line WWL, and a write bit line WBL; the read word line RWL is connected to the first end face of the first gate electrode G1, the read bit line RBL is connected to the second electrode P2, and the write word line WWL and the write bit line WBL are both connected to the write transistor WTR.

[0169] The read line RWL and write line WWL both extend along the column direction; the read bit line RBL and write bit line WBL both extend along a direction perpendicular to the substrate 10.

[0170] In the semiconductor device of this application embodiment, both the read bit line RBL and the write bit line WBL extend in a direction perpendicular to the substrate 10. By controlling the distance between the bit lines, the capacitive coupling between the bit lines can be reduced, which is more friendly to the circuit load.

[0171] In some embodiments of this application, as shown in Figures 2A to 2C, the write transistor WTr includes a third electrode P3 and a fourth electrode P4, a second semiconductor layer C2 located between the third electrode P3 and the fourth electrode P4, a third gate insulating layer 23, and a third gate electrode G3.

[0172] Both the second semiconductor layer C2 and the third gate electrode G3 extend along the row direction, and the second semiconductor layer C2 at least partially surrounds the third gate electrode G3.

[0173] The third gate electrode G3 is connected to the write word line WWL; the fourth electrode P4 is connected to the write bit line WBL.

[0174] In some embodiments of this application, as shown in FIG2B, at least a portion of the sidewalls of the second semiconductor layer C2 are surrounded by an etch barrier layer 13.

[0175] In some embodiments of this application, as shown in FIG2B, at least a portion of the sidewalls of the writing line WWL are surrounded by an etch barrier layer 13.

[0176] In some embodiments of this application, as shown in FIG2B, at least a portion of the sidewalls of the second gate electrode G2 are surrounded by an etch barrier layer 13.

[0177] In some embodiments of this application, as shown in Figures 2A to 2C and 2F, the second semiconductor layer C2 is a cylindrical structure with one end closed and the other end open, and the third gate electrode G3 extends into the interior of the cylindrical structure of the second semiconductor layer C2 through the opening.

[0178] In some embodiments of this application, as shown in Figures 2A and 2B, the storage unit further includes a storage node SN, which is connected to the read transistor RTR and the write transistor WTR, respectively.

[0179] As shown in Figures 2A and 2B, the storage node SN, the third electrode P3, and the second gate electrode G2 are integrated into one structure.

[0180] In some embodiments of this application, as shown in Figures 2A and 2B, the write bit line WBL includes a first sub-write bit line WBL1 and a second sub-write bit line WBL2; one end of the first sub-write bit line WBL1 and the second sub-write bit line WBL2 are connected, and the other end is spaced apart.

[0181] One end of the first sub-write bit line WBL1 and the second sub-write bit line WBL2, which are spaced apart, is connected to the sidewall of the second semiconductor layer C2.

[0182] In some embodiments of this application, as shown in FIG2B, the read word line RWL is connected to the first gate electrode G1 of a column of memory cells spaced apart along the column direction.

[0183] In some embodiments of this application, as shown in FIG2E, the read bit line RBL is connected to the second electrode P2 of a plurality of memory cells spaced apart along a direction perpendicular to the substrate 10.

[0184] In some embodiments of this application, as shown in FIG2B, the write line WWL is connected to the third gate electrode G3 of a column of memory cells spaced apart along the column direction.

[0185] In some embodiments of this application, as shown in FIG2F, the write bit line WBL is connected to the fourth electrode P4 of a plurality of memory cells spaced apart along a direction perpendicular to the substrate 10.

[0186] In some embodiments of this application, as shown in Figures 2A and 2B, the second electrode P2 and the read line RBL are an integral structure.

[0187] In some embodiments of this application, as shown in Figures 2A and 2B, the fourth electrode P4 and the write bit line WBL are an integral structure.

[0188] In this application, the first semiconductor layer and the second semiconductor layer can be understood as semiconductor materials, and their shape and structure are not emphasized, but only their function.

[0189] For example, the materials of the first semiconductor layer and the second semiconductor layer can each be independently silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or wide band gap materials, such as metal oxide materials with a band gap of greater than 1.65 eV.

[0190] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0191] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0192] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0193] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0194] In some embodiments of this application, the materials of the read bit line and the write bit line can be independently selected from any one or more other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0195] In some embodiments of this application, the materials of the reading lines and writing lines can each be independently selected from any one or more of the following different types of materials:

[0196] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0197] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials.

[0198] Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.

[0199] In some embodiments of this application, the materials of the first gate insulating layer, the second gate insulating layer, and the third gate insulating layer may each independently comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.

[0200] Low-K materials, such as silicon oxide.

[0201] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0202] This application also provides a method for manufacturing a semiconductor device. The semiconductor device described above can be obtained by this method.

[0203] Figure 3 is a process flow diagram of a semiconductor device manufacturing method according to an exemplary embodiment of this application. As shown in Figure 3, the manufacturing method includes:

[0204] An insulating layer and a sacrificial layer are alternately formed sequentially on a substrate to obtain a stacked structure;

[0205] In the stacked structure, a plurality of isolation holes are formed extending in a direction toward the substrate; the plurality of isolation holes are spaced apart in a column direction parallel to the substrate; the isolation holes include read regions and write regions distributed in a row direction parallel to the substrate;

[0206] An etch barrier layer and a first isolation layer are sequentially formed within the isolation hole;

[0207] Remove the sacrificial layer surrounding the read tube area to obtain a first channel groove located between two adjacent isolation holes;

[0208] A first semiconductor layer, a first gate insulating layer, and a first gate electrode are sequentially formed within the first channel trench;

[0209] The etching barrier layer and the first isolation layer of the read tube region are etched to form a first through-hole that penetrates the read tube region. Two adjacent first through-holes expose the two sidewalls of the first semiconductor layer distributed along the column direction.

[0210] A first electrode and a second electrode are respectively formed in two adjacent first through holes, located on the two sidewalls of the same first semiconductor layer distributed along the column direction;

[0211] Remove the insulating layer located on the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, exposing the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate;

[0212] Remove the exposed areas of the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate.

[0213] The manufacturing method of this application embodiment forms a read transistor between two adjacent isolation holes, such that the spacing between two adjacent isolation holes serves as the channel width between the source and drain of the read transistor. The spacing between two adjacent isolation holes can be designed according to the requirements of the channel width, thereby making it easier to control the gate length and gate width of the semiconductor device.

[0214] In some embodiments of this application, removing the sacrificial layer surrounding the read tube region to obtain a first channel groove located between two adjacent isolation holes includes:

[0215] The stacked structure located on the side of the read region away from the write region is etched along the direction toward the substrate to form a first trench that penetrates the stacked structure and extends along the column direction, the first trench exposing each of the sacrificial layers of the stacked structure;

[0216] The exposed sacrificial layers are laterally etched within the first trench to obtain the first channel trench and read word line trench located between two adjacent insulating layers; the first channel trench is located between two adjacent isolation holes, and the read word line trench is located on the side of the read tube area away from the write tube area and extends along the column direction.

[0217] In some embodiments of this application, the step of sequentially forming a first semiconductor layer, a first gate insulating layer, and a first gate electrode within the first channel trench includes:

[0218] A first semiconductor layer and a first gate insulating layer are sequentially formed in each of the first trenches, covering one end face of the read region away from the write region. The first semiconductor layers in each of the first trenches are connected to each other, and the first gate insulating layers in each of the first trenches are connected to each other.

[0219] Remove at least a portion of the first semiconductor layer and the first gate insulating layer located on the end face of the read tube region away from the write tube region, and disconnect the first semiconductor layer and the first gate insulating layer located in different first channel trenches;

[0220] The first gate electrode is formed in each of the first channel slots and the reading line is formed in the reading line slot, which is connected to the first gate electrode;

[0221] The first trench is filled with insulating material.

[0222] In some embodiments of this application, forming first and second electrodes on the sidewalls of the same first semiconductor layer distributed along the column direction within two adjacent first vias includes:

[0223] A first electrode layer is formed on the sidewall of the first through hole, and a second isolation layer is filled inside the first through hole;

[0224] The first isolation layer on both sides of the first via distributed along the row direction is etched along the direction toward the substrate, and a first opening penetrating the read tube region in the direction toward the substrate is formed on both sides of the first via distributed along the row direction, and the first opening exposes the first electrode layer.

[0225] The exposed first electrode layer is etched within the first opening, dividing the first electrode layer within the same first via into two portions located on the sidewalls of two adjacent first semiconductor layers. One portion of the first electrode layer includes a plurality of first electrodes distributed and connected along a direction perpendicular to the substrate, and the other portion of the first electrode layer includes a plurality of second electrodes distributed and connected along a direction perpendicular to the substrate. The first electrode and the second electrode formed by the first electrode layer within the same first via are each part of the read transistor of two adjacent memory cells. The plurality of connected second electrodes form a read bit line.

[0226] Fill the first opening with insulating material.

[0227] In some embodiments of this application, removing the insulating layer located on the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, thereby exposing the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, includes:

[0228] Remove the insulating material from the first trench to expose the first trench, thus exposing the insulating layer.

[0229] Laterally etch the exposed insulating layer within the first trench to remove the insulating layer surrounding the read tube region and the insulating layer located on the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, thereby exposing the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate.

[0230] In some embodiments of this application, the manufacturing method further includes: after forming the first isolation layer within the isolation hole, and before removing the sacrificial layer surrounding the read tube region,

[0231] The etching barrier layer and the first isolation layer of the write tube region are etched to form a second via through the write tube region. The second via penetrates the etching barrier layer in the column direction.

[0232] A second electrode layer is formed on the sidewall of the second through hole, and a second isolation layer is filled inside the second through hole;

[0233] The etching barrier layer and the first isolation layer on both sides of the second via distributed along the row direction are etched along the direction toward the substrate. Second openings penetrating the write tube region in the direction toward the substrate are formed on both sides of the second via distributed along the row direction. The second openings expose the second electrode layer.

[0234] The exposed second electrode layer is etched within the second opening, dividing the second electrode layer within the same second via into two parts distributed along the column direction. One part of the second electrode layer is a first sub-write bit line, and the other part of the second electrode layer is a second sub-write bit line. The first sub-write bit line and the second sub-write bit line formed by the second electrode layer within the same second via are each part of the write bit line of two adjacent memory cells. The second sub-write bit line includes a plurality of fourth electrodes distributed and connected along a direction perpendicular to the substrate.

[0235] In some embodiments of this application, the manufacturing method further includes: after removing exposed areas from the upper and lower surfaces of the first semiconductor layer distributed along a direction perpendicular to the substrate,

[0236] The stacked structure located on the side of the write region away from the read region is etched along the direction toward the substrate to form a second trench that penetrates the stacked structure and extends along the column direction, the second trench exposing each of the sacrificial layers of the stacked structure;

[0237] Laterally etch each of the exposed sacrificial layers in the second trench to obtain a second channel trench and a write line trench located between two adjacent insulating layers; the second channel trench is located between two adjacent isolation holes, and the second channel trench exposes the first semiconductor layer; the write line trench is located on the side of the write tube region away from the read tube region and extends along the column direction;

[0238] A second insulating layer and a second gate electrode are sequentially formed at one end of the second channel groove near the read tube area;

[0239] A second semiconductor layer, a third gate insulating layer, and a third gate electrode are sequentially formed in the remaining region of the second trench.

[0240] Writing lines are formed in the writing line groove, and insulating material is filled into the second groove.

[0241] In some embodiments of this application, the step of sequentially forming a second insulating layer and a second gate electrode at one end of the second channel trench near the read region includes:

[0242] A second gate insulating layer and a second gate electrode are sequentially formed in each of the second channel trenches, covering one end face of the write tube region away from the read tube region. The second insulating layers in each of the second channel trenches are connected to each other, and the second gate electrodes in each of the second channel trenches are connected to each other.

[0243] The second gate insulating layer and the second gate electrode in the second channel trench are etched back to disconnect the second gate insulating layer and the second gate electrode located in different second channel trenches.

[0244] In some embodiments of this application, the step of sequentially forming a second semiconductor layer, a third gate insulating layer, and a third gate electrode in the remaining region of the second trench includes:

[0245] A second semiconductor layer, a third gate insulating layer, and a third gate electrode are sequentially formed in each of the second channel trenches, covering one end face of the write region away from the read region. The second semiconductor layers in each of the second channel trenches are connected to each other, the third gate insulating layers in each of the second channel trenches are connected to each other, and the third gate electrodes in each of the second channel trenches are connected to each other.

[0246] At least a portion of the second semiconductor layer, the third gate insulating layer, and the third gate electrode located on the end face of the write region away from the read region are removed, and the second semiconductor layer, the third gate insulating layer, and the third gate electrode located in different second channel trenches are disconnected.

[0247] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0248] As shown in Figures 4A to 15D, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0249] S10: An insulating layer 14 and a sacrificial layer 15 are sequentially and alternately deposited on the substrate 10 to obtain a stacked structure composed of multiple insulating layers 14 and multiple sacrificial layers 15, as shown in Figures 4A to 4C.

[0250] In some embodiments of this application, the insulating layer can be made of a low-K dielectric material, i.e., a dielectric material with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon oxide or other silicon-containing films. For example, the first sacrificial layer can be made of silicon oxide, and the insulating layer can also be made of silicon oxide.

[0251] In some embodiments of this application, the material of the sacrificial layer may be silicon nitride (e.g., Si3N4), amorphous silicon, etc.

[0252] For illustrative purposes only, the stacked structures shown in Figures 4B and 4C include three insulating layers 14 and three sacrificial layers 15. In other embodiments, the stacked structures may include more or fewer layers of insulating layers 14 and sacrificial layers 15 arranged alternately.

[0253] S20: Isolation holes are defined in the stacked structure for forming read transistors and write transistors.

[0254] For example, step S20 may include:

[0255] S21: The stacked structure is etched along the direction toward the substrate 10 to form a plurality of isolation holes K3 penetrating the stacked structure; each isolation hole K3 extends along a row direction parallel to the substrate 10, and the plurality of isolation holes K3 are spaced apart along a column direction parallel to the substrate 10; the isolation hole K3 includes a read tube region and a write tube region distributed along a row direction parallel to the substrate 10; the read tube region is subsequently used to form a read transistor, and the write tube region is subsequently used to form a write transistor; in the semiconductor structure shown in FIG5A, the left side of the isolation hole K3 is the read tube region, and the right side is the write tube region;

[0256] S22: An etch barrier layer 13 is deposited on the inner wall of the isolation hole K3, and the first isolation layer 11 is filled in the isolation hole K3, as shown in Figures 5A to 5C.

[0257] As exemplarily shown in Figures 5B and 5C, the isolation hole K3 may extend along a direction perpendicular to the substrate 10.

[0258] In this application, the row direction intersects the column direction; for example, the row direction and the column direction can be perpendicular to each other. For example, the row direction can be the bb' direction as shown in Figure 5A; the column direction can be the cc' direction as shown in Figure 5A.

[0259] In this application, multiple components distributed along the row direction can be referred to as a row component, for example, a row of storage cells. Multiple components distributed along the column direction can be referred to as a column component, for example, a column of storage cells.

[0260] For example, the etching barrier layer can be a thin layer of silicon oxide, such as a SiO2 thin film formed by atomic layer deposition (ALD) process.

[0261] For example, the material of the first isolation layer can be silicon nitride, for example, Si3N4.

[0262] S30: A write bit line WBL is formed in the write tube region.

[0263] For example, step S30 may include steps S31 to S35 as described below.

[0264] S31: Etching the etch barrier layer 13 and the first isolation layer 11 of the write tube region along the direction toward the substrate 10 to form a second via K2 through the write tube region. The second via K2 penetrates the etch barrier layer 13 in the column direction.

[0265] S32: A second electrode layer 32 is formed on the sidewall of the second through hole K2. For example, the second electrode layer 32 can be formed on the inner wall (including the sidewall and bottom surface) of the second through hole K2 first, and then the second electrode layer 32 on the bottom surface of the second through hole K2 can be removed; then the second isolation layer 12 is filled in the second through hole K2, as shown in Figures 6A to 6C.

[0266] As exemplarily shown in Figures 6B and 6C, the second via K2 can extend along a direction perpendicular to the substrate 10.

[0267] For example, the material of the second electrode layer 32 can be selected from other metal materials such as nickel, aluminum, copper, and cobalt, or it can be formed into a corresponding metal silicide after annealing. This application does not limit this. For example, the material of the second isolation layer can be silicon oxide, for example, it can be the same as the material of the etching barrier layer, both of which are silicon oxide.

[0268] S33: Etching the etching barrier layer 13 and the first isolation layer 11 on both sides of the second via K2 distributed along the row direction in the direction toward the substrate 10, and forming a second opening through the write tube region on both sides of the second via K2 distributed along the row direction in the direction toward the substrate 10, the second opening exposing the second electrode layer 32.

[0269] S34: The exposed second electrode layer 32 is etched within the second opening, for example by wet etching, to divide the second electrode layer 32 within the same second via K2 into two portions spaced apart along the column direction. One portion of the second electrode layer 32 is a first sub-write bit line WBL1, and the other portion of the second electrode layer 32 is a second sub-write bit line WBL2. The first sub-write bit line WBL1 and the second sub-write bit line WBL2 formed by the second electrode layer 32 within the same second via K2 are respectively part of the write bit lines of two adjacent memory cells. The second sub-write bit line WBL2 includes a plurality of fourth electrodes P4 distributed and connected along a direction perpendicular to the substrate 10.

[0270] S35: Fill the empty space of the second opening and the second through hole K2 with the second isolation layer 12, as shown in Figures 7A and 7B.

[0271] Subsequently, the first sub-write bit line WBL1 and the second sub-write bit line WBL2, which are formed by the second electrode layers 32 in two different adjacent second vias K2, that is, the ends of the first sub-write bit line WBL1 and the second sub-write bit line WBL2 located in the same memory cell that are away from the substrate 10, can be connected together to form a write bit line WBL.

[0272] S40: Remove the sacrificial layer 15 surrounding the read tube area to obtain the first channel groove T1 located between two adjacent isolation holes K3.

[0273] For example, step S40 may include:

[0274] S41: The stacked structure located on the side of the read tube region away from the write tube region is etched along the direction toward the substrate 10 to form a first trench T3 that penetrates the stacked structure and extends along the column direction, the first trench T3 exposing each sacrificial layer 15 of the stacked structure;

[0275] S42: Laterally etch each exposed sacrificial layer 15 in the first trench T3, for example, by wet lateral etching, to obtain a first channel trench T1 and a read word line trench T5 located between two adjacent insulating layers 14; the first channel trench T1 is located between two adjacent isolation holes K3, and the read word line trench T5 is located on the side of the read tube area away from the write tube area and extends along the column direction, as shown in Figures 8A to 8D.

[0276] S50: A first semiconductor layer C1, a first gate insulating layer 21, and a first gate electrode G1 are sequentially formed in the first channel trench T1, and a read word line RWL is formed in the read word line trench T5, as shown in Figures 9A to 9D.

[0277] For example, step S50 may include:

[0278] S51: A first semiconductor layer C1 and a first gate insulating layer 21 are sequentially formed in each first channel trench T1, covering the end face of the read tube area away from the write tube area (i.e. the side of the read tube area closest to the read word line trench T5). The first semiconductor layers C1 in each first channel trench T1 located in the same layer are connected to each other, and the first gate insulating layers 21 in each first channel trench T1 located in the same layer are connected to each other.

[0279] S52: Using an etching process, such as a wet etching process, remove at least a portion of the first semiconductor layer C1 and at least a portion of the first gate insulating layer 21 on the end face of the read tube region away from the write tube region, disconnect the first semiconductor layer C1 located in different first channel trenches T1, and disconnect the first gate insulating layer 21 located in different first channel trenches T1.

[0280] S53: Deposit isolation material on the exposed end face of the first semiconductor layer C1 and the first gate insulating layer 21 near the read word groove T5 to prevent the first semiconductor layer C1 from being connected to the subsequently formed read word line;

[0281] S54: A first gate electrode G1 is formed in each first channel groove T1 and a read line RWL connected to multiple first gate electrodes G1 in the same layer is formed in the read line groove T5, and the first groove T3 is filled with insulating material, as shown in Figures 9A to 9D.

[0282] As shown in Figures 9A and 9D, the first semiconductor layer C1 obtained in step S50 is a cylindrical shape with one end closed and the other end open.

[0283] For example, the insulating material can be silicon nitride, such as SiN; the insulating material can be the same as the material of the insulating layer, for example, both can be silicon oxide.

[0284] S60: The first electrode P1, the second electrode P2, and the read bit line RWL of the read transistor are formed in the read tube region.

[0285] For example, step S60 may include steps S61 to S65 as described below.

[0286] S61: The etch barrier layer 13 and the first isolation layer 11 of the read tube region are etched along the direction toward the substrate 10 to form a first through hole K1 through the read tube region. Two adjacent first through holes K1 expose the two sidewalls of the first semiconductor layer C1 distributed along the column direction.

[0287] S62: A first electrode layer 31 is formed on the sidewall of the first through hole K1. For example, the first electrode layer 31 can be formed on the inner wall (including the sidewall and the bottom surface) of the first through hole K1 first, and then the first electrode layer 31 on the bottom surface of the first through hole K1 can be removed; then the second isolation layer 12 is filled into the first through hole K1, as shown in Figures 10A to 10C.

[0288] S63: Etch the etching barrier layer 13 and the first isolation layer 11 on both sides of the first via K1 distributed along the row direction in the direction toward the substrate 10, and form a first opening through the read tube region in the direction toward the substrate 10 on both sides of the first via K1 distributed along the row direction, with the first opening exposing the first electrode layer 31.

[0289] S64: The exposed first electrode layer 31 is etched within the first opening, for example, by wet etching, dividing the first electrode layer 31 within the same first via K1 into two parts located on the sidewalls of two adjacent first semiconductor layers C1. One part of the first electrode layer 31 includes a plurality of first electrodes P1 distributed and connected along a direction perpendicular to the substrate 10, and the other part of the first electrode layer 31 includes a plurality of second electrodes P2 distributed and connected along a direction perpendicular to the substrate 10. The first electrodes P1 and the second electrodes P2 formed by the first electrode layer 31 within the same first via K1 are respectively part of the read transistors of two adjacent memory cells. The plurality of connected second electrodes P2 form a read bit line RBL.

[0290] S65: Fill the first opening with the insulating material, as shown in Figures 11A and 11B.

[0291] S70: Remove the insulating layer 14 located on the upper and lower surfaces of the first semiconductor layer C1 distributed in a direction perpendicular to the substrate 10, expose the upper and lower surfaces of the first semiconductor layer C1 distributed in a direction perpendicular to the substrate 10, and remove the exposed area of ​​the upper and lower surfaces of the first semiconductor layer C1 distributed in a direction perpendicular to the substrate 10.

[0292] For example, step S70 may include:

[0293] S71: Remove the insulating material in the first trench T3 to expose the first trench T3, and expose the insulating layer 14 in the first trench T3;

[0294] S72: Laterally etch the exposed insulating layer 14 in the first trench T3. For example, wet etching can be used to remove the insulating layer 14 surrounding the read tube area and the insulating layer 14 located on the upper and lower surfaces of the first semiconductor layer C1 distributed in a direction perpendicular to the substrate 10, exposing the upper and lower surfaces of the first semiconductor layer C1 distributed in a direction perpendicular to the substrate 10, as shown in Figures 12A to 12D.

[0295] S73: Using an etching process, such as a wet etching process, the exposed areas of the upper and lower surfaces of the first semiconductor layer C1, distributed along a direction perpendicular to the substrate, are removed, as shown in Figures 13A and 13B. The positions of cross-section aa' in Figure 13A and cross-section cc' in Figure 13B are the same as in Figure 12A.

[0296] S80: Deposit the insulating material on the substrate 10 to fill the pores between the first trench T3 and the adjacent two read tube regions.

[0297] If the isolation material is silicon nitride, step S80 may further include: replacing the silicon nitride isolation material in the first opening with a material such as silicon oxide to reduce the parasitic capacitance between devices, as shown in Figures 14A to 14D.

[0298] S90: Forms the second gate electrode G2 of the read transistor.

[0299] For example, step S90 may include steps S91 to S93 as described below.

[0300] S91: The stacked structure located on the side of the write region away from the read region is etched along the direction toward the substrate 10 to form a second trench T4 that penetrates the stacked structure and extends along the column direction, the second trench T4 exposing each sacrificial layer 15 of the stacked structure;

[0301] S92: Laterally etch each exposed sacrificial layer 15 within the second trench T4, for example, by using wet etching to obtain a second channel trench T2 and a write line trench T6 located between two adjacent insulating layers 14; the second channel trench T2 is located between two adjacent isolation holes K3, and the second channel trench T2 exposes the first semiconductor layer C1; the write line trench T6 is located on the side of the write tube area away from the read tube area and extends along the column direction, as shown in Figures 15A to 15D;

[0302] S93: A second gate insulating layer 22 and a second gate electrode G2 are sequentially formed at one end of the second channel trench T2 near the read tube region.

[0303] For example, step S93 may include:

[0304] S931: A second gate insulating layer 22 and a second gate electrode G2 are sequentially formed in each second channel trench T2, covering one end face of the write tube area away from the read tube area. The second gate insulating layers 22 in each second channel trench T2 located in the same layer are connected to each other, and the second gate electrodes G2 in each second channel trench T2 located in the same layer are connected to each other.

[0305] S932: The second gate insulating layer 22 and the second gate electrode G2 in the second channel trench T2 are etched back, and the second gate insulating layer 22 and the second gate electrode G2 located in different second channel trenches T2 are disconnected, leaving only the second gate insulating layer 22 and the second gate electrode G2 at the end of the second channel trench T2 closest to the read tube region.

[0306] S100: The second semiconductor layer C2, the third gate insulating layer 23 and the third gate electrode G3 are sequentially formed in the remaining region of the second channel trench T2.

[0307] For example, step S100 may include:

[0308] S101: A second semiconductor layer C2, a third gate insulating layer 23, and a third gate electrode G3 are sequentially formed in each second channel trench T2, covering one end face of the write area away from the read area. The second semiconductor layers C2 in each second channel trench T2 are connected to each other, the third gate insulating layers 23 in each second channel trench T2 are connected to each other, and the third gate electrode G3 in each second channel trench T2 is connected to each other.

[0309] S102: Remove at least a portion of the second semiconductor layer C2, the third gate insulating layer 23, and the third gate electrode G3 located on the end face of the write region away from the read region, disconnect the second semiconductor layer C2 located in different second channel trenches T2, open the third gate insulating layer 23 located in different second channel trenches T2, and disconnect the third gate electrode G3 located in different second channel trenches T2.

[0310] S110: A writing line WWL connected to a plurality of third gate electrodes G3 located on the same layer is formed in the writing line groove T6, and the insulating material is filled in the second trench T4 to obtain the semiconductor device shown in Figures 2A to 2F.

[0311] This application also provides an electronic device, which includes the transistor or semiconductor device described above, or a semiconductor device obtained by the manufacturing method described above.

[0312] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0313] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A transistor, comprising: A first electrode and a second electrode located on a substrate, a first semiconductor layer located between the first electrode and the second electrode, a first gate insulating layer, and a first gate electrode; The first electrode and the second electrode are spaced apart in a column direction parallel to the substrate; The first gate electrode extends along a row direction parallel to the substrate. The first gate electrode includes a sidewall extending along the row direction and a first end face and a second end face spaced apart in the row direction. The first electrode and the second electrode are located on the sidewall of the first gate electrode. The first end face is used to connect with a word line. The second end face and the sidewall on which the first electrode and the second electrode are disposed are surrounded by the first semiconductor layer.

2. The transistor according to claim 1, wherein, The first semiconductor layer includes a first wall, a second wall, and a third wall located between the first wall and the second wall; the first wall and the second wall both extend along the row direction, and the third wall extends along the column direction; The first wall, the second wall, and the third wall all surround the first gate electrode; The first electrode is located on the first wall, and the second electrode is located on the second wall.

3. The transistor according to claim 2, wherein, The sidewalls of the first gate electrode include opposing first and second sidewalls, as well as opposing third and fourth sidewalls; The first wall surrounds the first sidewall, and the second wall surrounds the second sidewall; the first semiconductor layer is exposed to the third and fourth sidewalls.

4. The transistor according to any one of claims 1 to 3, further comprising a second gate electrode located on the side of the second end face away from the first end face, the first semiconductor layer located between the second gate electrode and the first gate electrode, and a second gate insulating layer being provided between the first semiconductor layer and the second gate electrode.

5. A semiconductor device, comprising: Multiple memory cells located on the substrate; The plurality of memory cells are located on different layers and are spaced apart along a direction perpendicular to the substrate; The storage unit includes a read transistor and a write transistor; the read transistor is a transistor according to any one of claims 1 to 4.

6. The semiconductor device according to claim 5 further includes a read word line, a read bit line, a write word line, and a write bit line; the read word line is connected to a first end face of the first gate electrode, the read bit line is connected to the second electrode, and the write word line and the write bit line are both connected to the write transistor; Both the read line and the write line extend along the column direction; both the read bit line and the write bit line extend in a direction perpendicular to the substrate.

7. The semiconductor device according to claim 6, wherein, The write transistor includes a third electrode and a fourth electrode, a second semiconductor layer located between the third electrode and the fourth electrode, a third gate insulating layer, and a third gate electrode; Both the second semiconductor layer and the third gate electrode extend along the row direction, and the second semiconductor layer at least partially surrounds the third gate electrode; The third gate electrode is connected to the write word line; the fourth electrode is connected to the write bit line.

8. The semiconductor device according to claim 7, wherein, At least a portion of the sidewalls of the second semiconductor layer are surrounded by an etch barrier layer; and / or, At least a portion of the sidewalls of the writing line are surrounded by an etched barrier layer.

9. The semiconductor device according to claim 7 or 8, wherein, The second semiconductor layer is a cylindrical structure that is closed at one end and open at the other end, and the third gate electrode extends into the interior of the cylindrical structure of the second semiconductor layer through the opening.

10. The semiconductor device according to any one of claims 7 to 9, wherein, The storage unit further includes a storage node, which is connected to the read transistor and the write transistor respectively; The storage node and the third electrode are integrated into one unit.

11. The semiconductor device according to any one of claims 7 to 10, wherein, The write bit line includes a first sub-write bit line and a second sub-write bit line, with one end of the first sub-write bit line and the second sub-write bit line connected and the other end spaced apart; One end of the first sub-write bit line and the second sub-write bit line, which are spaced apart, is connected to the sidewall of the second semiconductor layer.

12. The semiconductor device according to any one of claims 6 to 10, wherein, The read line is connected to the first gate electrode of a column of memory cells spaced apart along the column direction; and / or The read bit line is connected to the second electrode of a plurality of memory cells spaced apart along a direction perpendicular to the substrate; and / or, The write lines are connected to the third gate electrodes of a column of memory cells spaced apart along the column direction; and / or, The write bit line is connected to the fourth electrode of a plurality of memory cells spaced apart along a direction perpendicular to the substrate; and / or, The second electrode and the read line are integrally formed; and / or, The fourth electrode and the write bit line are an integral structure.

13. A method for manufacturing a semiconductor device, comprising: An insulating layer and a sacrificial layer are alternately formed sequentially on a substrate to obtain a stacked structure; A plurality of isolation holes are formed in the stacked structure, extending in a direction toward the substrate; The plurality of isolation holes are spaced apart along a column direction parallel to the substrate; the isolation holes include read and write regions distributed along a row direction parallel to the substrate. An etch barrier layer and a first isolation layer are sequentially formed within the isolation hole; Remove the sacrificial layer surrounding the read tube area to obtain a first channel groove located between two adjacent isolation holes; A first semiconductor layer, a first gate insulating layer, and a first gate electrode are sequentially formed within the first channel trench; The etching barrier layer and the first isolation layer of the read tube region are etched to form a first through-hole that penetrates the read tube region. Two adjacent first through-holes expose the two sidewalls of the first semiconductor layer distributed along the column direction. A first electrode and a second electrode are respectively formed in two adjacent first through holes, located on the two sidewalls of the same first semiconductor layer distributed along the column direction; Remove the insulating layer located on the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, exposing the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate; Remove the exposed areas of the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate.

14. The manufacturing method according to claim 13, wherein, The process of removing the sacrificial layer surrounding the read tube region to obtain a first channel groove located between two adjacent isolation holes includes: The stacked structure located on the side of the read region away from the write region is etched along the direction toward the substrate to form a first trench that penetrates the stacked structure and extends along the column direction, the first trench exposing each of the sacrificial layers of the stacked structure; The exposed sacrificial layers are laterally etched within the first trench to obtain the first channel trench and read word line trench located between two adjacent insulating layers; the first channel trench is located between two adjacent isolation holes, and the read word line trench is located on the side of the read tube area away from the write tube area and extends along the column direction.

15. The manufacturing method according to claim 14, wherein, The step of sequentially forming a first semiconductor layer, a first gate insulating layer, and a first gate electrode within the first channel trench includes: A first semiconductor layer and a first gate insulating layer are sequentially formed in each of the first trenches, covering one end face of the read region away from the write region. The first semiconductor layers in each of the first trenches are connected to each other, and the first gate insulating layers in each of the first trenches are connected to each other. Remove at least a portion of the first semiconductor layer and the first gate insulating layer located on the end face of the read tube region away from the write tube region, and disconnect the first semiconductor layer and the first gate insulating layer located in different first channel trenches; The first gate electrode is formed in each of the first channel slots and the reading line is formed in the reading line slot, which is connected to the first gate electrode; The first trench is filled with insulating material.

16. The manufacturing method according to any one of claims 13 to 15, wherein, The method of forming a first electrode and a second electrode on two sidewalls of the same first semiconductor layer along the column direction within two adjacent first vias includes: A first electrode layer is formed on the sidewall of the first through hole, and a second isolation layer is filled inside the first through hole; The first isolation layer on both sides of the first via distributed along the row direction is etched along the direction toward the substrate, and a first opening penetrating the read tube region in the direction toward the substrate is formed on both sides of the first via distributed along the row direction, and the first opening exposes the first electrode layer. The exposed first electrode layer is etched within the first opening, dividing the first electrode layer within the same first via into two portions located on the sidewalls of two adjacent first semiconductor layers. One portion of the first electrode layer includes a plurality of first electrodes distributed and connected along a direction perpendicular to the substrate, and the other portion of the first electrode layer includes a plurality of second electrodes distributed and connected along a direction perpendicular to the substrate. The first electrode and the second electrode formed by the first electrode layer within the same first via are each part of the read transistor of two adjacent memory cells. The plurality of connected second electrodes form a read bit line. Fill the first opening with insulating material.

17. The manufacturing method according to claim 15 or 16, wherein, Removing the insulating layer from the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, thereby exposing the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, includes: Remove the insulating material from the first trench to expose the first trench, thus exposing the insulating layer. Laterally etch the exposed insulating layer within the first trench to remove the insulating layer surrounding the read tube region and the insulating layer located on the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate, thereby exposing the upper and lower surfaces of the first semiconductor layer distributed in a direction perpendicular to the substrate.

18. The manufacturing method according to any one of claims 13 to 17, further comprising: After the first isolation layer is formed within the isolation hole, and before the sacrificial layer surrounding the read tube area is removed, The etching barrier layer and the first isolation layer of the write tube region are etched to form a second via through the write tube region. The second via penetrates the etching barrier layer in the column direction. A second electrode layer is formed on the sidewall of the second through hole, and a second isolation layer is filled inside the second through hole; The etching barrier layer and the first isolation layer on both sides of the second via distributed along the row direction are etched along the direction toward the substrate. Second openings penetrating the write tube region in the direction toward the substrate are formed on both sides of the second via distributed along the row direction. The second openings expose the second electrode layer. The exposed second electrode layer is etched within the second opening, dividing the second electrode layer within the same second via into two parts distributed along the column direction. One part of the second electrode layer is a first sub-write bit line, and the other part of the second electrode layer is a second sub-write bit line. The first sub-write bit line and the second sub-write bit line formed by the second electrode layer within the same second via are each part of the write bit line of two adjacent memory cells. The second sub-write bit line includes a plurality of fourth electrodes distributed and connected along a direction perpendicular to the substrate.

19. The manufacturing method according to any one of claims 13 to 17, further comprising: After removing the exposed areas of the upper and lower surfaces of the first semiconductor layer distributed along a direction perpendicular to the substrate, The stacked structure located on the side of the write region away from the read region is etched along the direction toward the substrate to form a second trench that penetrates the stacked structure and extends along the column direction, the second trench exposing each of the sacrificial layers of the stacked structure; Laterally etch each of the exposed sacrificial layers in the second trench to obtain a second channel trench and a write line trench located between two adjacent insulating layers; the second channel trench is located between two adjacent isolation holes, and the second channel trench exposes the first semiconductor layer; the write line trench is located on the side of the write tube region away from the read tube region and extends along the column direction; A second insulating layer and a second gate electrode are sequentially formed at one end of the second channel groove near the read tube area; A second semiconductor layer, a third gate insulating layer, and a third gate electrode are sequentially formed in the remaining region of the second trench. Writing lines are formed in the writing line groove, and insulating material is filled into the second groove.

20. The manufacturing method according to claim 19, wherein, The step of sequentially forming a second insulating layer and a second gate electrode at one end of the second channel near the read tube region includes: A second gate insulating layer and a second gate electrode are sequentially formed in each of the second channel trenches, covering one end face of the write tube region away from the read tube region. The second insulating layers in each of the second channel trenches are connected to each other, and the second gate electrodes in each of the second channel trenches are connected to each other. The second gate insulating layer and the second gate electrode in the second channel trench are etched back to disconnect the second gate insulating layer and the second gate electrode located in different second channel trenches.

21. The manufacturing method according to claim 19 or 20, wherein, The step of sequentially forming a second semiconductor layer, a third gate insulating layer, and a third gate electrode in the remaining region of the second trench includes: A second semiconductor layer, a third gate insulating layer, and a third gate electrode are sequentially formed in each of the second channel trenches, covering one end face of the write region away from the read region. The second semiconductor layers in each of the second channel trenches are connected to each other, the third gate insulating layers in each of the second channel trenches are connected to each other, and the third gate electrodes in each of the second channel trenches are connected to each other. At least a portion of the second semiconductor layer, the third gate insulating layer, and the third gate electrode located on the end face of the write region away from the read region are removed, and the second semiconductor layer, the third gate insulating layer, and the third gate electrode located in different second channel trenches are disconnected.

22. An electronic device comprising a transistor according to any one of claims 1 to 4, or comprising a semiconductor device according to any one of claims 5 to 12, or comprising a semiconductor device obtained by a manufacturing method according to any one of claims 13 to 21.

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