Semiconductor module, semiconductor device, and power conversion device

Abstract

As the power capacity controlled by a power conversion device increases, energy flowing into the semiconductor chips also increases in case of an accident. Accordingly, it is necessary to design a sufficiently strong structure in order to improve necessary explosion resistance capacity and provide a post-failure energization function and therefore, it is difficult to achieve reduction in size and weight. A semiconductor module according to the present disclosure has a plurality of semiconductor chips mounted thereon. The inside of the semiconductor module is divided into a plurality of small sections. The small sections are surrounded by walls, and all of the small sections are adjacent to at least one other small section via the walls. At least four small sections are provided, the semiconductor chips are disposed in at least two small sections among the four small sections, and chip-disposed small sections, which are small sections having disposed therein the semiconductor chips, have at least one chip-disposed small section that is not adjacent to the other chip-disposed small section.

Description

Semiconductor Module, Semiconductor Device, and Power Conversion Device

[0006] ,

[0001] The present disclosure relates to a semiconductor module, a semiconductor device, and a power conversion device.

[0002] A semiconductor module mounted in a power conversion device with a large power capacity such as for high-voltage DC power transmission applications is connected to an external electrical circuit via an upper electrode and a base plate to control power. However, when an unexpected failure occurs in the built-in semiconductor chip, the semiconductor chip is heated up by Joule heating due to overcurrent, the resistance of the semiconductor chip decreases due to the temperature rise, the current increases, and it may enter a runaway state where the Joule heating further increases. Once it enters the runaway state, the energy accumulated in the external circuit flows into the failed semiconductor chip, and eventually the semiconductor chip melts exceeding its heat-resistant temperature, an arc occurs, and an explosion may be caused. Therefore, a structure that gives the semiconductor module an explosion-proof function is known so as not to damage the outside of the semiconductor module due to an explosion.

[0003] Also, inside a power conversion device, a plurality of semiconductor modules are electrically connected in series to control a high voltage exceeding the rated voltage per semiconductor module. In a power conversion device that requires high operation continuity, in order to improve redundancy, when one semiconductor module fails, the upper electrode and the base plate of the semiconductor module are short-circuited, so that the failed semiconductor module is used as merely a current-carrying path, and it may be designed to be able to continue operation with only the remaining semiconductor modules connected in series. In order to achieve the post-failure current-carrying function of the semiconductor module in this way, the current-carrying structure between the base plate and the upper electrode inside the semiconductor module is required to be strong enough to withstand an explosion during an accident.

[0004] Therefore, in a conventional semiconductor module, there is known one provided with an explosion-proof structure to increase the explosion-proof tolerance.

[0005] Japanese Unexamined Patent Application Publication No. 2017 - 103279

[0006] However, in the technology described in Patent Document 1, as the power capacity controlled by the power converter increases, the energy flowing into the semiconductor chip during an accident also increases. Therefore, in order to improve the required explosion-proof resistance and enable power supply after failure, the structure needs to be designed to be sufficiently robust, making it difficult to miniaturize and lighten the device.

[0007] The semiconductor module of this disclosure is a semiconductor module on which a plurality of semiconductor chips are mounted, wherein the interior of the semiconductor module is divided into a plurality of subcompartments, each subcompartment is surrounded by a wall, each subcompartment is adjacent to at least one other subcompartment via the wall, there are four or more subcompartments, semiconductor chips are placed in at least two of the four subcompartments, and each of the chip placement subcompartments on which semiconductor chips are placed has one or more other chip placement subcompartments that are not adjacent to that chip placement subcompartment.

[0008] The first semiconductor device of this disclosure includes a semiconductor module equipped with a plurality of semiconductor chips connected in parallel, two external connection terminals for connecting the semiconductor module to the outside, a current sensor for detecting the current flowing through the semiconductor module, and a control device that outputs an on / off signal to each of the plurality of semiconductor chips having a switching function. The control device outputs an on signal to all other semiconductor chips that have not detected any signs of a large current exceeding the rated current when it detects signs of a large current flowing through any of the semiconductor chips based on the detection signal from the current sensor.

[0009] The second semiconductor device of this disclosure comprises a plurality of semiconductor modules, each mounted on a plurality of semiconductor chips connected in parallel; a plurality of current sensors provided corresponding to the semiconductor modules for detecting the current flowing through each semiconductor module; two external connection terminals for connecting the plurality of semiconductor modules to the outside; capacitors connected in parallel to the plurality of semiconductor modules; and a control device that outputs an on / off signal to each of the plurality of semiconductor chips having a switching function in each semiconductor module. The control device, for each semiconductor module, outputs an on signal to all other semiconductor chips that have not been detected as showing signs of high current when it detects, based on the detection signals of the current sensors, that a high current exceeding the rated current is flowing through any of the semiconductor chips.

[0010] The power converter of this disclosure comprises six arms, each consisting of two or more semiconductor devices connected in series, three AC terminals, and two DC terminals, with each arm connected in series to each of the six terminals, which are all possible combinations between the three AC terminals and the two DC terminals.

[0011] According to the semiconductor module of this disclosure, even if the wall thickness is insufficient to withstand an explosion in a small compartment adjacent to the wall, if it can withstand an explosion in a small compartment separated by one or more small compartments, the entire semiconductor module can achieve explosion-proof and post-failure energization functions. This allows the walls between small compartments to be made thinner, and enables the realization of a small and lightweight semiconductor module even when multiple semiconductor chips are mounted in parallel.

[0012] According to the first and second semiconductor devices of this disclosure, even if one of the semiconductor chips fails and a large fault current begins to rise, the extent of the explosion can be suppressed. Specifically, when an abnormal current rise is detected by a current sensor during the process of the fault current rising, the control device transmits an ON signal to all other semiconductor chips that have not detected any signs of a large current. By actively diverting the current to the semiconductor chip that receives the ON signal, a portion of the electrical energy stored in the circuit is not consumed by the failed semiconductor chip, thereby suppressing the extent of the explosion. Therefore, depending on the amount of explosion energy that can be suppressed, it becomes possible to reduce the thickness of the explosion-proof wall of the semiconductor module or increase the power capacity of the power converter, which means that the overall size and weight of the power converter per rated power capacity can be reduced.

[0013] According to the power conversion device of this disclosure, each semiconductor device constituting the power conversion device can be made smaller and lighter, thus enabling the overall power conversion device to be made smaller and lighter.

[0014] This is a top view showing the main part of a semiconductor module according to Embodiment 1 of the present disclosure. This is a cross-sectional view showing the main part of a semiconductor module according to Embodiment 1 of the present disclosure. This is a top view showing the main part of a semiconductor module according to Embodiment 1 of the present disclosure. This is a cross-sectional view showing the main part of a semiconductor module according to Embodiment 1 of the present disclosure. This is a cross-sectional view showing the main part of a semiconductor module according to Embodiment 1 of the present disclosure. This is a top view showing the main part of a semiconductor module according to Modification 1a of Embodiment 1 of the present disclosure. This is a top view showing the main part of a semiconductor module according to Modification 1b of Embodiment 1 of the present disclosure. This is a top view showing the main part of a semiconductor module according to Modification 1c of Embodiment 1 of the present disclosure. This is a block diagram showing the configuration of a semiconductor device according to Embodiment 2 of the present disclosure. This is a block diagram showing the configuration of a semiconductor device according to Embodiment 2 of the present disclosure. This is a block diagram showing the configuration of a power converter according to Embodiment 2 of the present disclosure.

[0015] 1. Embodiment 1 Figure 1 is a top view showing the main part of a semiconductor module 1 according to Embodiment 1 of this disclosure. Figure 2 is a cross-sectional view of the main part of the semiconductor module 1 shown in Figure 1, taken along cross-section A-A'.

[0016] Multiple flat semiconductor chips 2 are mounted on a flat base plate 4 made of a metal such as copper or aluminum. Figure 1 shows 40 semiconductor chips 2 mounted, but the number of semiconductor chips 2 is a design requirement and is not limited. These semiconductor chips 2 are, for example, silicon diodes having an anode and a cathode, which can control the current flowing through the semiconductor module 1. In addition to diodes, the semiconductor chips 2 may also be IGBTs (insulated gate bipolar transistors) or MOSFETs (metal-oxide-semiconductor field-effect transistors) that have switching functions. Regarding semiconductor materials, various materials other than silicon, such as silicon carbide and gallium nitride, are known and are not particularly limited.

[0017] The flat semiconductor chip 2 has a first main surface 21 that is in contact with the base plate 4, and a second main surface 22 provided on the surface opposite to the first main surface 21. Thin-film electrodes made of metal such as aluminum are formed on the first main surface 21 to conduct electricity to the semiconductor chip 2.

[0018] Figure 3 illustrates the second main surface 22 of the semiconductor chip 2. A thin-film chip electrode 23 made of a metal such as aluminum is formed on a part of the second main surface 22. When a semiconductor chip 2 with a switching function such as an IGBT is mounted as the semiconductor chip 2, auxiliary electrodes for current control are provided on the second main surface 22 of the semiconductor chip 2, and some kind of wiring is required as a current supply path to the auxiliary electrodes, but these are omitted in the figure. Also, when a temperature sensor and a current sensor 101 are mounted on the semiconductor chip 2, auxiliary electrodes and wiring to those auxiliary electrodes are required for each sensor, but these are also omitted.

[0019] The semiconductor module 1 will be described in detail based on Figures 1 and 2.

[0020] 1-1. Configuration of Semiconductor Module 1 The semiconductor module 1 is equipped with multiple semiconductor chips 2. The interior of the semiconductor module 1 is divided into multiple sub-compartments 5, and each sub-compartment 5 is surrounded by a wall. All sub-compartments 5 are adjacent to at least one other sub-compartment 5 via a wall. Four or more sub-compartments 5 are provided, and semiconductor chips 2 are arranged in at least two of the four sub-compartments 5. Each chip arrangement sub-compartment 12, which is a sub-compartment 5 on which semiconductor chips 2 are arranged, has one or more other chip arrangement sub-compartments 12 that are not adjacent to it.

[0021] According to this disclosure, even if the thickness of the wall is insufficient to withstand an explosion in the small compartment 5 adjacent to the wall, if it can withstand an explosion in a small compartment 5 separated by one or more small compartments 5, the semiconductor module 1 as a whole can achieve explosion-proof functionality and post-failure power-on functionality. Therefore, the walls between the small compartments 5 can be made thinner, and a small and lightweight semiconductor module 1 can be realized even if the semiconductor chips 2 mounted on it are arranged in multiple parallels.

[0022] As described above, the semiconductor module 1 is divided into multiple sub-compartments 5 by an insulating explosion-proof wall 3. Multiple semiconductor chips 2 are mounted in each of the divided sub-compartments 5. In this embodiment, it is divided into four sub-compartments 5, with 10 semiconductor chips 2 mounted in each sub-compartment 5, and 40 semiconductor chips 2 are mounted in the semiconductor module 1 as a whole. The number of divisions of the semiconductor module 1 (number of sub-compartments 5) and the number of semiconductor chips 2 mounted in each sub-compartment 5 are not limited to four and ten, respectively, and may be changed as appropriate to satisfy the required current capacity, the number of semiconductor chips 2 required to maintain the power supply function after a failure, and the dimensional constraints (aggregation ratio) required for the semiconductor module 1. The number of semiconductor chips 2 mounted in each divided sub-compartment 5 may be the same in all sub-compartments 5, or it may differ in some sub-compartments 5 from that of others.

[0023] As shown in Figure 2, the explosion-proof wall 3 is molded into a shape having multiple cylindrical spaces. One end of the cylindrical explosion-proof wall 3 is in contact with the base plate 4. To ensure the strength required for explosion protection, it is desirable that the explosion-proof wall 3 be manufactured as a single component for each semiconductor module 1. As the material for the explosion-proof wall 3, so-called engineering plastics such as Teflon® and polyphenylene sulfide can be used as a material that has high mechanical strength and heat resistance and is also lightweight. The most suitable material may be selected according to heat resistance, moldability, and other design requirements.

[0024] Figure 4 is a cross-sectional view showing the main part of the semiconductor module 1. In addition to the structure shown in Figure 2, the semiconductor module 1 includes an upper contact 6 that contacts the chip-top electrode 23 of the semiconductor chip 2, an upper electrode 7 made of a low-resistance metal such as copper that is in electrical and mechanical contact with the upper contact 6, and a case 8 for holding the upper electrode 7 while applying a downward pressure. The case 8 is made of an electrically insulating material and is fixed to the base plate 4 with bolts (not shown).

[0025] Figure 5 is a cross-sectional view showing an example of the internal structure of the upper contact 6. The upper contact 6 consists of a spring 9, a contact case 10, and a movable element 11. The spring 9 is located inside the contact case 10. One end of the spring 9 protrudes from the contact case 10 and strikes the upper electrode when assembled with the upper electrode 7, while the other end of the spring 9 strikes the movable element 11.

[0026] When the semiconductor module 1 is assembled, the spring 9 is preferably designed to be compressed beyond its natural length. With this configuration, the movable element 11 is pressed against and fixed to the chip-top electrode 23 of the semiconductor chip 2. This reduces the contact resistance of the pressure contact area between the movable element 11 and the chip-top electrode 23 of the semiconductor chip 2, thereby achieving reliable electrical contact. The configuration of the upper contact element 6 shown here is just one example, and other configurations may be used as long as good electrical contact can be achieved between the upper electrode 7 and the chip-top electrode 23 of the semiconductor chip 2.

[0027] In Figure 5, a wound coil spring 9 is shown, but other springs of any shape, such as disc springs or leaf springs, may be used depending on the spring constant and length design.

[0028] The structure of the semiconductor module 1 in this embodiment will now be described in detail. In this embodiment, as described above, the interior of the semiconductor module 1 is divided into a plurality of small compartments 5, and each small compartment 5 is surrounded by a wall. All small compartments 5 are adjacent to at least one other small compartment 5 via a wall. Four or more small compartments 5 are provided, and semiconductor chips 2 are arranged in at least two of the four small compartments 5. Each of the chip placement compartments 12, which are small compartments 5 on which semiconductor chips 2 are arranged, has one or more other chip placement compartments 12 that are not adjacent to it.

[0029] This configuration allows for damage to the sub-compartment 5 containing the exploded semiconductor chip 2 and adjacent sub-compartments 5, while preserving the structure in at least one sub-compartment, thereby securing a power supply path after the failure. As a result, the entire semiconductor module 1 retains power supply functionality after failure, and the entire semiconductor module 1 can be manufactured in a smaller and lighter form.

[0030] Furthermore, the wall thickness of a sub-compartment 5 adjacent to another sub-compartment 5 is thinner than the wall thickness of a sub-compartment 5 not adjacent to another sub-compartment 5. In other words, the explosion-proof wall 3 located between two sub-compartments 5 is thinner than the explosion-proof wall 3 located on the outer perimeter of the semiconductor module 1, on which one side does not touch a sub-compartment 5.

[0031] If we consider the maximum expected explosion energy, the thickness of the explosion-proof wall 3 required to achieve explosion protection with only one wall 3 is d, and the thickness required to achieve explosion protection with two walls 3 is d', then the relationship is d > d'. Here, while setting the outermost thickness of the explosion-proof wall 3 to d, the thickness of the explosion-proof wall 3 between adjacent sub-compartments 5 can be set to d', which is smaller than d. With this configuration, it is possible to prevent damage to the outermost explosion-proof wall 3 while allowing damage to the inner explosion-proof wall 3, thereby suppressing the effects of the explosion on the outside of the semiconductor module 1.

[0032] Several patterns can be considered as more specific arrangement methods. Four or more sub-sections 5 are provided, and all sub-sections 5 are arranged in a single line.

[0033] In other words, as shown in Figure 1, four small compartments 5 can be provided and arranged in a line. If an explosion occurs in the leftmost small compartment 5, the leftmost small compartment 5 and the second small compartment 5 from the left will be damaged, but the third and fourth small compartments 5 from the left will not be affected by the explosion and can remain as a power supply path. Similarly, if an explosion occurs in the second small compartment 5 from the left, the small compartments 5 up to the third small compartment from the left will be damaged, but the fourth small compartment 5 from the left will not be affected by the explosion and can remain as a power supply path. In this way, no matter which small compartment 5 explodes, there will always be at least one small compartment 5 that is not adjacent to the exploded small compartment 5. This configuration allows for miniaturization and weight reduction while ensuring power supply functionality even in the event of a malfunction.

[0034] 1-2. Modification 1a of Embodiment 1 Figure 6 shows a different example of the specific arrangement method of the small compartments 5 in the semiconductor module 1 according to Modification 1a of Embodiment 1. In this embodiment, nine or more small compartments 5 are provided, and the nine small compartments 5 are arranged in a 3x3 grid. The central small compartment 5 of the nine small compartments 5 does not have a semiconductor chip 2, while the other eight small compartments 5 have semiconductor chips 2.

[0035] In other words, the sub-compartments 5 are arranged in a 3x3 grid, and furthermore, only the central sub-compartment 5 is left without a semiconductor chip 2 inside. In this case, if an explosion occurs in a chip-placement sub-compartment 12 located at any of the four corners, the chip-placement sub-compartment 12 where the explosion occurred and the two adjacent chip-placement sub-compartments 12 will be damaged, but the remaining five chip-placement sub-compartments 12 will remain unaffected. Also, if an explosion occurs in a chip-placement sub-compartment 12 other than a corner, the chip-placement sub-compartment 12 where the explosion occurred and the four adjacent chip-placement sub-compartments 12 will be damaged, but the remaining three chip-placement sub-compartments 12 will remain unaffected. If a semiconductor chip 2 is placed in the central sub-compartment 5 and an explosion occurs in the central sub-compartment 5, all eight adjacent sub-compartments 5 will be damaged, and the number of unaffected chip-placement sub-compartments 12 will be zero. In this way, even if an explosion occurs in any of the chip placement compartments 12, there will be at least three chip placement compartments 12 that are not adjacent to the exploded chip placement compartment 12, ensuring that the power supply function in the event of a failure is maintained.

[0036] 1-3. Modification 1b of Embodiment 1 Figure 7 shows a different example of the specific arrangement method of the small compartments 5 in the semiconductor module 1 according to Modification 1b of Embodiment 1. In this embodiment, M × N or more small compartments 5 are provided, where M is a natural number of 1 or more, N is a natural number of 4 or more, and the M × N small compartments 5 are arranged in an M × N grid.

[0037] In this example, the sub-compartments 5 are arranged in a 4x4 grid. A semiconductor chip 2 is placed in all of the sub-compartments 5. In this example, the greatest amount of damage to sub-compartments 5 occurs when an explosion occurs in one of the four sub-compartments 5 closest to the center of the rectangular base plate 4, damaging a total of nine sub-compartments 5: the sub-compartment 5 where the explosion occurred and eight adjacent sub-compartments 5. In this case, seven sub-compartments 5 can be spared from the effects of the explosion. The arrangement method is not limited to a 4x4 grid. As mentioned above, depending on the design constraints of the semiconductor module 1, such as the number of chips mounted, the sub-compartments 5 may be divided into M x N using any natural number M greater than or equal to 1 and any natural number N greater than or equal to 4.

[0038] 1-4. Modification 1c of Embodiment 1 Figure 8 shows a different example of the specific arrangement method of the small compartments 5 in the semiconductor module 1 according to Modification 1c of Embodiment 1. In this embodiment, four or more natural number N rectangular small compartments 5 are provided on the same plane (in this example, on one surface of the base plate 4) when viewed in a direction perpendicular to the plane (in this example, one surface of the base plate 4). When i is increased by one from 1 to (N-1), the short side of the i-th small compartment 5 touches the long side of the (i+1)th small compartment 5, and the short side of the N-th small compartment 5 touches the long side of the first small compartment 5. Semiconductor chips 2 are arranged in the N small compartments 5. An (N+1)th small compartment 5 is provided surrounded by the N small compartments 5, and no semiconductor chips 2 are arranged in the (N+1)th small compartment 5.

[0039] That is, four or more rectangular compartments 5 are arranged in the same plane, with a natural number N in total, where the short side of the first rectangle touches the long side of the second rectangle, the short side of the second rectangle touches the long side of the third rectangle, and so on. This relationship is repeated until the short side of the (N-1)th rectangle touches the long side of the Nth rectangle, and finally the short side of the Nth rectangle touches the long side of the first rectangle. An (N+1)th region exists in the center surrounded by the N rectangles, and no semiconductor chip 2 is placed in this (i+1)th region.

[0040] With this configuration, even if an explosion occurs in any of the chip placement sub-compartments 12, at least the chip placement sub-compartments 12 will not be affected by the explosion. If, for example, a semiconductor chip 2 is mounted in the (N+1)th sub-compartment 5 and an explosion occurs in the (N+1)th sub-compartment 5, all N chip placement sub-compartments 12 will be damaged, and the number of unaffected chip placement sub-compartments 12 will be zero. Figure 8 illustrates an example where N=4, but the same effect can be obtained even if N is a natural number greater than or equal to 5. For example, if N is 5, five chip placement sub-compartments 12 are arranged in a pentagonal shape, and if N is 6, six chip placement sub-compartments 12 are arranged in a hexagonal shape.

[0041] Although four examples of sub-compartment 5 arrangements have been given above, there are countless ways to arrange sub-compartment 5 that satisfy the requirements of this disclosure, and the arrangement is not limited to any one of them. The arrangement of sub-compartment 5 is closely related to design items such as the dimensions of the semiconductor module 1, the number of semiconductor chips 2 mounted on the semiconductor module 1, and the configuration of the internal circuit, and the optimal arrangement should be selected according to the design.

[0042] 2. Embodiment 2 2-1. Diagram 9 of the configuration of the first semiconductor device 100 shows the configuration of the first semiconductor device 100 according to Embodiment 2 of the present disclosure.

[0043] The first semiconductor device 100 includes a semiconductor module 1 equipped with a plurality of semiconductor chips 2 connected in parallel, two external connection terminals 105 and 106 for connecting the semiconductor module 1 to the outside, a current sensor 101 for detecting the current flowing through the semiconductor module 1, and a control device 102 that outputs an on / off signal to each of the plurality of semiconductor chips 2 having a switching function. Based on the detection signal from the current sensor 101, the control device 102 outputs an on signal to all other semiconductor chips 2 that have not detected any signs of a large current flowing through any of the semiconductor chips 2.

[0044] As described above, the first semiconductor device 100 includes a semiconductor module 1, a current sensor 101, and a control device 102 for the semiconductor module 1. The semiconductor module 1 mounted on the first semiconductor device 100 is the semiconductor module 1 shown in Embodiment 1, and is equipped with multiple semiconductor chips 2, such as IGBTs and MOSFETs, which have a switching function that can change their electrical conductivity state in response to external signals. For example, if one semiconductor chip 2 short-circuits, current concentrates in that one semiconductor chip 2, and a large current exceeding the rated current flows. The current sensor 101 is connected in series with the semiconductor module 1. The current sensor 101 can monitor the current flowing through the semiconductor module 1 and has the function of sending a signal to the control device 102 during the short period of time when the fault current is increasing when a fault current exceeding the rated current flows through the semiconductor module 1.

[0045] The current sensor 101 may be selected such that its output update time is faster than the rise time of the fault current when a fault current exceeding the rating flows through the semiconductor module 1. For the current sensor 101, for example, a Rogowski coil type current sensor is used.

[0046] The control device 102 determines whether there is a sign that a large current exceeding the rated current flows through the semiconductor chip 2 based on the current detection value of the semiconductor module 1 detected by the current sensor 101. For example, when the rising speed of the current detection value exceeds the determination value, the control device 102 determines that there is a sign. Then, when the control device 102 determines that there is a sign, it outputs an on signal to all other semiconductor chips 2 in which no sign of a large current is detected. The current detection cycle and the control cycle for outputting the on signal are made sufficiently shorter than the rise time of the fault current. Alternatively, the control device 102 may provide a dedicated circuit for fault current that detects the current at high speed and outputs the on signal at high speed.

[0047] According to this configuration, the control device 102 can receive the fault current signal emitted by the current sensor 101 and transmit the on signal to all other semiconductor chips 2 during a short time in the process of increasing the fault current.

[0048] Further, even if an accident occurs in the semiconductor chip 2 mounted in any of the small sections 5, the semiconductor chips 2 mounted in all the small sections 5 not affected by other accidents are configured to maintain the switching function. It has a function capable of appropriately transmitting an on signal to all small sections 5 not affected by the accident.

[0049] For example, if an IGBT is mounted as a semiconductor chip 2, and gate signal wiring from the control device 102 to all IGBTs is provided by applying a predetermined voltage between the gate and emitter, and furthermore, the signal lines to each IGBT are transmitted without isolation from each other, then if a short circuit occurs between the gate and emitter on a faulty semiconductor chip 2, it becomes impossible to transmit gate signals to other semiconductor chips 2. To prevent this, it is effective to configure the gate wiring for each small section 5 as an isolated circuit using photocouplers or isolation amplifiers.

[0050] This configuration allows for the suppression of the explosion even if one of the semiconductor chips 2 fails and a large fault current begins to rise. Specifically, when the current sensor 101 detects an abnormal current increase during the process of the fault current rising, the control device 102 transmits an ON signal to the semiconductor chip 2. By actively diverting the current to the semiconductor chip 2 upon receiving the ON signal, a portion of the electrical energy stored in the circuit is not consumed by the failed semiconductor chip 2, thereby suppressing the explosion. Consequently, depending on the amount of explosion energy that can be suppressed, it becomes possible to reduce the thickness of the explosion-proof wall 3 of the semiconductor module 1 or increase the power capacity of the first semiconductor device 100, which means that the overall size and weight of the first semiconductor device 100 per rated power capacity can be reduced.

[0051] 2-2. Diagram 10 of the configuration of the second semiconductor device 104 shows the configuration of the second semiconductor device 104, which is a submodule of the modular multilevel converter.

[0052] The second semiconductor device 104 includes a plurality of semiconductor modules 1, each equipped with a plurality of semiconductor chips 2 connected in parallel; a plurality of current sensors 101 provided corresponding to the semiconductor modules 1 for detecting the current flowing through each semiconductor module 1; two external connection terminals 105 and 106 for connecting the plurality of semiconductor modules 1 to the outside; a capacitor 103 connected in parallel to the plurality of semiconductor modules 1; and a control device 102 that outputs an on / off signal to each of the plurality of semiconductor chips 2 having a switching function in each semiconductor module 1. The control device 102, for each semiconductor module 1, outputs an on signal to all other semiconductor chips 2 that have not detected any signs of high current when it detects an indication that a high current exceeding the rated current is flowing through any of the semiconductor chips 2 based on the detection signals from the current sensors 101.

[0053] In this example, at least two semiconductor modules 1 are mounted and connected in series, and the first external connection terminal 105 to an external circuit is connected to the intermediate connection point of the multiple semiconductor modules 1. A large-capacity capacitor 103 is provided in parallel with all the semiconductor modules 1 connected in series, and a second external connection terminal 106 to an external circuit is connected to one terminal of the capacitor 103. A semiconductor module 1 connected between the first external connection terminal 105 and the second external connection terminal 106 without going through the capacitor 103 is designated as semiconductor module B. A semiconductor module 1 connected between the first external connection terminal 105 and the second external connection terminal 106 via the capacitor 103 is designated as semiconductor module A. Semiconductor module A and semiconductor module B may each be multiple semiconductor modules 1 connected in series and parallel, respectively. A current sensor 101 is connected in series with semiconductor module A and semiconductor module B, respectively, and the output signal of each current sensor 101 is input to the control device 102. For example, a Rogowski coil type current sensor is used for each current sensor 101.

[0054] Similar to the control device 102 of the first semiconductor device 100, the control device 102, for each semiconductor module 1, outputs an ON signal to all other semiconductor chips 2 that have not detected any signs of high current flowing through any semiconductor chip 2, based on the detection signal from the current sensor 101.

[0055] With the second semiconductor device 104, similar to the first semiconductor device 100, the current can be diverted to a semiconductor chip 2 in a small compartment 5 within the semiconductor module 1 that is not affected by the explosion, thereby suppressing the degree of the explosion and enabling the second semiconductor device 100 to be made smaller and lighter in terms of rated power capacity.

[0056] 2-3. Figure 11 of the power converter 110 shows a power converter 110 which is a modular multilevel converter configured using a plurality of second semiconductor devices 104 (hereinafter also referred to as submodules 104) as shown in Figure 10.

[0057] The power converter 110 comprises six arms 109, each consisting of two or more (two in this example) second semiconductor devices 104 (submodules 104) connected in series, three AC terminals 107, and two DC terminals 108. Each arm 109 is connected in series to each of the six terminals, which are all possible combinations between the three AC terminals 107 and the two DC terminals 108.

[0058] This configuration allows for miniaturization and weight reduction of the semiconductor module 1 in each second semiconductor device 104 (each submodule 104) of the modular multilevel converter, thus achieving overall miniaturization and weight reduction of the modular multilevel converter.

[0059] Each arm 109 may be configured by connecting two or more (two in this example) first semiconductor devices 100 in series.

[0060] While this disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but are applicable individually or in various combinations to the embodiments. Accordingly, countless variations not illustrated are envisioned within the scope of the art disclosed in this disclosure. For example, these include modifying, adding or omitting at least one component, or extracting at least one component and combining it with a component from another embodiment.

[0061] 1 Semiconductor module, 2 Semiconductor chip, 3 Explosion-proof wall, 4 Base plate, 5 Small compartment, 6 Upper contact, 7 Upper electrode, 8 Case, 9 Spring, 10 Contact case, 11 Movable element, 12 Chip placement compartment, 21 First main surface, 22 Second main surface, 23 Chip upper electrode, 100 Semiconductor device, 101 Current sensor, 102 Control device, 103 Capacitor, 104 Semiconductor device (submodule), 105 External connection terminal, 106 External connection terminal, 107 Three AC terminals, 108 Two DC terminals, 109 Arm, 110 Power converter

Claims

1. A semiconductor module equipped with multiple semiconductor chips, wherein the interior of the semiconductor module is divided into multiple sub-compartments, each sub-compartment is surrounded by a wall, each sub-compartment is adjacent to at least one other sub-compartment via the wall, there are four or more sub-compartments, and semiconductor chips are arranged in at least two of the four sub-compartments, and each of the chip arrangement sub-compartments in which the semiconductor chips are arranged has one or more other chip arrangement sub-compartments that are not adjacent to the chip arrangement sub-compartment.

2. The semiconductor module according to claim 1, wherein the thickness of the wall in a portion of a sub-compartment adjacent to another sub-compartment is thinner than the thickness of the wall in a portion of a sub-compartment not adjacent to another sub-compartment.

3. The semiconductor module according to claim 1 or 2, wherein four or more of the sub-compartments are provided, and all of the sub-compartments are arranged in a line.

4. The semiconductor module according to claim 1 or 2, wherein nine or more sub-compartments are provided, the nine sub-compartments are arranged in a 3x3 grid, the central sub-compartment of the nine sub-compartments does not contain the semiconductor chip, and the other eight sub-compartments contain the semiconductor chip.

5. The semiconductor module according to claim 1 or 2, wherein M × N or more of the sub-sections are provided, M is a natural number of 1 or more, N is a natural number of 4 or more, and the M × N sub-sections are arranged in an M × N grid.

6. A semiconductor module according to claim 1 or 2, wherein four or more rectangular sub-sections are provided on the same plane when viewed in a direction perpendicular to the plane, and when i is increased by one from 1 to N-1, the short side of the i-th sub-section is in contact with the long side of the (i+1)th sub-section, the short side of the N-th sub-section is in contact with the long side of the first sub-section, the semiconductor chips are arranged in the N sub-sections, and an (N+1)th sub-section is provided surrounded by the N sub-sections, and no semiconductor chips are arranged in the (N+1)th sub-section.

7. A semiconductor device comprising: a semiconductor module equipped with the plurality of semiconductor chips connected in parallel as described in claim 1; two external connection terminals for connecting the semiconductor module to the outside; a current sensor for detecting the current flowing through the semiconductor module; and a control device that outputs an on / off signal to each of the plurality of semiconductor chips having a switching function, wherein the control device, based on the detection signal of the current sensor, detects an indication that a large current exceeding the rated current is flowing through any of the semiconductor chips, and outputs an on signal to all other semiconductor chips that have not detected an indication of a large current.

8. A semiconductor device comprising: a plurality of semiconductor modules, each mounted on a plurality of semiconductor chips connected in parallel as described in claim 1; a plurality of current sensors provided corresponding to each semiconductor module for detecting the current flowing through each semiconductor module; two external connection terminals for connecting the plurality of semiconductor modules to the outside; capacitors connected in parallel to the plurality of semiconductor modules; and a control device that outputs an on / off signal to each of the plurality of semiconductor chips having a switching function in each semiconductor module, wherein the control device, for each semiconductor module, detects an indication that a large current exceeding the rated current is flowing through any of the semiconductor chips based on the detection signals of the current sensors, and outputs an on signal to all other semiconductor chips that have not detected an indication of a large current.

9. A power converter according to claim 7 or 8, comprising six arms, each having two or more semiconductor devices connected in series, three AC terminals, and two DC terminals, wherein each arm is connected in series to each of the six terminals, which are all possible combinations between the three AC terminals and the two DC terminals.

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