Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a display area (100) and a bezel area (200), wherein the bezel area (200) at least comprises a first bezel area, a second bezel area and corner areas; the display area (100) comprises a plurality of circuit units, and at least one circuit unit comprises a first power line (61), a second power line (62), a first power connection line (73) and a second power connection line (74), the first power line (61) and the first power connection line (73) forming a mesh interconnection structure for transmitting a first power signal, and the second power line (62) and the second power connection line (74) forming a mesh interconnection structure for transmitting a second power signal; and at least one corner area comprises a multiplexer circuit (220) and a bezel power trace (160), the multiplexer circuit being connected to a data signal line (63), and the bezel power trace (160) being connected to the first power line (61).

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate, including a display area and a border area located around the display area. The border area includes at least two first border areas disposed opposite each other in a first direction, two second border areas disposed opposite each other in a second direction, and a corner area connecting the first border areas and the second border areas. The display area and the corner area have a stepped display area boundary, and the first direction and the second direction intersect. The display area includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. At least one circuit unit includes a pixel driving circuit, a first power connection line and a second power line extending along the first direction, a first power line, a second power connection line, and a data signal line extending along the second direction. The pixel driving circuit is configured to... To provide driving current to the connected light-emitting device, the first power line is configured to provide a first power signal to the pixel driving circuit, the data signal line is configured to provide a data signal to the pixel driving circuit, and the second power line is configured to provide a second power signal to the light-emitting device. The first power connection line is connected to the first power line to form a mesh interconnection structure for transmitting the first power signal, and the second power connection line is connected to the second power line to form a mesh interconnection structure for transmitting the second power signal. At least one corner area includes at least one multiplexer circuit and at least one bezel power trace. The multiplexer circuit is connected to the data signal line in the display area, and the bezel power trace is connected to the first power line in the display area.

[0005] In an exemplary embodiment, the bezel power trace includes at least a first connecting line extending along the first direction and a second connecting line extending along the second direction; in the second direction, the first connecting line is disposed on the side of the multiplexing circuit close to the display area and connected to the first power line in the display area; in the first direction, the second connecting line is disposed on the side of the multiplexing circuit away from the display area and connected to the first connecting line.

[0006] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers disposed on the substrate, the first connecting line and the second connecting line being disposed in the same layer and being an integral structure interconnected with each other.

[0007] In an exemplary embodiment, the first power line and the frame power trace are disposed in different conductive layers, and the first power line is connected to the first connecting line through a via.

[0008] In an exemplary embodiment, the plurality of conductive layers include at least a first conductive layer disposed on a substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, and a third conductive layer disposed on a side of the second conductive layer away from the substrate. The first connecting line, the second connecting line, and the second power line are disposed in the first conductive layer, the first power connecting line is disposed in the second conductive layer, and the first power line, the second power connecting line, and the data signal line are disposed in the third conductive layer.

[0009] In an exemplary embodiment, the display area includes at least a first area and a second area. The second area is disposed on both sides of the first area in the first direction. In the first area, the number of circuit units in the multiple unit columns is the same. In the second area, the number of circuit units in the multiple unit columns is different. Along the direction close to the first border area, the number of circuit units in the unit columns gradually decreases. The mesh interconnection structure for transmitting the first power signal and the mesh interconnection structure for transmitting the second power signal are disposed in the first area and the second area.

[0010] In an exemplary embodiment, in at least one circuit unit of the second region, in the second direction, the second power line is disposed on the side of the circuit unit close to the multiplexing circuit, and the second power connection line is connected to the second power line through a via.

[0011] In an exemplary embodiment, the second power line includes at least one straight portion extending along the first direction and at least one bent portion protruding toward the multiplexing circuit, and the second power connection line is connected to the bent portion through the via.

[0012] In an exemplary embodiment, in the first direction, the circuit unit where the bend is located is spaced at least two circuit units from the boundary of the display area.

[0013] In an exemplary embodiment, the display area includes at least a first area and a second area. The second area is disposed on both sides of the first area in the first direction. In the first area, the number of circuit units in the multiple unit columns is the same. In the second area, the number of circuit units in the multiple unit columns is different. Along the direction close to the first border area, the number of circuit units in the unit columns gradually decreases. The mesh interconnection structure for transmitting the first power signal is disposed in the first area and the second area, and the mesh interconnection structure for transmitting the second power signal is disposed only in the first area.

[0014] In an exemplary embodiment, the second power cord is only located in the first area.

[0015] In an exemplary embodiment, the pixel driving circuit includes at least a storage capacitor, the storage capacitor includes at least a first electrode plate and a second electrode plate, the orthographic projection of the second electrode plate on the display substrate at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate; in at least one unit row, a plurality of second electrode plates are interconnected by plate electrode connecting strips to form the first power connection line.

[0016] In an exemplary embodiment, at least one circuit unit further includes a first initial signal line extending along the first direction and a first initial connection line extending along the second direction, the first initial signal line being configured to provide a first initial signal to the pixel driving circuit, and the first initial connection line being connected to the first initial signal line to form a mesh interconnection structure for transmitting the first initial signal in the display area.

[0017] In an exemplary embodiment, at least one circuit unit further includes a second initial signal line extending along the first direction and a second initial connection line extending along the second direction. The second initial signal line is configured to provide a second initial signal to the pixel driving circuit, and the second initial connection line is connected to the second initial signal line to form a mesh interconnection structure for transmitting the second initial signal in the display area.

[0018] In an exemplary embodiment, the first initial connection line is disposed in a first unit column near the boundary of the display area, the second initial connection line is disposed in a second unit column on the side of the first unit column away from the boundary of the display area, and the second power connection line is disposed in a third unit column on the side of the second unit column away from the boundary of the display area.

[0019] In an exemplary embodiment, at least one corner region includes at least one capacitor bank, the capacitor bank including a plurality of compensation capacitors arranged sequentially along the first direction, the at least one compensation capacitor including a first compensation plate and a second compensation plate, the orthographic projection of the second compensation plate on the display substrate at least partially overlaps with the orthographic projection of the first compensation plate on the display substrate, the first compensation plate is connected to the data signal line, and the second compensation plate is connected to the first power line.

[0020] In an exemplary embodiment, in at least one capacitor bank, a plurality of first compensation plates are spaced apart in the first direction, and a plurality of second compensation plates are an integral structure interconnected with each other.

[0021] In an exemplary embodiment, in at least one capacitor bank, an isolation strip is provided between two adjacent first compensation plates.

[0022] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a semiconductor layer disposed on a substrate, a first conductive layer disposed on the semiconductor layer on a side away from the substrate, a second conductive layer disposed on the first conductive layer on a side away from the substrate, and a third conductive layer disposed on the second conductive layer on a side away from the substrate. The first compensation electrode is disposed in the first conductive layer, the second compensation electrode is disposed in the second conductive layer, the first power line and the data signal line are disposed in the third conductive layer, and the isolation strip is disposed in the semiconductor layer.

[0023] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0024] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0025] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0026] Figure 1 is a schematic diagram of the structure of a display device;

[0027] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0028] Figure 3 is a schematic diagram of the planar structure of the display area in a display substrate;

[0029] Figure 4 is a schematic cross-sectional view of the display area in a display substrate;

[0030] Figure 5 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0031] Figure 6 is a schematic diagram of a mesh interconnection structure in a display area according to an exemplary embodiment of the present disclosure;

[0032] Figure 7 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0033] Figure 8 is a schematic diagram of the semiconductor layer pattern formed on the display substrate of this disclosure;

[0034] Figures 9A and 9B are schematic diagrams of the display substrate after the formation of the first conductive layer pattern;

[0035] Figures 10A and 10B are schematic diagrams of the display substrate after the formation of the second conductive layer pattern;

[0036] Figure 11 is a schematic diagram of the display substrate after the formation of the third insulating layer pattern;

[0037] Figures 12A and 12B are schematic diagrams of the display substrate after the formation of the third conductive layer pattern;

[0038] Figure 13 is a schematic diagram of another display area mesh interconnection structure of an exemplary embodiment of the present disclosure;

[0039] Figure 14 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0040] Figure 15 is a schematic diagram of the structure of a compensation capacitor according to an exemplary embodiment of the present disclosure;

[0041] Figure 16 is a schematic diagram of the structure of another compensation capacitor in an exemplary embodiment of this disclosure.

[0042] Explanation of reference numerals in the attached figures: 11—First active layer; 12—Second active layer; 13—Third active layer; 14—Fourth active layer; 15—Fifth active layer; 16—Sixth active layer; 17—Seventh active layer; 21—First scan signal line; 22—Second scan signal line; 23—Third scan signal line; 24—Fourth scan signal line; 25—First light emission signal line; 26—Second light emission signal line; 27—Fourth gate electrode; 31—First electrode plate; 32—Second electrode plate; 33—Opening; 34—Electrode plate connecting strip; 41—First initial signal line; 42—Second initial signal line; 43—Shielding electrode; 51—First connecting electrode; 52—Second connecting electrode; 53—Third connecting electrode; 54—Fourth connecting electrode; 55—Fifth connecting electrode; 56—Sixth connecting electrode; 61—First power supply line; 62—Second power line; 62-1—Straight section; 62-2—Bend section; 63—Data signal line; 71—First initial connection line; 72—Second initial connection line; 73—First power connection line; 74—Second power connection line; 100—Display area; 100A—First area; 100B—Second area; 101—Substrate; 102—Driving structure layer; 103—Light-emitting structure layer; 104—Encapsulation structure layer; 110—First selection control line; 111—First selection active layer; 112—First selection gate electrode; 113—First selection source electrode; 114—First selection drain electrode; 115—First data connection line; 120—Second selection control line; 121—Second selection active layer; 122—Second selection gate electrode; 123—Second selection source electrode; 124—Second selection drain electrode; 125—Second data connection line; 130—Third selection control line; 131—Third selection active layer;132—Third selection gate electrode; 133—Third selection source electrode; 134—Third selection drain electrode; 135—Third data connection line; 140—Data signal transmission line; 141—Dummy active layer; 160—Border power supply trace; 161—First connection line; 162—Second connection line; 200—Border area; 201—First border area; 202—Second border area; 211—First corner area; 212—Second corner area; 213—Third corner area; 214—Fourth corner area; 220—Multiple-choice circuit; 301—First compensation plate; 302—Second compensation plate; 401—Isolation strip. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0044] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0045] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0046] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0047] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0048] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the area through which current primarily flows.

[0049] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0050] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0051] In this specification, "parallel" refers to two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" refers to two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0052] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0053] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances, and may include chamfers, curved edges, and other variations. The term "approximately" in this disclosure means that the limits are not strictly defined, and the values ​​are within the allowable range of process and measurement errors.

[0054] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple first light-emitting signal lines (E1 to Eo). n, m, and o can be natural numbers. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the first light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines DATA1, D2, D3, ..., Dn. For example, the data driver can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines DATA1 to Dn on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to the scan signal lines S1 to Sm. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. A light-emitting driver can generate transmit signals to be provided to the first light-emitting signal lines EM1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light-emitting driver can sequentially provide transmit signals with off-level pulses to the first light-emitting signal lines EM1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0055] Figure 2 is a schematic diagram of a planar structure of a display substrate, illustrating a display substrate with rounded corners in the display area. As shown in Figure 2, on a plane parallel to the display substrate, the display substrate may include a display area 100 and a border area 200 located around the display area 100. In an exemplary embodiment, the display area 100 may include a first edge (left edge) and a second edge (right edge) disposed opposite to each other in a first direction X, and a third edge (upper edge) and a fourth edge (lower edge) disposed opposite to each other in a second direction Y. Adjacent edges are connected by arc-shaped chamfers to form a rounded quadrilateral shape, and the first direction X and the second direction Y intersect.

[0056] In an exemplary embodiment, the display area 100 may be a flat area comprising a plurality of sub-pixels forming a pixel array, the plurality of sub-pixels being configured to display moving or still images, and the display area 100 may be referred to as the effective area (AA). In an exemplary embodiment, the display substrate may be deformable, for example, rolled up, bent, folded, or rolled up.

[0057] In an exemplary embodiment, the border region 200 may include at least a first border region (left border region and right border region) 201 disposed opposite to each other in the first direction X, a second border region (top border region and bottom border region) 202 disposed opposite to each other in the second direction Y, and a plurality of corner regions connecting the first border region 201 and the second border region 202. The plurality of corner regions may include a first corner region (top left corner region) 211, a second corner region (top right corner region) 212, a third corner region (bottom left corner region) 213 and a fourth corner region (bottom right corner region) 214.

[0058] In an exemplary embodiment, the lower border area may be referred to as the bonding border area, which may include a lead area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area 100. The lead area may include at least multiple data traces and multiple power traces, the driver chip area may include at least an integrated circuit (IC), and the bonding pin area may include at least multiple bonding pads configured to bond to an external flexible printed circuit (FPC).

[0059] In an exemplary embodiment, the first border area 201 may include at least a plurality of cascaded gate driving circuits, which may be respectively connected to the scan signal lines and light emission signal lines in the display area 100. The upper border area may include at least a plurality of detection circuits, which may be respectively connected to the data signal lines in the display area 100; however, this disclosure does not limit the scope of the invention.

[0060] In an exemplary embodiment, the border area 200 may also be provided with at least one isolation dam, which may extend along a direction parallel to the boundary of the display area to form a ring structure surrounding the display area 100. The boundary of the display area may be the edge of the display area near the border area.

[0061] Figure 3 is a schematic diagram of the planar structure of a display area in a display substrate. As shown in Figure 3, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel. The light-emitting unit is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0062] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a green sub-pixel (G) emitting green light, and the third sub-pixel P3 can be a blue sub-pixel (B) emitting blue light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. In some exemplary embodiments, a pixel unit can include four sub-pixels, which can be arranged horizontally side-by-side, vertically side-by-side, in a square, or in a diamond shape, etc., and this disclosure does not limit the arrangement.

[0063] In an exemplary embodiment, taking a pixel unit as an example, which includes three sub-pixels arranged in a horizontal parallel manner, the multiple sub-pixels of the display area can form multiple pixel rows and multiple pixel columns. A pixel row can include multiple sub-pixels arranged sequentially along a first direction X. Multiple pixel rows can be arranged sequentially along a second direction Y. A pixel column can include multiple sub-pixels arranged sequentially along a second direction Y. Multiple pixel columns can be arranged sequentially along a first direction X. The first direction X and the second direction Y intersect.

[0064] In an exemplary embodiment, for a display substrate with rounded corners, the number of sub-pixels differs in multiple pixel rows, or the number of sub-pixels differs in multiple pixel columns. Pixel columns located in the central part of the display area have a larger number of sub-pixels, and the number of sub-pixels in pixel columns gradually decreases along the direction closer to the first border area, resulting in a stepped display area boundary between the display area and the corner area.

[0065] In an exemplary embodiment, the display area may have a center line, and multiple sub-pixels in the display area may be symmetrically arranged relative to the center line. The center line may be a straight line that bisects the display area in a first direction X and extends along a second direction Y.

[0066] Figure 4 is a cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of three sub-pixels in the display area. As shown in Figure 4, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0067] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving structure layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit. The light-emitting structure layer 103 can include at least multiple light-emitting units, each of which can include at least a light-emitting device that emits light of a corresponding color under the drive of the pixel driving circuit. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external water and oxygen cannot enter the light-emitting structure layer 103.

[0068] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 5, the pixel driving circuit can include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to ten signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first light emission signal line EM1, second light emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA, and first power supply line VDD).

[0069] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second terminal of a first transistor, the first terminal of a second transistor T2, the gate electrode of a third transistor T3, and the second terminal of a storage capacitor C. The second node N2 is connected to the first terminal of a third transistor T3, the second terminal of a fourth transistor T4, and the second terminal of a fifth transistor T5. The third node N3 is connected to the second terminals of a second transistor T2, a third transistor T3, and a sixth transistor T6. The fourth node N4 is connected to the second terminal of a sixth transistor T6 and a seventh transistor T7.

[0070] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the first node N1.

[0071] In an exemplary embodiment, the first transistor T1 may be referred to as the first reset transistor. The gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1.

[0072] In an exemplary embodiment, the second transistor T2 can be referred to as a compensation transistor. The gate electrode of the second transistor T2 is connected to the third scan signal line S3, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0073] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0074] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor. The gate electrode of the fourth transistor T4 is connected to the second scan signal line S2, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0075] In an exemplary embodiment, the fifth transistor T5 can be referred to as the first light-emitting control transistor. The gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0076] In an exemplary embodiment, the sixth transistor T6 can be referred to as the second light-emitting control transistor. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0077] In an exemplary embodiment, the seventh transistor T7 can be referred to as the second reset transistor. The gate electrode of the seventh transistor T7 is connected to the fourth scan signal line S4, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0078] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0079] In an exemplary embodiment, the first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS can be configured to provide a constant second voltage signal to the light-emitting device. The voltage of the first voltage signal is greater than the voltage of the second voltage signal, i.e., the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial signal line INIT1 and the second initial signal line INIT2 can be configured to provide constant voltage signals to the pixel driving circuit; this disclosure does not limit the scope of the application.

[0080] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0081] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polycrystalline silicon (LTPS) transistors, or oxide transistors, or a combination of both. The active layer of the LTPS transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide transistor is made of oxide semiconductor. LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and oxide transistors onto a single display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0082] In an exemplary embodiment, in the pixel driving circuit shown in FIG5, the first transistor T1 to the seventh transistor T7 are all low-temperature polysilicon transistors (P-type transistors).

[0083] An exemplary embodiment of this disclosure provides a display substrate. In an exemplary embodiment, the display substrate includes a display area and a border area located around the display area. The border area includes at least two first border areas disposed opposite each other in a first direction, two second border areas disposed opposite each other in a second direction, and a corner area connecting the first border areas and the second border areas. The display area and the corner area have a stepped display area boundary, and the first direction and the second direction intersect. The display area includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. At least one circuit unit includes a pixel driving circuit, a first power connection line and a second power line extending along the first direction, a first power line, a second power connection line, and a data signal line extending along the second direction. The pixel driving circuit is configured to... A driving current is provided to the connected light-emitting device. The first power line is configured to provide a first power signal to the pixel driving circuit, the data signal line is configured to provide a data signal to the pixel driving circuit, and the second power line is configured to provide a second power signal to the light-emitting device. The first power connection line is connected to the first power line to form a mesh interconnection structure for transmitting the first power signal, and the second power connection line is connected to the second power line to form a mesh interconnection structure for transmitting the second power signal. At least one corner area includes at least one multiplexing circuit and at least one bezel power trace. The multiplexing circuit is connected to the data signal line in the display area, and the bezel power trace is connected to the first power line in the display area.

[0084] In an exemplary embodiment, the bezel power trace includes at least a first connecting line extending along the first direction and a second connecting line extending along the second direction; in the second direction, the first connecting line is disposed on the side of the multiplexing circuit close to the display area and connected to the first power line in the display area; in the first direction, the second connecting line is disposed on the side of the multiplexing circuit away from the display area and connected to the first connecting line.

[0085] In an exemplary embodiment, the display area includes at least a first area and a second area. The second area is disposed on both sides of the first area in the first direction. In the first area, the number of circuit units in the multiple unit columns is the same. In the second area, the number of circuit units in the multiple unit columns is different. Along the direction close to the first border area, the number of circuit units in the unit columns gradually decreases. The mesh interconnection structure for transmitting the first power signal and the mesh interconnection structure for transmitting the second power signal are disposed in the first area and the second area.

[0086] In an exemplary embodiment, the display area includes at least a first area and a second area. The second area is disposed on both sides of the first area in the first direction. In the first area, the number of circuit units in the multiple unit columns is the same. In the second area, the number of circuit units in the multiple unit columns is different. Along the direction close to the first border area, the number of circuit units in the unit columns gradually decreases. The mesh interconnection structure for transmitting the first power signal is disposed in the first area and the second area, and the mesh interconnection structure for transmitting the second power signal is disposed only in the first area.

[0087] Figure 6 is a schematic diagram of a mesh interconnection structure in a display area according to an exemplary embodiment of the present disclosure. In a direction perpendicular to the display substrate, the display area may include at least a driving structure layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. In a plane parallel to the display substrate, the display substrate may include a display area and a border area located around the display area. The driving structure layer of the display area may include multiple circuit units forming multiple unit rows and multiple unit columns. A unit row may include multiple circuit units sequentially arranged along a first direction X, and a unit column may include multiple circuit units sequentially arranged along a second direction Y. Each circuit unit may include at least a pixel driving circuit. The light-emitting structure layer of the display area may include multiple light-emitting units forming multiple light-emitting rows and multiple light-emitting columns. A light-emitting row may include multiple light-emitting units sequentially arranged along the first direction X, and a light-emitting column may include multiple light-emitting units sequentially arranged along the second direction Y. Each light-emitting unit may include at least a light-emitting device.

[0088] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to a pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to a light-emitting device. In exemplary embodiments, the orthographic projection of the light-emitting unit on the substrate and the orthographic projection of the circuit unit on the substrate may at least partially overlap, or the orthographic projection of the light-emitting unit on the substrate and the orthographic projection of the circuit unit on the substrate may not overlap.

[0089] In an exemplary embodiment, "first direction X" in this disclosure and the accompanying drawings refers to a direction from left to right. In the left region of the display area, first direction X refers to the direction from the left edge of the display area to the center line of the display area; in the right region of the display area, first direction X refers to the direction from the center line of the display area to the right edge of the display area.

[0090] In this embodiment and subsequent embodiments, the left-side area of ​​the display area is used as an example. Subpixels are defined by circuit units, where one circuit unit is one subpixel, one circuit row is one pixel row, and one circuit column is one pixel column. In some possible implementations, subpixels can be defined by light-emitting units, where one light-emitting unit is one subpixel, one light-emitting row is one pixel row, and one light-emitting column is one pixel column. This disclosure does not limit the scope of the invention.

[0091] In an exemplary embodiment, the display area may include multiple first power lines 61, multiple second power lines 62, multiple first power connection lines 73, and multiple second power connection lines 74. The shapes of the second power lines 62 and the first power connection lines 73 may be straight lines or broken lines extending along the first direction X of the main body. The shapes of the first power lines 61 and the second power connection lines 74 may be straight lines or broken lines extending along the second direction Y of the main body.

[0092] In an exemplary embodiment, the first power line 61 can be continuously arranged in each unit column of the display area, and the first power connection line 73 can be continuously arranged in each unit row of the display area. Multiple first power lines 61 are connected to multiple first power connection lines 73 respectively, and the first power lines 61 and the first power connection lines 73 form a mesh-like interconnected structure in the display area for transmitting the first power signal.

[0093] In an exemplary embodiment, the second power line 62 can be continuously arranged in each cell row of the display area, and the second power connection line 74 can be continuously arranged in each cell column of the display area. Multiple second power connection lines 74 are respectively connected to multiple second power lines 62, and the second power lines 62 and the second power connection lines 74 form a mesh-like interconnected structure in the display area for transmitting the second power signal.

[0094] In an exemplary embodiment, the display area may include a first area 100A and a second area 100B, wherein the second area 100B may be disposed on both sides of the first area 100A in a first direction X. In the first area 100A, the number of circuit units in the multiple unit columns may be substantially the same. In the second area 100B, the number of circuit units in the multiple unit columns is different. Along the direction close to the first border area, the number of circuit units in the unit columns of the second area 100B gradually decreases. That is, the first area 100A is not adjacent to the corner area in the border area, while the second area 100B is adjacent to the corner area in the border area.

[0095] In an exemplary embodiment, both the mesh interconnection structure for transmitting the first power signal and the mesh interconnection structure for transmitting the second power signal are disposed in the first region 100A and the second region 100B.

[0096] This disclosure, by setting a mesh connection structure for transmitting a first power signal and a mesh connection structure for transmitting a second power signal within the display area, can not only effectively reduce the resistance of the power line, reduce the voltage drop of the power signal, effectively improve the uniformity of the power signal, effectively improve the uniformity of the display, and improve the display quality, but also effectively reduce the power consumption of the display device.

[0097] Figure 7 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 7, in an exemplary embodiment, the display substrate may include a display area and a border area located around the display area. The border area includes at least two first border areas disposed opposite each other in a first direction X, two second border areas disposed opposite each other in a second direction Y, and a corner area connecting the first border areas and the second border areas. The display area and the corner area have a stepped display area boundary BY. Figure 7 illustrates the structure of the third corner area (lower left corner area) and the display area nearby in the display substrate.

[0098] In an exemplary embodiment, the display area may include at least a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns, and at least one circuit unit may include a pixel driving circuit configured to provide driving current to a connected light-emitting device.

[0099] In an exemplary embodiment, at least one circuit unit may further include a first power line 61, a second power line 62, a first power connection line 73, and a second power connection line 74. The shapes of the second power line 62 and the first power connection line 73 may be straight lines or broken lines with their main portions extending along a first direction X, and the shapes of the first power line 61 and the second power connection line 74 may be straight lines or broken lines with their main portions extending along a second direction Y. The first power line 61 is configured to provide a first power signal to the pixel driving circuit, the second power line 62 is configured to provide a second power signal to the light-emitting device, the first power connection line 73 is connected to the first power line 61 to form a mesh interconnection structure for transmitting the first power signal, and the second power connection line 74 is connected to the second power line 62 to form a mesh interconnection structure for transmitting the second power signal.

[0100] In an exemplary embodiment, the driving structure layer of the display substrate may include at least a first conductive layer (GATE1) disposed on the substrate, a second conductive layer (GATE2) disposed on the side of the first conductive layer away from the substrate, and a third conductive layer (SD1) disposed on the side of the second conductive layer away from the substrate. A second power line 62 may be disposed in the first conductive layer, a first power connection line 73 may be disposed in the second conductive layer, and a first power line 61 and a second power connection line 74 may be disposed in the third conductive layer. The first power line 61 may be connected to the first power connection line 73 via a via, and the second power connection line 74 may be connected to the second power line 62 via a via.

[0101] In an exemplary embodiment, in at least one circuit unit, the pixel driving circuit can be connected to the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the first light emission signal line 25, the second light emission signal line 26, the first initial signal line 41, the second initial signal line 42, the first power supply line 61, and the data signal line 63, respectively. The shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the first light emission signal line 25, the second light emission signal line 26, the first initial signal line 41, and the second initial signal line 42 can be straight lines or broken lines with their main body extending along the first direction X. The shapes of the first power supply line 61 and the data signal line 63 can be straight lines or broken lines with their main body extending along the second direction Y.

[0102] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the fourth scan signal line 24 are configured to provide a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the pixel driving circuit, respectively; the first light emission signal line 25 and the second light emission signal line 26 are configured to provide a first light emission signal and a second light emission signal to the pixel driving circuit, respectively; the first initial signal line 41 and the second initial signal line 42 are configured to provide a first initial signal and a second initial signal to the pixel driving circuit, respectively; and the data signal line 63 is configured to provide a data signal to the pixel driving circuit.

[0103] In an exemplary embodiment, the pixel driving circuit may include a first transistor T1 to a seventh transistor T7. The gate electrode of the first transistor T1 is connected to a first scan signal line 21, and its first terminal is connected to a first initial signal line 41. The second terminal of the first transistor is connected to the first terminal of the second transistor T2 and the gate electrode of the third transistor T3, respectively. The gate electrode of the second transistor T2 is connected to a third scan signal line 23, and its second terminal is connected to the second terminal of the third transistor T3 and the first terminal of the sixth transistor T6, respectively. The first terminal of the third transistor T3 is connected to the second terminals of the fourth transistor T4 and the fifth transistor T5, respectively. The gate electrode of the fourth transistor T4 is connected to a second scan signal line 22, and its first terminal is connected to a data signal line 63. The gate electrode of the fifth transistor T5 is connected to a first light emission signal line 25, and its first terminal is connected to a first power supply line 61. The gate electrode of the sixth transistor T6 is connected to a second light emission signal line 26, and its second terminal is connected to the second terminal of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the fourth scan signal line 24, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42.

[0104] In an exemplary embodiment, the pixel driving circuit may further include a storage capacitor, which may include a stacked first electrode plate and a second electrode plate, wherein the orthographic projection of the second electrode plate onto the substrate at least partially overlaps with the orthographic projection of the first electrode plate onto the substrate. In at least one circuit unit, the first electrode plate may serve as the gate electrode of the third transistor T3. In at least one unit row, a plurality of second electrode plates may be connected together by a plurality of plate connecting strips to form a first power connection line 73 extending along the first direction X of this disclosure.

[0105] In an exemplary embodiment, at least one circuit unit may further include a first initial connection line 71. The shape of the first initial connection line 71 may be a straight line or a broken line extending along the second direction Y. The first initial connection line 71 is connected to the first initial signal line 41 to form a mesh interconnection structure for transmitting the first initial signal in the display area.

[0106] In an exemplary embodiment, at least one circuit unit may further include a second initial connection line 72. The shape of the second initial connection line 72 may be a straight line or a broken line extending along the second direction Y. The second initial connection line 72 is connected to the second initial signal line 42 to form a mesh interconnection structure for transmitting the second initial signal in the display area.

[0107] In an exemplary embodiment, the first initial connection line 71, the second initial connection line 72, and the second power connection line 74 can be respectively arranged in different cell columns, and the first initial connection line 71, the second initial connection line 72, and the second power connection line 74 can be periodically arranged in the first direction X. For example, the first initial connection line 71 can be arranged in the Nth cell column and the N+3rd cell column, the second initial connection line 72 can be arranged in the N+1th cell column and the N+4th cell column, and the second power connection line 74 can be arranged in the N+2th cell column and the N+5th cell column.

[0108] In an exemplary embodiment, at least one corner region (such as the third corner region or the fourth corner region) of the bezel region may include at least one multiplexer circuit (MUX) 220 and at least one bezel power trace 160. The multiplexer circuit 220 may be connected to the data signal line 63 in the display region, and the bezel power trace 160 may be connected to the first power line 61 in the display region.

[0109] In an exemplary embodiment, the bezel power trace 160 may include at least a first connecting line 161 and a second connecting line 162. The shape of the first connecting line 161 may be a straight line or a broken line extending along the first direction X, and the shape of the second connecting line 162 may be a straight line or a broken line extending along the second direction Y. In the second direction Y, the first connecting line 161 may be located on the side of the multiplexing circuit 220 closer to the display area and connected to the two first power lines 61 in the display area. In the first direction X, the second connecting line 162 may be located on the side of the multiplexing circuit 220 away from the display area and connected to the first connecting line 161.

[0110] In an exemplary embodiment, the driving structure layer of the display substrate may include multiple conductive layers disposed on the substrate, and the first connecting line 161 and the second connecting line 162 may be disposed on the same layer and are an integral structure interconnected with each other.

[0111] In an exemplary embodiment, the first power line 61 and the frame power trace 160 can be disposed in different conductive layers, and the first power line 61 can be connected to the first connecting line 161 through a via.

[0112] In an exemplary embodiment, the first connecting line 161 and the second connecting line 162 may be disposed in the first conductive layer.

[0113] In an exemplary embodiment, the second region 100B is provided with a second power line 62 and a second power connection line 74, and the second power connection line 74 is connected to the second power line 62 through a via to form a mesh interconnection structure for transmitting the second power signal in the second region 100B. Since the second power line 62 and the first connection line 161 are arranged on the same layer, the second power line 62 and the second power connection line 74 arranged in the circuit units near the corner area of ​​the second region 100B will affect the connection between the first connection line 161 and the first power line 61.

[0114] In an exemplary embodiment, among the multiple circuit units in the second region 100B near the display area boundary BY, the first initial connection line 71 can be disposed in the first circuit unit closest to the display area boundary BY (such as the circuit unit defined by the Mth unit row and Nth unit column, and the circuit unit defined by the M+1th unit row and N+3th unit column), and the second initial connection line 72 can be disposed in the second circuit unit on the side of the first circuit unit away from the display area boundary BY (such as the circuit unit defined by the Mth unit row and N+1th unit column, the circuit unit defined by the M+1th unit row and N+3th unit column). The second power connection line 74 can be located in the third circuit unit on the side of the second circuit unit away from the display area boundary BY (such as the circuit unit defined by the Mth unit row and the N+2th unit column, the circuit unit defined by the M+1th unit row and the N+5th unit column). This allows the connection position of the second power line 62 and the second power connection line 74 to be as far away from the display area boundary BY as possible, leaving more space for the first connection line 161 so that the first connection line 161 can be connected to the first power line 61 in the two circuit units.

[0115] In an exemplary embodiment, in at least one circuit unit of the second region 100B, a second power line 62 may be disposed on the side of the circuit unit closer to the multiplexing circuit 220 in the second direction Y. The second power line 62 may include at least one straight portion 62-1 and at least one bent portion 62-2. The straight portion 62-1 may be a straight line extending along the first direction X, and the bent portion 62-2 may be an arc shape convex toward the multiplexing circuit 220. The straight portion 62-1 and the bent portion 62-2 are connected, and the second power connection line 74 may be connected to the bent portion 62-2 through a via.

[0116] In an exemplary embodiment, in the first direction X, the circuit unit where the bend 62-2 is located can be spaced at least two circuit units from the display area boundary BY. In the second direction Y, at least a portion of the first connecting line 161 can be disposed between the straight section 62-1 and the multiplexing circuit 220. Thus, except for the downward bend at the via location connecting the second power line 62 and the second power connection line 74, the second power line 62 at other locations can provide more space for the first connecting line 161, allowing the first connecting line 161 to connect to the first power line 61 in two circuit units.

[0117] In some possible implementations, the circuit unit where the bend 62-2 is located may be spaced one circuit unit from the boundary BY of the display area, which is not limited herein.

[0118] In an exemplary embodiment, for the stepped display area boundary BY, in the three circuit units corresponding to each step, the first connecting line 161 can be connected to the first power line 61 in two circuit units, that is, the first connecting line 161 has two access points. Thus, in the second region 100B, every other circuit unit, the frame power trace 160 has two connection points that connect to the first power line 61 in the display area, effectively improving the reliability of the connection between the first power line 61 and the frame power trace 160, and effectively improving the networking performance of the mesh interconnection structure for transmitting the first power signal.

[0119] The following exemplary description illustrates the fabrication process of the display substrate using this exemplary embodiment. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film layer, coating the film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating the organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0120] In an exemplary embodiment, taking the third corner region (lower left corner region) and its surrounding display area in the display substrate as an example, the manufacturing process of the display substrate in this embodiment may include the following operations.

[0121] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a semiconductor thin film on a substrate, patterning the semiconductor thin film by a patterning process, and forming a semiconductor layer pattern on the substrate, as shown in FIG8.

[0122] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the second active layer 12 to the fifth active layer 15 may be an integral structure interconnected with each other, and the sixth active layer 16 and the seventh active layer 17 may be an integral structure interconnected with each other.

[0123] In an exemplary embodiment, the first active layer 11, the second active layer 12 and the fourth active layer 14 may be located on the side opposite to the second direction Y of the third active layer 13, and the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be located on the side of the second direction Y of the third active layer 13.

[0124] In an exemplary embodiment, the first active layer 11 can be shaped like an "n", the second active layer 12 can be shaped like an "L", the third active layer 13 can be shaped like an "Ω", and the fourth active layer 14 to the seventh active layer 17 can be shaped like an "I".

[0125] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 12-2 of the second active layer and the second region 13-2 of the third active layer may be interconnected, and the second region 12-2 of the second active layer may serve as the second region 13-2 of the third active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be interconnected, and the first region 13-1 of the third active layer may simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be interconnected, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first active layer's first zone 11-1, the first active layer's second zone 11-2, the second active layer's first zone 12-1, the fourth active layer's first zone 14-1, the fifth active layer's first zone 15-1, the sixth active layer's first zone 16-1, and the seventh active layer's first zone 17-1 can be set individually.

[0126] In an exemplary embodiment, the first region 11-1 of the first active layer can serve as the first electrode of the first transistor T1, the second region 11-2 of the first active layer can serve as the second electrode of the first transistor T1, the first region 12-1 of the second active layer can serve as the first electrode of the second transistor T2, the second region 12-2 of the second active layer can serve as the second electrode of the second transistor T2, the first region 13-1 of the third active layer can serve as the first electrode of the third transistor T3, the second region 13-2 of the third active layer can serve as the second electrode of the third transistor T3, and the first region 14-1 of the fourth active layer can serve as the fourth transistor T4. The first electrode of the fourth active layer, the second region 14-2, can be used as the second electrode of the fourth transistor T4. The first region 15-1 of the fifth active layer can be used as the first electrode of the fifth transistor T5. The second region 15-2 of the fifth active layer can be used as the second electrode of the fifth transistor T5. The first region 16-1 of the sixth active layer can be used as the first electrode of the sixth transistor T6. The second region 16-2 of the sixth active layer can be used as the second electrode of the sixth transistor T6. The first region 17-1 of the seventh active layer can be used as the first electrode of the seventh transistor T7. The second region 17-2 of the seventh active layer can be used as the second electrode of the seventh transistor T7.

[0127] In an exemplary embodiment, the semiconductor layer pattern in the third corner region of the border region may include at least the first active layer 111 of the first active transistor TF1 to the third active layer 131 of the third active transistor TF3, and a dummy active layer 141.

[0128] In an exemplary embodiment, the first active selection layer 111, the second active selection layer 121, and the third active selection layer 131 can be block-shaped (e.g., rectangular) and arranged sequentially along the first direction X. There can be two of each of the first active selection layer 111, the second active selection layer 121, and the third active selection layer 131, and these two active selection layers can be arranged sequentially along the second direction Y to form a parallel-connected selection transistor.

[0129] In some possible implementations, the first selected active layer 111, the second selected active layer 121, and the third selected active layer 131 can be one, three, or four, and this disclosure does not limit them.

[0130] In an exemplary embodiment, the shape and size of the dummy active layer 141 may be substantially the same as the shape and size of the three selected active layers, and are respectively disposed between the first selected active layer 111 and the second selected active layer 121 and between the second selected active layer 121 and the third selected active layer 131. The dummy active layer 141 is configured to improve etching uniformity.

[0131] In an exemplary embodiment, the semiconductor layer may be polycrystalline silicon (p-Si), meaning that the first transistor T1 to the seventh transistor T7 are LTPS transistors. In an exemplary embodiment, patterning the semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film, then performing a hydrogen removal treatment on the amorphous silicon thin film, and finally performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form a semiconductor layer pattern.

[0132] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a first insulating layer covering the semiconductor layer; and a first conductive layer pattern disposed on the first insulating layer, as shown in Figures 9A and 9B, where Figure 9B is a planar schematic diagram of the first conductive layer in Figure 9A. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0133] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area may include at least a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a fourth scan signal line 24, a first light-emitting signal line 25, a second light-emitting signal line 26, a fourth gate electrode 27, a first electrode plate 31 of a storage capacitor, and a second power supply line 62.

[0134] In an exemplary embodiment, the first electrode plate 31 of the storage capacitor can be rectangular in shape, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the first electrode plate 31 on the substrate and the orthographic projection of the third active layer on the substrate at least partially overlap. The first electrode plate 31 can simultaneously serve as the lower electrode plate of the storage capacitor and the gate electrode of the third transistor T3.

[0135] In an exemplary embodiment, the shape of the first scan signal line 21 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row, and located on the side opposite to the second direction Y of the first electrode plate 31. The area where the first scan signal line 21 overlaps with the first active layer of each circuit unit can serve as the gate electrode of the first transistor T1 of the dual-gate structure.

[0136] In an exemplary embodiment, the shape of the second scan signal line 22 may be a straight line or a broken line extending along the first direction X, and may be continuously arranged in a unit row, and located on the side of the first scan signal line 21 close to the first electrode plate 31. The second scan signal line 22 is configured to be connected to the fourth gate electrode 27 through a subsequently formed third connection electrode.

[0137] In an exemplary embodiment, the third scan signal line 23 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row, located on the side of the second scan signal line 22 near the first electrode plate 31. A gate block 23-1 is provided on the third scan signal line 23. The gate block 23-1 can be a strip shape extending along the second direction Y. The first end of the gate block 23-1 is connected to the third scan signal line 23, and the second end of the gate block 23-1 extends towards the first electrode plate 31. The area where the third scan signal line 23 and the gate block 23-1 overlap with the second active layer of each circuit unit can serve as the gate electrode of the second transistor T2 of the dual-gate structure.

[0138] In an exemplary embodiment, in at least one cell row, the third scan signal line 23 and the gate blocks 23-1 of the plurality of circuit cells can be an integral structure interconnected with each other.

[0139] In an exemplary embodiment, the shape of the fourth scan signal line 24 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row and located on one side of the first electrode plate 31 in the second direction Y. The area where the fourth scan signal line 24 overlaps with the seventh active layer of each circuit unit can serve as the gate electrode of the seventh transistor T7.

[0140] In an exemplary embodiment, the shape of the first light-emitting signal line 25 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row and located on one side of the first electrode plate 31 in the second direction Y. The area where the first light-emitting signal line 25 overlaps with the fifth active layer of each circuit unit can serve as the gate electrode of the fifth transistor T5.

[0141] In an exemplary embodiment, the shape of the second light-emitting signal line 26 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row, and located on the side of the first light-emitting signal line 25 away from the first electrode plate 31. The area where the second light-emitting signal line 26 overlaps with the sixth active layer of each circuit unit can serve as the gate electrode of the sixth transistor T6.

[0142] In an exemplary embodiment, the fourth gate electrode 27 may be a strip shape extending along the first direction X, and may be disposed between the third scan signal line 23 and the first electrode plate 31. The region where the fourth gate electrode 27 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4. The fourth gate electrode 27 is configured to be connected to the second scan signal line 22 through a subsequently formed third connection electrode.

[0143] In an exemplary embodiment, the second power line 62 may be a zigzag line extending along the first direction X, may be continuously arranged in a unit row, and may be located on the side of the fourth scan signal line 24 away from the first electrode plate 31.

[0144] In an exemplary embodiment, the second power line 62 may include at least one straight portion 62-1 and at least one bent portion 62-2. The straight portion 62-1 may be a straight line extending along a first direction X and may be disposed on the side of the circuit unit near the plurality of selected active layers. The bent portion 62-2 may be an arc shape convex toward the plurality of selected active layers and may be disposed on one side of the straight portion 62-1. The straight portion 62-1 is connected to the bent portion 62-2, and the bent portion 62-2 is configured to be connected to a subsequently formed second power connection line.

[0145] In an exemplary embodiment, among the multiple circuit units near the display area boundary BY in the display area, the circuit unit containing the bending portion 62-2 may be spaced two circuit units away from the display area boundary BY, so as to be as far away from the display area boundary BY as possible. For example, the bending portion 62-2 may be provided in the circuit unit defined by the Mth unit row and the N+2th unit column. Alternatively, the bending portion 62-2 may be provided in the circuit unit defined by the M+1th unit row and the N+5th unit column.

[0146] In an exemplary embodiment, the first conductive layer pattern in the third corner region of the border area may include at least a first select gate electrode 112, a second select gate electrode 122, a third select gate electrode 132, a border power trace 160, and a plurality of first connection pins.

[0147] In an exemplary embodiment, the first selection gate electrode 112, the second selection gate electrode 122, and the third selection gate electrode 132 can be strip-shaped extending along the second direction Y, and are sequentially arranged along the first direction X. The region where the first selection gate electrode 112 overlaps with the two first selection active layers 111 can serve as the gate electrode of the two first selection transistors TF1, the region where the second selection gate electrode 122 overlaps with the two second selection active layers 121 can serve as the gate electrode of the two second selection transistors TF2, and the region where the third selection gate electrode 132 overlaps with the two third selection active layers 131 can serve as the gate electrode of the two third selection transistors TF3.

[0148] In an exemplary embodiment, the bezel power trace 160 can be zigzag-shaped and may include at least a first connecting line 161 and a second connecting line 162. The first connecting line 161 can be a straight line or a zigzag line extending along a first direction X. In the second direction Y, the first connecting line 161 can be positioned on the side of the plurality of select gate electrodes near the second power line 62. The first connecting line 161 is configured to connect to a first power line subsequently formed in the display area. The second connecting line 162 can be a straight line or a zigzag line extending along the second direction Y. In the first direction X, the second connecting line 162 can be positioned on the side of the plurality of select gate electrodes away from the display area. The first end of the second connecting line 162 is connected to the first connecting line 161, and the second end of the second connecting line 162 can extend along the direction of the display area boundary to the lower bezel area and connect to a bonding pin providing the first power signal.

[0149] In an exemplary embodiment, in the first direction X, the circuit unit where the bent portion 62-2 is located can be spaced at least two circuit units from the display area boundary BY. In the second direction Y, at least a portion of the first connecting line 161 can be disposed between the straight portion 62-1 and the plurality of selection gate electrodes.

[0150] In an exemplary embodiment, the extension length of the bend 62-2 can be approximately 0.4 to 0.6 times the size of the circuit unit to reduce the impact of the second power line 62 on the connection of the first connecting line 161 to the first power line.

[0151] In an exemplary embodiment, a plurality of first connection pins may be disposed on the side of the bezel area close to the display area, and are respectively connected to one or more of the signal lines of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the first light emission signal line 25, and the second light emission signal line 26 via a connecting strip. The plurality of first connection pins are configured to be connected to the output terminal of the gate drive circuit via a subsequently formed connecting line.

[0152] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a second insulating layer covering the first conductive layer pattern; and a second conductive layer pattern disposed on the second insulating layer, as shown in Figures 10A and 10B, where Figure 10B is a planar schematic diagram of the second conductive layer in Figure 10A. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0153] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display area includes at least: a second electrode 32 of a storage capacitor, a first initial signal line 41, a second initial signal line 42, and a shielding electrode 43.

[0154] In an exemplary embodiment, the outline of the second electrode plate 32 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as the upper electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute the storage capacitor.

[0155] In an exemplary embodiment, the second electrode plate 32 is provided with an opening 33. The opening 33 may be rectangular in shape and may be located in the central region of the second electrode plate 32, thereby forming a ring shape. The opening 33 exposes a second insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 onto the substrate includes the orthographic projection of the opening 33 onto the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a subsequently formed seventh via, which is located within the opening 33 and exposes the first electrode plate 31, allowing a subsequently formed first connecting electrode to be connected to the first electrode plate 31.

[0156] In an exemplary embodiment, the second electrode plate 32 may be provided with an electrode connecting strip 34. The shape of the electrode connecting strip 34 may be a strip extending along the first direction X. The electrode connecting strip 34 may be disposed on one side of the second electrode plate 32 in the first direction X or on the opposite side of the first direction X. The first end of the electrode connecting strip 34 is connected to the second electrode plate 32 in this circuit unit, and the second end of the electrode connecting strip 34 is connected to the second electrode plate 32 in an adjacent circuit unit in the first direction X.

[0157] In an exemplary embodiment, in a unit row, the second electrode plates 32 and the multiple plate electrode connecting strips 34 in the multiple circuit units can be an integral structure that is interconnected to form the first power connection line of this disclosure. This can ensure that the multiple second electrode plates in a unit row have the same potential, which is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0158] In an exemplary embodiment, the shape of the first initial signal line 41 can be a straight line or a broken line extending along the first direction X, and it can be disposed on the side of the first scan signal line 21 away from the second electrode plate 32. A first initial connection block 41-1 can be disposed on the first initial signal line 41. The shape of the first initial connection block 41-1 can be block-shaped (such as rectangular), and it is connected to the first initial signal line 41. The first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a subsequently formed fifth connection electrode.

[0159] In an exemplary embodiment, the orthographic projection of the first initial connection block 41-1 on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes in the first transistor T1 on the substrate. The first initial connection block 41-1 can shield the node between the two gate electrodes in the first transistor T1, avoid the impact of data voltage jumps on the first transistor T1, reduce the impact of data voltage jumps on the normal operation of the pixel driving circuit, and improve the display effect.

[0160] In an exemplary embodiment, in at least one unit row, the first initial signal line 41 and the plurality of first initial connection blocks 41-1 can be an integral structure that is interconnected.

[0161] In an exemplary embodiment, the second initial signal line 42 may be a straight line or a broken line extending along the first direction X, and may be disposed between the fourth scan signal line 24 and the second power line 62. A second initial connection block 42-1 may be disposed on the second initial signal line 42. The second initial connection block 42-1 may be block-shaped (e.g., rectangular) and connected to the second initial signal line 42. The second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer through a subsequently formed sixth connection electrode.

[0162] In an exemplary embodiment, in at least one unit row, the second initial signal line 42 and the plurality of second initial connection blocks 42-1 can be an integral structure that is interconnected.

[0163] In an exemplary embodiment, the shielding electrode 43 can be block-shaped (e.g., rectangular) and can be disposed on the side of the second electrode plate 32 near the third scan signal line 23. The first end of the shielding electrode 43 is connected to the side of the second electrode plate 32 near the third scan signal line 23, and the second end of the shielding electrode 43 extends towards the third scan signal line 23. The orthographic projection of the shielding electrode 43 on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes in the second transistor T2 on the substrate. In this exemplary embodiment, the shielding electrode 43 is configured to shield the node between the two gate electrodes in the second transistor T2, preventing the impact of data voltage jumps on the second transistor T2, reducing the impact of data voltage jumps on the normal operation of the pixel driving circuit, and improving the display effect.

[0164] In an exemplary embodiment, in at least one circuit unit, the second electrode 32 and the shielding electrode 43 can be an integral structure that is interconnected.

[0165] In an exemplary embodiment, the second conductive layer pattern in the third corner region of the border area may include at least a data signal transmission line 140 and a plurality of second connection pins.

[0166] In an exemplary embodiment, the data signal transmission line 140 may be a straight line or a broken line extending along the first direction X, and may be disposed on one side of the second direction Y of multiple selected active layers. The data signal transmission line 140 is configured to transmit the data signal of the data driver to the data signal line in the display area.

[0167] In an exemplary embodiment, a plurality of second connection pins may be disposed on the side of the bezel area close to the display area, and are respectively connected to one or two signal lines of the first initial signal line 41 and the second initial signal line 42 via a connecting strip. The plurality of second connection pins are configured to be connected to the initial signal lead in the lower bezel area via a subsequently formed connecting line.

[0168] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, and patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG11.

[0169] In an exemplary embodiment, the plurality of vias of at least one circuit unit in the display area may include at least: a first via V1 to a fifteenth via V15.

[0170] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The first insulating layer, the second insulating layer, and the third insulating layer within the first via V1 are etched away, exposing the surface of the first region of the first active layer. The first via V1 is configured to allow a subsequently formed fifth connection electrode to be connected to the first region of the first active layer through the via.

[0171] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second region of the first active layer onto the substrate. The first insulating layer, the second insulating layer, and the third insulating layer within the second via V2 are etched away, exposing the surface of the second region of the first active layer. The second via V2 is configured to allow a subsequently formed first connection electrode to be connected to the second region of the first active layer through the via.

[0172] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the second active layer onto the substrate. The first insulating layer, the second insulating layer, and the third insulating layer within the third via V3 are etched away, exposing the surface of the first region of the second active layer. The third via V3 is configured to allow a subsequently formed first connection electrode to be connected to the first region of the second active layer through the via.

[0173] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the second region of the second active layer (which is also the second region of the third active layer) onto the substrate. The first, second, and third insulating layers within the fourth via V4 are etched away, exposing the surface of the second region of the second active layer (which is also the second region of the third active layer). The fourth via V4 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the second active layer (which is also the second region of the third active layer) through the via.

[0174] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The first, second, and third insulating layers within the fifth via V5 are etched away, exposing the surface of the first region of the fourth active layer. The fifth via V5 is configured to allow subsequently formed data signal lines to be connected to the first region of the fourth active layer through the via.

[0175] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The first, second, and third insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the fifth active layer. The sixth via V6 is configured to allow a subsequently formed first power line to be connected to the first region of the fifth active layer through the via.

[0176] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the first region of the sixth active layer onto the substrate. The first, second, and third insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the sixth active layer. The seventh via V7 is configured to allow a subsequently formed second connection electrode to be connected to the first region of the sixth active layer through the via.

[0177] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate. The first, second, and third insulating layers within the eighth via V8 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The eighth via V8 is configured to allow a subsequently formed fourth connection electrode to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.

[0178] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the range of the orthographic projection of the first region of the seventh active layer onto the substrate. The first, second, and third insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the seventh active layer. The ninth via V9 is configured to allow the subsequently formed sixth connection electrode to be connected to the first region of the seventh active layer through the via.

[0179] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the opening 33 onto the substrate. The second and third insulating layers within the tenth via V10 are etched away, exposing the surface of the first electrode plate 31. The tenth via V10 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate 31 through the via.

[0180] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the second electrode plate 32 onto the substrate. The third insulating layer within the eleventh via V11 is etched away, exposing the surface of the second electrode plate 32. The eleventh via V11 is configured to allow a subsequently formed first power line to be connected to the second electrode plate 32 through the via.

[0181] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the first initial connection block 41-1 on the substrate of the first initial signal line 41. The third insulating layer in the twelfth via V12 is etched away, exposing the surface of the first initial connection block 41-1. The twelfth via V12 is configured to allow the subsequently formed fifth connection electrode to be connected to the first initial connection block 41-1 through the via.

[0182] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the second initial connection block 42-1 on the substrate of the second initial signal line 42. The third insulating layer in the thirteenth via V13 is etched away, exposing the surface of the second initial connection block 42-1. The thirteenth via V13 is configured to allow the subsequently formed sixth connection electrode to be connected to the second initial connection block 42-1 through the via.

[0183] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the fourth gate electrode 27 on the substrate. The second and third insulating layers within the fourteenth via V14 are etched away, exposing the surface of the fourth gate electrode 27. The fourteenth via V14 is configured to allow a subsequently formed third connection electrode to be connected to the fourth gate electrode 27 through the via.

[0184] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is within the range of the orthographic projection of the second scan signal line 22 on the substrate. The second and third insulating layers within the fifteenth via V15 are etched away, exposing the surface of the second scan signal line 22. The fifteenth via V15 is configured to allow a subsequently formed third connection electrode to be connected to the second scan signal line 22 through the via.

[0185] In an exemplary embodiment, at least one circuit unit in the display area may further include a sixteenth via V16. The orthographic projection of the sixteenth via V16 onto the substrate lies within the orthographic projection of the bend 62-2 of the second power line 62 onto the substrate. The second and third insulating layers within the sixteenth via V16 are etched away, exposing the surface of the bend 62-2. The sixteenth via V16 is configured to allow a subsequently formed second power connection line to connect to the bend 62-2 through the via.

[0186] In an exemplary embodiment, the circuit cell containing the sixteenth via V16 may be spaced two circuit cells away from the display area boundary BY, to be as far away from the display area boundary BY as possible. For example, the sixteenth via V16 may be located in the circuit cell defined by the Mth cell row and the N+2th cell column. Alternatively, the sixteenth via V16 may be located in the circuit cell defined by the M+1th cell row and the N+5th cell column.

[0187] In an exemplary embodiment, the third corner region of the border area may include at least the twenty-first through-hole to the thirty-fifth through-hole V35.

[0188] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the first region of the first selected active layer onto the substrate. The first insulating layer, the second insulating layer, and the third insulating layer within the 21st via V21 are etched away, exposing the surface of the first region of the first selected active layer. The 21st via V21 is configured to allow the subsequently formed first selected source electrode to be connected to the first region of the first selected active layer through the via.

[0189] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate is within the range of the orthographic projection of the second region of the first selected active layer onto the substrate. The first insulating layer, the second insulating layer, and the third insulating layer within the 22nd via V22 are etched away, exposing the surface of the second region of the first selected active layer. The 22nd via V22 is configured to allow the subsequently formed first selected drain electrode to be connected to the second region of the first selected active layer through the via.

[0190] In an exemplary embodiment, the orthographic projection of the 23rd via V23 onto the substrate is within the range of the orthographic projection of the first region of the second selective active layer onto the substrate. The first insulating layer, the second insulating layer, and the third insulating layer within the 23rd via V23 are etched away, exposing the surface of the first region of the second selective active layer. The 23rd via V23 is configured to allow the subsequently formed second selective source electrode to be connected to the first region of the second selective active layer through the via.

[0191] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate is within the range of the orthographic projection of the second region of the second selected active layer onto the substrate. The first insulating layer, the second insulating layer, and the third insulating layer within the 24th via V24 are etched away, exposing the surface of the second region of the second selected active layer. The 24th via V24 is configured to allow the subsequently formed second selected drain electrode to be connected to the second region of the second selected active layer through the via.

[0192] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate is within the range of the orthographic projection of the first region of the third selective active layer onto the substrate. The first, second, and third insulating layers within the 25th via V25 are etched away, exposing the surface of the first region of the third selective active layer. The 25th via V25 is configured to allow the subsequently formed third selective source electrode to be connected to the first region of the third selective active layer through the via.

[0193] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate is within the range of the orthographic projection of the second region of the third selective active layer onto the substrate. The first insulating layer, the second insulating layer, and the third insulating layer within the 26th via V26 are etched away, exposing the surface of the second region of the third selective active layer. The 26th via V26 is configured to allow the subsequently formed third selective drain electrode to be connected to the second region of the third selective active layer through the via.

[0194] In an exemplary embodiment, the orthographic projection of the 27th via V27 on the substrate is within the range of the orthographic projection of the data signal transmission line 140 on the substrate. The third insulating layer within the 27th via V27 is etched away, exposing the surface of the data signal transmission line 140. The 27th via V27 is configured to allow the subsequently formed first selection source electrode to be connected to the data signal transmission line 140 through the via.

[0195] In an exemplary embodiment, the 28th via V28 may be located on one side of the 27th via V27 in the first direction X. The orthographic projection of the 28th via V28 on the substrate is within the range of the orthographic projection of the data signal transmission line 140 on the substrate. The third insulating layer in the 28th via V28 is etched away, exposing the surface of the data signal transmission line 140. The 28th via V28 is configured to allow the subsequently formed second selection source electrode to be connected to the data signal transmission line 140 through the via.

[0196] In an exemplary embodiment, the 29th via V29 may be located on one side of the 28th via V28 in the first direction X. The orthographic projection of the 29th via V29 on the substrate is within the range of the orthographic projection of the data signal transmission line 140 on the substrate. The third insulating layer in the 29th via V29 is etched away, exposing the surface of the data signal transmission line 140. The 29th via V29 is configured to allow the subsequently formed third selection source electrode to be connected to the data signal transmission line 140 through the via.

[0197] In an exemplary embodiment, the orthogonal projection of the thirtieth via V30 onto the substrate is within the range of the orthogonal projection of the dummy active layer onto the substrate. The first, second, and third insulating layers within the thirtieth via V30 are etched away, exposing the surface of the dummy active layer. The position and shape of the thirtieth via V30 can be substantially the same as the position and shape of the twenty-first via V21 and the twenty-second via V22. The thirtieth via V30 can serve as a dummy via to improve etching uniformity.

[0198] In an exemplary embodiment, the orthographic projection of the 31st via V31 on the substrate is within the range of the orthographic projection of the first selection gate electrode 112 on the substrate. The second and third insulating layers within the 31st via V31 are etched away, exposing the surface of the first selection gate electrode 112. The 31st via V31 is configured to allow the subsequently formed first selection control line to be connected to the first selection gate electrode 112 through the via.

[0199] In an exemplary embodiment, the orthographic projection of the 32nd via V32 on the substrate is within the range of the orthographic projection of the second selection gate electrode 122 on the substrate. The second and third insulating layers within the 32nd via V32 are etched away, exposing the surface of the second selection gate electrode 122. The 32nd via V32 is configured to allow the subsequently formed second selection control line to be connected to the second selection gate electrode 122 through the via.

[0200] In an exemplary embodiment, the orthographic projection of the 33rd via V33 on the substrate is within the range of the orthographic projection of the third selection gate electrode 132 on the substrate. The second and third insulating layers within the 33rd via V33 are etched away, exposing the surface of the third selection gate electrode 132. The 33rd via V33 is configured to allow the subsequently formed third selection control line to be connected to the third selection gate electrode 132 through the via.

[0201] In an exemplary embodiment, the orthographic projection of the 34th via V34 on the substrate is within the range of the orthographic projection of the first connection line 161 on the substrate. The second and third insulating layers within the 34th via V34 are etched away, exposing the surface of the first connection line 161. The 34th via V34 is configured to allow the first power line of the subsequently formed Nth unit column to be connected to the first connection line 161 through the via.

[0202] In an exemplary embodiment, the orthographic projection of the 35th via V35 on the substrate is within the range of the orthographic projection of the first connection line 161 on the substrate. The second and third insulating layers within the 35th via V35 are etched away, exposing the surface of the first connection line 161. The 35th via V35 is configured to allow the first power line of the subsequently formed N+1th unit column to be connected to the first connection line 161 through the via.

[0203] In an exemplary embodiment, the thirty-fourth via V34 and the thirty-fifth via V35 can be respectively disposed at the positions corresponding to the Nth and N+1th unit columns in the third corner region.

[0204] In an exemplary embodiment, the border area may further include multiple pin vias, the orthographic projection of the pin vias on the substrate being within the range of the orthographic projection of the first connection pin or the second connection pin on the substrate, and the pin vias being configured to allow subsequently formed pin electrodes to be connected to the first connection pin or the second connection pin through the vias.

[0205] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a planar schematic diagram of the third conductive layer in Figure 12A. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0206] In an exemplary embodiment, the third conductive layer of each circuit unit in the display area includes at least: a first connection electrode 51 to a sixth connection electrode 56, a first power line 61, and a data signal line 63.

[0207] In an exemplary embodiment, the first connecting electrode 51 can be a strip shape in which the main body extends along the second direction Y. The first end of the first connecting electrode 51 is connected to the second region of the first active layer through the second via V2, and the second end of the first connecting electrode 51 is connected to the first electrode plate 31 through the tenth via V10. The portion between the first end and the second end is connected to the first region of the second active layer through the third via V3. Since the first electrode plate 31 serves as the gate electrode of the third transistor T3, the first connecting electrode 51 enables the interconnection between the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 of the storage capacitor, forming the first node N1 of the pixel driving circuit.

[0208] In an exemplary embodiment, the shape of the second connecting electrode 52 can be a strip shape in which the main body extends along the second direction Y. The first end of the second connecting electrode 52 is connected to the second region of the second active layer (which is also the second region of the third active layer) through the fourth via V4. The first end of the second connecting electrode 52 is connected to the first region of the sixth active layer through the seventh via V7. The second connecting electrode 52 realizes the interconnection between the second pole of the second transistor T2, the second pole of the third transistor T3 and the first pole of the sixth transistor T6, forming the third node N2 of the pixel driving circuit.

[0209] In an exemplary embodiment, the third connection electrode 53 can be a strip shape extending along the second direction Y. The first end of the third connection electrode 53 is connected to the fourth gate electrode 27 through the fourteenth via V14, and the second end of the third connection electrode 53 is connected to the second scan signal line 22 through the fifteenth via V15, thus realizing the connection between the second scan signal line 22 and the gate electrode of the fourth transistor T4.

[0210] In an exemplary embodiment, the fourth connection electrode 54 may be a strip shape extending along the second direction Y. The fourth connection electrode 54 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the eighth via V8. The fourth connection electrode 54 is configured to be connected to the first anode connection electrode formed subsequently.

[0211] In an exemplary embodiment, the fifth connection electrode 55 can be a strip extending along the second direction Y. The first end of the fifth connection electrode 55 is connected to the first region of the first active layer through the first via V1, and the second end of the fifth connection electrode 55 is connected to the first initial connection block 41-1 through the twelfth via V12. Since the first initial connection block 41-1 is connected to the first initial signal line 41, the fifth connection electrode 55 enables the first initial signal line 41 to write the first initial signal into the first electrode of the first transistor T1.

[0212] In an exemplary embodiment, the sixth connection electrode 56 can be a strip extending along the first direction X. The first end of the sixth connection electrode 56 is connected to the first region of the seventh active layer through the ninth via V9, and the second end of the sixth connection electrode 56 is connected to the second initial connection block 42-1 through the thirteenth via V13. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the sixth connection electrode 56 enables the second initial signal line 42 to write the second initial signal into the first electrode of the seventh transistor T7.

[0213] In an exemplary embodiment, the shape of the first power line 61 can be a straight line or a broken line extending along the second direction Y of the main body. The first power line 61 is connected to the first region of the fifth active layer through the sixth via V6 on one hand, and to the second electrode plate 32 through the eleventh via V11 on the other hand. Thus, the first power line 61 can write the first power signal into the second electrode plate 32 of the storage capacitor and the first electrode of the fifth transistor T5 respectively.

[0214] In an exemplary embodiment, the first power line 61 can be a straight line of varying width, and the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projection of the fourth gate electrode 27 on the substrate. The first power line 61 may include a first region that overlaps with the fourth gate electrode 27 and a second region that does not overlap with the fourth gate electrode 27. The width of the first region may be smaller than the width of the second region, and the width may be the dimension in the first direction X.

[0215] In an exemplary embodiment, the first power line 61 of the Nth unit column can also be connected to the first connection line 161 in the frame area through the thirty-fourth via V34, and the first power line 61 of the N+1th unit column can also be connected to the first connection line 161 in the frame area through the thirty-fifth via V35. Thus, the frame power trace in the frame area is connected to the first power line 61 in the two circuit columns, and the first power signal is transmitted to the first power line 61 in the display area.

[0216] In an exemplary embodiment, the data signal line 63 can be a straight line or a broken line extending along the second direction Y of the main body. The data signal line 63 is connected to the first region of the fourth active layer through the fifth via V5, thus enabling the data signal line 63 to write the data signal into the first pole of the fourth transistor T4.

[0217] In an exemplary embodiment, the third conductive layer of at least one circuit unit may further include a first initial connection line 71 and a first initial connection bar 71-1, which may be disposed in some circuit units.

[0218] In an exemplary embodiment, the shape of the first initial connecting line 71 can be a straight line or a broken line extending along the second direction Y of the main body. The shape of the first initial connecting strip 71-1 can be a strip extending along the first direction X. The first end of the first initial connecting strip 71-1 is connected to the first initial connecting line 71, and the second end of the first initial connecting strip 71-1 is connected to the fifth connecting electrode 55. Since the fifth connecting electrode 55 is connected to the first initial signal line 41, a mesh-like interconnection structure for transmitting the first initial signal is formed in the display area by the first initial signal line 41 extending along the first direction X and the first initial connecting line 71 extending along the second direction Y. This not only effectively reduces the resistance of the first initial signal line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal, effectively improves the display uniformity, and improves the display quality.

[0219] In an exemplary embodiment, the first initial connecting line 71 and the first initial connecting strip 71-1 can be disposed in the circuit units of the Nth unit column and the N+3th unit column. In at least one circuit unit, the fifth connecting electrode 55, the first initial connecting line 71 and the first initial connecting strip 71-1 can be an integral structure that is interconnected.

[0220] In an exemplary embodiment, the third conductive layer of at least one circuit unit may further include a second initial connection line 72 and a second initial connection bar 72-1, which may be disposed in some circuit units.

[0221] In an exemplary embodiment, the shape of the second initial connecting line 72 can be a straight line or a broken line extending along the second direction Y, and the shape of the second initial connecting strip 72-1 can be a strip extending along the first direction X. The first end of the second initial connecting strip 72-1 is connected to the second initial connecting line 72, and the second end of the second initial connecting strip 72-1 is connected to the sixth connecting electrode 56. Since the sixth connecting electrode 56 is connected to the second initial signal line 42, a mesh-like interconnection structure for transmitting the second initial signal is formed in the display area by the second initial signal line 42 extending along the first direction X and the second initial connecting line 72 extending along the second direction Y. This not only effectively reduces the resistance of the second initial signal line and reduces the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal, effectively improves display uniformity, and enhances display quality.

[0222] In an exemplary embodiment, the second initial connecting line 72 and the second initial connecting strip 72-1 can be disposed in the circuit units of the N+1th and N+4th unit columns. In at least one circuit unit, the sixth connecting electrode 56, the second initial connecting line 72 and the second initial connecting strip 72-1 can be an integral structure that is interconnected.

[0223] In an exemplary embodiment, the third conductive layer of at least one circuit unit may further include a second power connection line 74, which may be disposed in a portion of the circuit unit.

[0224] In an exemplary embodiment, the shape of the second power connection line 74 can be a straight line or a broken line extending along the second direction Y of the main body. The second power connection line 74 can be connected to the bending part 62-2 through the sixteenth through hole V16, thus realizing that the second power line 62 extending along the first direction X and the second power connection line 74 extending along the second direction Y form a mesh-like interconnection structure for transmitting the second power signal in the display area. This can not only effectively reduce the resistance of the second power line and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal and the uniformity of the display, thereby improving the display quality and display performance.

[0225] In an exemplary embodiment, the second power connection line 74 may be provided in the circuit cells of the N+2 and N+5 cell columns.

[0226] In an exemplary embodiment, the first initial connection line 71, the second initial connection line 72, and the second power connection line 74 can be respectively arranged in different unit columns, and the first initial connection line 71, the second initial connection line 72, and the second power connection line 74 can be periodically arranged in the first direction X.

[0227] In an exemplary embodiment, in the second region 100B, among the multiple unit columns near the display area boundary BY, the first initial connection line 71 can be set in the first unit column closest to the display area boundary BY (such as the Nth unit column and the N+3th unit column), the second initial connection line 72 can be set in the second unit column on the side of the first unit column away from the display area boundary BY (such as the N+1th unit column and the N+4th unit column), and the second power connection line 74 can be set in the third unit column on the side of the second unit column away from the display area boundary BY (such as the N+2th unit column and the N+5th unit column). This allows the connection positions of the second power line 62 and the second power connection line 74 to be as far away from the display area boundary BY as possible, so that the first connection line 161 can be connected to the first power line 61 in the two unit columns.

[0228] In an exemplary embodiment, the third conductive layer in the third corner region of the border region may include at least: a first selection control line 110, a second selection control line 120, a third selection control line 130, a first selection source electrode 113, a first selection drain electrode 114, a first data connection line 115, a second selection source electrode 123, a second selection drain electrode 124, a second data connection line 125, a third selection source electrode 133, a third selection drain electrode 134, and a third data connection line 135.

[0229] In an exemplary embodiment, the shape of the first selection control line 110 can be a straight line or a broken line extending along the first direction X, and it can be set on one side of the data signal transmission line 140 in the second direction Y. The first selection control line 110 is connected to the first selection gate electrode 112 through the thirty-first via V31, so the first selection control line 110 can control the conduction or disconnection of the first selection transistor TF1.

[0230] In an exemplary embodiment, the shape of the second selection control line 120 can be a straight line or a broken line extending along the first direction X, and it can be set on one side of the first selection control line 110 in the second direction Y. The second selection control line 120 is connected to the second selection gate electrode 122 through the 32nd via V32, so the second selection control line 120 can control the conduction or disconnection of the second selection transistor TF2.

[0231] In an exemplary embodiment, the shape of the third selection control line 130 can be a straight line or a broken line extending along the first direction X, and can be disposed on one side of the second selection control line 120 in the second direction Y. The third selection control line 130 is connected to the third selection gate electrode 132 through the thirty-third via V33, so the third selection control line 130 can control the conduction or disconnection of the third selection transistor TF3.

[0232] In an exemplary embodiment, the first selected source electrode 113 and the first selected drain electrode 114 can be straight lines extending along the second direction Y, and the first data connection line 115 can be a broken line extending along the first direction X. The first selected source electrode 113 is connected to the first region of the first selected active layer through the twenty-first via V21 and to the data signal transmission line 140 through the twenty-seventh via V27. The first selected drain electrode 114 is connected to the second region of the first selected active layer through the twenty-second via V22 and to the data signal line 63 in the Nth unit column through the first data connection line 115. When the first selected control line 110 controls the first selected transistor TF1 to be turned on, the data signal transmission line 140 transmits the data signal of the data driver to the data signal line 63 in the Nth unit column.

[0233] In an exemplary embodiment, the second selection source electrode 123 and the second selection drain electrode 124 can be straight lines extending along the second direction Y, and the second data connection line 125 can be a broken line extending along the first direction X. The second selection source electrode 123 is connected to the first region of the second selection active layer via the twenty-third via V23 and to the data signal transmission line 140 via the twenty-eighth via V28. The second selection drain electrode 124 is connected to the second region of the second selection active layer via the twenty-fourth via V24 and to the data signal line 63 in the N+1th unit column via the second data connection line 125. When the second selection control line 120 controls the second selection transistor TF2 to be turned on, the data signal transmission line 140 transmits the data signal from the data driver to the data signal line 63 in the N+1th unit column.

[0234] In an exemplary embodiment, the third selection source electrode 133 and the third selection drain electrode 134 can be straight lines extending along the second direction Y, and the third data connection line 135 can be a broken line extending along the first direction X. The third selection source electrode 133 is connected to the first region of the third selection active layer through the twenty-fifth via V25 and to the data signal transmission line 140 through the twenty-ninth via V29. The third selection drain electrode 134 is connected to the second region of the third selection active layer through the twenty-sixth via V26 and to the data signal line 63 in the N+2th unit column through the third data connection line 135. When the third selection control line 130 controls the third selection transistor TF3 to be turned on, the data signal transmission line 140 transmits the data signal of the data driver to the data signal line 63 in the N+2th unit column.

[0235] In an exemplary embodiment, the third conductive layer of the border area may further include multiple pin electrodes. The shape of the pin electrodes may be block-shaped (such as rectangular). The pin electrodes may be connected to the first connection pin or the second connection pin through pin vias.

[0236] Subsequent fabrication processes may include forming a first planarization layer, a fourth conductive layer, and a second planarization layer, etc., which will not be elaborated here.

[0237] Thus, the driving structure layer of the display substrate in this embodiment is completed. In a plane parallel to the display substrate, the driving structure layer may include a display area and a bezel area. The display area may include multiple circuit units, at least one of which may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a first light-emitting signal line, a second light-emitting signal line, a first initial signal line, a second initial signal line, a first power line, and a data signal line connected to the pixel driving circuit. The bezel area may include at least one bezel power trace and at least one multiplexer circuit. In a plane perpendicular to the display substrate, the driving structure layer may include at least a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer sequentially disposed on the substrate. The semiconductor layer may include at least an active layer of multiple transistors and an active layer of multiple selection transistors. The first conductive layer may include at least a first electrode of a storage capacitor, a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a first light-emitting signal line, a second light-emitting signal line, a second power supply line, a frame power supply trace, a first selection gate electrode, a second selection gate electrode, and a third selection gate electrode. The second conductive layer may include at least a second electrode of a storage capacitor, a first initial signal line, a second initial signal line, and a data signal transmission line 140. The third conductive layer may include at least multiple connection electrodes, a first power supply line, a data signal line, a first initial connection line, a second initial connection line, a second power supply connection line, a first selection control line, a second selection control line, a third selection control line, a first selection source electrode, a first selection drain electrode, a first data connection line, a second selection source electrode, a second selection drain electrode, a second data connection line, a third selection source electrode, a third selection drain electrode, and a third data connection line.

[0238] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0239] In an exemplary embodiment, the first, second, and third insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first, second, third, and fourth conductive layers can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti. The first and second planarization layers can be made of organic materials, such as resin or polyimide.

[0240] In an exemplary embodiment, after the driving structure layer is fabricated, a light-emitting structure layer can be fabricated on the driving structure layer, and an encapsulation structure layer can be fabricated on the light-emitting structure layer, which will not be described in detail here.

[0241] An exemplary embodiment of this disclosure provides a display substrate that, by providing a mesh-like interconnection structure for transmitting a first power signal and a mesh-like interconnection structure for transmitting a second power signal within the display area, can not only effectively reduce the resistance of the power lines, reduce the voltage drop of the power signal, effectively improve the uniformity of the power signal, effectively improve the uniformity of the display, and improve the display quality, but also effectively reduce the power consumption of the display device.

[0242] This embodiment of the invention adjusts the structure and connection position of the second power line and the second power connection line, keeping the connection position of the second power line and the second power connection line as far away from the boundary of the display area as possible. This allows for more space for the frame power traces, resulting in more connection points for the frame power traces to connect with the first power line. This effectively improves the reliability of the connection between the first power line and the frame power traces, and effectively improves the networking performance of the mesh interconnection structure for transmitting the first power signal.

[0243] This embodiment of the disclosure, by setting a first initial connection line and a second initial connection line, forms a mesh-like interconnected structure in the display area to transmit the first initial signal, and the second initial connection line and the second initial signal line form a mesh-like interconnected structure in the display area to transmit the second initial signal. This not only effectively reduces the resistance of the initial signal line and the voltage drop of the initial signal, but also effectively improves the uniformity of the initial signal, effectively improves the display uniformity, and enhances the display quality.

[0244] In this embodiment, the first initial connection line, the second initial connection line, and the second power connection line are respectively arranged in different unit columns, and the first initial connection line, the second initial connection line, and the second power connection line are periodically arranged in the first direction X. The first initial connection line is arranged in the unit column near the boundary of the display area, and the second power connection line is arranged in the unit column far away from the boundary of the display area. Therefore, more space is left for the bezel power trace, so that the bezel power trace can be connected to multiple first power lines.

[0245] The preparation process of this disclosure is well compatible with existing preparation processes. The process is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0246] The structure and preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure can be modified according to actual needs, and this disclosure does not limit it.

[0247] Figure 13 is a schematic diagram of a mesh interconnection structure in another display area according to an exemplary embodiment of the present disclosure. As shown in Figure 13, the mesh interconnection structure of the display area in this embodiment is substantially the same as that in the embodiment shown in Figure 6, except that the mesh interconnection structure for transmitting the second power signal is only provided in the first area 100A.

[0248] In an exemplary embodiment, the display area may include multiple first power lines 61, multiple second power lines 62, multiple first power connection lines 73, and multiple second power connection lines 74. The first power lines 61 may be continuously arranged in each unit column of the first region 100A and the second region 100B. The first power connection lines 73 may be continuously arranged in each unit row of the first region 100A and the second region 100B. The multiple first power lines 61 and the multiple first power connection lines 73 form a mesh-like interconnected structure in the first region 100A and the second region 100B for transmitting first power signals. The second power lines 62 may be continuously arranged in each unit row of the first region 100A. The second power connection lines 74 may be continuously arranged in each unit column of the first region 100A. The multiple second power lines 62 and the multiple second power connection lines 74 form a mesh-like interconnected structure in the first region 100A for transmitting second power signals; that is, no mesh-like interconnected structure for transmitting second power signals is formed in the second region 100B.

[0249] Figure 14 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 14, the structure of the display substrate in this embodiment is substantially the same as that in the embodiment shown in Figure 7, except that the second power line 62 and the second power connection line 74 are only provided in the first region 100A.

[0250] In an exemplary embodiment, the second power line 62 and the second power connection line 74 may only be provided in the first region 100A, while the second region 100B does not have the second power line 62 and the second power connection line 74. Therefore, it will not affect the connection between the first connection line 161 and the first power line 61, so that the first connection line 161 can be connected to the first power line 61 in the three circuit units.

[0251] In an exemplary embodiment, in the second region 100B, the first initial connection line 71 and the second initial connection line 72 can be alternately arranged in the first direction X, while in the first region 100A, the first initial connection line 71, the second initial connection line 72, and the second power connection line 74 can be periodically arranged in the first direction X. For example, the first initial connection line 71 in the second region 100B can be arranged in the Nth, N+2nd, and N+4th unit columns, and the second initial connection line 72 in the second region 100B can be arranged in the N+1th, N+3rd, and N+5th unit columns.

[0252] In some possible implementations, the second power line 62 may be disposed only in the first region 100A, while the second power connection line 74 may be disposed in both the first region 100A and the second region 100B. In the second region 100B, the first initial connection line 71, the second initial connection line 72, and the second power connection line 74 may be periodically arranged in the first direction X, but the second power connection line 74 may be in a floating state or connected to other constant voltage signal lines, which is not limited herein.

[0253] This embodiment adjusts the positions of the second power line and the second power connection line, placing them only in the first area. This allows for more space for the frame power traces, providing more connection points between the frame power traces and the first power line. This further improves the reliability of the connection between the first power line and the frame power traces, and further enhances the meshing performance of the mesh structure for transmitting the first power signal.

[0254] A display substrate with rounded corners has a problem where the number of circuit units in multiple unit columns in the second region varies, gradually decreasing along the direction closer to the first border region. This results in significant differences in the extension length of data signal lines in the display region, leading to variations in data voltage load and affecting the display effect. To reduce these variations in data voltage load, this disclosure employs a compensation capacitor. By placing a compensation capacitor in the border region, the differences in data voltage load are reduced, thereby optimizing the display effect.

[0255] Figure 15 is a schematic diagram of the structure of a compensation capacitor according to an exemplary embodiment of the present disclosure, illustrating the structure of a first corner region (upper left corner region) in a display substrate. As shown in Figure 15, at least one corner region of the frame area (such as the first corner region or the second corner region) may include at least one capacitor group. The capacitor group may include three compensation capacitors arranged sequentially along the first direction X. At least one compensation capacitor may include a first compensation electrode 301 and a second compensation electrode 302. The orthographic projection of the second compensation electrode 302 on the substrate at least partially overlaps with the orthographic projection of the first compensation electrode 301 on the substrate.

[0256] In an exemplary embodiment, the first compensation electrode 301 may be rectangular in shape, disposed in the first conductive layer, and connected to the data signal line of the display area via a corresponding connection electrode. The second compensation electrode 302 may be rectangular in shape, disposed in the second conductive layer, and connected to the first power line of the display area via a corresponding connection electrode.

[0257] In some possible implementations, the first compensation plate 301 may be connected to the first power line, and the second compensation plate 302 may be connected to the data signal line; however, this disclosure does not limit the scope of the invention.

[0258] In an exemplary embodiment, the three first compensation plates 301 in at least one capacitor bank can be spaced apart along a first direction X, and the areas of the orthographic projections of the three first compensation plates 301 onto the substrate can be substantially the same. The three second compensation plates 302 in at least one capacitor bank can be interconnected and are an integral structure interconnected.

[0259] Figure 16 is a schematic diagram of another compensation capacitor structure in an exemplary embodiment of the present disclosure. As shown in Figure 16, the structure of the compensation capacitor in this embodiment is basically the same as that in the embodiment shown in Figure 15, except that an isolation strip 401 is provided between two adjacent first compensation plates 301.

[0260] In an exemplary embodiment, the first compensation electrode 301 can be disposed in the first conductive layer and connected to the data signal line of the display area; the second compensation electrode 302 can be disposed in the second conductive layer and connected to the first power line of the display area; and the isolation strip 401 can be disposed in the semiconductor layer and connected to the constant voltage signal line, which can effectively shield the data signal in the first compensation electrode 301. The constant voltage signal line can be the first power line, the second power line, the first initial signal line, or the second initial signal line.

[0261] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and this disclosure is not limited thereto.

[0262] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising a display area and a border area surrounding the display area, the border area comprising at least two first border areas disposed opposite each other in a first direction, two second border areas disposed opposite each other in a second direction, and a corner area connecting the first border areas and the second border areas, the display area and the corner area having a stepped display area boundary, the first direction and the second direction intersecting; the display area comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, a first power connection line and a second power line extending along the first direction, a first power line, a second power connection line and a data signal line extending along the second direction, the pixel driving circuit being configured to drive the display area to a display area. The connected light-emitting device provides driving current. The first power line is configured to provide a first power signal to the pixel driving circuit. The data signal line is configured to provide a data signal to the pixel driving circuit. The second power line is configured to provide a second power signal to the light-emitting device. The first power connection line is connected to the first power line to form a mesh interconnection structure for transmitting the first power signal. The second power connection line is connected to the second power line to form a mesh interconnection structure for transmitting the second power signal. At least one corner area includes at least one multiplexer circuit and at least one bezel power trace. The multiplexer circuit is connected to the data signal line in the display area, and the bezel power trace is connected to the first power line in the display area. 2.The display substrate of claim 1, wherein, The bezel power trace includes at least a first connecting line extending along the first direction and a second connecting line extending along the second direction; in the second direction, the first connecting line is disposed on the side of the multiplexing circuit closer to the display area and connected to the first power line in the display area; in the first direction, the second connecting line is disposed on the side of the multiplexing circuit away from the display area and connected to the first connecting line. 3.The display substrate of claim 2, wherein, In a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers disposed on the substrate, the first connecting line and the second connecting line are disposed in the same layer and are an integral structure interconnected with each other. 4.The display substrate of claim 3, wherein, The first power line and the frame power trace are disposed in different conductive layers, and the first power line is connected to the first connecting line through a via. 5.The display substrate of claim 4, wherein, The plurality of conductive layers include at least a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, and a third conductive layer disposed on the side of the second conductive layer away from the substrate. The first connecting line, the second connecting line, and the second power line are disposed in the first conductive layer, the first power connecting line is disposed in the second conductive layer, and the first power line, the second power connecting line, and the data signal line are disposed in the third conductive layer. 6.The display substrate according to any one of claims 1 to 5, wherein The display area includes at least a first area and a second area. The second area is disposed on both sides of the first area in the first direction. In the first area, the number of circuit units in multiple unit columns is the same. In the second area, the number of circuit units in multiple unit columns is different. Along the direction close to the first border area, the number of circuit units in the unit columns gradually decreases. A mesh interconnection structure for transmitting the first power signal and a mesh interconnection structure for transmitting the second power signal are disposed in the first area and the second area. 7.The display substrate of claim 6, wherein, In at least one circuit unit in the second region, in the second direction, the second power line is disposed on the side of the circuit unit closer to the multiplexing circuit, and the second power connection line is connected to the second power line through a via. 8.The display substrate of claim 7, wherein, The second power line includes at least one straight portion extending along the first direction and at least one bent portion protruding toward the multiplexing circuit, and the second power connection line is connected to the bent portion through the via. 9.The display substrate of claim 8, wherein, In the first direction, the circuit unit where the bend is located is spaced at least two circuit units away from the boundary of the display area. 10.The display substrate of any one of claims 1-5, wherein, The display area includes at least a first area and a second area. The second area is disposed on both sides of the first area in the first direction. In the first area, the number of circuit units in multiple unit columns is the same. In the second area, the number of circuit units in multiple unit columns is different. Along the direction close to the first border area, the number of circuit units in the unit columns gradually decreases. The mesh interconnection structure for transmitting the first power signal is disposed in the first area and the second area. The mesh interconnection structure for transmitting the second power signal is disposed only in the first area. 11.The display substrate of claim 10, wherein, The second power cord is only located in the first area. 12.The display substrate according to any one of claims 1 to 5, wherein The pixel driving circuit includes at least a storage capacitor, and the storage capacitor includes at least a first electrode plate and a second electrode plate. The orthographic projection of the second electrode plate on the display substrate at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate. In at least one unit row, multiple second electrode plates are interconnected by plate electrode connecting strips to form the first power connection line.

13. The display substrate according to any one of claims 1 to 5, wherein, At least one circuit unit further includes a first initial signal line extending along the first direction and a first initial connection line extending along the second direction, the first initial signal line being configured to provide a first initial signal to the pixel driving circuit, and the first initial connection line being connected to the first initial signal line to form a mesh interconnection structure for transmitting the first initial signal in the display area. 14.The display substrate of claim 13, wherein, At least one circuit unit further includes a second initial signal line extending along the first direction and a second initial connection line extending along the second direction, the second initial signal line being configured to provide a second initial signal to the pixel driving circuit, and the second initial connection line being connected to the second initial signal line to form a mesh interconnection structure for transmitting the second initial signal in the display area. 15.The display substrate of claim 14, wherein, The first initial connection line is disposed in a first unit column near the boundary of the display area, the second initial connection line is disposed in a second unit column on the side of the first unit column away from the boundary of the display area, and the second power connection line is disposed in a third unit column on the side of the second unit column away from the boundary of the display area.

16. The display substrate according to any one of claims 1 to 5, wherein At least one corner region includes at least one capacitor bank, the capacitor bank including a plurality of compensation capacitors arranged sequentially along the first direction, the at least one compensation capacitor including a first compensation plate and a second compensation plate, the orthographic projection of the second compensation plate on the display substrate at least partially overlaps with the orthographic projection of the first compensation plate on the display substrate, the first compensation plate is connected to the data signal line, and the second compensation plate is connected to the first power line. 17.The display substrate of claim 16, wherein, In at least one capacitor bank, a plurality of first compensation plates are spaced apart in the first direction, and a plurality of second compensation plates are an integral structure interconnected with each other. 18.The display substrate of claim 16, wherein, In at least one capacitor bank, an isolation strip is provided between two adjacent first compensation plates.

19. The display substrate of claim 18, wherein, In a direction perpendicular to the display substrate, the display substrate includes a semiconductor layer disposed on a substrate, a first conductive layer disposed on the semiconductor layer away from the substrate, a second conductive layer disposed on the first conductive layer away from the substrate, and a third conductive layer disposed on the second conductive layer away from the substrate. A first compensation electrode is disposed in the first conductive layer, a second compensation electrode is disposed in the second conductive layer, a first power line and a data signal line are disposed in the third conductive layer, and an isolation strip is disposed in the semiconductor layer.

20. A display device comprising a display substrate as claimed in any one of claims 1 to 19.

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