Super junction device and forming method therefor

Abstract

The present invention provides a super junction device and a forming method therefor. The super junction device comprises: a substrate, the substrate comprising a first surface; a deep trench located in the substrate from the first surface; an insulating layer located on the sidewall surface of the deep trench; a doped pillar located in the deep trench, the doped pillar having first dopant ions therein, wherein in the direction perpendicular to the surface of the substrate, the concentration of the first dopant ions in the doped pillar and the width of the deep trench have a self-adaptive matching relationship, and wherein the doped pillar comprises: a first polysilicon layer located on the surface of the insulating layer and the bottom surface of the deep trench, the first polysilicon layer having the first dopant ions therein; and a second polysilicon layer located on the surface of the first polysilicon layer, wherein a portion of the first dopant ions in the first polysilicon layer diffuses into the second polysilicon layer. The super junction device effectively increases the breakdown voltage, provides the possibility for further reduction of the device size, and has a wide range of applications.

Description

Superjunction Devices and Their Formation Methods

[0001] This application claims priority to Chinese Patent Application No. 2025101880187, filed on February 19, 2025, entitled "Superjunction Device and Method for Forming the Same", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor manufacturing technology, and in particular to a superjunction device and a method for forming the same. Background Technology

[0003] The principle behind the breakdown voltage of power devices is to lightly dope the drift region, enabling the device to generate a large depletion region at high voltages, thus achieving the breakdown voltage effect. Because vertical devices have a thicker drift region, they are the better choice for high-voltage applications.

[0004] Superjunction devices combine the advantages of low loss during switching of VDMOS and low loss during conduction of IGBT, and have been widely used due to their excellent performance.

[0005] However, the performance of existing superjunction devices still needs to be improved. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a superjunction device and a method for forming the same, which effectively improves the breakdown voltage of the superjunction device and provides the possibility for further reduction in device size, and has a wide range of applications.

[0007] To address the aforementioned problems, this invention provides a superjunction device, comprising: a substrate including a first surface; a deep trench located within the substrate from the first surface; an insulating layer located on the sidewall surface of the deep trench; and a doped pillar located within the deep trench, the doped pillar containing first doped ions, wherein the concentration of the first doped ions in the doped pillar in a direction perpendicular to the substrate surface is adaptively matched to the width of the deep trench, wherein the doped pillar comprises: a first polysilicon layer located on the surface of the insulating layer and the bottom surface of the deep trench, the first polysilicon layer containing the first doped ions; and a second polysilicon layer located on the surface of the first polysilicon layer, wherein a portion of the first doped ions in the first polysilicon layer diffuses into the second polysilicon layer.

[0008] Optionally, the concentration of the first doped ions within the doped pillar is uniformly distributed in a direction parallel to the surface of the substrate.

[0009] Optionally, the concentration of the first doped ion within the doped pillar in the direction perpendicular to the substrate surface is inversely correlated with the width of the deep trench.

[0010] Optionally, the substrate further includes a second surface opposite to the first surface, wherein the width of the deep trench gradually decreases from the first surface to the second surface.

[0011] Optionally, it may also include: body regions located on both sides of the doped pillar; gate trenches located within a portion of the doped pillar; trench gate structures located within the gate trenches; source regions located within the body regions on both sides of the trench gate structures; and drain regions located within the substrate on the second surface.

[0012] A method for forming a superjunction device includes the steps of: providing a substrate, the substrate including a first surface; etching the substrate from the first surface to form a deep trench within the substrate; forming an insulating layer on the sidewall surface of the deep trench; forming a first polysilicon layer on the surface of the insulating layer and the bottom surface of the deep trench, the first polysilicon layer containing first doped ions; forming a second polysilicon layer on the surface of the first polysilicon layer, the second polysilicon layer filling the deep trench; after forming the second polysilicon layer, performing an annealing process, wherein some of the first doped ions diffuse into the second polysilicon layer, forming doped pillars within the deep trench, wherein the concentration of the first doped ions within the doped pillars in a direction perpendicular to the substrate surface is adaptively matched to the width of the deep trench.

[0013] Optionally, the concentration of the first doped ions within the doped pillar is uniformly distributed in a direction parallel to the surface of the substrate.

[0014] Optionally, the concentration of the first doped ion within the doped pillar in the direction perpendicular to the substrate surface is inversely correlated with the width of the deep trench.

[0015] Optionally, the substrate further includes a second surface opposite to the first surface, wherein the width of the deep trench gradually decreases from the first surface to the second surface.

[0016] Optionally, the material of the insulating layer includes one or more combinations of silicon oxide, silicon nitride, and silicon carbide.

[0017] Optionally, the substrate contains a second doped ion, the type of which is opposite to that of the first doped ion.

[0018] Optionally, the concentration of the second doped ion within the doped pillar in the direction perpendicular to the substrate surface is inversely correlated with the width of the deep trench.

[0019] Optionally, the method of forming the insulating layer on the sidewall surface of the deep trench includes: forming an initial insulating layer on the sidewall and bottom surface of the deep trench; etching away the initial insulating layer on the bottom surface of the deep trench to the substrate surface exposing the bottom of the deep trench, thereby forming the insulating layer.

[0020] Optionally, after forming the doped pillar, the method further includes: forming a body region in the substrate on both sides of the doped pillar from the first surface, wherein the depth of the body region is less than the depth of the doped pillar.

[0021] Optionally, after forming the doped pillar, the method further includes: etching a portion of the thickness of the doped pillar from the first surface; forming a gate trench within the doped pillar; forming a trench gate structure within the gate trench; the trench gate structure including forming a gate dielectric layer on the sidewall surface and bottom surface of the gate trench; forming a gate layer on the surface of the gate dielectric layer; the gate layer filling the gate trench; and the depth of the gate trench being greater than the depth of the body region.

[0022] Optionally, it further includes: forming a source region in the body region on both sides of the trench gate structure; forming a drain region in the substrate from the second surface, the second surface exposing the top surface of the drain region.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0024] In the superjunction device of this invention, a deep trench extends from the first surface of the substrate and is located within the substrate. Doped pillars are located within the deep trenches, each containing first doped ions. The concentration of the first doped ions within the pillars in the direction perpendicular to the substrate surface is adaptively matched to the width of the deep trench. Each doped pillar comprises a first polysilicon layer located on the surface of an insulating layer and the bottom surface of the deep trench, containing the first doped ions. A second polysilicon layer is located on the surface of the first polysilicon layer, filling the deep trench. A portion of the first doped ions in the first polysilicon layer diffuses into the second polysilicon layer, forming doped pillars containing the first doped ions. By utilizing the adaptive matching relationship between the concentration of the first doped ions within the pillars and the width of the deep trench—that is, a larger deep trench corresponds to a lower concentration of first doped ions within the pillars, and vice versa—the difficulty of matching doped pillars in superjunction devices is reduced, the process window is increased, and feasibility is provided for future optimization of the breakdown voltage (BV) and continuous size reduction of superjunction devices. This method has a wide range of applications. Attached Figure Description

[0025] Figures 1 to 6 are schematic diagrams illustrating the formation process of a superjunction device according to an embodiment of the present invention;

[0026] Figure 7 is a schematic diagram of the doping distribution in one embodiment of the present invention;

[0027] Figure 8 is a schematic diagram showing the relationship between gate voltage and leakage current in one embodiment of the present invention. Detailed Implementation

[0028] The electrical performance of existing superjunction devices still needs to be improved.

[0029] Traditional superjunction devices require deep trenches to be dug on an N-type substrate and epitaxially filled with in-situ doped P-type pillars. The N-type substrate and P-type doped pillars are matched and depleted in the vertical direction of the silicon wafer to achieve a very high breakdown voltage (BV) with a very small lateral dimension.

[0030] The inventors discovered that conventional superjunction devices, due to the poor filling capability of the single-crystal silicon epitaxial layer, struggle to perfectly fill deep and narrow trenches. This limits further increases in trench depth and the potential for further increases in breakdown voltage (BV). Furthermore, the trenches need to be inverted trapezoidal to satisfy the filling feasibility of the single-crystal silicon epitaxial layer. However, this inverted trapezoidal shape results in wider P-type doped pillars at the top and narrower P-type doped pillars at the bottom. The total amount of P-type impurities within the doped pillars at different widths, i.e., different depths within the trench, varies: the top trench is wider with more P-type impurities, while the adjacent N-type region is narrower with fewer N-type impurities; the bottom is the opposite, with fewer P-type impurities and more adjacent N-type impurities. Perfect matching and depletion of N-type and P-type ions cannot be achieved simultaneously from the top to the bottom of the trench, ultimately resulting in a lower device breakdown voltage (BV) than designed. If the trench is made straight with no angle on the sidewalls, matching of N-type and P-type ions is easy, but seamless filling cannot be achieved in single-crystal silicon epitaxy. After forming the P-type doped pillar, there is still a large amount of unavoidable thermal budget, which causes ions to diffuse laterally within the doped pillar, compressing the width of the current path in the N-type region and ultimately reducing the current density.

[0031] The inventors discovered that after forming a deep trench in a substrate, an insulating layer is formed on the sidewalls of the deep trench. A first polysilicon layer containing first doped ions is formed on the bottom surface of the deep trench and the surface of the insulating layer. A second polysilicon layer is formed on the surface of the first polysilicon layer, filling the deep trench. Some of the first doped ions in the first polysilicon layer diffuse into the second polysilicon layer, forming doped pillars containing the first doped ions. An insulating layer is first formed as a diffusion stop layer, with an opening at the bottom of the deep trench. The insulating layer can suppress the diffusion of the first doped ions in the subsequently filled first polysilicon layer without affecting the charge balance between the subsequent doped pillars and the substrate. Therefore, the filling cost and difficulty of doped pillars can be reduced, and the on-resistance of the device can be further reduced. Simultaneously, a first polysilicon layer with a high doping concentration of first doped ions is deposited encapsulatingly on the sidewalls and bottom of the deep trench. Then, an undoped intrinsic state second polysilicon layer is filled inside the deep trench, followed by annealing. This allows the first doped ions to diffuse uniformly laterally (parallel to the substrate surface) and longitudinally (perpendicular to the substrate surface) within the deep trench, forming an adaptive doping concentration for different trench widths. This formation method will significantly reduce the difficulty of doped pillar matching in superjunction devices, increase the process window, and provide feasibility for further optimization of the breakdown voltage (BV) and continuous reduction of the pitch size of superjunction devices.

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] First, referring to Figure 1, a substrate 100 is provided, the substrate 100 including a first surface 100a.

[0034] In this embodiment, the substrate 100 contains a second doped ion, which is an N-type ion.

[0035] In this embodiment, the substrate 100 is made of one or more of semiconductor materials such as silicon, germanium silicon, and germanium.

[0036] Please continue to refer to Figure 1. The substrate 100 is etched from the first surface 100a to form a deep trench 102 in the substrate 100.

[0037] In this embodiment, the method for forming the deep trench 102 includes: forming a hard mask layer (not shown in the figure) on the surface of the substrate 100, etching the substrate 100 with the hard mask layer as a mask to form the deep trench 102; and then removing the hard mask layer.

[0038] In this embodiment, the substrate 100 further includes a second surface 100b opposite to the first surface 100a, and the width d of the deep trench 102 gradually decreases from the first surface 100a to the second surface 100b.

[0039] Please continue to refer to Figure 1, where an initial insulating layer 101 is formed on the sidewalls and bottom surface of the deep trench 102.

[0040] In this embodiment, the initial insulating layer 101 is formed by an oxidation process.

[0041] In some embodiments, the initial insulating layer may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc.

[0042] Referring to Figure 2, the initial insulating layer 101 on the bottom surface of the deep trench 102 is etched away to expose the bottom of the substrate 100 surface of the deep trench 102, forming the insulating layer 103.

[0043] In this embodiment, the initial insulating layer 101 at the bottom of the deep trench 102 is exposed by an etching process to form a channel for charge carriers, thereby preventing excessive voltage at the bottom of the deep trench 102 from causing breakdown.

[0044] In this embodiment, the insulating layer 103 is made of silicon oxide.

[0045] In some embodiments, the material of the insulating layer 103 includes one or more combinations of silicon oxide, silicon nitride, and silicon carbide.

[0046] Please refer to Figure 3. A first polysilicon layer 104 is formed on the surface of the insulating layer 103 and the bottom surface of the deep trench 102. The first polysilicon layer 104 contains a first doped ion.

[0047] In this embodiment, the first doped ion is a P-type ion.

[0048] In this embodiment, the first doped ion is boron.

[0049] In this embodiment, a high concentration of the first doped ions is formed within the first polysilicon layer 104, wherein the specific doping concentration is adjusted according to application requirements.

[0050] In this embodiment, an undoped first polysilicon layer is first formed, and then the first dopant ions are doped in situ to form the first polysilicon layer 104 having the first dopant ions.

[0051] Please refer to Figure 4. A second polysilicon layer 105 is formed on the surface of the first polysilicon layer 104, and the second polysilicon layer 105 fills the deep trench 102.

[0052] In this embodiment, the second polysilicon layer 105 is not doped with any type of ions.

[0053] Please refer to Figure 5. After annealing, some of the first doped ions diffuse into the second polysilicon layer 105, forming doped pillars 106 in the deep trench 102.

[0054] In this embodiment, the concentration of the first doped ion in the doped pillar 106 in the direction perpendicular to the surface of the substrate 100 is adaptively matched with the width d of the deep trench 102.

[0055] Specifically, the concentration of the second doped ion in the doped pillar 106 in the direction Y perpendicular to the surface of the substrate 100 is inversely related to the width d of the deep trench 102. That is, the larger the width d of the deep trench 102, the smaller the concentration of the first doped ion in the corresponding doped pillar 106; the smaller the width d of the deep trench 102, the larger the concentration of the first doped ion in the corresponding doped pillar 106.

[0056] In this embodiment, an insulating layer 103 is first formed as a diffusion stop layer, and an opening of the insulating layer 103 is left at the bottom of the deep trench 102. The insulating layer 103 can suppress the diffusion of the first doped ions in the subsequently filled first polysilicon layer 104 without affecting the charge balance between the subsequent doped pillars and the substrate 100. Therefore, the filling cost and difficulty of the doped pillars 106 can be reduced, and the on-resistance of the device can be further reduced. At the same time, a first polysilicon layer 104 is deposited encapsulatingly on the sidewalls and bottom of the deep trench 102, wherein the first polysilicon layer 104 has a high doping concentration of first doped ions. Then, an undoped intrinsic state second polysilicon layer 105 is filled inside the deep trench 102 and annealed to make the first doped ions diffuse uniformly in the lateral direction (parallel to the surface direction X of the substrate) and form a concentration gradient in the longitudinal direction (perpendicular to the surface direction Y of the substrate) in the deep trench, forming an adaptive doping concentration relative to different trench 102 widths. This formation method will greatly reduce the difficulty of matching the doped pillars of super junction devices, increase the process window, and also provide feasibility for the continued optimization of the breakdown voltage (BV) of super junction devices and the continuous reduction of the pitch size in the future.

[0057] In this embodiment, the concentration of the first doped ions within the doped pillar 106 is uniformly distributed in the surface direction X parallel to the substrate 100.

[0058] Please refer to Figure 6. A body region 107 is formed in the substrate 100 on both sides of the doped pillar 106 from the first surface 100a. The depth of the body region 107 is less than the depth of the doped pillar 106.

[0059] Please continue referring to Figure 6. The doped pillar 106 with a partial thickness etched on the first surface 100a is formed. A gate trench (not marked in the figure) is formed in the doped pillar 106. A trench gate structure 108 is formed in the gate trench (not marked in the figure). The trench gate structure 108 includes a gate dielectric layer 108a formed on the sidewall surface and bottom surface of the gate trench (not marked in the figure). A gate layer 108b is formed on the surface of the gate dielectric layer 108a. The gate layer 108b fills the gate trench (not marked in the figure). The depth of the gate trench (not marked in the figure) is greater than the depth of the body region 107.

[0060] Please continue to refer to Figure 6. Source regions 109 are formed in the body regions 107 on both sides of the trench gate structure 108; drain regions 110 are formed in the substrate 100 from the second surface 100b, and the top surface of the drain regions 110 is exposed by the second surface 100b.

[0061] Accordingly, the present invention also provides a superjunction device, comprising: a substrate 100, the substrate 100 including a first surface 100a; a deep trench 102 located within the substrate 100 from the first surface 100a; an insulating layer 103 located on the sidewall surface of the deep trench 102; and doped pillars 106 located within the deep trench 102, the doped pillars 106 containing first doped ions, wherein the concentration of the first doped ions in the doped pillars 106 in a direction perpendicular to the surface of the substrate 100 is adaptively matched with the width d of the deep trench 102, wherein the doped pillars 106 include: a first polysilicon layer 104 located on the surface of the insulating layer 103 and the bottom surface of the deep trench 102, the first polysilicon layer 104 containing first doped ions; and a second polysilicon layer 105 located on the surface of the first polysilicon layer 104, wherein a portion of the first doped ions in the first polysilicon layer 104 diffuses to the second polysilicon layer 105.

[0062] In this embodiment, the concentration of the first doped ions within the doped pillar 106 is uniformly distributed in a direction parallel to the surface of the substrate 100.

[0063] In this embodiment, the concentration of the first doped ion in the doped pillar 106 in the direction perpendicular to the surface of the substrate 100 is inversely correlated with the width d of the deep trench 102.

[0064] In this embodiment, the substrate 100 further includes a second surface 100b opposite to the first surface 100a, and the width d of the deep trench 102 gradually decreases from the first surface 100a to the second surface 100b.

[0065] In this embodiment, it further includes: body regions 107 located on both sides of the doped pillar 106; gate trenches (not marked in the figure) located in a portion of the doped pillar 106; trench gate structures 108 located in the gate trenches (not marked in the figure); source regions 109 located in the body regions 107 on both sides of the trench gate structures 108; and drain regions 110 located in the substrate 100 of the second surface 100b.

[0066] In this embodiment, the concentration of the first doped ion in the doped pillar 106 is adaptively matched with the width d of the deep trench 102. That is, when the width d of the deep trench 102 is large, the concentration of the first doped ion in the doped pillar 106 is small; when the width d of the deep trench 102 is small, the concentration of the first doped ion in the doped pillar 106 is large. This reduces the difficulty of matching the doped pillar 106 in the superjunction device, increases the process window, and also provides feasibility for the continued optimization of the breakdown voltage (BV) and the continuous reduction of the size of the superjunction device in the future. It has a wide range of applications.

[0067] Please refer to Figure 7. The insulating layer prevents the diffusion of the first doped ions, making the N-type drift region of the trench gate structure of the superjunction device in this embodiment wider.

[0068] Please refer to Figure 8. The superjunction device in this embodiment can greatly reduce the Rsp of the device.

[0069] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A superjunction device, characterized in that, include: Substrate, the substrate including a first surface; A deep trench located within the substrate from the first surface; An insulating layer located on the sidewall surface of the deep trench; A doped pillar located within the deep trench contains a first doped ion. The concentration of the first doped ion within the doped pillar in a direction perpendicular to the substrate surface is adaptively matched to the width of the deep trench. The doped pillar comprises: a first polysilicon layer located on the surface of the insulating layer and the bottom surface of the deep trench, the first polysilicon layer containing the first doped ion; and a second polysilicon layer located on the surface of the first polysilicon layer, wherein a portion of the first doped ion in the first polysilicon layer diffuses into the second polysilicon layer.

2. The superjunction device as described in claim 1, characterized in that, The concentration of the first doped ions within the doped pillar is uniformly distributed in a direction parallel to the surface of the substrate.

3. The superjunction device as described in claim 1, characterized in that, The concentration of the first doped ion within the doped pillar in the direction perpendicular to the substrate surface is inversely correlated with the width of the deep trench.

4. The superjunction device as described in claim 1, characterized in that, The substrate also includes a second surface opposite to the first surface, and the width of the deep trench gradually decreases from the first surface to the second surface.

5. The superjunction device as described in claim 4, characterized in that, Also includes: Body regions located on both sides of the doped pillar; gate trenches located within a portion of the doped pillar; The trench gate structure is located within the gate trench; The source region is located in the body region on both sides of the trench gate structure; the drain region is located in the substrate on the second surface.

6. A method for forming a superjunction device, characterized in that, Including the following steps: A substrate is provided, the substrate including a first surface; The substrate is etched from the first surface to form a deep trench within the substrate; An insulating layer is formed on the sidewall surface of the deep trench; A first polysilicon layer is formed on the surface of the insulating layer and the bottom surface of the deep trench, and the first polysilicon layer contains a first doped ion; A second polysilicon layer is formed on the surface of the first polysilicon layer, and the second polysilicon layer fills the deep trench; After the second polysilicon layer is formed, an annealing process is performed, and some of the first doped ions diffuse into the second polysilicon layer to form doped pillars in the deep trench. The concentration of the first doped ions in the doped pillars in the direction perpendicular to the substrate surface is adaptively matched with the width of the deep trench.

7. The method for forming a superjunction device as described in claim 6, characterized in that, The concentration of the first doped ions within the doped pillar is uniformly distributed in a direction parallel to the surface of the substrate.

8. The method for forming a superjunction device as described in claim 6, characterized in that, The concentration of the first doped ion within the doped pillar in the direction perpendicular to the substrate surface is inversely correlated with the width of the deep trench.

9. The method for forming a superjunction device as described in claim 6, characterized in that, The substrate also includes a second surface opposite to the first surface, and the width of the deep trench gradually decreases from the first surface to the second surface.

10. The method for forming the superjunction device according to claim 6, characterized in that, The insulating layer is made of one or more of silicon oxide, silicon nitride, and silicon carbide.

11. The method for forming the superjunction device according to claim 6, characterized in that, The substrate contains a second doped ion, and the type of the first doped ion is opposite to that of the second doped ion.

12. The method for forming the superjunction device according to claim 11, characterized in that, The concentration of the second doped ion within the doped pillar in the direction perpendicular to the substrate surface is inversely correlated with the width of the deep trench.

13. The method for forming the superjunction device according to claim 6, characterized in that, The method of forming the insulating layer on the sidewall surface of the deep trench includes: forming an initial insulating layer on the sidewall and bottom surface of the deep trench; etching away the initial insulating layer on the bottom surface of the deep trench to the substrate surface exposing the bottom of the deep trench, thereby forming the insulating layer.

14. The method for forming the superjunction device according to claim 9, characterized in that, After forming the doped pillar, the method further includes: forming a body region in the substrate on both sides of the doped pillar from the first surface, wherein the depth of the body region is less than the depth of the doped pillar.

15. The method for forming the superjunction device according to claim 14, characterized in that, After forming the doped pillar, the method further includes: etching a portion of the thickness of the doped pillar from the first surface; forming a gate trench within the doped pillar; forming a trench gate structure within the gate trench; the trench gate structure includes forming a gate dielectric layer on the sidewall surface and bottom surface of the gate trench; forming a gate layer on the surface of the gate dielectric layer; the gate layer filling the gate trench; and the depth of the gate trench being greater than the depth of the body region.

16. The method for forming the superjunction device according to claim 15, characterized in that, Also includes: A source region is formed in the body region on both sides of the trench gate structure; a drain region is formed in the substrate from the second surface, the second surface exposing the top surface of the drain region.

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