Physical signal monitoring-based transmission link fault location method and system

Abstract

The present invention provides a physical signal monitoring-based transmission link fault location method and system in the technical field of transmission link fault location. The method comprises: step S1, a layer 2 switching chip creating a register group, and an MCU creating a MAC address table; step S2, when a new network device is accessed, the MCU performing anomaly verification on a new MAC address by means of the MAC address table and then updating the MAC address table; step S3, performing fault location by means of a queue controller watchdog event, and updating an event register on the basis of a fault type; step S4, the MCU reading the fault type from the event register to match a fault handling measure from a fault management table; and step S5, when a fault handling measure is found, executing a transmission link recovery operation on the basis of the fault handling measure, and when no fault handling measure is found, reading switch data from the register group and uploading the switch data to a server for fault location, or executing fault location on the basis of a console command inputted from a Console interface. The present invention has the advantage that the convenience and timeliness of transmission link fault location are greatly improved.

Description

A method and system for locating transmission link faults based on physical signal monitoring Technical Field

[0001] This invention relates to the field of transmission link fault location technology, and in particular to a method and system for transmission link fault location based on physical signal monitoring. Background Technology

[0002] The transmission link involves numerous types of physical nodes (network transmission devices). When a physical node fails, it will cause network transmission anomalies, requiring fault location. Layer 2 switches are one type of physical node on the transmission link. Currently, Layer 2 switches using low-end Layer 2 switching chips lack management interfaces and only possess essential components such as clocks, power supplies, and storage. Therefore, when this physical node experiences faults such as data forwarding failures, interface link establishment failures, or transmission link blockages due to compatibility issues, it is difficult to quickly locate the problem, causing significant inconvenience to the operation and maintenance of the transmission link.

[0003] A search revealed that Chinese invention patent application number CN202310073106.3 and classification number H04B10 / 073 discloses a method, apparatus, communication equipment and storage medium for testing switches. This patent is specifically for testing switches to determine whether the transmission link is normal.

[0004] Therefore, how to provide a method and system for locating transmission link faults based on physical signal monitoring, so as to improve the convenience and timeliness of transmission link fault location, has become an urgent technical problem to be solved. Technical issues

[0005] The technical problem to be solved by the present invention is to provide a method and system for locating transmission link faults based on physical signal monitoring, so as to improve the convenience and timeliness of transmission link fault location. Technical solutions

[0006] In a first aspect, the present invention provides a method for locating transmission link faults based on physical signal monitoring, comprising the following steps:

[0007] Step S1: The Layer 2 switching chip of the Layer 2 switch located in the transmission link creates a register group including control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register and global reset register.

[0008] Step S2: The MCU of the Layer 2 switch creates a MAC address table to store the MAC addresses of the current network. The MAC address table stores the MsbMac and LsbMac of the MAC address in a two-dimensional array structure, and sets the sorting rules of the MAC address table. MsbMac and LsbMac are the high 3 bytes and low 3 bytes of data of the MAC address, respectively, and are represented by 32-bit integers.

[0009] Step S3: When the Layer 2 switching chip connects to a new network device through a physical port, it reads the new MAC address of the new network device and sends it to the MCU through the SMI interface. The MCU performs anomaly verification on the new MAC address through the MAC address table, generates a MAC verification result, displays the MAC verification result in real time on the LCD screen, and updates the MAC address table based on the MAC verification result and sorting rules.

[0010] Step S4: During the operation of the Layer 2 switch, the Layer 2 switching chip monitors the physical signals in real time and performs fault location based on the physical signals through the queue controller watchdog event. When a fault is located, the event register is updated based on the fault type, and an interrupt event is sent to the MCU through the interrupt pin.

[0011] Step S5: Based on the received interrupt event, the MCU reads the fault type from the event register of the Layer 2 switching chip through the SMI interface, matches the fault handling measures with the fault type from the preset fault management table, and displays the fault type in real time on the LCD screen.

[0012] Step S6: When the MCU matches the fault handling measure, it performs a transmission link recovery operation based on the fault handling measure; when the fault handling measure is not matched, it reads the switch data from the register group and uploads the switch data to the server for fault location through the Console interface, or performs fault location and transmission link recovery operations based on the console command input from the Console interface.

[0013] Furthermore, in step S1, the control register is used to identify the interface configuration mode; the status register is used to identify the interface status; the auto-negotiation capability register is used to identify the interface auto-negotiation status; the master-slave mode register is used to identify the master-slave status; the PHY register is used to identify the PHY manufacturer and model; the custom register is used to identify custom content; the event register is used to identify the fault type; and the global reset register is used to identify whether a global reset is performed.

[0014] Furthermore, in step S2, the sorting rule is specifically as follows:

[0015] First, sort the MAC addresses based on LsbMac. Then, for MAC addresses with the same LsbMac, sort the MAC addresses again based on MsbMac.

[0016] Furthermore, step S3 specifically includes:

[0017] When a Layer 2 switching chip connects to a new network device through a physical port, it reads the new MAC address of the new network device in real time and sends it to the MCU via the SMI interface. The MCU uses a binary search method to match the new MAC address with the MAC address table to perform address conflict verification, and performs MAC address loop verification based on the MAC address table to generate a MAC verification result. The MAC verification result is displayed in real time on the LCD screen. When the MAC verification result is normal, the new MAC address is updated to the MAC address table based on the sorting rules.

[0018] Furthermore, in step S6, uploading the switch data to the server via the Console interface for fault location specifically involves:

[0019] The server creates a fault location model based on a neural network, sets the loss function of the fault location model to the cross-entropy loss function, acquires a large amount of historical switch data, performs data cleaning preprocessing on each of the historical switch data, and then labels the preprocessed historical switch data with fault type, fault level and fault handling measures to construct a dataset.

[0020] The server divides the dataset into training, validation, and test sets based on a preset ratio. The fault location model is trained using the training set until the cross-entropy loss function is less than a preset loss function. During training, the hyperparameters of the fault location model are continuously optimized. The fault location accuracy is then calculated using the validation set to validate the trained fault location model. The confidence score is calculated using the test set to test the validated fault location model. Finally, the tested fault location model is deployed.

[0021] The MCU uploads the switch data to the server via the Console interface. The server uses the deployed fault location model to locate faults in the switch data and generates a fault location report that includes the fault type, fault level, fault handling measures, and detection time. The server stores and backs up the fault location report and feeds it back to the MCU. The MCU performs a transmission link recovery operation based on the received fault location report.

[0022] Secondly, the present invention provides a transmission link fault location system based on physical signal monitoring, comprising the following modules:

[0023] The register group creation module is used to create a register group for the Layer 2 switching chip of the Layer 2 switch located in the transmission link, including control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register and global reset register.

[0024] The MAC address table creation module is used by the MCU of the Layer 2 switch to create a MAC address table for storing the MAC addresses of the current network. The MAC address table stores the MsbMac and LsbMac of the MAC address in a two-dimensional array structure, and sets the sorting rules of the MAC address table. MsbMac and LsbMac are the high 3 bytes and low 3 bytes of data of the MAC address, respectively, and are represented by 32-bit integers.

[0025] The MAC address verification module is used when the Layer 2 switching chip connects to a new network device through a physical port. It reads the new MAC address of the new network device and sends it to the MCU through the SMI interface. The MCU performs anomaly verification on the new MAC address through the MAC address table, generates a MAC verification result, displays the MAC verification result in real time on the LCD screen, and updates the MAC address table based on the MAC verification result and sorting rules.

[0026] The fault location module is used during the operation of the Layer 2 switch. The Layer 2 switching chip monitors physical signals in real time and performs fault location based on the physical signals through the watchdog event of the queue controller. When a fault is located, the event register is updated based on the fault type, and an interrupt event is sent to the MCU through the interrupt pin.

[0027] The fault handling measure matching module is used by the MCU to read the fault type from the event register of the Layer 2 switching chip through the SMI interface based on the received interrupt event, match the fault handling measure from the preset fault management table according to the fault type, and display the fault type in real time through the LCD screen.

[0028] The fault recovery module is used to perform a transmission link recovery operation based on the fault handling measures when the MCU matches the fault handling measures; when the fault handling measures are not matched, it reads switch data from the register group and uploads the switch data to the server for fault location through the Console interface, or performs fault location and transmission link recovery operations based on console commands input from the Console interface.

[0029] Furthermore, in the register group creation module, the control register is used to identify the interface configuration mode; the status register is used to identify the interface status; the auto-negotiation capability register is used to identify the interface auto-negotiation status; the master-slave mode register is used to identify the master-slave status; the PHY register is used to identify the PHY manufacturer and model; the custom register is used to identify custom content; the event register is used to identify the fault type; and the global reset register is used to identify whether a global reset is performed.

[0030] Furthermore, in the MAC address table creation module, the sorting rule is specifically as follows:

[0031] First, sort the MAC addresses based on LsbMac. Then, for MAC addresses with the same LsbMac, sort the MAC addresses again based on MsbMac.

[0032] Furthermore, the MAC address verification module is specifically used for:

[0033] When a Layer 2 switching chip connects to a new network device through a physical port, it reads the new MAC address of the new network device in real time and sends it to the MCU via the SMI interface. The MCU uses a binary search method to match the new MAC address with the MAC address table to perform address conflict verification, and performs MAC address loop verification based on the MAC address table to generate a MAC verification result. The MAC verification result is displayed in real time on the LCD screen. When the MAC verification result is normal, the new MAC address is updated to the MAC address table based on the sorting rules.

[0034] Furthermore, in the fault recovery module, the step of uploading the switch data to the server via the Console interface for fault location specifically involves:

[0035] The server creates a fault location model based on a neural network, sets the loss function of the fault location model to the cross-entropy loss function, acquires a large amount of historical switch data, performs data cleaning preprocessing on each of the historical switch data, and then labels the preprocessed historical switch data with fault type, fault level and fault handling measures to construct a dataset.

[0036] The server divides the dataset into training, validation, and test sets based on a preset ratio. The fault location model is trained using the training set until the cross-entropy loss function is less than a preset loss function. During training, the hyperparameters of the fault location model are continuously optimized. The fault location accuracy is then calculated using the validation set to validate the trained fault location model. The confidence score is calculated using the test set to test the validated fault location model. Finally, the tested fault location model is deployed.

[0037] The MCU uploads the switch data to the server via the Console interface. The server uses the deployed fault location model to locate faults in the switch data and generates a fault location report that includes the fault type, fault level, fault handling measures, and detection time. The server stores and backs up the fault location report and feeds it back to the MCU. The MCU performs a transmission link recovery operation based on the received fault location report. Beneficial effects

[0038] The advantages of this invention are:

[0039] 1. A register set is created by the Layer 2 switching chip of the Layer 2 switch located on the transmission link, including a control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register, and global reset register. The MCU of the Layer 2 switch creates a MAC address table and sets the sorting rules for the MAC address table. When the Layer 2 switching chip connects to a new network device through a physical port, it reads the new MAC address of the new network device and sends it to the MCU through the SMI interface. The MCU performs anomaly verification on the new MAC address through the MAC address table and displays the MAC verification result in real time on the LCD screen. Based on the MAC verification result and the sorting rules, the MAC address table is updated. During the operation of the Layer 2 switch, the Layer 2 switching chip monitors physical signals in real time and performs fault location based on physical signals through the queue controller watchdog event. When a fault is located, the event register is updated based on the fault type, and an interrupt event is sent to the MCU through the interrupt pin. Based on the interrupt event, the MCU reads the fault type from the event register of the Layer 2 switching chip through the SMI interface, matches the fault handling measures from the preset fault management table according to the fault type, and displays the fault type in real time on the LCD screen. When the MCU matches a fault handling measure, it performs transmission link restoration based on the fault handling measure. Operation: When no fault handling measures are matched, the switch data is read from the register group and uploaded to the server for fault location via the Console interface, or fault location and transmission link restoration operations are performed based on console commands input from the Console interface. In other words, this invention adds an MCU, an LCD display, and a Console interface to a traditional Layer 2 switch. When a fault occurs in the Layer 2 switching chip, an interrupt event is sent to the MCU via the interrupt pin. After receiving the interrupt event, the MCU reads the fault type from the Layer 2 switching chip via the SMI interface and matches fault handling measures based on the fault management table. If no fault handling measures are matched, switch data can be uploaded via the Console interface for fault location, or fault location and transmission link restoration operations can be performed based on console commands input from the Console interface. The MCU also stores a MAC address table for address conflict and loop verification and displays relevant data during the fault location process on the LCD display. That is, the Layer 2 switch first detects and handles faults locally; if the fault cannot be eliminated, it then performs cloud-based detection via the server. It can also combine console commands and display relevant data in real time on the LCD display, ultimately greatly improving the convenience and timeliness of transmission link fault location.

[0040] 2. By creating a register group in the Layer 2 switching chip, including a control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register, and global reset register; the control register is used to identify the interface configuration mode; the status register is used to identify the interface status; the auto-negotiation capability register is used to identify the interface auto-negotiation status; the master-slave mode register is used to identify the master-slave status; the PHY register is used to identify the PHY manufacturer and model; the custom register is used to identify custom content; the event register is used to identify the fault type; and the global reset register is used to indicate whether a global reset has been performed. Subsequently, the switch data stored in the register group can be used for rapid and comprehensive fault location, thereby greatly improving the timeliness and accuracy of Layer 2 switch fault location.

[0041] 3. By setting up a MAC address table to store the MsbMac and LsbMac of MAC addresses in a two-dimensional array structure, each row of the MAC address table contains two columns, each storing MsbMac and LsbMac respectively. MsbMac and LsbMac together form a complete MAC address. The sorting rule of the MAC address table is to first sort the MAC addresses based on LsbMac, and for MAC addresses with the same LsbMac, then sort the MAC addresses again based on MsbMac. Subsequently, a binary search method can be used to quickly look up MAC addresses in the MAC address table or quickly insert MAC addresses into the MAC address table, thereby greatly improving the efficiency of MAC address management.

[0042] 4. By setting the MAC address to be represented by a 32-bit integer, it has the advantages of small space occupation, high calculation efficiency, easy integration and easy indexing, which further improves the management efficiency of MAC addresses.

[0043] 5. A fault location model is created on the server based on a neural network. The loss function of the fault location model is set as the cross-entropy loss function. A large amount of historical switch data is preprocessed and labeled to construct a dataset. The dataset is divided into training set, validation set, and test set. The fault location model is trained on the training set until the loss value of the cross-entropy loss function is less than the preset loss function. During the training process, the hyperparameters of the fault location model are continuously optimized. The trained fault location model is then validated on the validation set and tested on the test set. The tested fault location model is then deployed. Subsequently, the uploaded switch data is input into the deployed fault location model for rapid fault location. Because the neural network can effectively learn fault features, and it is trained with big data (a large amount of historical switch data), combined with model optimization, validation, and testing, the fault location accuracy is greatly improved. Attached Figure Description

[0044] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0045] Figure 1 is a flowchart of a transmission link fault location method based on physical signal monitoring according to the present invention.

[0046] Figure 2 is a schematic diagram of the structure of a transmission link fault location system based on physical signal monitoring according to the present invention.

[0047] Figure 3 is a hardware architecture diagram of the Layer 2 switch of the present invention. Embodiments of the present invention

[0048] The overall concept of the technical solution in this application embodiment is as follows: An MCU, an LCD display, and a Console interface are added to a traditional Layer 2 switch. When a fault occurs in the Layer 2 switching chip, an interrupt event is sent to the MCU via an interrupt pin. After receiving the interrupt event, the MCU reads the fault type from the Layer 2 switching chip through the SMI interface and matches fault handling measures based on the fault management table. If no fault handling measures are matched, switch data can be uploaded through the Console interface for fault location, or fault location and transmission link restoration operations can be performed based on console commands input from the Console interface. The MCU also stores a MAC address table for address conflict and loop verification and displays relevant data during the fault location process on the LCD display to improve the convenience and timeliness of transmission link fault location.

[0049] Please refer to Figures 1 to 3. The present invention requires the use of a Layer 2 switch, including a Layer 2 switch chip, an MCU, an LCD display, a Console interface (RJ45 interface), a power module, a clock module, and a memory.

[0050] The Layer 2 switching chip is connected to the MCU via an interrupt pin (INT) and an SMI interface; the MCU is connected to the Console interface via a UART and to the LCD display via an I2C bus; the Layer 2 switching chip is also connected to the power module, clock module, and memory.

[0051] The LCD display screen is used to display the current network status, abnormal information, number of terminals in the local area network, MAC address conflicts, interface connection status changes, and other information.

[0052] A preferred embodiment of the transmission link fault location method based on physical signal monitoring of the present invention includes the following steps:

[0053] Step S1: The Layer 2 switching chip of the Layer 2 switch located in the transmission link creates a register group including control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register and global reset register.

[0054] Step S2: The MCU of the Layer 2 switch creates a MAC address table to store the MAC addresses of the current network. The MAC address table stores the MsbMac and LsbMac of the MAC address in a two-dimensional array structure, and sets the sorting rules of the MAC address table. MsbMac and LsbMac are the high 3 bytes and low 3 bytes of data of the MAC address, respectively, and are represented by 32-bit integers.

[0055] By setting MAC addresses to be represented by 32-bit integers, the advantages of small space occupation, high computational efficiency, easy integration, and easy indexing are achieved, further improving the management efficiency of MAC addresses.

[0056] Step S3: When the Layer 2 switching chip connects to a new network device through a physical port, it reads the new MAC address of the new network device and sends it to the MCU through the SMI interface. The MCU performs anomaly verification on the new MAC address through the MAC address table, generates a MAC verification result, displays the MAC verification result in real time on the LCD screen, and updates the MAC address table based on the MAC verification result and sorting rules.

[0057] In practical implementation, a network topology may contain multiple Layer 2 switches, each with multiple network devices connected to it. This can result in multiple MAC addresses appearing simultaneously in a single Layer 2 network. Since some of these MAC addresses are already in the MAC address table, it's necessary to distinguish which MAC address belongs to the newly connected network device and verify that MAC address. Specifically:

[0058] When a new network device connects, all the MAC addresses are read and a CRC check value is calculated. The CRC check value is compared with the previously calculated CRC check value. If the values ​​are inconsistent, it indicates that there has been a change in the MAC address. Then, the MAC addresses are sorted according to the sorting rules to update the MAC address table. The newly connected MAC address is located by comparing the updated MAC address table with the MAC address table before the update, and then the MAC address is verified.

[0059] Step S4: During the operation of the Layer 2 switch, the Layer 2 switching chip locates faults through the Queue Controller Watch Dog Event. When a fault is detected, the event register is updated based on the fault type, and an interrupt event is sent to the MCU through the interrupt pin.

[0060] Layer 2 switching chips provide fault location mechanisms (anomaly detection mechanisms), such as whether an internal interrupt of the Layer 2 switching chip's forwarding logic has been triggered, or whether abnormal network traffic has triggered an internal buffer waterline anomaly in the Layer 2 switching chip.

[0061] Step S5: Based on the received interrupt event, the MCU reads the fault type from the event register of the Layer 2 switching chip through the SMI interface, matches the fault handling measures with the fault type from the preset fault management table, and displays the fault type in real time on the LCD screen. In specific implementation, if the specific fault type cannot be determined, the MCU can also determine which port's interface status has changed through the status register to assist in fault location.

[0062] Step S6: When the MCU matches the fault handling measure, it executes a transmission link recovery operation based on the fault handling measure. The interrupt triggering mechanism allows for rapid response and handling of Layer 2 switching chip faults, achieving network self-recovery within milliseconds. If no fault handling measure is matched, the MCU reads switch data from the register group and uploads the switch data to the server for fault location via the Console interface, or executes fault location and transmission link recovery operations based on console commands input from the Console interface. The switch data refers to the data stored in each register of the register group.

[0063] In step S1, the control register is used to identify the interface configuration mode, including whether auto-negotiation is enabled, and the configuration of speed and duplex mode; the status register is used to identify the interface status, including the auto-negotiation status and link status; the auto-negotiation capability register is used to identify the interface auto-negotiation status, including the auto-negotiation capability enabled on the local end and the auto-negotiation capability and status on the remote end; the master-slave mode register is used to identify the master-slave status, i.e., it is used to view and configure the master-slave mode status under 1000base-T and 100base-T2 modes; the PHY register is used to identify the PHY manufacturer and model, which can also be used for fault location. For example, when a certain model of a Layer 2 switch from a certain manufacturer experiences a certain situation, big data analysis technology can be used to determine the most likely fault and how to handle it; the custom register is used to identify custom content; the event register is used to identify the fault type; and the global reset register is used to identify whether a global reset is performed.

[0064] By creating a register group in the Layer 2 switching chip, including a control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register, and global reset register; the control register is used to identify the interface configuration mode; the status register is used to identify the interface status; the auto-negotiation capability register is used to identify the interface auto-negotiation status; the master-slave mode register is used to identify the master-slave status; the PHY register is used to identify the PHY manufacturer and model; the custom register is used to identify custom content; the event register is used to identify the fault type; and the global reset register is used to indicate whether a global reset has been performed. Subsequently, the switch data stored in the register group can be used for rapid and comprehensive fault location, thereby greatly improving the timeliness and accuracy of Layer 2 switch fault location.

[0065] In step S2, the sorting rule is specifically as follows:

[0066] First, sort the MAC addresses based on LsbMac. Then, for MAC addresses with the same LsbMac, sort the MAC addresses again based on MsbMac.

[0067] By setting up a MAC address table to store the MsbMac and LsbMac of MAC addresses in a two-dimensional array structure, each row of the MAC address table contains two columns, each storing MsbMac and LsbMac respectively. MsbMac and LsbMac together form a complete MAC address. The sorting rule of the MAC address table is to first sort the MAC addresses based on LsbMac, and for MAC addresses with the same LsbMac, then sort the MAC addresses again based on MsbMac. Subsequently, a binary search method can be used to quickly look up MAC addresses in the MAC address table or quickly insert MAC addresses into the MAC address table, thereby greatly improving the efficiency of MAC address management.

[0068] Step S3 specifically involves:

[0069] When a Layer 2 switching chip connects to a new network device through a physical port, it reads the new MAC address of the new network device in real time and sends it to the MCU via the SMI interface. The MCU uses a binary search method to match the new MAC address with the MAC address table to perform address conflict verification, and performs MAC address loop verification based on the MAC address table to generate a MAC verification result. The MAC verification result is displayed in real time on the LCD screen. When the MAC verification result is normal, the new MAC address is updated to the MAC address table based on the sorting rules.

[0070] If the new MAC address does not exist in the MAC address table, the new MAC address will be stored; otherwise, an error will be displayed.

[0071] In step S6, uploading the switch data to the server via the Console interface for fault location specifically involves:

[0072] The server creates a fault location model based on a neural network, sets the loss function of the fault location model to the cross-entropy loss function, acquires a large amount of historical switch data, performs data cleaning preprocessing on each of the historical switch data, and then labels the preprocessed historical switch data with fault type, fault level and fault handling measures to construct a dataset.

[0073] The server divides the dataset into training, validation, and test sets based on a preset ratio. The fault location model is trained using the training set until the cross-entropy loss function is less than a preset loss function. During training, the hyperparameters of the fault location model are continuously optimized. The fault location accuracy is then calculated using the validation set to validate the trained fault location model. The confidence score is calculated using the test set to test the validated fault location model. Finally, the tested fault location model is deployed.

[0074] The MCU uploads the switch data to the server via the Console interface. The server uses the deployed fault location model to locate faults in the switch data and generates a fault location report that includes the fault type, fault level, fault handling measures, and detection time. The server stores and backs up the fault location report and feeds it back to the MCU. The MCU performs a transmission link recovery operation based on the received fault location report.

[0075] A fault location model based on a neural network is created on a server. The loss function of the fault location model is set as the cross-entropy loss function. A large amount of historical switch data is acquired, preprocessed, and labeled to construct a dataset. The dataset is divided into training, validation, and test sets. The fault location model is trained on the training set until the loss value of the cross-entropy loss function is less than the preset loss function. During the training process, the hyperparameters of the fault location model are continuously optimized. The trained fault location model is then validated on the validation set and tested on the test set. The tested fault location model is then deployed. Subsequently, the uploaded switch data is input into the deployed fault location model for rapid fault location. Because the neural network can effectively learn fault characteristics, and it is trained with large amounts of historical switch data, combined with model optimization, validation, and testing, the fault location accuracy is greatly improved.

[0076] The MCU records operational logs in real time, including at least the switch data, fault location reports, and fault handling results. These operational logs are encrypted using both the SDES and ChaCha20 algorithms, stored, and backed up to the server. Storing these operational logs facilitates later traceability, and encrypting them using two algorithms prevents them from being stolen or tampered with in plaintext, thus greatly improving the security of the operational log storage.

[0077] A preferred embodiment of the transmission link fault location system based on physical signal monitoring of the present invention includes the following modules:

[0078] The register group creation module is used to create a register group for the Layer 2 switching chip of the Layer 2 switch located in the transmission link, including control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register and global reset register.

[0079] The MAC address table creation module is used by the MCU of the Layer 2 switch to create a MAC address table for storing the MAC addresses of the current network. The MAC address table stores the MsbMac and LsbMac of the MAC address in a two-dimensional array structure, and sets the sorting rules of the MAC address table. MsbMac and LsbMac are the high 3 bytes and low 3 bytes of data of the MAC address, respectively, and are represented by 32-bit integers.

[0080] By setting MAC addresses to be represented by 32-bit integers, the advantages of small space occupation, high computational efficiency, easy integration, and easy indexing are achieved, further improving the management efficiency of MAC addresses.

[0081] The MAC address verification module is used when the Layer 2 switching chip connects to a new network device through a physical port. It reads the new MAC address of the new network device and sends it to the MCU through the SMI interface. The MCU performs anomaly verification on the new MAC address through the MAC address table, generates a MAC verification result, displays the MAC verification result in real time on the LCD screen, and updates the MAC address table based on the MAC verification result and sorting rules.

[0082] In practical implementation, a network topology may contain multiple Layer 2 switches, each with multiple network devices connected to it. This can result in multiple MAC addresses appearing simultaneously in a single Layer 2 network. Since some of these MAC addresses are already in the MAC address table, it's necessary to distinguish which MAC address belongs to the newly connected network device and verify that MAC address. Specifically:

[0083] When a new network device connects, all the MAC addresses are read and a CRC check value is calculated. The CRC check value is compared with the previously calculated CRC check value. If the values ​​are inconsistent, it indicates that there has been a change in the MAC address. Then, the MAC addresses are sorted according to the sorting rules to update the MAC address table. The newly connected MAC address is located by comparing the updated MAC address table with the MAC address table before the update, and then the MAC address is verified.

[0084] The fault location module is used during the operation of the Layer 2 switch. The Layer 2 switching chip locates faults through the Queue Controller Watch Dog Event. When a fault is detected, the event register is updated based on the fault type, and an interrupt event is sent to the MCU through the interrupt pin.

[0085] Layer 2 switching chips provide fault location mechanisms (anomaly detection mechanisms), such as whether an internal interrupt of the Layer 2 switching chip's forwarding logic has been triggered, or whether abnormal network traffic has triggered an internal buffer waterline anomaly in the Layer 2 switching chip.

[0086] The fault handling measure matching module is used by the MCU to read the fault type from the event register of the Layer 2 switching chip through the SMI interface based on the received interrupt event, match the fault handling measure from the preset fault management table according to the fault type, and display the fault type in real time on the LCD screen. In specific implementation, if the specific fault type cannot be determined, the MCU can also determine which port's interface status has changed through the status register to assist in fault location.

[0087] The fault recovery module is used to perform transmission link recovery operations based on the fault handling measures when the MCU matches them. Through an interrupt-triggered mechanism, it can quickly respond to and handle Layer 2 switching chip faults, achieving network self-recovery in milliseconds. When no fault handling measures are matched, it reads switch data from the register group and uploads the switch data to the server for fault location via the Console interface, or performs fault location and transmission link recovery operations based on console commands input from the Console interface. The switch data refers to the data stored in each register of the register group.

[0088] In the register group creation module, the control register is used to identify the interface configuration mode, including whether auto-negotiation, speed, and duplex mode configuration are enabled; the status register is used to identify the interface status, including auto-negotiation status and link status; the auto-negotiation capability register is used to identify the interface auto-negotiation status, including the auto-negotiation capability enabled on the local end and the auto-negotiation capability and status on the remote end; the master-slave mode register is used to identify the master-slave status, i.e., to view and configure the master-slave mode status under 1000base-T and 100base-T2 modes; the PHY register is used to identify the PHY manufacturer and model, which can also be used for fault location. For example, when a certain model of a Layer 2 switch from a certain manufacturer experiences a certain situation, big data analysis technology can be used to determine the most likely fault and how to handle it; the custom register is used to identify custom content; the event register is used to identify the fault type; and the global reset register is used to indicate whether a global reset is performed.

[0089] By creating a register group in the Layer 2 switching chip, including a control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register, and global reset register; the control register is used to identify the interface configuration mode; the status register is used to identify the interface status; the auto-negotiation capability register is used to identify the interface auto-negotiation status; the master-slave mode register is used to identify the master-slave status; the PHY register is used to identify the PHY manufacturer and model; the custom register is used to identify custom content; the event register is used to identify the fault type; and the global reset register is used to indicate whether a global reset has been performed. Subsequently, the switch data stored in the register group can be used for rapid and comprehensive fault location, thereby greatly improving the timeliness and accuracy of Layer 2 switch fault location.

[0090] In the MAC address table creation module, the sorting rule is specifically as follows:

[0091] First, sort the MAC addresses based on LsbMac. Then, for MAC addresses with the same LsbMac, sort the MAC addresses again based on MsbMac.

[0092] By setting up a MAC address table to store the MsbMac and LsbMac of MAC addresses in a two-dimensional array structure, each row of the MAC address table contains two columns, each storing MsbMac and LsbMac respectively. MsbMac and LsbMac together form a complete MAC address. The sorting rule of the MAC address table is to first sort the MAC addresses based on LsbMac, and for MAC addresses with the same LsbMac, then sort the MAC addresses again based on MsbMac. Subsequently, a binary search method can be used to quickly look up MAC addresses in the MAC address table or quickly insert MAC addresses into the MAC address table, thereby greatly improving the efficiency of MAC address management.

[0093] The MAC address verification module is specifically used for:

[0094] When a Layer 2 switching chip connects to a new network device through a physical port, it reads the new MAC address of the new network device in real time and sends it to the MCU via the SMI interface. The MCU uses a binary search method to match the new MAC address with the MAC address table to perform address conflict verification, and performs MAC address loop verification based on the MAC address table to generate a MAC verification result. The MAC verification result is displayed in real time on the LCD screen. When the MAC verification result is normal, the new MAC address is updated to the MAC address table based on the sorting rules.

[0095] If the new MAC address does not exist in the MAC address table, the new MAC address will be stored; otherwise, an error will be displayed.

[0096] In the fault recovery module, the step of uploading the switch data to the server via the Console interface for fault location specifically involves:

[0097] The server creates a fault location model based on a neural network, sets the loss function of the fault location model to the cross-entropy loss function, acquires a large amount of historical switch data, performs data cleaning preprocessing on each of the historical switch data, and then labels the preprocessed historical switch data with fault type, fault level and fault handling measures to construct a dataset.

[0098] The server divides the dataset into training, validation, and test sets based on a preset ratio. The fault location model is trained using the training set until the cross-entropy loss function is less than a preset loss function. During training, the hyperparameters of the fault location model are continuously optimized. The fault location accuracy is then calculated using the validation set to validate the trained fault location model. The confidence score is calculated using the test set to test the validated fault location model. Finally, the tested fault location model is deployed.

[0099] The MCU uploads the switch data to the server via the Console interface. The server uses the deployed fault location model to locate faults in the switch data and generates a fault location report that includes the fault type, fault level, fault handling measures, and detection time. The server stores and backs up the fault location report and feeds it back to the MCU. The MCU performs a transmission link recovery operation based on the received fault location report.

[0100] A fault location model based on a neural network is created on a server. The loss function of the fault location model is set as the cross-entropy loss function. A large amount of historical switch data is acquired, preprocessed, and labeled to construct a dataset. The dataset is divided into training, validation, and test sets. The fault location model is trained on the training set until the loss value of the cross-entropy loss function is less than the preset loss function. During the training process, the hyperparameters of the fault location model are continuously optimized. The trained fault location model is then validated on the validation set and tested on the test set. The tested fault location model is then deployed. Subsequently, the uploaded switch data is input into the deployed fault location model for rapid fault location. Because the neural network can effectively learn fault characteristics, and it is trained with large amounts of historical switch data, combined with model optimization, validation, and testing, the fault location accuracy is greatly improved.

[0101] The MCU records operational logs in real time, including at least the switch data, fault location reports, and fault handling results. These operational logs are encrypted using both the SDES and ChaCha20 algorithms, stored, and backed up to the server. Storing these operational logs facilitates later traceability, and encrypting them using two algorithms prevents them from being stolen or tampered with in plaintext, thus greatly improving the security of the operational log storage.

[0102] In summary, the advantages of this invention are as follows:

[0103] 1. A register set is created by the Layer 2 switching chip of the Layer 2 switch located on the transmission link, including a control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register, and global reset register. The MCU of the Layer 2 switch creates a MAC address table and sets the sorting rules for the MAC address table. When the Layer 2 switching chip connects to a new network device through a physical port, it reads the new MAC address of the new network device and sends it to the MCU through the SMI interface. The MCU performs anomaly verification on the new MAC address through the MAC address table and displays the MAC verification result in real time on the LCD screen. Based on the MAC verification result and the sorting rules, the MAC address table is updated. During the operation of the Layer 2 switch, the Layer 2 switching chip monitors physical signals in real time and performs fault location based on physical signals through the queue controller watchdog event. When a fault is located, the event register is updated based on the fault type, and an interrupt event is sent to the MCU through the interrupt pin. Based on the interrupt event, the MCU reads the fault type from the event register of the Layer 2 switching chip through the SMI interface, matches the fault handling measures from the preset fault management table according to the fault type, and displays the fault type in real time on the LCD screen. When the MCU matches a fault handling measure, it performs transmission link restoration based on the fault handling measure. Operation: When no fault handling measures are matched, the switch data is read from the register group and uploaded to the server for fault location via the Console interface, or fault location and transmission link restoration operations are performed based on console commands input from the Console interface. In other words, this invention adds an MCU, an LCD display, and a Console interface to a traditional Layer 2 switch. When a fault occurs in the Layer 2 switching chip, an interrupt event is sent to the MCU via the interrupt pin. After receiving the interrupt event, the MCU reads the fault type from the Layer 2 switching chip via the SMI interface and matches fault handling measures based on the fault management table. If no fault handling measures are matched, switch data can be uploaded via the Console interface for fault location, or fault location and transmission link restoration operations can be performed based on console commands input from the Console interface. The MCU also stores a MAC address table for address conflict and loop verification and displays relevant data during the fault location process on the LCD display. That is, the Layer 2 switch first detects and handles faults locally; if the fault cannot be eliminated, it then performs cloud-based detection via the server. It can also combine console commands and display relevant data in real time on the LCD display, ultimately greatly improving the convenience and timeliness of transmission link fault location.

[0104] 2. By creating a register group in the Layer 2 switching chip, including a control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register, and global reset register; the control register is used to identify the interface configuration mode; the status register is used to identify the interface status; the auto-negotiation capability register is used to identify the interface auto-negotiation status; the master-slave mode register is used to identify the master-slave status; the PHY register is used to identify the PHY manufacturer and model; the custom register is used to identify custom content; the event register is used to identify the fault type; and the global reset register is used to indicate whether a global reset has been performed. Subsequently, the switch data stored in the register group can be used for rapid and comprehensive fault location, thereby greatly improving the timeliness and accuracy of Layer 2 switch fault location.

[0105] 3. By setting up a MAC address table to store the MsbMac and LsbMac of MAC addresses in a two-dimensional array structure, each row of the MAC address table contains two columns, each storing MsbMac and LsbMac respectively. MsbMac and LsbMac together form a complete MAC address. The sorting rule of the MAC address table is to first sort the MAC addresses based on LsbMac, and for MAC addresses with the same LsbMac, then sort the MAC addresses again based on MsbMac. Subsequently, a binary search method can be used to quickly look up MAC addresses in the MAC address table or quickly insert MAC addresses into the MAC address table, thereby greatly improving the efficiency of MAC address management.

[0106] 4. By setting the MAC address to be represented by a 32-bit integer, it has the advantages of small space occupation, high calculation efficiency, easy integration and easy indexing, which further improves the management efficiency of MAC addresses.

[0107] 5. A fault location model is created on the server based on a neural network. The loss function of the fault location model is set as the cross-entropy loss function. A large amount of historical switch data is preprocessed and labeled to construct a dataset. The dataset is divided into training set, validation set, and test set. The fault location model is trained on the training set until the loss value of the cross-entropy loss function is less than the preset loss function. During the training process, the hyperparameters of the fault location model are continuously optimized. The trained fault location model is then validated on the validation set and tested on the test set. The tested fault location model is then deployed. Subsequently, the uploaded switch data is input into the deployed fault location model for rapid fault location. Because the neural network can effectively learn fault features, and it is trained with big data (a large amount of historical switch data), combined with model optimization, validation, and testing, the fault location accuracy is greatly improved.

[0108] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for locating transmission link faults based on physical signal monitoring, characterized in that: Includes the following steps: Step S1: The Layer 2 switching chip of the Layer 2 switch located in the transmission link creates a register group including control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register and global reset register. Step S2: The MCU of the Layer 2 switch creates a MAC address table to store the MAC addresses of the current network. The MAC address table stores the MsbMac and LsbMac of the MAC address in a two-dimensional array structure, and sets the sorting rules of the MAC address table. MsbMac and LsbMac are the high 3 bytes and low 3 bytes of data of the MAC address, respectively, and are represented by 32-bit integers. Step S3: When the Layer 2 switching chip connects to a new network device through a physical port, it reads the new MAC address of the new network device and sends it to the MCU through the SMI interface. The MCU performs anomaly verification on the new MAC address through the MAC address table, generates a MAC verification result, displays the MAC verification result in real time on the LCD screen, and updates the MAC address table based on the MAC verification result and sorting rules. Step S4: During the operation of the Layer 2 switch, the Layer 2 switching chip monitors the physical signals in real time and performs fault location based on the physical signals through the queue controller watchdog event. When a fault is located, the event register is updated based on the fault type, and an interrupt event is sent to the MCU through the interrupt pin. Step S5: Based on the received interrupt event, the MCU reads the fault type from the event register of the Layer 2 switching chip through the SMI interface, matches the fault handling measures with the fault type from the preset fault management table, and displays the fault type in real time on the LCD screen. Step S6: When the MCU matches the fault handling measure, it performs a transmission link recovery operation based on the fault handling measure; when the fault handling measure is not matched, it reads the switch data from the register group and uploads the switch data to the server for fault location through the Console interface, or performs fault location and transmission link recovery operations based on the console command input from the Console interface.

2. The method for locating transmission link faults based on physical signal monitoring as described in claim 1, characterized in that: In step S1, the control register is used to identify the interface configuration mode; the status register is used to identify the interface status; the auto-negotiation capability register is used to identify the interface auto-negotiation status; the master-slave mode register is used to identify the master-slave status; the PHY register is used to identify the PHY manufacturer and model; the custom register is used to identify custom content; the event register is used to identify the fault type; and the global reset register is used to identify whether a global reset is performed.

3. The method for locating transmission link faults based on physical signal monitoring as described in claim 1, characterized in that: In step S2, the sorting rule is specifically as follows: First, sort the MAC addresses based on LsbMac. Then, for MAC addresses with the same LsbMac, sort the MAC addresses again based on MsbMac.

4. The method for locating transmission link faults based on physical signal monitoring as described in claim 1, characterized in that: Step S3 specifically involves: When a Layer 2 switching chip connects to a new network device through a physical port, it reads the new MAC address of the new network device in real time and sends it to the MCU via the SMI interface. The MCU uses a binary search method to match the new MAC address with the MAC address table to perform address conflict verification, and performs MAC address loop verification based on the MAC address table to generate a MAC verification result. The MAC verification result is displayed in real time on the LCD screen. When the MAC verification result is normal, the new MAC address is updated to the MAC address table based on the sorting rules.

5. The method for locating transmission link faults based on physical signal monitoring as described in claim 1, characterized in that: In step S6, uploading the switch data to the server via the Console interface for fault location specifically involves: The server creates a fault location model based on a neural network, sets the loss function of the fault location model to the cross-entropy loss function, acquires a large amount of historical switch data, performs data cleaning preprocessing on each of the historical switch data, and then labels the preprocessed historical switch data with fault type, fault level and fault handling measures to construct a dataset. The server divides the dataset into training, validation, and test sets based on a preset ratio. The fault location model is trained using the training set until the cross-entropy loss function is less than a preset loss function. During training, the hyperparameters of the fault location model are continuously optimized. The fault location accuracy is then calculated using the validation set to validate the trained fault location model. The confidence score is calculated using the test set to test the validated fault location model. Finally, the tested fault location model is deployed. The MCU uploads the switch data to the server via the Console interface. The server uses the deployed fault location model to locate faults in the switch data and generates a fault location report that includes the fault type, fault level, fault handling measures, and detection time. The server stores and backs up the fault location report and feeds it back to the MCU. The MCU performs a transmission link recovery operation based on the received fault location report.

6. A transmission link fault location system based on physical signal monitoring, characterized in that: Includes the following modules: The register group creation module is used to create a register group for the Layer 2 switching chip of the Layer 2 switch located in the transmission link, including control register, status register, auto-negotiation capability register, master-slave mode register, PHY register, custom register, event register and global reset register. The MAC address table creation module is used by the MCU of the Layer 2 switch to create a MAC address table for storing the MAC addresses of the current network. The MAC address table stores the MsbMac and LsbMac of the MAC address in a two-dimensional array structure, and sets the sorting rules of the MAC address table. MsbMac and LsbMac are the high 3 bytes and low 3 bytes of data of the MAC address, respectively, and are represented by 32-bit integers. The MAC address verification module is used when the Layer 2 switching chip connects to a new network device through a physical port. It reads the new MAC address of the new network device and sends it to the MCU through the SMI interface. The MCU performs anomaly verification on the new MAC address through the MAC address table, generates a MAC verification result, displays the MAC verification result in real time on the LCD screen, and updates the MAC address table based on the MAC verification result and sorting rules. The fault location module is used during the operation of the Layer 2 switch. The Layer 2 switching chip monitors physical signals in real time and performs fault location based on the physical signals through the watchdog event of the queue controller. When a fault is located, the event register is updated based on the fault type, and an interrupt event is sent to the MCU through the interrupt pin. The fault handling measure matching module is used by the MCU to read the fault type from the event register of the Layer 2 switching chip through the SMI interface based on the received interrupt event, match the fault handling measure from the preset fault management table according to the fault type, and display the fault type in real time through the LCD screen. The fault recovery module is used to perform a transmission link recovery operation based on the fault handling measures when the MCU matches the fault handling measures; when the fault handling measures are not matched, it reads switch data from the register group and uploads the switch data to the server for fault location through the Console interface, or performs fault location and transmission link recovery operations based on console commands input from the Console interface.

7. The transmission link fault location system based on physical signal monitoring as described in claim 6, characterized in that: In the register group creation module, the control register is used to identify the interface configuration mode; the status register is used to identify the interface status; the auto-negotiation capability register is used to identify the interface auto-negotiation status; the master-slave mode register is used to identify the master-slave status; the PHY register is used to identify the PHY manufacturer and model; the custom register is used to identify custom content; the event register is used to identify the fault type; and the global reset register is used to identify whether a global reset is performed.

8. The transmission link fault location system based on physical signal monitoring as described in claim 6, characterized in that: In the MAC address table creation module, the sorting rule is specifically as follows: First, sort the MAC addresses based on LsbMac. Then, for MAC addresses with the same LsbMac, sort the MAC addresses again based on MsbMac.

9. The transmission link fault location system based on physical signal monitoring as described in claim 6, characterized in that: The MAC address verification module is specifically used for: When a Layer 2 switching chip connects to a new network device through a physical port, it reads the new MAC address of the new network device in real time and sends it to the MCU via the SMI interface. The MCU uses a binary search method to match the new MAC address with the MAC address table to perform address conflict verification, and performs MAC address loop verification based on the MAC address table to generate a MAC verification result. The MAC verification result is displayed in real time on the LCD screen. When the MAC verification result is normal, the new MAC address is updated to the MAC address table based on the sorting rules.

10. A transmission link fault location system based on physical signal monitoring as described in claim 6, characterized in that: In the fault recovery module, the step of uploading the switch data to the server via the Console interface for fault location specifically involves: The server creates a fault location model based on a neural network, sets the loss function of the fault location model to the cross-entropy loss function, acquires a large amount of historical switch data, performs data cleaning preprocessing on each of the historical switch data, and then labels the preprocessed historical switch data with fault type, fault level and fault handling measures to construct a dataset. The server divides the dataset into training, validation, and test sets based on a preset ratio. The fault location model is trained using the training set until the cross-entropy loss function is less than a preset loss function. During training, the hyperparameters of the fault location model are continuously optimized. The fault location accuracy is then calculated using the validation set to validate the trained fault location model. The confidence score is calculated using the test set to test the validated fault location model. Finally, the tested fault location model is deployed. The MCU uploads the switch data to the server via the Console interface. The server uses the deployed fault location model to locate faults in the switch data and generates a fault location report that includes the fault type, fault level, fault handling measures, and detection time. The server stores and backs up the fault location report and feeds it back to the MCU. The MCU performs a transmission link recovery operation based on the received fault location report.

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