Back contact cell and photovoltaic module

Abstract

The present application discloses a back contact cell and a photovoltaic module. The back contact cell comprises a plurality of first doping units, each first doping unit comprising a first doped conductive layer, a second doped conductive layer, and a first isolation region; the height of a first grid line on a first doped conductive layer is less than the height of a second grid line on an adjacent second doped conductive layer.

Description

Back contact batteries and photovoltaic modules

[0001] Cross-references

[0002] This disclosure incorporates, in its entirety, Chinese Patent Application No. 202520268929.6, filed on February 19, 2025, entitled “Back Contact Solar Cell, Back Contact Battery String, Photovoltaic Module and Photovoltaic System”, which is hereby incorporated by reference. Technical Field

[0003] This application relates to the field of solar cell technology, and in particular to a back-contact solar cell, a back-contact cell string, a photovoltaic module, and a photovoltaic system. Background Technology

[0004] Back-contact solar cell technology moves the PN junction and metal contact to the back of the cell, eliminating electrode obstruction on the front and allowing for a larger area of ​​sunlight absorption, resulting in higher photoelectric conversion efficiency. However, because the electrodes of back-contact solar cells are all located on the back, severe back-side shading significantly impacts the bifaciality of the solar cell.

[0005] Public content

[0006] The technical problem to be solved by this application is to provide a back-contact solar cell that can improve the bifaciality and yield of the back-contact solar cell.

[0007] The technical problem to be solved by this application is to provide a back-contact cell string including the above-mentioned back-contact solar cells, a corresponding photovoltaic module and a photovoltaic system.

[0008] To solve the above-mentioned technical problems, this application provides a back contact solar cell, including a plurality of first doped units. Each first doped unit includes a first doped conductive layer, a second doped conductive layer and a first isolation region disposed on the back side of a silicon substrate. The doping types of the first doped conductive layer and the second doped conductive layer are opposite, and the first isolation region is disposed between the first doped conductive layer and the second doped conductive layer.

[0009] The surface of the first isolation region is recessed into the silicon substrate relative to the surface of the first doped conductive layer; the surface of the first doped conductive layer is recessed into the silicon substrate relative to the surface of the second doped conductive layer.

[0010] A first gate line is provided on a first doped conductive layer, and a second gate line is provided on a second doped conductive layer. The height of the first gate line is less than the height of the adjacent second gate line.

[0011] In some embodiments, the depth to which the surface of the first doped conductive layer away from the silicon substrate is recessed into the silicon substrate relative to the surface of the second doped conductive layer away from the silicon substrate is 1.5 μm to 3.5 μm.

[0012] In some embodiments, the surface of the first gate line away from the silicon substrate is flush with the surface of the second doped conductive layer away from the silicon substrate.

[0013] In some implementations, the difference between the height of the first gate line and the height of the second gate line is Δh1, and the value of Δh1 ranges from 0.01 μm to 5 μm.

[0014] In some implementations, the value of h1 ranges from 0.8 μm to 2 μm.

[0015] In some embodiments, the surface of the first isolation region is recessed into the silicon substrate to a depth of 2 μm to 5 μm relative to the surface of the first doped conductive layer that is away from the silicon substrate.

[0016] In some embodiments, the thickness of the first doped conductive layer is smaller than the thickness of the second doped conductive layer;

[0017] The thickness of the first doped conductive layer is 120 nm to 300 nm, and the thickness of the second doped conductive layer is 150 nm to 400 nm.

[0018] In some embodiments, the width of the first doped conductive layer is smaller than the width of the second doped conductive layer;

[0019] The width of the first doped conductive layer is 50 μm to 500 μm, and the width of the second doped conductive layer is 60 μm to 600 μm.

[0020] In some embodiments, the surface of the first doped conductive layer is textured, and the surface of the second doped conductive layer is textured; or,

[0021] The surface of the first doped conductive layer is polished, and the surface of the second doped conductive layer is textured; or,

[0022] The surface of the first doped conductive layer is textured, and the surface of the second doped conductive layer is polished; or,

[0023] The surface of the first doped conductive layer is polished, and the surface of the second doped conductive layer is also polished.

[0024] In some embodiments, the first doped conductive layer is an N-type doped conductive layer, and the second doped conductive layer is a P-type doped conductive layer.

[0025] In some embodiments, a plurality of second doped units are also included, each second doped unit including a third doped conductive layer, a fourth doped conductive layer and a second isolation region disposed on the back side of the silicon substrate, wherein the doping types of the third doped conductive layer and the fourth doped conductive layer are opposite, and the second isolation region is disposed between the third doped conductive layer and the fourth doped conductive layer.

[0026] A third gate line is provided on the third doped conductive layer, and a fourth gate line is provided on the fourth doped conductive layer. The height of the third gate line is less than or equal to the height of the adjacent fourth gate line.

[0027] In some embodiments, the surface of the third doped conductive layer away from the silicon substrate is recessed into the silicon substrate to a depth of 1.5 μm to 3.5 μm relative to the surface of the fourth doped conductive layer away from the silicon substrate.

[0028] In some implementations, the surface of the third gate line away from the silicon substrate is flush with the surface of the fourth doped conductive layer away from the silicon substrate.

[0029] In some implementations, the difference between the height of the third gate line and the height of the fourth gate line is Δh2, where Δh2 < Δh1.

[0030] In some implementations, the value of Δh2 ranges from 0.01 μm to 3 μm.

[0031] In some embodiments, the surface of the second isolation region is recessed into the silicon substrate to a depth of 2 μm to 5 μm relative to the surface of the third doped conductive layer away from the silicon substrate.

[0032] In some embodiments, the thickness of the third doped conductive layer is less than the thickness of the fourth doped conductive layer;

[0033] The thickness of the third doped conductive layer is 120 nm to 300 nm, and the thickness of the fourth doped conductive layer is 150 nm to 400 nm.

[0034] In some embodiments, the width of the third doped conductive layer is smaller than the width of the fourth doped conductive layer;

[0035] The width of the third doped conductive layer is 50 μm to 500 μm, and the width of the fourth doped conductive layer is 60 μm to 600 μm.

[0036] In some embodiments, the surface of the third doped conductive layer is textured, and the surface of the fourth doped conductive layer is textured; or,

[0037] The surface of the third doped conductive layer is polished, and the surface of the fourth doped conductive layer is textured; or,

[0038] The surface of the third doped conductive layer is textured, and the surface of the fourth doped conductive layer is polished; or,

[0039] The surface of the third doped conductive layer is polished, and the surface of the fourth doped conductive layer is also polished.

[0040] In some embodiments, the third doped conductive layer is an N-type doped conductive layer, and the fourth doped conductive layer is a P-type doped conductive layer.

[0041] In some embodiments, the area of ​​the first doped unit accounts for 60% to 99% of the area of ​​the back contact solar cell, and the area of ​​the second doped unit accounts for 1% to 40% of the area of ​​the back contact solar cell.

[0042] In some embodiments, the area of ​​the first doped unit accounts for 80% to 99% of the area of ​​the back contact solar cell, and the area of ​​the second doped unit accounts for 1% to 20% of the area of ​​the back contact solar cell.

[0043] In some embodiments, the first doped unit is disposed in the middle of the back contact solar cell, and the second doped unit is disposed on both sides of the back contact solar cell.

[0044] In some embodiments, the first doped unit and the second doped unit are alternately disposed on the back contact solar cell.

[0045] This application also discloses a back-contact battery string, including the aforementioned back-contact solar cell.

[0046] This application also discloses a photovoltaic module, including the aforementioned back-contact battery string.

[0047] This application also discloses a photovoltaic system, including the aforementioned photovoltaic module.

[0048] This application has the following beneficial effects:

[0049] In the first doped unit of the back-contact solar cell provided in this application, the height of the first grid line is less than the height of the second grid line, and the surface of the first doped conductive layer is recessed into the silicon substrate relative to the surface of the second doped conductive layer. The surface of the first isolation region is also recessed into the silicon substrate relative to the surface of the first doped conductive layer. This height difference between the surfaces of the first and second grid lines reduces light shading by the grid lines, allowing more light to enter the silicon substrate through the sidewalls of the first isolation region, thus improving the bifaciality of the back-contact solar cell. Furthermore, the height of the second grid line is greater than the height of the first grid line, resulting in greater tensile strength at the second grid line. This effectively disperses stress when the back-contact solar cell is subjected to external pressure, improving the reliability of the back-contact solar cell and thereby increasing the yield of the solar cell. Attached Figure Description

[0050] Figure 1 is a schematic diagram of the structure of a first doped unit provided in an embodiment of this application;

[0051] Figure 2 is a schematic diagram of the structure of the first doped unit provided in another embodiment of this application;

[0052] Figure 3 is a schematic diagram of the structure of the second doped unit provided in an embodiment of this application;

[0053] Figure 4 is a schematic diagram of the structure of the second doped unit provided in another embodiment of this application;

[0054] Figure 5 is a schematic diagram of the structure of a back-contact solar cell provided in an embodiment of this application;

[0055] Figure 6 is a schematic diagram of the structure of a back-contact solar cell provided in another embodiment of this application.

[0056] Explanation of reference numerals in the attached figures: 1. First doped unit; 2. Second doped unit; 100. Silicon substrate; 110. First doped conductive layer; 120. Second doped conductive layer; 130. First isolation region; 140. Third doped conductive layer; 150. Fourth doped conductive layer; 160. Second isolation region; 210. First gate line; 220. Second gate line; 230. Third gate line; 240. Fourth gate line; 310. First tunneling layer; 320. Second tunneling layer; 330. Third tunneling layer; 340. Fourth tunneling layer. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, a further detailed description of this application will be provided below in conjunction with the accompanying drawings. It is hereby declared that the terms "up," "down," "left," "right," "front," "back," "inner," and "outer," etc., appearing or about to appear in this application, are based solely on the accompanying drawings and are not intended to specifically limit this application.

[0058] As shown in Figure 1, this embodiment of the application provides a back-contact solar cell, including a plurality of first doped units 1. Each first doped unit 1 includes a first doped conductive layer 110, a second doped conductive layer 120, and a first isolation region 130 disposed on the back side of a silicon substrate 100. The first doped conductive layer 110 and the second doped conductive layer 120 are alternately disposed, and the doping types of the first doped conductive layer 110 and the second doped conductive layer 120 are opposite. The first isolation region 130 is disposed between the first doped conductive layer 110 and the second doped conductive layer 120, and the surface of the first isolation region 130 is recessed into the silicon substrate 100 relative to the surface of the first doped conductive layer 110; the surface of the first doped conductive layer 110 is also recessed into the silicon substrate 100 relative to the surface of the second doped conductive layer 120.

[0059] A first gate line 210 is provided on the first doped conductive layer 110, and a second gate line 220 is provided on the second doped conductive layer 120. The height of the first gate line 210 is less than the height of the adjacent second gate line 220.

[0060] The back-contact solar cell provided in this application embodiment, compared to existing back-contact solar cells, features multiple first doped units. In each first doped unit, the height of the first grid line is less than the height of the second grid line. Furthermore, the surface of the first doped conductive layer is recessed into the silicon substrate relative to the surface of the second doped conductive layer, and the surface of the first isolation region is also recessed into the silicon substrate relative to the surface of the first doped conductive layer. This height difference between the surfaces of the first and second grid lines reduces the obstruction of incident light by the grid lines, especially the first grid line. Light can enter the cell through the sidewall of the first isolation region near the second doped conductive layer, allowing more light to be utilized by the silicon substrate and improving the light extraction efficiency of the back side of the back-contact solar cell, thereby increasing the bifaciality of the back-contact solar cell. In addition, the height of the second grid line is greater than the height of the first grid line, resulting in greater tensile strength at the second grid line. This creates an alternating structure of varying tensile strength on the back side of the back-contact solar cell, effectively dispersing stress when the back-contact solar cell is subjected to external pressure, thus improving the yield of the back-contact solar cell.

[0061] It is understood that the first doped conductive layer 110 and the second doped conductive layer 120 are disposed on the silicon substrate 100, and the doping types of the first doped conductive layer 110 and the silicon substrate 100 are the same or opposite. In some embodiments, the silicon substrate 100 is an N-type silicon substrate, the first doped conductive layer 110 is an N-type doped conductive layer, and the second doped conductive layer 120 is a P-type doped conductive layer; or, the silicon substrate 100 is a P-type silicon substrate, the first doped conductive layer 110 is a P-type doped conductive layer, and the second doped conductive layer 120 is an N-type doped conductive layer. No specific limitation is made here. In some embodiments, the doping type of the first doped conductive layer 110 is the same as the doping type of the silicon substrate 100. Based on this, the efficiency of fabricating back-contact solar cells can be improved, and leakage caused by residues on the surfaces of the first doped conductive layer 110, or the second doped conductive layer 120, or the first doped conductive layer 110 and the second doped conductive layer 120, can be avoided.

[0062] In some embodiments, the depth H1 of the surface of the first doped conductive layer 110 away from the silicon substrate 100 recessed into the silicon substrate 100 relative to the surface of the second doped conductive layer 120 away from the silicon substrate 100 is 1.5 μm to 3.5 μm, exemplarily 1.75 μm, 2 μm, 2.25 μm, 2.5 μm, 2.75 μm or 3 μm, but not limited thereto. If the depth of the recess of the surface of the first doped conductive layer 110 away from the silicon substrate 100 relative to the surface of the second doped conductive layer 120 away from the silicon substrate 100 is too small, the degree of misalignment between the first doped conductive layer 110 and the second doped conductive layer 120 in the thickness direction is small, resulting in a high risk of leakage and less light incident from the sidewall of the first isolation region 130. If the depth of the recess of the surface of the first doped conductive layer 110 away from the silicon substrate 100 relative to the surface of the second doped conductive layer 120 away from the silicon substrate 100 is too large, the movement distance of charge carriers around the first isolation region 130 is large, resulting in an increase in the carrier recombination rate in the first isolation region 130, which is not conducive to improving battery performance.

[0063] In some embodiments, to further increase the light incident amount, the surface of the first gate line 210 is flush with the surface of the second doped conductive layer 120. In this embodiment, the flushness of the surface of the first gate line 210 with the surface of the second doped conductive layer 120 can be understood as the height H2 of the first gate line 210 being equal to the depth H1 of the surface of the first doped conductive layer 110 recessed into the silicon substrate 100 relative to the surface of the second doped conductive layer 120, or the difference between H2 and H1 being less than or equal to 50 nm.

[0064] In some embodiments, the difference Δh1 (i.e., h1 = H3 - H2) between the height H2 of the first gate line 210 and the height H3 of the second gate line 220 ranges from 0.01 μm to 5 μm, exemplarily 0.1 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, or 4 μm, but is not limited thereto. In some embodiments, the value of Δh1 ranges from 0.8 μm to 1.2 μm. If Δh1 is too small, it is not conducive to effectively dispersing external forces, and the gate line increases the obstruction of light incident from the sidewall of the isolation area; if Δh1 is too large, it wastes the gate line printing paste and is not conducive to the connection of subsequent electrodes.

[0065] It is understood that the surface of the first isolation region 130 is recessed into the silicon substrate 100 relative to the surfaces of the first doped conductive layer 110 and the second doped conductive layer 120 away from the silicon substrate 100, in order to form a better isolation effect between the first doped conductive layer 110 and the second doped conductive layer 120. In some embodiments, the depth H4 of the recess of the surface of the first isolation region 130 relative to the surface of the first doped conductive layer 110 away from the silicon substrate 100 into the silicon substrate 100 is 2μm to 5μm, exemplary values ​​are 2.5μm, 2.8μm, 3μm, 3.5μm, 4μm or 4.5μm, but not limited thereto. If H4 is too small, it will increase the risk of leakage; if H4 is too large, it will increase the risk of microcracks in the solar cell.

[0066] As shown in Figure 2, in some embodiments, the thickness H5 of the first doped conductive layer 110 is less than the thickness H6 of the second doped conductive layer 120, which can further increase the degree of misalignment between the first doped conductive layer 110 and the second doped conductive layer 120 in the thickness direction, thereby increasing the light incident rate. For example, the thickness of the first doped conductive layer 110 is 150nm, 180nm, 200nm, 220nm, 240nm, or 260nm, but is not limited thereto; the thickness of the second doped conductive layer 120 is 180nm, 200nm, 240nm, 280nm, 300nm, or 340nm, but is not limited thereto. In some embodiments, the width S1 of the first doped conductive layer 110 is less than the width S2 of the second doped conductive layer 120, which can effectively increase the emitter area and avoid the reduction in battery efficiency caused by low current collection efficiency. For example, the width of the first doped conductive layer 110 is 100 μm, 150 μm, 250 μm, 300 μm, 350 μm or 400 μm, but is not limited thereto, and the width of the second doped conductive layer 120 is 100 μm, 150 μm, 200 μm, 300 μm, 400 μm or 500 μm, but is not limited thereto.

[0067] In some embodiments, as shown in FIG3, in addition to a plurality of first doped units 1, the back contact solar cell of this application embodiment also includes a plurality of second doped units 2. Each second doped unit 2 includes a third doped conductive layer 140, a fourth doped conductive layer 150 and a second isolation region 160 disposed on the back side of the silicon substrate 100. The doping types of the third doped conductive layer 140 and the fourth doped conductive layer 150 are opposite. The second isolation region 160 is disposed between the third doped conductive layer 140 and the fourth doped conductive layer 150.

[0068] A third gate line 230 is provided on the third doped conductive layer 140, and a fourth gate line 240 is provided on the fourth doped conductive layer 150. The height of the third gate line 230 is less than or equal to the height of the adjacent fourth gate line 240.

[0069] It is understood that the arrangement of the first doping unit 1 and the second doping unit 2 can be selected according to the actual situation. In one embodiment, as shown in Figure 5, multiple first doping units 1 are continuously disposed in the middle of the back contact solar cell, and multiple second doping units 2 are respectively continuously disposed on both sides of the back contact solar cell. In another embodiment, as shown in Figure 6, the first doping unit 1 and the second doping unit 2 are alternately disposed on the back contact solar cell. In yet another embodiment, multiple first doping units 1 are continuously disposed in the middle of the back contact solar cell, and the first doping unit 1 and the second doping unit 2 are alternately disposed on both sides of the back contact solar cell.

[0070] In some embodiments, the area of ​​the first doped unit 1 accounts for 60% to 99% of the area of ​​the back contact solar cell, and the area of ​​the second doped unit 2 accounts for 1% to 40% of the area of ​​the back contact solar cell. In some embodiments, the area of ​​the first doped unit 1 accounts for 80% to 99% of the area of ​​the back contact solar cell, and the area of ​​the second doped unit 2 accounts for 1% to 20% of the area of ​​the back contact solar cell. By limiting the areas of the first doped unit 1 and the second doped unit 2, the bifaciality and yield of the back contact solar cell are further improved.

[0071] It is understandable that the second doped unit 2 can use an existing structure, that is, the height of the third gate line 230 is equal to the height of the adjacent fourth gate line 240.

[0072] In some embodiments, the height of the third gate line 230 is less than the height of the adjacent fourth gate line 240, and the difference between the height H8 of the third gate line 230 and the height H9 of the fourth gate line 240 is Δh2 (i.e.,

[0073] △h2 = H9 - H8), △h2 < △h1. The value of △h2 ranges from 0.01 μm to 3 μm, with exemplary values ​​of 0.05 μm, 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, or 2 μm, but is not limited thereto. In some embodiments, △h2 is 0.05 μm to 0.5 μm.

[0074] It is understood that the depth H7 of the recess of the surface of the third doped conductive layer 140 away from the silicon substrate 100 relative to the surface of the fourth doped conductive layer 150 away from the silicon substrate 100 can be the same as or different from H1. In some embodiments, the surface of the third gate line 230 away from the silicon substrate 100 is flush with the surface of the fourth doped conductive layer 150 away from the silicon substrate 100. The depth H10 of the recess of the surface of the second isolation region 160 relative to the surface of the third doped conductive layer 140 away from the silicon substrate 100 can be the same as or different from H4. In some embodiments, as shown in FIG4, the thickness H11 of the third doped conductive layer 140 is less than the thickness H12 of the fourth doped conductive layer 150, and the width S3 of the third doped conductive layer 140 is less than the width S4 of the fourth doped conductive layer 150. To improve fabrication efficiency, the structures of the third doped conductive layer 140, the fourth doped conductive layer 150, and the second isolation region 160 can be the same as those of the first doped conductive layer 110, the second doped conductive layer 120, and the first isolation region 130, with the difference being the height difference Δh2 between the third gate line 230 and the fourth gate line 240.

[0075] In one scenario, a passivation layer is also provided on the side of the doped conductive layer away from the silicon substrate. For example, the passivation layer may include an aluminum oxide layer and a silicon nitride layer. The gate line passes through the passivation layer in part or all of the region and contacts the corresponding doped conductive layer. As a measurement method, a cross-section can be made along the direction perpendicular to the extension direction of the gate line, and the gate line height can be measured from the side of the corresponding doped conductive layer away from the silicon substrate using SEM or TEM, or by using a 3D microscope.

[0076] In some implementations, some metal particles may have entered the doped conductive layer of the gate line. As a measurement method, the height of the gate line can also be measured starting from the metal particles.

[0077] The heights of the first, second, third, and fourth grid lines are measured in the same way.

[0078] In some embodiments, the surface of the first doped conductive layer 110 is textured, and the surface of the second doped conductive layer 120 is textured; or, the surface of the first doped conductive layer 110 is polished, and the surface of the second doped conductive layer 120 is textured; or, the surface of the first doped conductive layer 110 is textured, and the surface of the second doped conductive layer 120 is polished; or, the surface of the first doped conductive layer 110 is polished, and the surface of the second doped conductive layer 120 is polished. In some embodiments, the textured surfaces of the first doped conductive layer 110 and the second doped conductive layer 120 allow some light transmitted to the back of the back contact solar cell to be reflected or refracted back into the silicon substrate, increasing the light absorption efficiency of the silicon substrate and improving the photoelectric conversion efficiency of the back contact solar cell.

[0079] Similarly, the surface of the third doped conductive layer 140 is textured, and the surface of the fourth doped conductive layer 150 is textured; or, the surface of the third doped conductive layer 140 is polished, and the surface of the fourth doped conductive layer 150 is textured; or, the surface of the third doped conductive layer 140 is textured, and the surface of the fourth doped conductive layer 150 is polished; or, the surface of the third doped conductive layer 140 is polished, and the surface of the fourth doped conductive layer 150 is polished. The specific effects are the same as those of the first doped conductive layer 110 and the second doped conductive layer 120, and will not be elaborated further here.

[0080] In addition to the first doped conductive layer 110 and the second doped conductive layer 120, the sidewalls of the first isolation region 130 near the first doped conductive layer 110 and the sidewalls of the first isolation region 130 near the second doped conductive layer 120 can be textured or polished. In some embodiments, the sidewalls of the first isolation region 130 near the first doped conductive layer 110 and the sidewalls of the first isolation region 130 near the second doped conductive layer 120 are textured. The light-trapping effect of the textured surface increases the incident light, thereby improving the photoelectric conversion efficiency of the back-contact solar cell. Similarly, the surfaces of the second isolation region 160 near the third doped conductive layer 140 and the sidewalls of the second isolation region 160 near the fourth doped conductive layer 150 can also be textured or polished. The specific effects are the same as those of the first doped conductive layer 110 and the second doped conductive layer 120, and will not be elaborated further here.

[0081] In addition to the above structure, the first doped unit 1 of the back-contact solar cell also includes a first tunneling layer 310 disposed between the first doped conductive layer 110 and the silicon substrate 100. In some embodiments, the first tunneling layer 310 is one or more of a silicon oxide layer, a silicon carbide layer, a silicon nitride layer, and an aluminum oxide layer. Correspondingly, the back-contact solar cell also includes a second tunneling layer 320 disposed between the second doped conductive layer 120 and the silicon substrate 100. In some embodiments, the second tunneling layer 320 is one or more of a silicon oxide layer, a silicon carbide layer, a silicon nitride layer, and an aluminum oxide layer. The first tunneling layer 310 allows majority carriers to tunnel into the first doped conductive layer 110 while blocking minority carriers from passing through, and the second tunneling layer 320 allows majority carriers to tunnel into the second doped conductive layer 120 while blocking minority carriers from passing through, thereby achieving selective collection of carriers and further improving the photoelectric conversion efficiency of the back-contact solar cell. Correspondingly, the second doping unit 2 also includes a third tunneling layer 330 disposed between the third doped conductive layer 140 and the silicon substrate 100 and a fourth tunneling layer 340 disposed between the fourth doped conductive layer 150 and the silicon substrate 100. The third tunneling layer 330 and the fourth tunneling layer 340 can be one or more of silicon oxide, silicon carbide, silicon nitride and aluminum oxide.

[0082] In some embodiments, a front antireflection layer may be disposed on the front side of the silicon substrate 100. In some embodiments, the surface of the front antireflection layer is textured, which can achieve a good light trapping effect and improve the conversion efficiency of the back contact solar cell. In addition, the back contact solar cell may also include a back passivation layer located on the surfaces of the first doped conductive layer 110, the second doped conductive layer 120, the third doped conductive layer 140, and the fourth doped conductive layer 150 to further improve the conversion efficiency of the back contact solar cell.

[0083] Accordingly, this application also provides a back-contact solar cell string, including the aforementioned back-contact solar cells. Each back-contact solar cell string includes multiple back-contact solar cells connected in series, and these multiple back-contact solar cells can be partially overlapped to form a back-contact solar cell string. In some embodiments, the back-contact solar cells can be a single back-contact solar cell or segmented back-contact solar cells (such as half-segmented back-contact solar cells or one-third-segmented back-contact solar cells, etc.). The overlapping areas of adjacent back-contact solar cells in the back-contact solar cell string are provided with series solder strips to fix and connect adjacent back-contact solar cells in series. Different back-contact solar cell strings are obtained by connecting them in series, or in parallel, or in series and in parallel.

[0084] Accordingly, this application also provides a photovoltaic module, including the aforementioned back-contact battery string. The photovoltaic module may further include a metal frame, a backsheet, photovoltaic glass, and an encapsulating film. The photovoltaic glass can cover the front of the back-contact battery string, the encapsulating film can bond the photovoltaic glass and the back-contact battery string together, and the backsheet can be attached to the back of the back-contact battery string via the encapsulating film. The presence of the encapsulating film can seal and insulate the back-contact battery string to achieve waterproofing and moisture resistance. The entire assembly consisting of the backsheet, back-contact battery string, encapsulating film, and photovoltaic glass can be mounted on the metal frame. The metal frame serves as the main external support structure for the entire photovoltaic module, providing stable support and installation for the photovoltaic module.

[0085] Accordingly, this application also provides a photovoltaic system. The photovoltaic system composed of photovoltaic modules can be applied in photovoltaic power plants or in equipment or devices that generate electricity using solar energy. It is understood that the application scenarios of the photovoltaic system are not limited to these.

[0086] The beneficial effects of the back-contact battery string, photovoltaic module, and photovoltaic system provided in the embodiments of this application can be found in the analysis of the beneficial effects of the back-contact solar cell and its various implementation methods provided in the embodiments of this application, which will not be elaborated here.

[0087] The present application will be further described below with reference to specific embodiments:

[0088] Example 1

[0089] This embodiment provides a back-contact solar cell, including a plurality of first doped units. Each first doped unit includes a first doped conductive layer, a second doped conductive layer and a first isolation region disposed on the back side of a silicon substrate. The first doped conductive layer is an N-type doped conductive layer, the second doped conductive layer is a P-type doped conductive layer, and the first isolation region is disposed between the first doped conductive layer and the second doped conductive layer.

[0090] The surface of the first isolation region is recessed into the silicon substrate relative to the surface of the first doped conductive layer that is away from the silicon substrate, with a recess depth of 4 μm. The surface of the first doped conductive layer that is away from the silicon substrate is also recessed into the silicon substrate relative to the surface of the second doped conductive layer that is away from the silicon substrate, with a recess depth of 3 μm.

[0091] A first gate line is provided on a first doped conductive layer, and a second gate line is provided on a second doped conductive layer. The height of the first gate line is 3.338 μm, and the height of the second gate line is 5.338 μm.

[0092] The back-contact solar cell provided in this embodiment also includes a plurality of second doped units. Each second doped unit includes a third doped conductive layer, a fourth doped conductive layer and a second isolation region disposed on the back side of the silicon substrate. The third doped conductive layer is an N-type doped conductive layer, the fourth doped conductive layer is a P-type doped conductive layer and the second isolation region is disposed between the third doped conductive layer and the fourth doped conductive layer.

[0093] The surface of the second isolation region is recessed into the silicon substrate relative to the surface of the third doped conductive layer away from the silicon substrate, with a recess depth of 4 μm. The surface of the third doped conductive layer away from the silicon substrate is also recessed into the silicon substrate relative to the surface of the fourth doped conductive layer away from the silicon substrate, with a recess depth of 2 μm.

[0094] A third gate line is provided on the third doped conductive layer, and a fourth gate line is provided on the fourth doped conductive layer. The height of the third gate line is 3.338 μm, and the height of the fourth gate line is 3.338 μm.

[0095] The area of ​​the first doped unit accounts for 60% of the area of ​​the back contact solar cell, and the area of ​​the second doped unit accounts for 40% of the area of ​​the back contact solar cell. The first doped unit is located in the middle of the back contact solar cell, and the second doped unit is located on both sides of the back contact solar cell.

[0096] Example 2

[0097] This embodiment provides a back-contact solar cell, which differs from Embodiment 1 in that the height of the second grid line is 4.523 μm. All other aspects are the same as in Embodiment 1.

[0098] Example 3

[0099] This embodiment provides a back-contact solar cell, which differs from Embodiment 2 in that the surface of the first doped conductive layer is recessed into the silicon substrate to a depth of 3.338 μm relative to the surface of the second doped conductive layer. All other aspects are the same as in Embodiment 2.

[0100] Example 4

[0101] This embodiment provides a back-contact solar cell, which differs from Embodiment 3 in that the height of the fourth grid line is 4.247 μm. All other aspects are the same as in Embodiment 3.

[0102] Example 5

[0103] This embodiment provides a back-contact solar cell, which differs from Embodiment 4 in that the area of ​​the first doped unit accounts for 90% of the area of ​​the back-contact solar cell, and the area of ​​the second doped unit accounts for 10% of the area of ​​the back-contact solar cell. The first doped unit is located in the middle of the back-contact solar cell, and the second doped unit is located on both sides of the back-contact solar cell. All other aspects are the same as in Embodiment 4.

[0104] Example 6

[0105] This embodiment provides a back-contact solar cell, which differs from Embodiment 5 in that the area of ​​the first doped unit accounts for 90% of the area of ​​the back-contact solar cell, the area of ​​the second doped unit accounts for 10% of the area of ​​the back-contact solar cell, the first doped unit, which accounts for 80% of the area of ​​the back-contact solar cell, is located in the middle of the back-contact solar cell, and the first doped unit and the second doped unit, which account for 10% of the area of ​​the back-contact solar cell, are alternately located on both sides of the back-contact solar cell. All other aspects are the same as in Embodiment 5.

[0106] Comparative Example 1

[0107] This comparative example provides a back-contact solar cell, including a first doped conductive layer, a second doped conductive layer, and a first isolation region disposed on the back side of a silicon substrate. The first doped conductive layer is an N-type doped conductive layer, the second doped conductive layer is a P-type doped conductive layer, and the first isolation region is disposed between the first doped conductive layer and the second doped conductive layer.

[0108] The surface of the first isolation region is recessed into the silicon substrate relative to the surface of the first doped conductive layer that is away from the silicon substrate, with a recess depth of 4 μm. The surface of the first doped conductive layer that is away from the silicon substrate is also recessed into the silicon substrate relative to the surface of the second doped conductive layer that is away from the silicon substrate, with a recess depth of 3 μm.

[0109] A first gate line is provided on a first doped conductive layer, and a second gate line is provided on a second doped conductive layer. The height of the first gate line is 3.338 μm, and the height of the second gate line is 3.338 μm.

[0110] Performance tests were conducted on the back-contact solar cells provided in Examples 1 to 6 and Comparative Example 1. The bifaciality and yield were tested respectively. The improvement in bifaciality and yield of Examples 1 to 6 compared with Comparative Example 1 were calculated. The results are shown in the table below.

[0111] The above are preferred embodiments of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A back-contact solar cell, comprising a plurality of first doped units, each first doped unit comprising a first doped conductive layer, a second doped conductive layer and a first isolation region disposed on the back side of a silicon substrate, wherein the doping types of the first doped conductive layer and the second doped conductive layer are opposite, and the first isolation region is disposed between the first doped conductive layer and the second doped conductive layer. The surface of the first isolation region is recessed into the silicon substrate relative to the surface of the first doped conductive layer; the surface of the first doped conductive layer is recessed into the silicon substrate relative to the surface of the second doped conductive layer. The first doped conductive layer has a first gate line, and the second doped conductive layer has a second gate line. The height of the first gate line is less than the height of the adjacent second gate line.

2. The back-contact solar cell as described in claim 1, wherein, The depth to which the surface of the first doped conductive layer away from the silicon substrate is recessed into the silicon substrate relative to the surface of the second doped conductive layer away from the silicon substrate is 1.5 μm to 3.5 μm.

3. The back-contact solar cell as described in claim 1, wherein, The surface of the first gate line away from the silicon substrate is flush with the surface of the second doped conductive layer away from the silicon substrate.

4. The back-contact solar cell as described in claim 1, wherein, The difference between the height of the first gate line and the height of the second gate line is Δh1, and the value of Δh1 ranges from 0.01μm to 5μm.

5. The back-contact solar cell as described in claim 4, wherein, The value of △h1 ranges from 0.8μm to 2μm.

6. The back-contact solar cell as claimed in claim 1, wherein, The surface of the first isolation region is recessed into the silicon substrate to a depth of 2 μm to 5 μm relative to the surface of the first doped conductive layer that is away from the silicon substrate.

7. The back-contact solar cell as claimed in claim 1, wherein, The thickness of the first doped conductive layer is smaller than the thickness of the second doped conductive layer; The thickness of the first doped conductive layer is 120nm to 300nm, and the thickness of the second doped conductive layer is 150nm to 400nm.

8. The back-contact solar cell as claimed in claim 1, wherein, The width of the first doped conductive layer is smaller than the width of the second doped conductive layer; The width of the first doped conductive layer is 50 μm to 500 μm, and the width of the second doped conductive layer is 60 μm to 600 μm.

9. The back-contact solar cell as claimed in claim 1, wherein, The surface of the first doped conductive layer is textured, and the surface of the second doped conductive layer is textured; or, The surface of the first doped conductive layer is polished, and the surface of the second doped conductive layer is textured. or, The surface of the first doped conductive layer is textured, and the surface of the second doped conductive layer is polished; or, The surface of the first doped conductive layer is polished, and the surface of the second doped conductive layer is also polished.

10. The back-contact solar cell as claimed in claim 1, wherein, The first doped conductive layer is an N-type doped conductive layer, and the second doped conductive layer is a P-type doped conductive layer.

11. The back-contact solar cell as claimed in claim 4, wherein, It also includes multiple second doping units, each second doping unit including a third doped conductive layer, a fourth doped conductive layer and a second isolation region disposed on the back side of the silicon substrate, wherein the doping types of the third doped conductive layer and the fourth doped conductive layer are opposite, and the second isolation region is disposed between the third doped conductive layer and the fourth doped conductive layer; The third doped conductive layer has a third gate line, and the fourth doped conductive layer has a fourth gate line. The height of the third gate line is less than or equal to the height of the adjacent fourth gate line.

12. The back-contact solar cell of claim 11, wherein, The surface of the third doped conductive layer away from the silicon substrate is recessed into the silicon substrate to a depth of 1.5 μm to 3.5 μm relative to the surface of the fourth doped conductive layer away from the silicon substrate.

13. The back-contact solar cell of claim 11, wherein, The surface of the third gate line away from the silicon substrate is flush with the surface of the fourth doped conductive layer away from the silicon substrate.

14. The back-contact solar cell of claim 11, wherein, The difference between the height of the third gate line and the height of the fourth gate line is △h2, where △h2 < △h1.

15. The back-contact solar cell as claimed in claim 14, wherein, The value of Δh2 ranges from 0.01μm to 3μm.

16. The back-contact solar cell of claim 11, wherein, The surface of the second isolation region is recessed into the silicon substrate to a depth of 2 μm to 5 μm relative to the surface of the third doped conductive layer that is away from the silicon substrate.

17. The back-contact solar cell of claim 11, wherein, The thickness of the third doped conductive layer is less than the thickness of the fourth doped conductive layer; The thickness of the third doped conductive layer is 120nm to 300nm, and the thickness of the fourth doped conductive layer is 150nm to 400nm.

18. The back-contact solar cell of claim 11, wherein, The width of the third doped conductive layer is smaller than the width of the fourth doped conductive layer; The width of the third doped conductive layer is 50 μm to 500 μm, and the width of the fourth doped conductive layer is 60 μm to 600 μm.

19. The back-contact solar cell of claim 11, wherein, The surface of the third doped conductive layer is textured, and the surface of the fourth doped conductive layer is textured; or, The surface of the third doped conductive layer is polished, and the surface of the fourth doped conductive layer is textured; or, The surface of the third doped conductive layer is textured, and the surface of the fourth doped conductive layer is polished; or, The surface of the third doped conductive layer is polished, and the surface of the fourth doped conductive layer is also polished.

20. The back-contact solar cell of claim 11, wherein, The third doped conductive layer is an N-type doped conductive layer, and the fourth doped conductive layer is a P-type doped conductive layer.

21. The back-contact solar cell of claim 11, wherein, The area of ​​the first doped unit accounts for 60% to 99% of the area of ​​the back contact solar cell, and the area of ​​the second doped unit accounts for 1% to 40% of the area of ​​the back contact solar cell.

22. The back-contact solar cell of claim 21, wherein, The area of ​​the first doped unit accounts for 80% to 99% of the area of ​​the back contact solar cell, and the area of ​​the second doped unit accounts for 1% to 20% of the area of ​​the back contact solar cell.

23. The back-contact solar cell of claim 11, wherein, The first doped unit is located in the middle of the back contact solar cell, and the second doped unit is located on both sides of the back contact solar cell.

24. The back-contact solar cell of claim 11, wherein, The first doped unit and the second doped unit are alternately disposed on the back contact solar cell.

25. A back-contact battery string, comprising a back-contact solar cell as described in any one of claims 1 to 24.

26. A photovoltaic module comprising a back-contact cell string as described in claim 25.

27. A photovoltaic system comprising the photovoltaic module as described in claim 26.

Images