Wiring board

Abstract

The purpose of the present invention is to provide a wiring board (1) that makes it possible to dispose more wiring in the same layer. Provided is a wiring board (1) in which a plurality of bump lands (20) and a plurality of surface layer via lands (30) are provided to a surface layer (10), and which has a bump land part (18) in the surface layer (10). Formed in the bump land part (18) are a plurality of bump land rows (100) in which at least some of the plurality of bump lands (20) are disposed in a row, and at least one via land row (120) in which at least some of the plurality of surface layer via lands (30) are disposed in a row. The bump land rows (100) and the via land row (120) are parallel with each other. One via land row (120) is with respect to a plurality of bump land rows (100).

Description

Wiring board

[0001] The present invention relates to a wiring board.

[0002] The arrangement of bumps in a chiplet may be defined by a standard. As a standard for defining the arrangement of bumps, for example, there is the UCIe (Universal Chiplet Interconnect Express) standard.

[0003] For example, when based on the UCIe standard, the layout is required to be accommodated within a predetermined module width. On the other hand, for the layout, in order to pass high data rate signals such as 32 Gbps, it is required to widen the wiring width and reduce the wiring resistance. That is, conflicting matters are required for the layout. As a document disclosing such a technology related to the layout, there is Non-Patent Document 1 below.

[0004] Signal Integrity Designs at Organic Interposer CoWoS-R for HBM3-9.2Gbps High Speed Interconnection of 2.5D-IC Chiplets Integration (2024 IEEE 74th Electronic Components and Technology Conference (ECTC))

[0005] By the way, depending on the standard, the bumps are arranged in a staggered pattern. When the pad and the via have a pad-on-via configuration, the space between the columns arranged in a staggered pattern depends on the arrangement of the bumps. That is, the number of signal wirings that can be arranged between the columns depends on the arrangement of the bumps at the positions where the vias are formed. In Non-Patent Document 1, the position of the vias is not considered.

[0006] Further, when using a wiring board composed of an organic substrate as a rewiring layer, usually, the via land diameter is larger than the wiring width. Therefore, the via land diameter reduces the wiring area and becomes a factor in increasing the number of wiring layers.

[0007] Therefore, an object of the present invention is to provide a wiring board capable of arranging more wirings in the same layer.

[0008] The wiring board of the present invention is a wiring board having a plurality of bump lands and a plurality of surface beer lands on its surface, wherein the surface has a bump land portion, and the bump land portion has a plurality of bump land rows formed by at least a portion of the plurality of bump lands being arranged side by side, and at least one beer land row formed by at least a portion of the plurality of surface beer lands being arranged side by side, the bump land rows and the beer land rows are parallel, and one beer land row is arranged for each of the plurality of bump land rows.

[0009] According to the present invention, it is possible to provide a wiring board that can arrange more wiring on the same layer.

[0010] Figure 1A shows the surface layer of a wiring board according to an embodiment of the present invention. Figure 1B shows an example of a bump map. Figure 2 shows the surface layer of a wiring board according to another embodiment of the present invention. Figure 3 shows an example of ground shield wiring arrangement. Figure 4 shows the surface layer of a conventional wiring board. Figure 5 is a cross-sectional view of a wiring board, etc. Figure 6 is a cross-sectional view of a wiring board, etc., with a different configuration of the present invention. Figure 7 is a schematic diagram showing the relationship between the surface layer and bump map of a wiring board according to another embodiment of the present invention. Figure 8 shows details of the surface layer of a wiring board according to another embodiment of the present invention. Figure 9 shows an example of ground shield wiring arrangement according to another embodiment of the present invention.

[0011] (First Embodiment) Embodiments for carrying out the invention will be described with reference to the drawings. First, the wiring board 1 of the first embodiment will be described with reference to Figure 1A. One main surface of the wiring board 1 is defined as the surface layer 10. Figure 1A is a view of the surface layer 10 of the wiring board 1 from a direction perpendicular to the surface layer 10. As shown in Figure 1A, a plurality of bump lands 20 and a plurality of surface via lands 30 are arranged on the surface layer 10. Bump lands are also called UBM (Under Bump Metallization). UBM means, for example, terminal metal or bump receiving pad.

[0012] (Cross-sectional structure of the wiring board) An example of the use of the wiring board 1 will be explained with reference to Figure 5. Figure 5 is a cross-sectional view of the wiring board 1 and the like to explain an example of the use of the wiring board 1. Two or more chiplets 200 can be mounted on the wiring board 1. A chiplet is also called a die. Figure 5 shows the state in which a first chiplet 201 and a second chiplet 202 are mounted on the wiring board 1. The first chiplet 201 and the second chiplet 202 are electrically connected via the wiring board 1.

[0013] (Direction Definition) The direction in which the wiring board 1 and the chiplet 200 are stacked is defined as the stacking direction 1010. The direction from the wiring board 1 toward the chiplet 200 is defined as the upward direction 1011. The direction from the chiplet 200 toward the wiring board 1 is defined as the downward direction 1012. The upward direction 1011 and the downward direction 1012 are parallel to the stacking direction 1010. The upward direction 1011 and the downward direction 1012 are opposite directions.

[0014] The direction in which the first chiplet 201 and the second chiplet 202 face each other is defined as the column direction 1020. Also, as shown in Figure 1A, the direction perpendicular to the stacking direction 1010 and the column direction 1020 is defined as the row direction 1030.

[0015] In this application, "up" and "down" refer to the upward direction 1011 and the downward direction 1012. Furthermore, in this application, a top view means viewing the object from the position above 1011 of the object in the downward direction 1012.

[0016] As shown in Figure 5, the wiring board 1 has at least one signal layer 12 placed below the surface layer 10. An insulating layer 14 is placed between the surface layer 10 and the signal layer 12. Vias 50 connecting the surface layer 10 and the signal layer 12 are placed on the insulating layer 14. The shape of the vias 50 can be, for example, cylindrical or frustoconical.

[0017] The insulating layer 14 can be formed from, for example, an organic insulating material. Furthermore, the conductive portion included in the wiring board 1 can be formed from, for example, copper, gold, or the like.

[0018] A surface via land 30 is positioned on the surface layer 10 at the location corresponding to the via 50. The surface of the via 50 on the surface layer 10 is defined as the via surface 54. In a top view, the surface via land 30 overlaps with at least a portion of the via surface 54. The shape of the surface via land 30 in a top view can be, for example, circular.

[0019] Bump lands 20 are placed on the surface layer 10. Bump lands 20 are lands for connecting chiplets 200 to the wiring board 1. In the example shown in Figure 5, the bump lands 20 and the surface via lands 30 are placed at the same position on the surface layer 10. Figure 5 shows the arrangement of so-called pad-on-via. The bump lands 20 and the surface via lands 30 are stacked with the bump lands 20 on top.

[0020] The bumpland 20 and the surface beerland 30 do not need to be placed in the same position on the surface 10. The bumpland 20 and the surface beerland 30 can be placed in different positions on the surface 10. If the beer 50 is placed in a different position from the bumpland 20, then the bumpland 20 and the surface beerland 30 will be placed in different positions on the surface 10.

[0021] When the bumpland 20 and the surface beerland 30 are located at different positions on the surface 10, the bumpland 20 and the surface beerland 30 can be connected by surface wiring located on the surface 10. Surface wiring is not shown in Figure 5. Surface wiring will be explained later.

[0022] (Surface Land) Note that Bumpland 20 and Surface Beerland 30 can be collectively referred to as Surface Land.

[0023] Furthermore, in the case of the pad-on-beer arrangement shown in Figure 5, instead of providing the bump land 20 separately from the surface beer land 30, the surface beer land 30 may also function as the bump land 20. In other words, the bump land 20 may be absorbed into the surface beer land 30, and the bump land 20 and the surface beer land 30 may be integrated. When the bump land 20 and the surface beer land 30 are integrated, it can be called both the bump land 20 and the surface beer land 30. It can also be called the surface land.

[0024] A signal layer via land 40 is placed at the position corresponding to the via 50 in the signal layer 12. The surface of the via 50 in the signal layer 12 is defined as the via signal layer surface 56. In a top view, the signal layer via land 40 overlaps with at least a portion of the via signal layer surface 56. The shape of the signal layer via land 40 in a top view can be, for example, circular. However, the shape of the signal layer via land 40 in a top view is not limited to circular. If the shape of the signal layer via land 40 in a top view is not circular, the diameter of the signal layer via land 40 can be read as the diameter equivalent to a circle.

[0025] The diameter of the bump land 20 is smaller than the diameter of the surface via land 30. The diameter of the surface via land 30 is usually set to a value greater than or equal to the diameter of the via 50, and especially the diameter of the via surface 54. In particular, when the insulating layer 14 is formed of an organic insulating material, the diameter of the via 50 tends to be relatively large. Therefore, the diameter of the surface via land 30 tends to be large. As a result, the diameter of the bump land 20 tends to be smaller than the diameter of the surface via land 30. Note that for the bump land 20, surface via land 30, via 50, and via surface 54, if their shapes in a top view are not circular, their diameters can be read as equivalent to circular diameters.

[0026] Signal layer wiring 60 is arranged in signal layer 12. Signal layer wiring 60 electrically connects the first chiplet 201 and the second chiplet 202.

[0027] As shown in Figure 5, the chiplet 200 is connected to the signal layer via land 40 via bump land 20, surface via land 30, and via 50.

[0028] The first chiplet 201 is connected to a signal layer via land 40 via a via 50 located 1012 below it, and this is defined as the first chiplet via land 401. The second chiplet 202 is connected to a signal layer via land 40 via a via 50 located 1012 below it, and this is defined as the second chiplet via land 402. The signal layer wiring 60 is arranged to connect the first chiplet via land 401 and the second chiplet via land 402.

[0029] As described above, the wiring board 1 has the function of connecting multiple chiplets 200 mounted on the wiring board 1. In addition, the wiring board 1 has the function of a rewiring layer for the chiplets 200.

[0030] (Bump Land Section) The arrangement of bump land 20, surface via land 30, and surface wiring 62 on the surface layer 10 will be described with reference to Figures 1A and 1B. Figure 1B is a diagram showing an example of the arrangement of bumps 220 of a chiplet 200 mounted on a wiring board 1. Figure 1B is a so-called bump map.

[0031] Regarding the arrangement of bumps 220 on the chiplets 200 mounted on the wiring board 1, standards such as UCIe (Universal Chiplet Interconnect Express) have been proposed. Figure 1B shows the arrangement of bumps 220 according to UCIe. In the example shown in Figure 1B, the bumps 220 are arranged in a staggered pattern.

[0032] The framed area 2010 in Figure 1A corresponds to the framed area 2010 in Figure 1B. As shown in Figure 1A, bump lands 20 are placed on the surface layer 10 of the wiring board 1 at positions corresponding to the bump map shown in Figure 1B, for example.

[0033] Multiple chiplets 200 are mounted on the wiring board 1. Figure 1A shows bumplands 20 corresponding to two adjacent chiplets. The first chiplet edge 211 indicates the position of the chiplet edge when, for example, the first chiplet 201 shown in Figure 5 is mounted on the wiring board 1. The second chiplet edge 212 indicates the position of the chiplet edge when, for example, the second chiplet 202 shown in Figure 5 is mounted on the wiring board 1.

[0034] The first chiplet 201 and the second chiplet 202 are connected via signal layer wiring 60. More specifically, for example, the electrodes of the first chiplet 201 and the electrodes of the second chiplet 202 are connected to each other. Therefore, the bump land 20 corresponding to the first chiplet 201 and the bump land 20 corresponding to the second chiplet 202 are connected via signal layer wiring 60.

[0035] As shown in Figure 5, the signal layer wiring 60 is located on the signal layer 12. Therefore, in order to connect the first chiplet 201 and the second chiplet 202, it is necessary to connect the bump land 20 of the surface layer 10 to the signal layer wiring 60 of the signal layer 12. The connection between the surface layer 10 and the signal layer 12 is made via 50.

[0036] The wiring board 1 of this embodiment includes two types of arrangements for the bump land 20 and the vias 50 to which the bump land 20 is connected. One arrangement is in which the vias 50 are arranged below 1012 of the bump land 20. This arrangement is the so-called pad-on-via arrangement described with reference to Figure 5. The other arrangement is in which the vias 50 are arranged at a different position from the bump land 20.

[0037] (Bump Land Section) In the surface layer 10, the portion where at least some of the bump lands 20 are arranged in a row is defined as the bump land section 18. Figure 1A shows a portion of the bump land section 18 in the surface layer 10.

[0038] (Bump Land Column) As shown in Figure 1A, in the bump land section 18, a column formed by multiple bump lands 20 being arranged in the column direction 1020 is defined as a bump land column 100.

[0039] (First Bump Land Row and Second Bump Land Row) Of the bump land rows 100, the bump land row 100 formed by one of the bumps 220 (shown in Figure 1B) arranged in a staggered pattern is defined as the first bump land row 101. The bump land row 100 formed by the other of the bumps 220 arranged in a staggered pattern is defined as the second bump land row 102. The first bump land row 101 and the second bump land row 102 are adjacent in the row direction 1030.

[0040] Regarding the arrangement of the bump land 20 and the via 50 to which the bump land 20 is connected, the bump land 20 included in the first bump land row 101 is arranged such that the via 50 is located below the bump land 20. On the other hand, the bump land 20 included in the second bump land row 102 is arranged such that the via 50 is located at a different position from the bump land 20.

[0041] (Direct vias and relocated vias) A via 50 located 1012 below the connected bump land 20 is defined as a direct via 51. A via 50 located at a different position from the connected bump land 20 is defined as a relocated via 52.

[0042] (Directly beneath the beer land and relocated beer land) The surface beer land 30 corresponding to the directly beneath beer 51 is defined as the directly beneath beer land 31. The surface beer land 30 corresponding to the relocated beer 52 is defined as the relocated beer land 32.

[0043] (Direct via bump land and relocated via bump land) A bump land 20 in which the connected via 50 is positioned downwards 1012 is defined as a direct via bump land 21. A bump land 20 in which the connected via 50 is positioned at a different location is defined as a relocated via bump land 22.

[0044] The direct-under via bump land 21 and the direct-under via land 31 overlap at least partially in a top view. The relocated via bump land 22 and the relocated via land 32 do not overlap in a top view.

[0045] In the example shown in FIG. 1A, all of the bump lands 20 included in the first bump land row 101 are direct-under via bump lands 21. All of the bump lands 20 included in the second bump land row 102 are relocated via bump lands 22.

[0046] (Via land row) In the bump land portion 18, a row formed by arranging a plurality of surface via lands 30 in the column direction 1020 is defined as a via land row 120.

[0047] As shown in FIG. 1A, the bump land row 100 and the via land row 120 are parallel. Here, "parallel" does not mean parallel in a strict sense. "Parallel" means that the via land row 120 extends substantially in the same direction along the bump land row 100.

[0048] In the present embodiment, one via land row 120 is arranged for two bump land rows 100.

[0049] (Direct-under via land row and relocated via land row) A via land row 120 formed by the direct-under via lands 31 is defined as a direct-under via land row 121. A via land row 120 formed by the relocated via lands 32 is defined as a relocated via land row 122.

[0050] As shown in FIG. 1A, in the present embodiment, the direct-under via land row 121 and the relocated via land row 122 are located at the same position. That is, in the present embodiment, the direct-under via land row 121 and the relocated via land row 122 are located on the same line. Therefore, a via land row 120 formed by the direct-under via land row 121 and the relocated via land row 122 is defined as an integrated via land row 123.

[0051] The integrated via land row 123 is a corresponding via land row that is a via land row arranged corresponding to the first bump land row 101 and the second bump land row 102, which are two bump land rows 100 adjacent to each other in the solder direction 1030.

[0052] The sum of the number of bumplands 20 in the first bumpland column 101 and the number of bumplands 20 in the second bumpland column 102 corresponds to the number of surface beerlands 30 in the corresponding beerland column. Corresponding usually means that the numbers are approximately the same.

[0053] It should be noted that descriptions such as "on the same line" and "straight line" in this application do not mean identical or straight lines in a strict sense. For example, when viewed in the direction in which lines extend, if there are overlapping parts, they are said to be on the same line and form a straight line, that is, straight line.

[0054] Similarly, the statement in this application that items are aligned in a predetermined direction does not strictly mean that they are aligned in a straight line parallel to that direction. It means that they are aligned in a direction along the predetermined direction; for example, if there are overlapping parts when viewed in the direction in which the arrangement extends, they are said to be aligned in the predetermined direction.

[0055] In this embodiment, a single Beerland row 120, which is an integrated Beerland row 123, is arranged for two Bumpland rows 100, which are the first Bumpland row 101 and the second Bumpland row 102.

[0056] In this embodiment, the relocated via 52 is positioned on the row formed by the via 51 directly below it. In other words, the via 51 directly below it and the relocated via 52 are positioned on the same straight line. Therefore, the row of vias 121 directly below it and the row of relocated vias 122 are located on the same straight line.

[0057] (Surface Wiring) The connection between the relocated via bush land 22 and the relocated via 52 will now be explained. Wiring arranged on the surface layer 10 that connects the relocated via bush land 22 and the relocated via land 32 is defined as surface wiring 62. The relocated via bush land 22 is connected to the relocated via 52 via surface wiring 62 and the relocated via land 32.

[0058] In other words, the surface wiring 62 is wiring that connects the bump land 20 included in the bump land row 100, which does not overlap with the corresponding bump land row in a top view, among the first bump land row 101 and the second bump land row 102, to the surface bump land 30 included in the corresponding bump land row.

[0059] In this embodiment, all bump lands 20 included in the first bump land row 101 are direct via bump lands 21. On the other hand, all bump lands 20 included in the second bump land row 102 are relocated via bump lands 22. Therefore, surface wiring 62 is arranged to connect the bump lands 20 included in the second bump land row 102 to the relocated via lands 32 of the relocated via 52 to which the bump lands 20 are connected. In the example shown in Figure 1A, the surface wiring 62 is arranged along the low direction 1030 from the relocated via bump land 22 to the relocated via lands 32.

[0060] In this embodiment, a portion of the bump land 20 is connected to vias 50 located at a different position from itself.

[0061] (Number of wires) In this embodiment, the above configuration makes it possible to increase the number of wires that can be placed between vias 50 in the signal layer 12.

[0062] (Conventional Wiring Board) Here, with reference to Figure 4, a conventional wiring board 90 will be described. Figure 4 is a diagram showing the surface layer 10 of a conventional wiring board 90. The conventional wiring board 90 will be described focusing on the differences from the wiring board 1 of this embodiment. Matters of the conventional wiring board 90 that are not specifically described can be the same as those of the wiring board 1 of this embodiment.

[0063] As shown in Figure 4, in the conventional wiring board 90, the vias 50 connected to all bump lands 20 are located at the same position as the bump lands 20. In other words, all bump lands 20 have a pad-on-via configuration. Therefore, all bump lands 20 are direct-beam via bump lands 21.

[0064] (Number of Wires) The number of wires that can be placed between vias 50 in the signal layer 12 will be explained with reference to Figures 1A and 4. In Figures 1A and 4, Y represents the bump pitch. The bump pitch Y is the pitch of the repeating unit of bumps in the row direction 1030, when the first bump land row 101 and the second bump land row 102 are considered as a repeating unit (one unit).

[0065] In the conventional wiring board 90 shown in Figure 4, the pitch of adjacent vias 50 in the row direction 1030 is Y / 2. In the conventional wiring board 90, all bump lands 20 are direct via bump lands 21. Therefore, between the first row of bump lands 101 and the first row of bump lands 101, there are vias 50 connected to the bump lands 20 included in the second row of bump lands 102. As a result, the pitch of the vias 50 is Y / 2.

[0066] Let V be the diameter of the signal layer via land 40. The end position of the signal layer via land 40 in the row direction 1030 is defined as the via land end 131. In a conventional wiring board 90, the distance between vias 50 of the signal layer 12, or more specifically, the distance between signal layer via lands 40, is Y / 2 - V / 2 - V / 2 = Y / 2 - V. In a conventional wiring board 90, there are two Y / 2 - V units. Therefore, in a conventional wiring board 90, the total distance between signal layer via lands 40 in one unit is Y - 2V.

[0067] On the other hand, in the wiring board 1 of this embodiment, as shown in Figure 1A, the pitch of adjacent vias 50 in the row direction 1030 is Y. In the wiring board 1 of this embodiment, the bump land 20 included in the second bump land row 102 is a relocated via bump land 22. Also, the relocated via 52 to which the relocated via bump land 22 is connected is arranged on the same line as the via 51 directly below it. Therefore, there are no vias 50 connected to the bump land 20 included in the second bump land row 102 between the first bump land row 101 and the first bump land row 101. Therefore, the pitch of the vias 50 is Y.

[0068] In the wiring board 1 of this embodiment, the distance between signal layer via lands 40 is Y - V / 2 - V / 2 = Y - V.

[0069] Thus, in the wiring board 1 of this embodiment, the spacing between signal layer via lands 40 on which signal layer wiring 60 can be arranged in the signal layer 12 is wider by V than that of a conventional wiring board 90.

[0070] As a result, more wiring can be placed between adjacent vias 50 in the signal layer 12.

[0071] Typically, the diameter of the signal layer via lands 40 is greater than the line width of the signal layer wiring 60.

[0072] Let's describe an example of wiring arrangement. The bump pitch Y is set to 77.76 μm. The diameter of the signal layer via land 40 is set to 20 μm. Also, the line and space (L / S) of the signal layer wiring 60 is set to 2 μm / 2 μm. In this case, a conventional wiring board 90 can accommodate 10 signal layer wirings. In contrast, the wiring board 1 of this embodiment can accommodate 13 signal layer wirings.

[0073] In the wiring board 1 of Embodiment 1, at least one of the first bump land row 101 and the second bump land row 102 does not overlap with the integrated bump land row 123, which is the corresponding bump land row, when viewed from a direction perpendicular to the surface layer 10.

[0074] In the wiring board 1 of Embodiment 1, two chiplets can be connected by equal-length wiring. Furthermore, by making the bump lands 20 included in the first bump lands row 101 direct via bump lands 21 and the bump lands 20 included in the second bump lands row 102 relocated via bump lands 22, the number of surface wirings 62 to be arranged can be reduced compared to the case where all bump lands 20 are relocated via bump lands 22.

[0075] Figure 6 shows a cross-section of the wiring board 1 in another configuration of this embodiment. As shown in Figure 6, the surface wiring 62 is arranged on the surface layer 10 to connect the relocated via bump land 22 and the relocated via land 32. Also, in the example shown in Figure 5, the signal layer 12 is shown as being arranged as a single layer below the surface layer 10. As shown in Figure 6, the signal layer 12 may be arranged as multiple layers below the surface layer 10.

[0076] Furthermore, when describing this embodiment using the term "surface land" as described above, it can also be described as follows. That is, in this embodiment, a row formed by multiple surface lands (bump lands 20, surface via lands 30) aligning in the column direction 1020 on the surface layer 10 of the wiring board 1 can be defined as a surface land row. Also, a row formed by multiple vias 50 aligning in the column direction 1020 in the insulating layer 14 of the wiring board 1 can be defined as a via row. Also, a row formed by multiple signal layer via lands 40 aligning in the column direction 1020 on the signal layer 12 of the wiring board 1 can be defined as a signal layer via land row. The surface land rows and via rows are parallel, and one via row is provided for every two surface land rows. Also, the surface land rows and signal layer via land rows are parallel, and one signal layer via land row is provided for every two surface land rows. Typically, the diameter of the signal layer via lands 40 is larger than the line width of the signal layer wiring 60. The diameter of via 50 may be greater than the line width of the signal layer wiring 60.

[0077] (Embodiment 2) The wiring board 1 of Embodiment 2 will be described with reference to Figure 2. Figure 2 is a diagram showing the surface layer 10 of the wiring board 1 of Embodiment 2. The wiring board 1 of Embodiment 2 will be described focusing on the differences from the wiring board 1 of Embodiment 1. Matters of the wiring board 1 of Embodiment 2 that are not specifically described can be the same as those of the wiring board 1 of Embodiment 1.

[0078] As shown in Figure 2, in the wiring board 1 of Embodiment 2, all bump lands 20 are configured as relocated via bump lands 22. In the wiring board 1 of Embodiment 1, as shown in Figure 1A, the bump lands 20 included in the second bump land row 102 were configured as relocated via bump lands 22, while the bump lands 20 included in the first bump land row 101 were configured as direct via bump lands 21.

[0079] In contrast, in the wiring board 1 of Embodiment 2, the bump land 20 included in the first bump land row 101 is also configured as a relocated via bump land 22. In other words, all bump land 20 are configured as relocated via bump land 22.

[0080] Furthermore, for the bumplands 20 included in the first bumpland row 101 and the bumplands 20 included in the second bumpland row 102, the relocated vias 52 are arranged on a single straight line parallel to the column direction 1020. In other words, the vialand row 120 consists of only one relocated vialand row 122.

[0081] The Beerland row 120 is positioned in the row direction 1030 between the first bumpland row 101 and the second bumpland row 102. In particular, the Beerland row 120 is positioned in the center between the first bumpland row 101 and the second bumpland row 102 in the row direction 1030.

[0082] In the wiring board 1 of Embodiment 2, neither the first bump land row 101 nor the second bump land row 102 overlaps with the corresponding bump land row, the relocated bump land row 122, when viewed from a direction perpendicular to the surface layer 10.

[0083] (Number of wires) In Embodiment 2, as in Embodiment 1, the number of wires that can be placed between vias 50 in the signal layer 12 can be increased.

[0084] Furthermore, in the wiring board 1 of Embodiment 2, the two chiplets can be connected with a shorter wiring length than in the wiring board 1 of Embodiment 1. In Embodiment 2, as in Embodiment 1, the two chiplets are connected with equal-length wiring.

[0085] (Surface Wiring) In Embodiment 2, both the bump land 20 included in the first bump land row 101 and the bump land 20 included in the second bump land row 102 are connected to the bump land 20 via surface wiring 62. However, the arrangement of the surface wiring 62 in Embodiment 1 and the surface wiring 62 in Embodiment 2 are different. The surface wiring 62 in Embodiment 1 extended in the row direction 1030. In contrast, the surface wiring 62 in Embodiment 2 extends in a direction inclined with respect to the row direction 1030. This increases the degree of freedom in routing the wiring for connecting the two chiplets in Embodiment 2.

[0086] (Ground Shield Wiring) Note that the arrangement of signal layer wiring 60 and the like shown in Figure 3 is illustrative. For wiring to connect two chiplets, for example, ground shield wiring 66 may be provided. The ground shield wiring 66 is provided on the signal layer 12 in the same way as the signal layer wiring 60. Figure 3 is a diagram showing an example of arrangement when ground shield wiring 66 is provided. As shown in Figure 3, the ground shield wiring 66 is formed so that, for example, the entire structure has the same potential. Even when ground shield wiring 66 is provided, the wiring board 1 of this embodiment can be made to increase the number of wires provided between vias.

[0087] (Embodiment 3) The wiring board 1 of Embodiment 3 will be described with reference to Figures 7 to 9. Figure 7 is a schematic diagram showing the relationship between the surface layer of the wiring board 1 according to Embodiment 3 of the present invention and the bump map of the chiplets 200. Figure 7 shows an example of the arrangement of two chiplets 200, a first chiplet 200A and a second chiplet 200B, which are mounted on the wiring board 1 (shown in Figure 8).

[0088] The first tiplet edge 211 of the first tiplet 200A and the second tiplet edge 212 of the second tiplet 200B face each other in the column direction 1020.

[0089] The first chiplet 200A and the second chiplet 200B, like the chiplet 200 shown in Figure 1B, each have 10 bumpland rows 100. The 10 bumpland rows 100 are referred to, in order from one side in the row direction 1030, as the first bumpland row 101, the second bumpland row 102, the third bumpland row 103, the fourth bumpland row 104, the fifth bumpland row 105, the sixth bumpland row 106, the seventh bumpland row 107, the eighth bumpland row 108, the ninth bumpland row 109, and the tenth bumpland row 110.

[0090] The wiring board 1 includes via land rows 120, similar to Embodiment 2 shown in Figure 2.

[0091] (Area on the side of the first chiplet 200A) First, the area on the side of the first chiplet 200A of the wiring board 1 will be described. The area on the side of the first chiplet 200A of the wiring board 1 is provided with three beer land rows 120. In the example shown in Figure 7, all three beer land rows 120 are relocated beer land rows 122. The three beer land rows 120 will be referred to as the first beer land row 161, the second beer land row 162, and the third beer land row 163.

[0092] In the region of the wiring board 1 on the side of the first chiplet 200A, the first bump land row 101, the second bump land row 102, the third bump land row 103, and the fourth bump land row 104 are referred to as the first column group 141. The fifth bump land row 105 and the sixth bump land row 106 are referred to as the second column group 142. The seventh bump land row 107, the eighth bump land row 108, the ninth bump land row 109, and the tenth bump land row 110 are referred to as the third column group 143.

[0093] The first via row 161 is connected to the bump land 20 belonging to the four bump land rows 100 included in the first column group 141 via surface wiring 62. Thus, the first column group 141 has a configuration in which one via row is arranged for every four bump rows.

[0094] The same applies to the third column group 143. That is, the bump lands 20 belonging to the four bump land rows 100 included in the third column group 143 are connected to the third via land row 163 via the surface wiring 62. In this way, the third column group 143, like the first column group 141, has a configuration in which one via row is arranged for each of the four bump rows.

[0095] In contrast, the second column group 142 has a configuration in which one via row is arranged for two bump rows. The second via row 162 is connected to two bump lands 20 belonging to two bump land rows 100 included in the second column group 142 via surface wiring 62.

[0096] Thus, in the region of the wiring board 1 on the side of the first chiplet 200A, via land rows 120 are arranged in the row direction 1030 as follows: (one via row per four bump rows) - (one via row per two bump rows) - (one via row per four bump rows).

[0097] Thus, in Embodiment 3, by further increasing the number of Bumpland columns per Viarland row, it becomes possible to arrange more wiring and increase the wiring width.

[0098] In the example above, arranging one vialand column for every four bumpland columns makes it possible to wire a greater number of signals. However, four columns is just one example, and the number of columns can be any number. For example, one vialand column may be arranged for every three or more bumpland columns. In other words, one vialand column may be placed for every three or more bumpland columns.

[0099] (Region on the side of the second chiplet 200B) Next, the region on the side of the second chiplet 200B of the wiring board 1 will be described. The region of the second chiplet 200B will be described as having a different configuration from the region on the side of the first chiplet 200A. In the example shown in Figure 7, as described above, the region on the side of the first chiplet 200A of the wiring board 1 includes a configuration of one via row per four bump rows, whereas the second chiplet 200B includes a configuration of one via row per three bump rows.

[0100] The area of ​​the wiring board 1 on the side of the second chiplet 200B is provided with four beer land rows 120. In the example shown in Figure 7, all four beer land rows 120 are relocated beer land rows 122. The four beer land rows 120 are referred to as the first beer land row 161, the second beer land row 162, the third beer land row 163, and the fourth beer land row 164.

[0101] In the region of the wiring board 1 on the second chiplet 200B side, the first bump land row 101 and the second bump land row 102 are referred to as the first column group 151. The third bump land row 103, the fourth bump land row 104, and the fifth bump land row 105 are referred to as the second column group 152. The sixth bump land row 106, the seventh bump land row 107, and the eighth bump land row 108 are referred to as the third column group 153. The ninth bump land row 109 and the tenth bump land row 110 are referred to as the fourth column group 154.

[0102] The first via row 161 is connected to two bump rows 100 belonging to the first column group 151 via surface wiring 62. Thus, the first column group 151 has a configuration in which one via row is arranged for every two bump rows.

[0103] The same applies to the fourth column group 154. That is, the bump lands 20 belonging to the two bump land rows 100 included in the fourth column group 154 ​​are connected to the fourth via land row 164 via the surface wiring 62. In this way, the fourth column group 154, like the first column group 151, has a configuration in which one via row is arranged for every two bump rows.

[0104] In contrast, the second column group 152 has a configuration in which one via row is arranged for each of the three bump rows. The bump lands 20 belonging to the three bump land rows 100 included in the second column group 152 are connected to the second via land row 162 via surface wiring 62.

[0105] The same applies to the third column group 153. That is, the bump lands 20 belonging to the three bump land rows 100 included in the third column group 153 are connected to the third via land row 163 via the surface wiring 62. In this way, the third column group 153, like the second column group 152, has a configuration in which one via row is arranged for three bump rows.

[0106] Thus, in the region of the wiring board 1 on the second chiplet 200B side, via land rows 120 are arranged in the row direction 1030 as follows: (one via row per two columns of bump rows) - (one via row per three columns of bump rows) - (one via row per three columns of bump rows) - (one via row per two columns of bump rows).

[0107] As shown in Figure 7, by combining a first chiplet 200A having the configuration "(one via array per four bump rows) - (one via array per two bump rows) - (one via array per four bump rows)" and a second chiplet 200B having the configuration "(one via array per two bump rows) - (one via array per three bump rows) - (one via array per three bump rows) - (one via array per two bump rows)", the wiring efficiency when connecting them can be improved. Here, wiring efficiency refers to the ability to place more wires and to increase the width of the wires.

[0108] In addition to arranging one via row per bump row with multiple columns, the degree of freedom in controlling the wiring density can be increased by changing the number of columns per via row of opposing devices, such as the first chiplet 200A and the second chiplet 200B.

[0109] The explanation will be given with reference to Figure 8. Figure 8 is a diagram showing the details of the surface layer 10 of the wiring board 1 of Embodiment 3. Figure 8 corresponds to Figure 2 in Embodiment 2. The wiring board 1 of Embodiment 3 will be explained focusing on the differences from the wiring board 1 of Embodiment 2. Matters of the wiring board 1 of Embodiment 3 that are not specifically explained can be the same as those of the wiring board 1 of Embodiment 2.

[0110] Figure 8 shows the portions corresponding to the third column group 143 in the first chiplet 200A shown in Figure 7, and the third column group 153 and fourth column group 154 ​​in the second chiplet 200B shown in Figure 7.

[0111] In the example shown in Figure 8, the bumplands 20 included in the four bumpland rows 100 belonging to the third column group 143 of the first chiplet 200A, namely the seventh bumpland row 107, the eighth bumpland row 108, the ninth bumpland row 109, and the tenth bumpland row 110, are connected to the second chiplet 200B via a single beerland row 120, namely the third beerland row 163.

[0112] Specifically, each signal layer wiring 60 connected to the third vialand row 163 is divided and connected to the vialand row 120 to which the bumpland 20 belonging to the third column group 153 in the second chiplet 200B is connected, i.e., the third vialand row 163, and to the vialand row 120 to which the bumpland 20 belonging to the fourth column group 154 ​​is connected, i.e., the fourth vialand row 164.

[0113] More specifically, via the aforementioned Beerland row 120, the bumpland 20 belonging to the 7th bumpland row 107 of the first chiplet 200A is connected to the bumpland 20 belonging to the 7th bumpland row 107 of the second chiplet 200B. Similarly, the bumpland 20 belonging to the 8th bumpland row 108 of the first chiplet 200A is connected to the bumpland 20 belonging to the 8th bumpland row 108 of the second chiplet 200B, the bumpland 20 belonging to the 9th bumpland row 109 of the first chiplet 200A is connected to the bumpland 20 belonging to the 9th bumpland row 109 of the second chiplet 200B, and the bumpland 20 belonging to the 10th bumpland row 110 of the first chiplet 200A is connected to the bumpland 20 belonging to the 10th bumpland row 110 of the second chiplet 200B.

[0114] By connecting the first chiplet 200A and the second chiplet 200B as described above, wiring can be improved. This will be explained below.

[0115] For example, in the case of a UCIe-A10 column module, with a 4-column, 1-signal via array (one via array per 4-column bump array), the wiring exit area at half the width of the row direction 1030 of the chiplet 200 is (5 / 2) × Y (denoted as 5 / 2Y in Figure 8; similarly, (1 / 4) × Y is denoted as 1 / 4Y, and (1 / 2) × V is denoted as 1 / 2V) as shown in Figure 8. Since there are 1 + 1 / 2 via lands in between, the width of the row direction 1030 where wiring can be placed is (5 / 2) × Y - (3 / 2) × V.

[0116] Within a range of half the width of the row direction 1030 in the chiplet 200, there are five bump land rows. Therefore, the wiring exit area per bump land row is (1 / 2) × Y - (3 / 10) × V.

[0117] In a 4-column, 1-signal via array, the wiring pull-out area per bump land row is (1 / 5) × V larger than in a 2-column, 1-signal via array (1 via row per 2-column bump row). Therefore, if the via land diameter is 20 μm, the area per bump land row will be 4 μm larger.

[0118] If a shielded wiring with L / s = 2 / 2um is passed between via lands, and the via land diameter is 5.25um, the wiring exit area per bump row will be 1.05um larger than that of a 2-column 1-signal via row.

[0119] For example, if Y = 77.76 μm and V = 20 μm, the wiring lead-out area will be as follows. That is, for a 4-column 1-signal via array, it will be 194.4 - 30 = 164.4 μm, and for a 2-column 1-signal via array, it will be 57.76 μm. The effect of a 4-column 1-signal via array on a 2-column 1-signal via array is (3Y - V) / 2.

[0120] (Ground Shield Wiring) Figure 9 shows an example of the arrangement when ground shield wiring 66 is arranged in the configuration of Embodiment 3. As shown in Figure 3 in Embodiment 2, in the configuration of Embodiment 3, ground shield wiring 66 may also be arranged for the wiring that connects the two chiplets. Ground shield wiring 66 is arranged in the signal layer 12 in the same way as signal layer wiring 60. As shown in Figure 9, ground shield wiring 66 is formed so that it has the same potential as a whole. Even when ground shield wiring 66 is formed, the number of wires arranged between vias can be increased in the wiring board 1 of this embodiment. Note that, as with Embodiment 2, the arrangement of signal layer wiring 60 etc. shown in Figure 9 etc. in Embodiment 3 is illustrative.

[0121] The embodiments of the present invention have been described above. The present invention is not limited to the embodiments described above, and various modifications, variations, and combinations are possible.

[0122] In the wiring board 1 of the embodiment of the present invention, many signals can be wired on the same layer. Furthermore, because a large number of signals can be wired on the same layer, the number of wiring layers (signal layers) can be reduced. In addition, it becomes easier to widen the wiring width, which reduces wiring resistance.

[0123] Furthermore, the configuration of the wiring board 1 in the embodiment of the present invention ensures (increases) wiring space, improving the degree of freedom in wiring design. This allows for appropriate adjustment of the width of signal wiring and GND wiring, and for example, the characteristics of VTF (Voltage Transfer Function) insertion loss and crosstalk as defined by UCIe can be improved without increasing the number of layers on the board.

[0124] <1> The wiring board is a wiring board having a plurality of bump lands and a plurality of surface via lands on its surface, wherein the surface has a bump land portion, and the bump land portion has a plurality of bump land rows formed by at least a portion of the plurality of bump lands being arranged side by side, and at least one via land row formed by at least a portion of the plurality of surface via lands being arranged side by side, the bump land rows and the via land rows are parallel, and one via land row is arranged for every two bump land rows.

[0125] <2> When two adjacent bumpland rows are designated as the first bumpland row and the second bumpland row, and the beerland row arranged in correspondence with the first bumpland row and the second bumpland row is designated as the corresponding beerland row, the wiring board according to <1> wherein the bumpland included in the first bumpland row and the bumpland included in the second bumpland row are connected to the surface beerland included in the corresponding beerland row.

[0126] <3> The wiring board according to <2>, wherein at least one of the first bump land row and the second bump land row does not overlap with the corresponding via land row when viewed from a direction perpendicular to the surface layer.

[0127] <4> The wiring board according to <2>, wherein neither the first bump land row nor the second bump land row overlaps with the corresponding via land row when viewed from a direction perpendicular to the surface layer.

[0128] <5> The wiring board according to <3> or <4>, wherein the surface layer is provided with wiring that connects the bump land included in the bump land row that does not overlap with the corresponding beer land row when viewed from a direction perpendicular to the surface layer, among the first bump land row and the second bump land row, and the surface beer land included in the corresponding beer land row.

[0129] <6> The wiring board according to <4>, wherein the corresponding vialand row is positioned between the first bumpland row and the second bumpland row in a direction intersecting with the first bumpland row.

[0130] <7> The sum of the number of bumplands included in the first bumpland row and the number of bumplands included in the second bumpland row, and the number of surface beerlands included in the corresponding beerland row, corresponds to the wiring board described in <2>.

[0131] <8> A wiring board according to any one of <1> to <7>, comprising vias connected to the surface via land and disposed between the surface layer and the signal layer, wherein the signal layer has signal layer via lands connected to the vias, wiring is connected to the signal layer via lands, and the diameter of the signal layer via land is greater than the width of the wiring.

[0132] <9> The surface layer is provided with wiring that connects the bump land included in the bump land rows of the first bump land row and the second bump land row that do not overlap with the corresponding bump land row when viewed from a direction perpendicular to the surface layer, and the surface bump land included in the corresponding bump land row, the wiring extends in a direction inclined with respect to the direction perpendicular to the first bump land row, and the corresponding bump land row is positioned at the center of the first bump land row and the second bump land row in the direction perpendicular to the first bump land row, as described in <6>.

[0133] Furthermore, the wiring board of one embodiment of the present invention may be the following wiring board: (1) A wiring board having a surface layer, a signal layer, a plurality of surface lands provided on the surface layer, and a plurality of vias connecting the surface layer and the signal layer, wherein the wiring board has a plurality of surface land rows in which at least a portion of the plurality of surface lands are arranged side by side, and at least one via row in which at least a portion of the plurality of vias are arranged side by side, the surface land rows and the via rows are parallel, and one via row is arranged for every two of the surface land rows.

[0134] (2) The wiring board of (1), wherein the signal layer has a plurality of signal layer via lands connected to the plurality of vias, and has a plurality of signal layer via land rows in which at least a portion of the plurality of signal layer via lands are arranged side by side, the surface land rows and the signal layer via land rows are parallel, and one signal layer via land row is arranged for every two surface land rows.

[0135] Furthermore, the wiring board of the embodiment of the present invention can be the following wiring board.

[0136] [1] A wiring board having a plurality of bump lands and a plurality of surface via lands on its surface, wherein the surface has a bump land portion, the bump land portion has a plurality of bump land rows formed by at least a portion of the plurality of bump lands being arranged side by side, and at least one via land row formed by at least a portion of the plurality of surface via lands being arranged side by side, the bump land row and the via land row are parallel, and one via land row is arranged for each of the plurality of bump land rows.

[0137] [2] The wiring board according to [1], wherein the vialand row is arranged one for every three or more bumpland rows.

[0138] [3] The wiring board according to [1], wherein a plurality of vialand rows are formed, at least one vialand row is arranged for a first number of bumpland rows which is two or more, and at least one vialand row is arranged for a second number of bumpland rows which is different from the first number and is two or more.

[0139] 1 Wiring board 10 Surface layer 12 Signal layer 14 Insulation layer 18 Bump land section 20 Bump land 21 Direct via bump land 22 Relocated via bump land 30 Surface via land 31 Direct via land 32 Relocated via land 40 Signal layer via land 50 Via 51 Direct via 52 Relocated via 54 Via surface 56 Via signal layer surface 60 Signal layer wiring 62 Surface wiring 66 Ground shield wiring 90 Wiring board 100 Bump land row 101 First bump land row 102 Second bump land row 103 Third bump land row 104 Fourth bump land row 105 Fifth bump land row 106 Sixth bump land row 107 Seventh bump land row 108 Eighth bump land row 109 9th Bumpland Row 110 10th Bumpland Row 120 Beerland Row 121 Directly Below Beerland Row 122 Relocated Beerland Row 123 Integrated Beerland Row 131 Beerland End 141 1st Column Group 142 2nd Column Group 143 3rd Column Group 151 1st Column Group 152 2nd Column Group 153 3rd Column Group 154 ​​4th Column Group 161 1st Beerland Row 162 2nd Beerland Row 163 3rd Beerland Row 164 4th Beerland Row 200 Chiplet 200A 1st Chiplet 200B 2nd Chiplet 201 1st Chiplet 202 2nd Chiplet 211 1st Chiplet Edge 212 2nd Chiplet Edge 220 Bump 401 First Chiplet Beer Land 402 Second Chiplet Beer Land 1010 Stacking Direction 1011 Upward Direction 1012 Downward Direction 1020 Column Direction 1030 Row Direction 2010 Bordered Area

Claims

1. A wiring board having a plurality of bump lands and a plurality of surface via lands on its surface, wherein the surface has a bump land portion, the bump land portion has a plurality of bump land rows formed by at least a portion of the plurality of bump lands being arranged side by side, and at least one via land row formed by at least a portion of the plurality of surface via lands being arranged side by side, the bump land rows and the via land rows are parallel, and one via land row is arranged for each of the plurality of bump land rows.

2. The wiring board according to claim 1, wherein one vialand row is arranged for three or more bumpland rows.

3. When two adjacent bumpland rows are designated as a first bumpland row and a second bumpland row, and the beerland rows arranged in correspondence with the first bumpland row and the second bumpland row are designated as corresponding beerland rows, the bumpland included in the first bumpland row and the bumpland included in the second bumpland row are connected to the surface beerland included in the corresponding beerland row, the wiring board according to claim 1.

4. The wiring board according to claim 3, wherein at least one of the first bump land row and the second bump land row does not overlap with the corresponding via land row when viewed from a direction perpendicular to the surface layer.

5. The wiring board according to claim 3, wherein neither the first bump land row nor the second bump land row overlaps with the corresponding via land row when viewed from a direction perpendicular to the surface layer.

6. The wiring board according to claim 4, wherein the surface layer is provided with wiring that connects the bump land included in the bump land rows of the first bump land row and the second bump land row that do not overlap with the corresponding beer land row when viewed from a direction perpendicular to the surface layer, and the surface beer land included in the corresponding beer land row.

7. The wiring board according to claim 5, wherein the corresponding vialand row is arranged between the first bumpland row and the second bumpland row in a direction intersecting with the first bumpland row.

8. The sum of the number of bumplands included in the first bumpland row and the number of bumplands included in the second bumpland row, and the number of surface beerlands included in the corresponding beerland row, is the corresponding wiring board according to claim 3.

9. A wiring board according to claim 1, comprising vias connected to the surface via lands and disposed between the surface layer and the signal layer, wherein the signal layer has signal layer via lands connected to the vias, wiring is connected to the signal layer via lands, and the diameter of the signal layer via lands is greater than the width of the wiring.

10. The surface layer is provided with wiring connecting the bump land included in the bump land rows of the first bump land row and the second bump land row that do not overlap with the corresponding bump land row when viewed from a direction perpendicular to the surface layer, and the surface bump land included in the corresponding bump land row, the wiring extending in a direction inclined with respect to the direction perpendicular to the first bump land row, and the corresponding bump land row being positioned at the center of the first bump land row and the second bump land row in the direction perpendicular to the first bump land row, as described in claim 7.

11. The wiring board according to claim 1, wherein a plurality of vialand rows are formed, at least one vialand row is arranged one for a first number of vialand rows which is two or more, and at least one vialand row is arranged one for a second number of vialand rows which is different from the first number and which is two or more.

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