Global-clock-assisted in-pixel time-to-digital converter architecture for high-precision depth sensing

Abstract

A method for measuring a time-of-flight interval in a depth sensing system includes generating a coarse time count using a global clock signal shared across a plurality of pixels and external to the sensor array, wherein the coarse time count provides the most significant bits of the time-of-flight interval free of inter-pixel process variation; generating an intermediate time count within a pixel using a local ring oscillator based on completed oscillation cycles during a measurement interval; generating a fine time residual within the pixel based on at least one phase state of the ring oscillator, wherein the fine time residual provides the least significant bits; and deriving the time-of-flight interval from a combination of the coarse time count, the intermediate time count, and the fine time residual.

Description

Atty. Docket No. 4502-90500 (6000777PCT01)GLOBAL-CLOCK-ASSISTED IN-PIXEL TIME-TO-DIGITAL CONVERTER ARCHITECTURE FOR HIGH-PRECISION DEPTH SENSINGCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] NoneTECHNICAL FIELD

[0002] Disclosed embodiments relate generally to time-of-flight depth sensing and, more particularly, to, and more specifically to a global-clock-assisted in-pixel time-to-digital converter architecture for high-precision depth sensing.BACKGROUND

[0003] Three-dimensional depth sensing based on direct time-of-flight (dToF) measurement is a fundamental enabling technology for autonomous vehicle perception, robotic manipulation, facial recognition, industrial metrology, and three-dimensional scene reconstruction.SUMMARY

[0004] A first aspect relates to a method for measuring a time-of-flight interval in a depth sensing system. The method includes generating a coarse time count using a global clock signal shared across a plurality of pixels, generating an intermediate time count within a pixel using a local ring oscillator, generating a fine time residual based on at least one phase state of the ring oscillator, and deriving the time-of-flight interval from the combination of the coarse time count, the intermediate time count, and the fine time residual.

[0005] Optionally, in a first implementation according to the first aspect, the method further includes receiving a start signal upon emission of a laser pulse, incrementing a global counter on each rising edge of the global clock signal, and generating the coarse time count based on the global counter in response to a stop signal.

[0006] Optionally, in a second implementation according to the first aspect or any implementation thereof, generating the intermediate time count comprises setting a local counter to a maximum value in response to the stop signal, decrementing the local counter on each completed cycle of the ring oscillator, and setting the value of the local counter at the next rising edge of the global clock signal as the intermediate time count.Atty. Docket No. 4502-90500 (6000777PCT01)

[0007] Optionally, in a third implementation according to the first aspect or any implementation thereof, generating the fine time residual comprises storing a first phase state of the ring oscillator at the stop signal, storing a second phase state at the next rising edge of the global clock signal, and generating the fine time residual based on a decoded difference between the two phase states through correlated double sampling.

[0008] Optionally, in a fourth implementation according to the first aspect or any implementation thereof, the global counter has n bits, the local counter has i bits, and the fine time residual has j bits of phase resolution, such that the time-of-flight interval is represented as N = n + i + j bits.

[0009] Optionally, in a fifth implementation according to the first aspect or any implementation thereof, the time-of-flight interval is expressed as AT = (n+1) x TG - (TG - Tres).

[0010] Optionally, in a sixth implementation according to the first aspect or any implementation thereof, the method further includes operating a phase-locked loop circuit external to the sensor array to lock a dummy ring oscillator and distributing a common bias voltage to each pixel’s ring oscillator to reduce inter-pixel variation.

[0011] Optionally, in a seventh implementation according to the first aspect or any implementation thereof, the dummy ring oscillator has the same design as the ring oscillator within the pixel.

[0012] A second aspect relates to a method for measuring a time-of-flight interval (AT) in a depth sensing system having a sensor array of pixels. The method includes receiving a start signal, resetting a global counter, generating a coarse time count using a global clock signal, receiving a stop signal from a SPAD, latching phase states of a local ring oscillator, generating an intermediate time count and a fine time residual (Tres), and deriving AT according to AT = (n+1) x TG - (TG -Tres).

[0013] Optionally, in a first implementation according to the second aspect, the local counter has i bits and the fine time residual provides j bits of phase resolution such that the time-of-flight interval is represented by N = n + i + j bits.

[0014] Optionally, in a second implementation according to the second aspect or any implementation thereof, the decoded difference cancels propagation delay of the global clock signal and the start signal along with any unknown starting phase of the local ring oscillator.

[0015] Optionally, in a third implementation according to the second aspect or anyAtty. Docket No. 4502-90500 (6000777PCT01)implementation thereof, the method further includes operating a phase-locked loop circuit with a dummy ring oscillator and distributing a common bias voltage to reduce inter-pixel ring oscillator period variation.

[0016] A third aspect relates to a system for measuring a time-of-flight interval. The system comprises a global clock circuit, a global counter, a ring oscillator local to each pixel, and processing circuitry within the pixel configured to generate the intermediate time count, fine time residual, and derive the time-of-flight interval.

[0017] Optionally, in a first implementation according to the third aspect, the system further comprises a laser source generating a start signal, wherein the global counter resets in response to the start signal.

[0018] Optionally, in a second implementation according to the third aspect or any implementation thereof, the pixel comprises a local counter configured to be set to a maximum value and decrement on each cycle of the ring oscillator to generate the intermediate time count.

[0019] Optionally, in a third implementation according to the third aspect or any implementation thereof, the pixel further comprises first and second registers for latching phase states of the ring oscillator to generate the fine time residual.

[0020] Optionally, in a fourth implementation according to the third aspect or any implementation thereof, the system further comprises a phase-locked loop circuit, a dummy ring oscillator, and a bias distribution network to reduce inter-pixel variation.

[0021] A fourth aspect relates to a time-to-digital converter integrated circuit of a pixel in a sensor array for measuring a time-of-flight interval (AT). The depth sensor pixel and time-to-digital converter integrated circuit comprises a global counter, a SPAD, a ring oscillator, first and second registers, a local counter, and processing circuitry configured to generate the intermediate time count, fine time residual, and derive AT according to the specified formula.

[0022] Optionally, in a first implementation according to the fourth aspect, the local counter has i bits and the fine time residual provides j bits of phase resolution such that N = n + i + j bits.

[0023] Optionally, in a second implementation according to the fourth aspect or any implementation thereof, the decoded difference cancels propagation delay and unknown starting phase.

[0024] A fifth aspect relates to an apparatus comprising a memory configured to store instructions; and one or more processors coupled to the memory and configured to execute theAtty. Docket No. 4502-90500 (6000777PCT01)instructions to cause the apparatus to perform the method according to the first aspect or any implementation thereof.

[0025] A sixth aspect relates to a computer program product comprising computer-executable instructions stored on a non-transitory computer-readable storage medium and that, when executed by one or more processors, cause the apparatus to perform any one of the methods according to the first or second aspect or any implementation thereof.

[0026] For clarity, any one of the foregoing aspects may be combined with any one or more of the other foregoing aspects to create a new embodiment within the scope of the present disclosure.

[0027] These and other features, and the advantages thereof, will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims.BRIEF DESCRIPTION OF DRAWINGS

[0028] For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.

[0029] FIG. 1 is a diagram illustrating an example a light detection and ranging (LIDAR) unit in accordance with one or more embodiments of the disclosure.

[0030] FIG. 2 is a diagram illustrating an example of a real-world use case of LIDAR in accordance with one or more embodiments of the disclosure.

[0031] FIG. 3 is a diagram illustrating a single-photon avalanche diode (SPAD) array for depth sensing in accordance with one or more embodiments of the disclosure.

[0032] FIG. 4 is a diagram illustrating a two-wafer stacking SPAD array architecture in accordance with one or more embodiments of the disclosure.

[0033] FIG. 5 is a diagram illustrating a dToF LIDAR depth sensing system working principle in accordance with one or more embodiments of the disclosure.

[0034] FIG. 6 is a diagram illustrating a SPAD-based dToF array architecture in accordance with one or more embodiments of the disclosure.

[0035] FIG. 7 is a diagram illustrating a traditional pixel time to digital converter (TDC) architecture with a ring oscillator in accordance with one or more embodiments of the disclosure.Atty. Docket No. 4502-90500 (6000777PCT01)

[0036] FIG. 8 is a diagram illustrating conventional in-pixel circuit of a SPAD-based dToF array.

[0037] FIG. 9A and FIG. 9B are diagrams illustrating a comparison between a traditional inpixel TDC architecture and a new global-clock-assisted TDC architecture in accordance with one or more embodiments of the disclosure.

[0038] FIG. 10 is a timing diagram illustrating the time-of-flight measurement interval AT and the challenge of aligning the global clock domain with the local pixel ring oscillator in accordance with one or more embodiments of the disclosure.

[0039] FIG. 11 is a timing diagram comparing two candidate methods for measuring the residual time in accordance with one or more embodiments of the disclosure.

[0040] FIG. 12 is a timing diagram illustrating the mathematical derivation of the time-of-flight interval AT using a reverse data- tracking method in accordance with one or more embodiments of the disclosure.

[0041] FIG. 13 is a diagram illustrating an architecture of a pixel TDC integrated circuit (IC) in accordance with one or more embodiments of the disclosure.

[0042] FIG. 14 is a combined waveform and data diagram illustrating the complete operation of a TDC architecture in accordance with one or more embodiments of the disclosure.

[0043] FIG. 15 is a flowchart illustrating a method for determining a dToF measurement in accordance with one or more embodiments of the disclosure.

[0044] FIG. 16 is a diagram illustrating an optional clock domain alignment technique in accordance with one or more embodiments of the disclosure.

[0045] FIG. 17 is a flowchart illustrating a method for measuring a time-of-flight interval in a depth sensing system in accordance with one or more embodiments of the disclosure.DESCRIPTION OF EMBODIMENTS

[0046] It should be understood at the outset that, although illustrative implementations of one or more embodiments are provided below, the disclosed systems and / or methods may be implemented using any number of techniques, whether currently known or in existence. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary designs and implementations illustrated andAtty. Docket No. 4502-90500 (6000777PCT01)described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents.

[0047] The present disclosure provides a framework, architecture, systems, and methods of a global-clock-assisted in-pixel time-to-digital converter architecture for high-precision depth sensing.

[0048] FIG. 1 is a diagram illustrating an example a LIDAR system 100 in accordance with one or more embodiments of the disclosure. The LIDAR system 100 is configured to perform dTOF measurements, which may be used to generate three-dimensional environmental mapping. In dToF systems, a light source emits a laser pulse toward a target scene, and a photodetector measures the elapsed time AT between emission of the pulse and detection of the reflected photon. The distance d to the target is derived from the relationship d = c x AT / 2, where c is the speed of light. Because one millimeter of distance corresponds to approximately 6.7 picoseconds of elapsed time, the accuracy of the distance measurement is directly determined by the precision of the time measurement circuitry.

[0049] The LIDAR system 100 comprises a rotating sensor unit mounted on a motor housing 102. The sensor unit includes a substantially cylindrical housing 104 that encloses and supports an array of laser emitters 106 and corresponding laser receivers 108, with the entire unit designed to rotate continuously about a vertical axis. This rotational motion enables azimuthal scanning of the surrounding environment, allowing the system to capture distance data across a full 360-degree field of view in successive horizontal planes.

[0050] In an embodiment, the laser emitters 106 are generally arranged in discrete groups (e.g., each group containing 16 individual emitter elements) and are positioned on the outer periphery of the sensor unit. The laser emitters 106 may be solid-state laser diodes operating in the nearinfrared wavelength range, and are configured to generate collimated pulsed laser beams that are projected outward from the rotating housing. Each emitter group is aligned to transmit beams along dedicated optical paths, ensuring that the emitted pulses are directed toward specific angular sectors during rotation. The emitters are driven by associated control electronics to produce short-duration, high-intensity optical pulses, with precise timing synchronized to the rotational position of the unit for accurate angular registration of each measurement.

[0051] The laser receivers 108 may also be organized in groups, where each group comprises a plurality of discrete sensor elements. In some embodiments, each receiver element consists of aAtty. Docket No. 4502-90500 (6000777PCT01)SPAD detector paired with dedicated optics, such as a lens or aperture, configured to collect backscattered photons from the corresponding transmitted laser pulse. SPADs are widely employed as detectors in dToF depth sensing systems due to their ability to detect individual photons with sub-nanosecond temporal resolution. The laser receivers 108 are spatially aligned with the laser emitters 106 such that each detector element is optically coupled to a dedicated laser beam path, forming discrete transmit-receive channels. Upon return of the reflected photons, the SPAD detectors register individual photon arrivals with high temporal resolution. Time-of-flight circuitry measures the precise interval between pulse emission and photon detection, enabling calculation of the range to the target surface using the known speed of light.

[0052] In some implementations, the motor housing 102, positioned at the base of the cylindrical unit, contains an electric motor for use in sustaining the controlled rotation of the entire sensor assembly. Encoders or similar position-sensing devices may be integrated with the motor to provide real-time angular position data, which is correlated with each time-of-flight measurement to map the received signals into a spherical or cylindrical coordinate system. The housing may further incorporates power and data interfaces to supply electrical power to the emitters, receivers, and motor while transmitting raw or processed data to external processing units.

[0053] FIG. 2 is a diagram illustrating an example of a real-world use case of the LIDAR system 100 mounted on a vehicle in accordance with one or more embodiments of the disclosure. In operation, the rotating LIDAR system 100 sequentially illuminates the environment with laser pulses from the laser emitters 106 as it spins as shown in FIG. 2. Reflected light from objects within the field of view is collected by the aligned receiver groups, where the SPAD arrays convert the optical returns into a time stamp electrical signal. Signal processing electronics within or coupled to the unit perform histogram-based or direct time-stamping analysis on the photon arrival times to determine distances, while compensating for factors such as ambient light noise and sensor dead time. The resulting data forms a dense three-dimensional point cloud representing the scanned scene, which may be then used, along with other data if available such as camera images, for autonomous operation of the vehicle.

[0054] FIG. 3 is a diagram illustrating a SPAD array 300 for depth sensing in accordance with one or more embodiments of the disclosure. In contrast to the conventional LIDAR system 100, which is built with discrete sensor components, typically it is large and costly to manufacture, theAtty. Docket No. 4502-90500 (6000777PCT01)chip level integrated SPAD array 300 may be implemented entirely on a single processor or chip. In an embodiment, the SPAD array 300 comprises a plurality of pixel units (or pixels) 302 arranged in a two-dimensional grid. Each pixel unit 302 includes a SPAD-based semiconductor photodetector element designed to detect individual echo photon of light with extremely high sensitivity and precise timing. In an embodiment, the SPAD-based semiconductor photodetector element is a p-n junction photodiode that is reverse-biased well above a breakdown voltage (typically by several volts). This operating mode is called Geiger mode. When no light is present, the photodiode remains in a stable ready state with a very high electric field in the depletion region. When a single photon strikes the active area of the pixel and is absorbed, it generates an electronhole pair. The strong electric field accelerates the charge carrier, which then triggers impact ionization, creating a self-sustaining avalanche of millions of electrons in a very short time (picoseconds). This avalanche produces a fast, detectable digital-like current pulse (a “click”), signaling the arrival of even a single photon. In an embodiment, the SPAD array 300 architecture enables single-flash illumination in which the entire scene is illuminated simultaneously and all pixels acquire their depth measurements in a single measurement cycle. In some embodiments, due to the volume of raw timing data being produced by a large SPAD array, each pixel 302 may have its own TDC to perform local, in-pixel time measurement instead of routing the data off-chip for centralized measurement. The SPAD array 300 may include shared circuitry 304 (labeled as global electronics in FIG. 3) configured to manage signal routing to direct timing and control signals to the appropriate pixels across the array. The SPAD array 300 may also include a demultiplexer (DEMUX) 306 configured to multiplex / demultiplex incoming and outgoing signals to / from the sensor array to other processing electronics. In some embodiments, the signal routing, control, and timing management functions performed by the shared circuitry 304 may be implemented in dedicated hardware, such as an application-specific integrated circuit (ASIC), or alternatively by one or more processors coupled to a memory storing instructions that, when executed, cause the one or more processors to perform such functions.

[0055] FIG. 4 is a diagram illustrating a vertically stacked two-wafer SPAD array architecture 400 in accordance with one or more embodiments of the disclosure. In an embodiment, the SPAD array 300 may be implemented using the SPAD array architecture 400. The SPAD array architecture 400 comprises a pixel array layer 402 as a top layer and a timing and processing circuit layer 404 as a bottom layer. In an embodiment, the pixel array layer 402 is fabricated on a sensorAtty. Docket No. 4502-90500 (6000777PCT01)wafer and is bonded to a circuit wafer containing the timing and processing circuit layer 404. In an embodiment, the timing and processing circuit layer 404 is reconfigurable pixel logic that can be programmed or adjusted, giving the chip flexibility across different sensing modes or applications. In an embodiment, the timing and processing circuit layer 404 comprises operation control, quenching and TDC circuitry such as, but not limited to, clock, counter, register memory and other timing logic that is kept off-pixel. In some embodiments, vertical electrical connections such as, but not limited to, microscopic metal pillars or hybrid bonding contacts that pass signals directly between the two wafers at each pixel location. The vertically stacked two-wafer SPAD array architecture 400 enables the discrete components from the LIDAR system 100 in FIG. 1 to move to a chip solution, and from a single sensor to an array solution, by packing the SPAD array and all its supporting TDC circuitry into a single compact chip. In some embodiments, the timing and processing circuit layer 404 may be realized as a dedicated ASIC, or may incorporate one or more processors coupled to a non-volatile memory storing firmware instructions that, when executed, perform the measurement, quenching, and pixel logic functions described herein.

[0056] FIG. 5 is a diagram illustrating a dToF LIDAR depth sensing system 500 in accordance with one or more embodiments of the disclosure. The system 500 comprises a controller 502 that coordinates the timing and measurement operations of the system 500. The controller 502 includes a synchronization unit 504 and a TDC 506. The synchronization unit 504 generates a timing reference signal associated with the emission of a laser pulse from a laser 508. The laser 508 may include a pulsed laser diode, a vertical-cavity surface-emitting laser (VCSEL), or a distributed feedback (DFB) laser, among other suitable types. The TDC 506 uses this timing reference to mark the START time for determining the time-of-flight measurement interval AT. The laser 508 emits a pulsed optical signal that passes through a transmit optics assembly 510, which collimates and directs the outgoing pulse along the optical path toward a target 512 located at a distance d from the system 500. Upon striking the target 512, a portion of the emitted optical pulse is reflected back toward the system 500 as a return echo. The return echo is received and focused by a receive optics assembly 514, which directs the incoming optical signal onto a detector 516. In an embodiment, the detector 516 comprises a SPAD configured to detect individual photons of the return echo and, upon detection, generates and sends an electrical pulse STOP signal marking the precise moment of photon arrival to the TDC 506. The TDC 506 measures the elapsed time interval AT between the START and STOP events, and converts that interval into a digital outputAtty. Docket No. 4502-90500 (6000777PCT01)value. A processing unit 518 computes the distance d between the system 500 and the target 512 according to the formula d = c x AT / 2, wherein c is the speed of light and the factor of one-half accounts for the round-trip nature of the optical path from the system 500 to the target 512 and back. Because light travels extremely fast at 299,792,458 meters per second (e.g., 1 mm of depth distance corresponds to 6.7 picoseconds of time), one goal of the disclosed embodiments is to improve the precision of the timing measurement through implementation of a new pixel level TDC, which would result in a more precise distance measurement. This precision is important not only for autonomous driving, but in other areas such as, but not limited to, manufacturing, facial recognition, or robotics. In some embodiments, the controller 502 and / or the processing unit 518 may each be implemented as a dedicated ASIC, a field-programmable gate array (FPGA), or a general-purpose processor coupled to a memory configured to store instructions that, when executed, cause the processor to perform the time-of-flight measurement coordination and distance computation functions described herein, or any combination of hardware and software implementation.

[0057] FIG. 6 is a diagram illustrating a SPAD-based dToF array 600 in accordance with one or more embodiments of the disclosure. The SPAD-based dToF array 600 may be implemented similar to the vertically stacked two-wafer SPAD array architecture 400 in FIG. 4 (i.e., a SPAD array on a top / sensor wafer bonded to a complementary metal-oxide- semiconductor (CMOS) integrated circuit (IC) array on a bottom / circuit wafer). In an embodiment, the SPAD-based dToF array 600 includes a SPAD and a TDC circuit built directly inside each individual pixel cell (i.e., an in-pixel TDC). In an embodiment, the SPAD may be located on the top sensor wafer to detect the arrival of a photon and generate an electrical signal in response, which is passed to the TDC circuitry in the corresponding pixel in the circuit wafer. The in-pixel TDC is configured to measure AT within the pixel in the digital domain. In an embodiment, wafer-to-wafer hybrid bonding may be used to bond the sensor wafer to the circuit wafer. Wafer-to-wafer hybrid bonding is an advanced semiconductor manufacturing technique for permanently joining two silicon wafers into a single monolithic structure through direct material fusion, without the use of solder, adhesive, or metal bumps. In this process, both wafer surfaces are first polished to near-perfect flatness and chemically cleaned, then coated with a dielectric material (e.g., silicon dioxide) into which copper pads are precisely patterned at each intended connection point. When the two prepared surfaces are brought into contact, they bond spontaneously through molecular attraction between the ultraAtty. Docket No. 4502-90500 (6000777PCT01)flat dielectric surfaces. The bonded pair is then annealed at elevated temperatures, causing the copper pads on each wafer to expand thermally, press into one another, and form permanent metal-to-metal copper fusion bonds at every connection point simultaneously across the entire wafer surface, while the surrounding dielectric surfaces form permanent covalent oxide bonds. The result is a two- wafer stack in which each pixel or circuit element on one wafer is electrically connected to its corresponding counterpart on the other wafer through a copper bond interface measured in nanometers rather than micrometers. This extremely fine connection pitch minimizes signal propagation delay between the two layers and allows each wafer to be fabricated on a separate process node optimized for its specific function.

[0058] FIG. 7 is a diagram illustrating a traditional pixel TDC architecture and a corresponding timing diagram in accordance with one or more embodiments of the disclosure. The traditional pixel TDC architecture comprises a ring oscillator 702 and a counter 704. The ring oscillator 702 is a closed-loop chain of logic inverter stages that oscillates continuously at a frequency determined by the propagation delay of each inverter stage. The ring oscillator 702 provides local time fine resolution at the pixel level, functioning as the local in-pixel time counting element in the digital domain. The ring oscillator 702 outputs a fine state 706, which is a multi-bit digital value representing the instantaneous phase position of the oscillation within one complete cycle. The fine state 706 captures the sub-clock-period timing resolution of the TDC and constitutes the overall time-of-flight measurement. The counter 704 receives the output of the ring oscillator 702 and increments by one each time the ring oscillator 702 completes a full oscillation cycle. The counter 704 outputs a coarse state 708, which is a multi-bit digital value representing the total number of completed ring oscillator cycles elapsed since the start of the measurement. The coarse state 708 constitutes the most significant bits of the overall time measurement and extends the dynamic range of the TDC beyond what the ring oscillator 702 alone can resolve within a single cycle. The most significant bits are the leftmost bits of a binary number because they have constitute the largest weight (highest power of 2), thus contributing the most to the total value. In contrast, the rightmost bits in a binary number are the least significant bits as they contribute the least to the total value. Both the ring oscillator 702 and the counter 704 are controlled by a shared enable signal 710 and a reset signal 712. The enable signal 710 gates the operation of both the ring oscillator 702 and the counter 704, initiating and terminating the measurement interval. For instance, in an embodiment, when the enable signal 710 goes high, the TDC becomes active andAtty. Docket No. 4502-90500 (6000777PCT01)starts counting. The reset signal 712 returns both the ring oscillator 702 and the counter 704 to their respective initial states at the beginning of each new measurement cycle. The ring oscillator 702 outputs a clock signal 714 to the counter 704 as a reference timing input governing the counter’s operation. The total time measurement produced by this architecture is an N-bit digital value formed by concatenating the coarse state 708 bits from the counter 704 as the most significant bits with the fine state 706 bits from the ring oscillator 702 as the least significant bits. The corresponding timing diagram illustrates the sequential behavior of the fine state 706 and the coarse state 708 over time, where N is the total number of states given by the ring oscillator 702. The fine state 706 cycles sequentially through values 0, 1, 2, and onward through N-l before returning to 0, representing one complete oscillation cycle of the ring oscillator 702. Each time the fine state 706 completes a full cycle and resets to 0. the coarse state 708 increments by one, reflecting the completion of one full ring oscillator cycle. This interplay between the fine state 706 and the coarse state 708 enables the architecture to measure time intervals exceeding one ring oscillator period while preserving the fine sub-cycle resolution of the ring oscillator 702. In this traditional architecture, total timing, counting, and recording are all performed inside the pixel, with a total N-bit representation. If the ring oscillator has a time error due to process nonuniformity or variation, then the total cumulative error is N x 6TRO, where STRO is the per-stage timing error of the ring oscillator 702. Because all N bits of the time measurement are generated entirely within the pixel using a locally fabricated ring oscillator 702, every bit of the measurement is subject to the frequency and phase variation of that local oscillator. Since manufacturing process variation causes each pixel’s ring oscillator 702 to run at a slightly different frequency from neighboring pixels, the cumulative timing error grows proportionally with N (e.g., the wider the measurement, the larger the potential error) establishing the fundamental limitation that motivates the improved architecture described herein.

[0059] FIG. 8 is a diagram illustrating a conventional in-pixel circuit of a SPAD-based dToF array. The conventional in-pixel circuit comprises a single-photon avalanche diode (SPAD) 802, a ring oscillator (RO) 804, and a counter 806. As shown, a laser signal generates a START pulse provided to the counter 806 as a reset (RST) signal, thereby initializing the counter at the moment the laser pulse is emitted. The SPAD 802 is configured to detect a returning photon reflected from a target and, upon detection, to generate a STOP signal. The time interval AT between the START pulse and the STOP signal corresponds to the round-trip time-of-flight of the laser pulse. DuringAtty. Docket No. 4502-90500 (6000777PCT01)this interval, the ring oscillator 804 continuously oscillates (as indicated by the circular arrow) and supplies periodic pulses to the counter 806, incrementing the counter by +1 for each cycle. When the STOP signal arrives, the accumulated count of the counter 806 represents the coarse time measurement, while the residual time within the current incomplete ring oscillator cycle at the moment that the STOP signal is generated represents the fine time measurement. The total elapsed time AT between the START and STOP events is expressed by the relationship AT = N x TRO + Tres, where TRO is the period of the ring oscillator, Tres is the time residual defined within one ring oscillator period, and N is the number of completed ring oscillator cycles counted between the START and STOP events.

[0060] A fundamental limitation of this conventional architecture is that it is susceptible to process-variation-induced timing errors due to semiconductor manufacturing processes introducing variations in transistor characteristics across a wafer, causing the ring oscillator period to differ from pixel to pixel. That is, because each pixel’s ring oscillator is fabricated independently under non-uniform process conditions across the wafer, each ring oscillator 804 operates at a slightly different frequency from every other pixel’s ring oscillator. Thus, the ring oscillator period TRO is further defined as TRO = Tp+ 8TRO, where Tpis the standard ring oscillator period and 8TRO is the variation of a given ring oscillator from the standard period due to the manufacturing process variation. This per-pixel frequency variation means that the value of STRO is unique to each pixel and cannot be known or corrected in advance without a calibration or compensation mechanism. This manufacturing process variation gives rise to two major problems. The first is local ring oscillator starting time ambiguity (i.e., the phase of the ring oscillator at the moment the START signal arrives is unknown and unpredictable) introduces uncertainty into the fine time measurement Tres. The second is individual ring oscillator intrinsic clock difference error STRO due to each pixel’s ring oscillator running at a slightly different frequency. As a result, the total system accumulation error Ten- grows with the number of counts N according to the relationship Terr = N x 8TRO. That is, the longer the time-of-flight interval and therefore the larger the value of N, the greater the cumulative timing error introduced by ring oscillator frequency variation. Simulated and experimental results show that the variation of inter-pixel period difference can be approximately ±5-10% due to process variation. For a full detection range of one hundred meters, a five-percent period variation results in an accumulated distance error of approximately five meters, which is unacceptable for precision depth sensing. Thus, thisAtty. Docket No. 4502-90500 (6000777PCT01)accumulated error directly degrades depth measurement accuracy.

[0061] One known approach to reducing inter-pixel ring oscillator variation uses a voltage-controlled ring oscillator in each pixel, and then duplicate (or mimic) an identical reference ring oscillator placed outside the pixel array to generate a global bias voltage. Utilizing a Phase-locked Loop (PLL) to sync up the ring loop with the counter clock by tuning the bias voltage. The finalized biasing voltage will be distributed to all in-pixel ring oscillators, partially equalizing their periods. Experimental results indicate that this technique achieves an improvement of approximately 4.27 times, reducing residual timing variation to approximately ±1.17 percent. While this improvement is meaningful, the residual accumulated distance error over a one-hundred-meter range remains on the order of one meter, which is insufficient for many precision applications. Furthermore, this technique addresses only the magnitude of the inter-pixel period variation and does not eliminate the fundamental mechanism of error accumulation.

[0062] Another approach involves post-fabrication per-pixel calibration, in which the TDC of each pixel is individually characterized and a correction table is stored in memory and applied to raw measurement data. Calibration-based correction is, however, complex to implement at array scale, consumes significant memory and computational resources, degrades measurement throughput, and may fail to account for temperature-dependent or time-dependent drift.

[0063] In contrast, the disclosed embodiments present a global-clock-assisted in-pixel TDC architecture for high-precision depth sensing that fundamentally eliminates, rather than merely partially mitigates, the accumulation of process-variation-induced timing error in SPAD-based depth sensing arrays, without requiring complex per-pixel calibration, and that is compatible with compact, high-resolution, two-dimensional solid-state chip integration.

[0064] FIG. 9A and FIG. 9B are diagrams illustrating a comparison between a traditional inpixel TDC architecture and a new global-clock-assisted TDC architecture in accordance with one or more embodiments of the disclosure. In the traditional architecture shown in FIG. 9A, all timing, counting, and recording functions are performed entirely within each pixel. In this example, the traditional architecture includes an RO 902, which is a local clock. The counter 904 counts the total number of cycles completed by the RO 902 between start and stop signals, and outputs the result in N - 3 bits. The RO 902 feeds an 8-bit signal indicating its current position into a decoder (DEC) 906 which produces a 3-bit output representing the residual time within the current incomplete ring oscillator cycle at the moment that the STOP signal is received. The N -Atty. Docket No. 4502-90500 (6000777PCT01)3 bits of the counter 904 and 3 bits of decoder 906 together accumulate and represent the full N-bit time interval AT. As described above, because all N bits of timing information are generated within the pixel by the ring oscillator 902, the total system cumulative error 910 is expressed as N x 8TRO. That is, the per-pixel ring oscillator frequency variation error accumulates across all N bits of the measurement, degrading depth accuracy proportionally with the total bit count.

[0065] FIG. 9B is a diagram illustrating a new global-clock-assisted partitioned TDC architecture in accordance with one or more embodiments of the disclosure that substantially eliminates the accumulation of process-variation-induced timing error in SPAD-based depth sensing arrays, without requiring complex per-pixel calibration. As shown in FIG. 9B, the total N-bit timing representation is partitioned into three distinct functional components: (i) a main global counter 922 of n bits driven by a precise external global clock 924 located outside the pixel array; (ii) a local counter 926 of i bits, located within each pixel; and (iii) a free-running ring oscillator 928 of j bits, also located within each pixel, where the total bit-width satisfies the relationship N = n + i + j. That is, the n mo st- significant bits (MSBs) of the coarse timing measurement is no longer incremented by a pixel’s local counter, but instead by a single precise external global clock 924 shared across all pixels. The local counter 926 and ring oscillator 928 together constitute the pixel data path, responsible for encoding only the lower m = i + j bits of fine timing information. Thus, any process variation between pixels is limited to only the leastsignificant portion of the total measurement. In an embodiment, a DEC 906 produces a 3-bit output representing the residual time within the current incomplete ring oscillator cycle at the moment that the STOP signal for the j bits in the N-bit timing representation. The local counter 926 counts the total number of cycles completed by ring oscillator 928 between start and stop signals, and outputs the result in m - 3 bits for the i (=3 in this case) bits in the N-bit timing representation. A counter 932 outputs a count between the start and the stop signals using n bits based on the external global clock 924, which is used for the main global counter 922 in the total N-bit timing to form the complete N-bit total time-of-flight measurement AT. Because the global counter 922 is precise and not subject to per-pixel ring oscillator process variation, the cumulative timing error is reduced from N x 5TRO to only m x 5TRO, representing an improvement factor of 2n.

[0066] The global clock 924 and the internal pixel clock (e.g., the ring oscillator 928) operate in two independent timing domains, and bridging these two domains accurately ensures the correct operation of the partitioned TDC architecture. If the boundary between the globally counted coarseAtty. Docket No. 4502-90500 (6000777PCT01)time and the locally measured fine time is not precisely established for each individual pixel, the two portions of the output data word will not concatenate correctly, and the resulting time-of-flight measurement will contain an error at the domain boundary that negates the accuracy improvement achieved by the global counter partitioning. For instance, FIG. 10 is a timing diagram illustrating the time-of-flight measurement interval AT and the challenge of aligning the global clock domain with the local pixel ring oscillator. The diagram shows the START event at laser emission and the STOP event at photon detection, separated by the full time-of-flight interval AT. The global clock divides time into counting the number of periods with duration TG, and the STOP event falls at a point within a particular global clock period. The entire time counting cycles through time phases Ai, A2, ... till An, before the STOP signal happened at time point B. The time difference between Anand B defines the fine time resolution. The time-of-flight interval is then expressed as AT = n x TG + Ties, where n is the number of complete global clock periods elapsed between the START event and the STOP event, and Tresis the time elapsed from the beginning of the last complete global clock period prior to the STOP event to the STOP event itself. While the coarse component n x TG is determined by the global clock and is therefore accurate, the residual time Trcsmust be measured locally within the pixel using the ring oscillator. As stated above, a challenge arises from two independent sources of uncertainty. First, the START signal and the global clock must each propagate from their sources at the chip periphery to each individual pixel, and the propagation delay varies with the pixel's physical location within the array, so pixels at different positions receive these signals at different times. Second, the ring oscillator begins oscillation at an arbitrary phase relative to the global clock and this initial phase is unknown and unrepeatable. The consequence is that at any given rising edge of the global clock, the instantaneous phase state of the RO is different in each pixel and cannot be predicted. Both of these uncertainties would corrupt the fine time measurement Tresif not properly addressed, negating the accuracy improvement of the partitioned architecture. To correct this misalignment, a correlated doublesampling reverse data-tracking method is employed as described below.

[0067] FIG. 11 is a timing diagram comparing two candidate methods for measuring the residual time Tres, designated Method A and Method B, and illustrating Method B as an embodiment of the present invention. In Method A, the state of the ring oscillator is sampled at every positive-rising edge of the global clock signal from the START event until the STOP event. The ring oscillator state sample taken at the global clock edge immediately preceding the STOPAtty. Docket No. 4502-90500 (6000777PCT01)event, combined with the ring oscillator state at the STOP event, is used to estimate Tres. However, Method A requires up to n + 1 individual pixel tracking state samples (one for each global clock edge between the START event and the STOP event), which is operationally complex and remains sensitive to the ring oscillator’s starting phase at the START event because the ring oscillator’s phase at any subsequent global clock edge depends on the exact moment the oscillator began oscillating.

[0068] In contrast, rather than measuring Tresdirectly as the time from the most recent global clock edge before the STOP event to the STOP event, Method B measures the time from the STOP signal to the next global clock pulse, obtaining the complementary interval TG - Tres. The actual Tres is then obtained by subtracting this value from TG. This complementary interval TG - Tresis measured using exactly two ring oscillator state samples: one sample captured at the STOP event and one sample captured at the next positive-rising edge of the global clock following the STOP event. Method B significantly reduces the required state sampling time from n + 1 to just 2. This correlated double-sampling tracks the random phase state of the oscillator, making it independent of their status and location.

[0069] FIG. 12 is a timing diagram illustrating the mathematical derivation of the time-of-tlight interval AT using the reverse data-tracking method. The diagram shows the total measurement interval AT partitioned into the coarse component n x TG and the residual Tres, and the complementary interval TG - Tresmeasured by the two-sample reverse tracking method. Beginning with AT = n x TG + Tres, the expression is rewritten by substituting Tres= TG - (TG -Tres), yielding AT = n x TG + TG - (TG - Tres), which simplifies to AT = (n + 1) x TG - (TG - Tres). The first term, (n + 1) x TG, is determined entirely by the global counter value n and the global clock period TG, both of which are precise and free of ring oscillator variation. The second term, (TG - Tres), is the complementary interval measured by the two ring oscillator state samples spanning at most one global clock period. Because the START signal and the most recently tracked positive-rising global clock edge travel through the same signal distribution network to any given pixel, their propagation delays to that pixel are identical, and this common delay cancels exactly when the difference is taken. Furthermore, because neither of the two ring oscillator state samples is captured at the START event, the initial phase of the ring oscillator when the ring oscillator began oscillating is irrelevant to the measurement. The double sampling is therefore independent from the location and propagation delay of the pixel.Atty. Docket No. 4502-90500 (6000777PCT01)

[0070] FIG. 13 is a diagram illustrating an architecture of a pixel TDC IC 1300 in accordance with one or more embodiments of the disclosure. The pixel TDC IC 1300 comprises a RO 1302, a local counter 1304, a Register A 1306. a Register B 1308, an “&” logic unit 1310, a global counter 1312, and a SPAD 1314. When a laser pulse is emitted, a START signal 1318 is generated and distributed to all pixels. The START signal 1318 is configured to reset the global counter 1312 to zero. Each subsequent rising edge of a global clock 1316, which is distributed from a precision time source external to the pixel array and shared across all pixels, increments the global counter 1312 by one. The global counter 1312 has n bits and provides the n most significant bits of the final N-bit output data word. Because the global counter 1312 is driven exclusively by the external global clock 1316, rather than by the local RO 1302, these n most significant bits are entirely free of inter-pixel ring oscillator period variation. The RO 1302 has j bits of phase resolution 2jdistinct phase positions, and provides the finest time resolution of the TDC. In one example embodiment, j equals three and 2jequals eight, providing eight distinct ring oscillator phase positions. The local counter 1304 has i bits and is coupled to the RO 1302. Thelogic unit 1310 is shared among a plurality of pixels and receives the photon detection output of the SPAD 1314. When the SPAD 1314 detects a reflected photon (hv), the “&” logic unit 1310 receives a STOP signal.

[0071] In an embodiment, Register A 1306 and Register B 1308 are I (2j)-bit registers, which also match to the number of ring loop bit positions. Register A 1306 and Register B 1308 are provided to address the time alignment requirement (i.e., RO 1302). As stated above, because the RO 1302 in each pixel begins oscillating at an arbitrary phase relative to the global clock 1316, and because the START signal 1318 and the global clock 1316 each experience a propagation delay to each pixel that varies depending on that pixel’s physical location within the array, the instantaneous phase of the RO 1302 at any given global clock edge is unknown and pixel-position-dependent. This means the residual time Tres(i.e., the time from the beginning of the last global clock period prior to the STOP event to the STOP event itself) cannot be measured reliably by simply reading the RO 1302 state at a single point in time. To address this time misalignment between the global clock and the internal pixel time (i.e., RO 1302), Register A 1306 and Register B 1308 are used together to implement the correlated double-sampling technique described above in FIG. 11 and FIG. 12 using exactly two RO phase state captures, without requiring knowledge of the starting phase of the RO 1302 or the propagation delay to the pixel.

[0072] In an embodiment, upon receiving the STOP signal, two simultaneous actions are takenAtty. Docket No. 4502-90500 (6000777PCT01)within the pixel. First, the current phase state of the RO 1302 is latched (i.e., captured and stored) into Register A 1306. Second, the local counter 1304 is reset to a maximum value based on the number of bits of the local counter (e.g.. maximum value of a 3-bit local counter is 7) and begins counting downward. The local counter 1304 decrements by one upon each complete oscillation cycle of the RO 1302. This downward counting continues until the next first positive-going edge of the global clock 1316 following the STOP signal. At that moment, the current phase state of the RO 1302 is latched into Register B 1308 and the local counter 1304 holds a value equal to its initialized maximum value minus the number of complete RO cycles that elapsed between the STOP signal and that global clock edge. Because the START signal 1318 and the most recently tracked positive-rising edge of the global clock 1316 travel through the same signal distribution network to reach any given pixel, their propagation delays to that pixel are identical and cancel exactly when their difference is computed. Furthermore, because neither Register A 1306 nor Register B 1308 captures the RO 1302 state at the START event, the initial phase of the RO 1302 when it began oscillating has no effect on the measurement. The double sampling tracks the random phase state of the oscillator, making the measurement independent of the status and location of the pixel. The decoded digital difference between the state held in Register A 1306 and the state held in Register B 1308 provides the j least significant bits 1320 of the output data word, encoding the fractional ring oscillator cycle elapsed between the STOP signal and the next global clock edge with a timing resolution of approximately 10 picoseconds, independent of the phase or position of the RO 1302. The final output data word has N = n + i + j bits in total, with the n most significant bits provided by the global counter 1312, the i intermediate bits provided by the local counter 1304, and the j least significant bits decoded from the difference between Register A 1306 and Register B 1308. In one embodiment, n equals 10, i equals 3, and j equals 3, yielding a 16-bit output data word.

[0073] FIG. 14 is a combined waveform and data diagram illustrating the complete operation of a TDC architecture in accordance with one or more embodiments of the disclosure. FIG. 14 includes a global counter, a global clock signal, and a ring oscillator waveform. The global counter begins at zero upon the START event and increments by one on each rising edge of the global clock signal. The ring oscillator waveform runs continuously, cycling through its eight phase positions. When the SPAD detects a reflected photon and the STOP event is asserted. Register A is written with the current state of the ring oscillator. Simultaneously, local counter is initializedAtty. Docket No. 4502-90500 (6000777PCT01)to its maximum value (e.g., 7) and begins decrementing by one after each complete ring oscillator cycle. At the first rising edge of the global clock following the STOP event, Register B is written with the current state of the ring oscillator. As an example, a 16-bit TDC output data word is assembled with the 10-bit global counter value occupying the most significant bit positions, the 3-bit local counter value in the intermediate positions, and the 3-bit decoded digital difference between Register A and Register B occupying the least significant bit positions, yielding the example 16-bits output word. The 10 most significant bits of this output word are determined entirely by the external global clock and cany no accumulated ring oscillator timing error. The 3-bit local counter value encodes the number of complete ring oscillator cycles elapsed between the STOP event and the next global clock edge, and the 3-bit decoded register difference encodes the fractional ring oscillator cycle within that interval. In an embodiment, the timing resolution of the encoded time is approximately 10 picoseconds.

[0074] FIG. 15 is a flowchart illustrating a method 1500 for determining a dToF measurement in accordance with one or more embodiments of the disclosure. In an embodiment, the method 1100 may be implemented by the pixel TDC IC 1300 in FIG. 13. At step 1502, when a laser is emitted, the pixel TDC IC receives a START signal and resets the global counter to 0. At step 1504, the pixel TDC IC waits for one of two events to occur: a rising edge of the global clock signal 1506 or a STOP signal 1510. At step 1508, when a rising edge of the global clock signal occurs, the pixel TDC IC increments the global counter by 1. The global counter continues to get incremented on each rising edge of the global clock signal until a STOP signal is received at step 1510 (i.e., until the SPAD detects the return echo). At step 1512, once the STOP signal is received, the pixel TDC IC writes the current phase state of the RO into a first register (e.g., Register A in FIG. 13) and resets the local counter to its max value such as 7 (e.g., setting all 3-bits to 1 for a 3-bit local counter) for backward counting down.

[0075] At step 1514, the pixel TDC IC waits for one of two events to occur: a rising edge of the global clock signal 1518 or the RO to finish a full oscillation cycle 1516. At step 1520, when the RO completes a cycle, the pixel TDC IC decrements the local counter by 1. The pixel TDC IC continues to decrement the local counter by 1 for each completed RO cycle until a rising edge of the global clock signal is received at step 1518. Once the rising edge of the global clock signal is received, the pixel TDC IC, at step 1522, writes the current phase state of the RO into a second register (e.g., Register B in FIG. 13). At step 1524, pixel TDC IC calculates the decoded digitalAtty. Docket No. 4502-90500 (6000777PCT01)difference between the phase state stored in the first register and the phase state stored in the second register. This decoded difference provides the j least significant bits of the output data word. Since after the STOP signal, the local counter is set to its maximum and counting down, the residue time representation should be exactly the remaining data at the moment when counting is ended. In this process, setting one maximum value represents one TG, the counting down refers to subtraction, and the code difference (including the local counter) from STOP signal to following rising edge of global clock gives TG - Tres. Therefore, mathematically we have Tres=TG - (TG - Tres). Combining MSB in the global counter and the Treswe then obtain the final total digital time recording at TDC output.

[0076] As discussed above with respect to FIG. 10, Register A and Register B together implement a correlated double- sampling technique that resolves the alignment uncertainty between the global clock domain and the local pixel clock domain. Because the RO begins oscillating at an arbitrary and unknown phase relative to the global clock, and because the propagation delay of the global clock to each pixel varies with the pixel's physical location within the array, the fine time residual TrCs cannot be determined from a single RO phase state sample. By capturing two RO phase state samples (one at the STOP event into Register A and one at the next rising edge of the global clock into Register B) method 1500 measures only the complementary interval TG - Tiesbetween these two precisely defined events. The START signal and the most recently tracked rising edge of the global clock travel the same signal distribution path to any given pixel, so their propagation delays are equal and cancel when their difference is computed. The double sampling therefore tracks the random phase state of the oscillator, making the measurement independent of the status and location of the pixel. Thus, method 1500 provides an accurate finest time resolution (~10ps) independent from the phase and position of the RO.

[0077] At step 1526, the pixel TDC IC outputs the complete N-bit data word comprising the global counter value, the local counter value, and the decoded register difference as the n most significant bits, the i intermediate bits, and the j least significant bits, respectively. Therefore, with the proposed new TDC architecture, this processing loop can improve the process variation error by 211times. In one embodiment, n equals 10, i equals 3, and j equals 3, yielding a 16-bit output data word. The method ends at step 1528.

[0078] FIG. 16 is a diagram illustrating an optional clock domain alignment technique in accordance with one or more embodiments of the disclosure. This optional clock domainAtty. Docket No. 4502-90500 (6000777PCT01)alignment technique may further reduce residual inter-pixel ring oscillator period variation beyond the improvement achieved by the global counter partitioning embodiments described above. In this system, a voltage controlled tunable ring oscillator is used in every pixel. In an embodiment, a phase-locked loop 1600 is implemented externally to a pixel array 1608. A dummy ring oscillator 1604, having the same design as the ring oscillators within the pixels of the pixel array 1608, is coupled to the phase-locked loop 1600 and operated outside the pixel array where its frequency can be directly monitored and controlled. The phase-locked loop 1600 locks the full-cycle period of the dummy ring oscillator 1604 to a target period aligned with the least significant bit period of the pixel counter 1610. A common bias voltage Vb 1602, generated by the phase-locked loop 1600, is distributed to the ring oscillators of all pixels in the array to align the local ring and counter clock to the external global clock so that the full cycle of local clock are aligned to the least significant bits (LSB) of the main counter. Because all ring oscillators in the pixel array are biased by the same voltage Vb 1602 derived from the same phase-locked loop 1600, the systematic component of inter-pixel ring oscillator period variation attributable to process non-uniformity is substantially reduced across the array.

[0079] The disclosed embodiments may be extended using a method to align a local ring oscillator and counter in the traditional pixel TDC (as introduced in TCAS-I, VOL. 69, NO. 2, FEBRUARY 2022. doi:10.1109 / TCSI.2020.3048367) to align a pixel ring oscillator timing with the off array global clock. Based on the measured data, the variation error across the array can be reduced to approximately ±1.17%, which is corresponding to an error of 1.17% x 100 m = 1.17 m over a 100-meter detection range, representing a 4.27x improvement relative to the uncompensated ring oscillator case. When combined with the 2n-times improvement proposed by the disclosed embodiments achieved by the global counter partitioning, the overall improvement in timing accuracy relative to the conventional all-local ring oscillator TDC architecture is approximately 2“ x 4.27, which for the preferred embodiment with n = 10 corresponds to approximately 4,370 times. At this level of timing accuracy, the ring oscillator fine-time resolution of approximately 10 picoseconds corresponds to a depth resolution of approximately 1.5 millimeters, enabling millimeter-precision three-dimensional depth sensing across the full pixel array without complicated pixel-by-pixel calibration.

[0080] FIG. 17 is a flowchart illustrating a method 1800 for measuring a time-of-flight interval in a depth sensing system in accordance with one or more embodiments of the disclosure. MethodAtty. Docket No. 4502-90500 (6000777PCT01)1800 corresponds to the partitioned measurement approach of the disclosed global-clock-assisted TDC architecture and may be implemented by the pixel TDC IC 1300 of FIG. 13 or any equivalent embodiment. At step 1802, a coarse time count is generated using a global clock signal that is shared across a plurality of pixels of a sensor array and sourced externally to the sensor array. The coarse time count provides the most significant bits of the time-of-flight interval for all pixels and is free of accumulated timing error attributable to inter-pixel process variation, because the counting is governed by a single, precise external clock rather than by individual, locally fabricated ring oscillators subject to manufacturing variation. At step 1804, an intermediate time count is generated within a pixel of the sensor array using a ring oscillator local to that pixel, based on the number of completed oscillation cycles of the ring oscillator during a measurement interval. The intermediate time count provides bits of the time-of-flight interval that are less significant than the most significant bits generated at step 1802. At step 1806, a fine time residual is generated within the pixel based on at least one phase state of the ring oscillator. The fine time residual provides the least significant bits of the time-of-flight interval, encoding the fractional ring oscillator cycle with two correlated registered time tracking. At step 1808, the time-of-flight interval AT is derived from a combination of the coarse time count, the intermediate time count, and the fine time residual. The method ends at step 1810. Because the most significant bits are determined entirely by the external global clock, accumulated process-variation-induced timing error is confined to only the lower-order bits, achieving a reduction in cumulative timing error of at least 2nrelative to a conventional all-local ring oscillator TDC architecture.

[0081] The present disclosure may be a system, a method, and / or a computer program product at any possible technical detail level of integration. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0082] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasableAtty. Docket No. 4502-90500 (6000777PCT01)programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0083] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0084] Computer readable program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user’ s computer, partly on the user’s computer, as a standalone software package, partly on the user’s computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user’s computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, FPGAs, or programmable logicAtty. Docket No. 4502-90500 (6000777PCT01)arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0085] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0086] These computer readable program instructions may be provided to a processor of a general-purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function / act specified in the flowchart and / or block diagram block or blocks.

[0087] The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0088] The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks mayAtty. Docket No. 4502-90500 (6000777PCT01)occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustration, and combinations of blocks in the block diagrams and / or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

[0089] While several embodiments have been provided in the present disclosure, it may be understood that the disclosed systems and methods might be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the disclosure is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system, or certain features may be omitted or not implemented.

[0090] In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and may be made without departing from the spirit and scope disclosed herein.

Claims

Atty. Docket No. 4502-90500 (6000777PCT01)CLAIMSWhat is claimed is:

1. A method for measuring a time-of-flight interval in a depth sensing system, the method comprising:generating a coarse time count using a global clock signal shared across a plurality of pixels of a sensor array and external to the sensor array, wherein the coarse time count provides a most significant bits of the time-of-flight interval for all of the plurality of pixels and is free of accumulated timing error attributable to inter-pixel process variation;generating an intermediate time count within a pixel of the sensor array using a ring oscillator local to the pixel based on a number of completed cycles of the ring oscillator during a measurement interval, wherein the intermediate time count provides bits of the time-of-flight interval less significant than the most significant bits;generating a fine time residual within the pixel based on at least one phase state of the ring oscillator, wherein the fine time residual provides a least significant bits of the time-of-flight interval; andderiving the time-of-flight interval from a combination of the coarse time count, the intermediate time count, and the fine time residual.

2. The method of claim 1 , further comprising:receiving a start signal upon emission of a laser pulse;incrementing a global counter by one on each rising edge of the global clock signal following the start signal; andgenerating the coarse time count based on the global counter in response to a stop signal.

3. The method according to any of claims 1-2, wherein generating the intermediate time count comprises:setting a local counter to a maximum value in response to the stop signal; decrementing the local counter by one on each completed cycle of the ring oscillator until a next rising edge of the global clock signal following the stop signal is detected: andsetting a value of the local counter when the next rising edge of the global clock signal following the stop signal is detected as the intermediate time count.Atty. Docket No. 4502-90500 (6000777PCT01)4. The method according to any of claims 1-3, wherein generating the fine time residual comprises:storing a first phase state of the ring oscillator captured at the stop signal;storing a second phase state of the ring oscillator captured at a next rising edge of the global clock signal following the stop signal; andgenerating the fine time residual based on a decoded difference between the first phase state and the second phase state through correlated double sampling.

5. The method according to any of claims 1-4, wherein the global counter has n bits, the local counter has i bits, and the fine time residual has j bits of phase resolution, such that the time-of-flight interval is represented as N = n + i + j bits.

6. The method according to any of claims 1-5, wherein an accuracy improvement relative to a time-to-digital converter in which all N bits are derived from a local ring oscillator is at least 2ntimes.

7. The method according to any of claims 1-6, wherein the time-of-flight interval is expressed as AT = (n+1) x TG - (TG - Tres), wherein n is a count value of the global counter at a time of a stop signal is generated upon detection of a reflected photon, TG is a period of the global clock signal, and Tres is the fine time residual.

8. The method according to any of claims 1-7, further comprising:operating a phase-locked loop circuit external to the sensor array;locking, using the phase-locked loop circuit, a cycle period of a dummy ring oscillator external to the sensor array to a target period aligned with a least significant bit period of the global counter driven by the global clock signal shared across all pixels of the sensor array; and distributing a common bias voltage generated by the phase-locked loop circuit to the ring oscillator of each pixel in the sensor array to reduce inter-pixel ring oscillator period variation across the sensor array.

9. The method according to claim 8, wherein the dummy ring oscillator has a same design as the ring oscillator within the pixel.Atty. Docket No. 4502-90500 (6000777PCT01)10. The method of claim 9, wherein a reduction in the inter-pixel ring oscillator period variation combined with a coarse time count accuracy improvement achieved by the global counter yields an overall timing accuracy improvement of at least 2nx 4 relative to a time-to-digital converter in which all bits of a time-of-flight measurement are derived from a local ring oscillator, and wherein n is a bit-width of the global counter.

11. A method for measuring a time-of-flight interval (AT) in a depth sensing system having a sensor array of pixels, the method comprising:receiving a start signal upon emission of a laser pulse;resetting a global counter to zero in response to the start signal;generating a coarse time count using a global clock signal that is distributed to every pixel of the sensor array from a source external to the sensor array by incrementing the global counter by one on each rising edge of the global clock signal, wherein the coarse time count provides the most significant bits (n bits) of the time-of-flight interval (AT) for all pixels and being free of accumulated timing error attributable to inter-pixel process variation;receiving a stop signal generated by a single-photon avalanche diode (SPAD) within a pixel upon detection of a reflected photon;in response to the stop signal:latching a first phase state of a ring oscillator local to the pixel into a first register; setting a local counter within the pixel to a maximum value and beginning reverse counting on each completed cycle of the local ring oscillator; andlatching a second phase state of the local ring oscillator into a second register upon the next rising edge of the global clock signal following the stop signal;generating an intermediate time count from a value of the local counter at a time the second phase state is latched;generating a fine time residual (Tres) from a decoded difference between the first phase state and second phase state; andderiving the time-of-flight interval (AT) by combining the coarse time count, the intermediate time count, and the fine time residual (Tres) according to AT = (n+1) x TG - (TG -Tres), wherein TG is a period of the global clock signal and n is a count value of a global counter at a time of the stop signal.Atty. Docket No. 4502-90500 (6000777PCT01)12. The method of claim 11, wherein the local counter has i bits and the fine time residual provides j bits of phase resolution such that the time-of-flight interval (AT) is represented by a total of N bits, where N = n + i + j bits.

13. The method of any of claims 11-12, wherein the decoded difference cancels propagation delay of the global clock signal and the start signal to the pixel along with any unknown starting phase of the local ring oscillator.

14. The method of any of claims 11-13, further comprising:operating a phase-locked loop circuit external to the sensor array;locking, using the phase-locked loop circuit, a cycle period of a dummy ring oscillator external to the sensor array to a target period aligned with a least significant bit period of the global counter driven by the global clock signal shared across all pixels of the sensor array; and distributing a common bias voltage generated by the phase-locked loop circuit to the ring oscillator of each pixel in the sensor array to reduce inter-pixel ring oscillator period variation across the sensor array.

15. A system for measuring a time-of-flight interval, the system comprising:a global clock circuit external to a sensor array and configured to generate a global clock signal shared across a plurality of pixels of the sensor array;a global counter driven by the global clock signal and configured to generate a coarse time count providing the most significant bits of the time-of-flight interval for all pixels of the sensor array, wherein the coarse time count is free of accumulated timing error attributable to inter-pixel process variation;a ring oscillator local to a pixel of the sensor array and configured to support generation of an intermediate time count providing bits of the time-of-flight interval less significant than the most significant bits based on a number of completed cycles of the ring oscillator during a measurement interval; andprocessing circuitry within the pixel configured to generate a fine time residual based on at least one phase state of the ring oscillator, wherein the fine time residual providing the least significant bits of the time-of-flight interval, and to derive the time-of-flight interval from a combination of the coarse time count, the intermediate time count, and the fine time residual.Atty. Docket No. 4502-90500 (6000777PCT01)16. The system of claim 15, further comprising:a laser source configured to emit a laser pulse and to generate a start signal upon emission of the laser pulse;wherein the global counter is further configured to reset to zero in response to the start signal and to increment by one on each rising edge of the global clock signal following the start signal; andwherein the processing circuitry is further configured to generate the coarse time count from a value of the global counter in response to a stop signal.

17. The system according to any of claims 15-16, wherein the pixel comprises a local counter configured to;be set to a maximum value in response to the stop signal;decrement by one on each completed cycle of the ring oscillator until a next rising edge of the global clock signal following the stop signal is detected; andprovide a value at the time the next rising edge is detected as the intermediate time count.

18. The system according to any of claims 15-17, wherein the pixel further comprises a first register and a second register, and wherein the processing circuitry is further configured to generate the fine time residual by:storing a first phase state of the ring oscillator captured at the stop signal into the first register;storing a second phase state of the ring oscillator captured at a next rising edge of the global clock signal following the stop signal into a second register; andgenerating the fine time residual based on a decoded difference between the first phase state and the second phase state.

19. The system according to any of claims 15-18, wherein the global counter has n bits, the local counter has i bits, and the fine time residual has j bits of phase resolution, such that the time-of-flight interval is represented as N = n + i + j bits.

20. The system according to any of claims 15-19, wherein an accuracy improvement relative to a time-to-digital converter in which all N bits are derived from a local ring oscillator is at least 2Utimes.Atty. Docket No. 4502-90500 (6000777PCT01)21. The system according to any of claims 15-20, wherein the processing circuitry is further configured to derive the time-of-flight interval expressed as AT = (n+1) x TG - (TG - Tres), wherein n is a count value of the global counter at a time of the stop signal, TG is a period of the global clock signal, and Tresis the fine time residual.

22. The system according to any of claims 15-21, further comprising:a phase-locked loop circuit external to the sensor array;a dummy ring oscillator external to the sensor array, coupled to the phase-locked loop circuit such that the phase-locked loop circuit locks a cycle period of the dummy ring oscillator to a target period aligned with a least significant bit period of the global counter; anda bias distribution network configured to distribute a common bias voltage generated by the phase-locked loop circuit to the ring oscillator of each pixel in the sensor array to reduce interpixel ring oscillator period variation across the sensor array.

23. The system of claim 22, wherein the dummy ring oscillator has a same design as the ring oscillator within the pixel.

24. The system of claim 23, wherein a reduction in the inter-pixel ring oscillator period variation combined with a coarse time count accuracy improvement achieved by the global counter yields an overall timing accuracy improvement of at least 2nx 4 relative to a time-to-digital converter in which all bits of the time-of-flight interval are derived from a local ring oscillator, and wherein n is a bit- width of the global counter.

25. A time-to-digital converter integrated circuit of a pixel in a sensor array for measuring a time-of-flight interval (AT), the time-to-digital converter integrated circuit comprising:a global counter driven by a global clock signal distributed to every pixel of the sensor array from a source external to the sensor array, the global counter configured to reset to zero in response to a start signal generated upon emission of a laser pulse and to increment by one on each rising edge of the global clock signal, wherein the global counter generates a coarse time count providing the most significant bits (n bits) of the time-of-flight interval (AT) for all pixels and being free of accumulated timing error attributable to inter-pixel process variation;a single-photon avalanche diode (SPAD) within the pixel configured to generate a stop signal upon detection of a reflected photon;Atty. Docket No. 4502-90500 (6000777PCT01)a ring oscillator local to the pixel;a first register configured to latch a first phase state of the ring oscillator at the time of the stop signal;a local counter within the pixel configured to be set to a maximum value in response to the stop signal and to decrement by one on each completed cycle of the ring oscillator;a second register configured to latch a second phase state of the ring oscillator upon a next rising edge of the global clock signal following the stop signal; andprocessing circuitry configured to generate an intermediate time count from a value of the local counter at the time the second phase state is latched, generate a fine time residual (Tres) from a decoded difference between the first phase state and the second phase state, and derive the time-of-flight interval (AT) according to AT = (n+1) x TG - (TG - Tres), wherein TG is a period of the global clock signal and n is a count value of the global counter at a time of the stop signal.

26. The time-to-digital converter integrated circuit of claim 25, wherein the local counter has i bits and the fine time residual provides j bits of phase resolution such that the time-of-flight interval (AT) is represented by a total of N bits, where N = n + i + j bits.

27. The time-to-digital converter integrated circuit of any of claims 25-26, wherein the decoded difference cancels propagation delay of the global clock signal and the start signal to the pixel along with any unknown starting phase of the ring oscillator.

28. An apparatus, comprising:one or more processors or processing means; anda memory or storage means storing instructions that, when executed by the one or more processors or processing means, cause the apparatus to perform any one of the methods in claims 1-14.

29. A computer program product comprising computer-executable instructions stored on a non-transitory computer-readable storage medium and that, when executed by one or more processors or processing means of an apparatus, cause the apparatus to perform any one of the methods in claims 1-14.

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