A broadband out-of-phase power amplifier transmission system based on FPGA

Abstract

The invention discloses a broadband out-of-phase power amplifier transmitting system based on FPGA, which comprises an FPGA out-of-phase signal generating part and an out-of-phase class E power amplifying part; wherein the FPGA out-of-phase signal generating part comprises an out-of-phase decomposition module, a linear digital interpolation phase modulation module, a single-bit quantizer and a high-speed parallel-to-serial converter; the out-of-phase class E power amplifying part is designed by integrating the class E power amplifier and the out-of-phase power superposition part. The technical implementation of the invention makes the radio frequency front end digital and integrated, the transmitting frequency is flexible and controllable, the realization difficulty of the transmitter is reduced, and the transmitting efficiency of a high peak-to-average ratio signal is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communications, and in particular to a broadband out-of-phase power amplifier transmission system based on FPGA. Background Art

[0002] Traditional digital out-of-phase transmission systems use the sampling and holding method for phase modulation, which requires a very high sampling rate while ensuring linearity for broadband signals, and even higher requirements for hardware. Therefore, how to modulate and reduce the sampling rate requirement has become a research hotspot for improving transmitter efficiency and linearization technology. At the same time, traditional out-of-phase amplification systems use class B power amplifiers and Chreix power synthesizers. The theoretical maximum efficiency of class B power amplifiers is 75%, which is relatively low compared with switch-type power amplifiers; and the Chreix power synthesizer only has a compensation effect at a single frequency point, and its implementation method is complex, which can no longer meet the needs of modern communications with a certain bandwidth. Therefore, it is urgent to develop a broadband out-of-phase power amplifier transmission system with a new digital modulation method to meet the needs of modern communication systems for digitization and integration, and improve the efficiency, power and linearity of the system. Summary of the invention

[0003] In order to overcome the defects and shortcomings of the prior art, the present invention provides a broadband out-of-phase power amplifier transmission system based on FPGA to meet the demand for digital broadband multi-frequency multi-mode transmission system in current wireless communications.

[0004] The present invention adopts the following technical solution:

[0005] A broadband out-of-phase power amplifier transmission system based on FPGA, comprising an FPGA out-of-phase signal generation part and an out-of-phase Class E power amplifier part;

[0006] The FPGA out-of-phase signal generation part includes an out-of-phase decomposition module, a linear digital interpolation phase modulation module, a single-bit quantizer and a high-speed parallel-to-serial converter connected in sequence;

[0007] The out-of-phase class E power amplification part includes an out-of-phase class E power amplifier, the baseband signal is input into an out-of-phase decomposition module, the output signal of the high-speed parallel-to-serial converter is connected to the input end of the out-of-phase class E power amplifier, and the out-of-phase class E power amplifier outputs a radio frequency transmission signal.

[0008] The out-of-phase decomposition module includes an amplitude-to-phase separator, an out-of-phase angle converter, a register, an adder and a subtractor. The output end of the amplitude-to-phase separator is respectively connected to the input end of the out-of-phase angle converter and the input end of the register. The output end of the out-of-phase angle converter and the output end of the register are connected to the input end of the adder. The output end of the register and the output end of the out-of-phase angle converter are connected to the input end of the subtractor. The output end of the adder and the output end of the subtractor are respectively connected to the linear digital interpolation phase modulation module:

[0009] An amplitude-phase separator is used to calculate the normalized baseband signal to obtain an amplitude signal and a phase angle signal;

[0010] An out-of-phase angle converter converts the amplitude signal into a corresponding out-of-phase angle after normalization processing;

[0011] A register for storing a phase angle signal generated by the amplitude-phase separator;

[0012] an adder for adding the phase angle and the out-of-phase angle;

[0013] A subtractor for subtracting the phase angle from the out-of-phase angle.

[0014] The out-of-phase class E power amplifier includes two broadband input matching circuits, two class E amplifiers, an out-of-phase power superposition network and an impedance conversion circuit. The two broadband input matching circuits are respectively connected to the two class E amplifiers, the two class E amplifiers are respectively connected to one end of the out-of-phase power superposition network, and the other end of the out-of-phase power superposition network is connected to the impedance conversion circuit.

[0015] The out-of-phase power superposition network is a three-port network.

[0016] The three-port network is obtained by arbitrarily cascading two two-port networks.

[0017] The two-port network is implemented by a T-type network or a Π-type network.

[0018] The microstrip distribution parameters in the T-type network and the Π-type network are calculated based on the optimal load impedance and the back-off load impedance.

[0019] The linear digital interpolation phase modulation module specifically calculates the phase angles of two out-of-phase signals after digital frequency conversion, performs linear digital interpolation on the phase angle of each modulated out-of-phase signal, linearly inserts N-1 phase points between two phase sampling points, and performs parallel amplitude calculation on the N phase points.

[0020] Beneficial effects of the present invention:

[0021] Compared with the traditional analog transmitter, the present invention reduces the difficulty of realizing the transmitter and is easy to promote;

[0022] The present invention introduces linear digital interpolation phase modulation to improve the linearity of the signal;

[0023] The present invention introduces an out-of-phase power superposition network to improve the transmission efficiency of high peak-to-average ratio signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the structure of the present invention;

[0025] Figure 2 yes Figure 1 Schematic diagram of the specific implementation structure;

[0026] Figure 3 It is a schematic diagram of the structure of the out-of-phase class E power amplifier of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below in conjunction with embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0028] Example

[0029] like Figure 1 As shown, a broadband out-of-phase power amplifier transmission system based on FPGA includes an FPGA out-of-phase signal generating part 10 and an out-of-phase Class E power amplifying part.

[0030] The FPGA out-of-phase signal generation part is implemented by using Verilog language programming on the XCVU095 chip of Xilinx, and includes an out-of-phase decomposition module 11, a linear digital interpolation phase modulation module 12, a single-bit quantizer 13 and a high-speed parallel-to-serial converter 14 connected in sequence;

[0031] A heterogeneous phase decomposition module is used to perform heterogeneous phase separation on the normalized vector discrete signal and generate two discrete heterogeneous phase signals;

[0032] A linear digital interpolation phase modulation module, used for linearly interpolating the discrete out-of-phase phase signals, and performing parallel phase modulation on the phase signals obtained after the linear interpolation;

[0033] A single-bit quantizer, used for quantizing the signal after the linear digital interpolation parallel phase modulation, and outputting a parallel digital modulation signal;

[0034] High-speed parallel-to-serial converters are used to convert parallel signals into serial signals and realize signal conversion from digital domain to analog domain.

[0035] Further, such as Figure 2 As shown, the heterogeneous decomposition module includes:

[0036] The out-of-phase decomposition module includes an amplitude-to-phase separator, an out-of-phase angle converter, a register, an adder and a subtractor. The output end of the amplitude-to-phase separator is respectively connected to the input end of the out-of-phase angle converter and the input end of the register. The output end of the out-of-phase angle converter and the output end of the register are connected to the input end of the adder. The output end of the register and the output end of the out-of-phase angle converter are connected to the input end of the subtractor. The output end of the adder and the output end of the subtractor are respectively connected to the linear digital interpolation phase modulation module:

[0037] Amplitude-phase separator 111: calculates the normalized baseband signal to obtain an amplitude signal and a phase angle signal;

[0038] The out-of-phase angle converter 112 converts the amplitude signal into a corresponding out-of-phase angle after normalization processing;

[0039] Register 113: used to store the phase angle signal generated by the amplitude-phase separator;

[0040] Adder 114: used for adding the phase angle and the out-of-phase angle, and outputting the phase angle of one of the two out-of-phase signals;

[0041] Subtractor 115 is used for subtracting the phase angle from the out-of-phase angle, and outputting the phase angle of the other signal of the two out-of-phase signals.

[0042] Furthermore, the linear digital interpolation phase modulation module 121 specifically calculates the phase angles of the two out-of-phase signals after digital frequency conversion, performs linear digital interpolation on the phase angle of each modulated out-of-phase signal, linearly inserts N-1 phase points between two phase sampling points, and performs parallel amplitude calculation on the N phase points.

[0043] Furthermore, the single-bit quantizer is specifically an N-channel single-bit quantizer 131, which quantizes the multi-bit out-of-phase signal into a single-bit signal, uses the sign bit of the multi-bit signal as a decision threshold for quantization, and outputs a single-bit digital modulation signal.

[0044] The high-speed parallel-to-serial converter 141 is specifically implemented using the seders module on the FPGA, converting multiple parallel digital modulation signals into serial digital modulation signals, and converting from the digital domain to the analog domain, outputting two constant envelope out-of-phase signals. The transmission bit rate of the high-speed parallel-to-serial converter is N times the sampling rate.

[0045] like Figure 2 As shown, the amplitude-phase separator uses a Cartesian coordinate system to polar coordinate system conversion algorithm to output the amplitude a of the baseband signal n and Phase Prior to this, the input baseband signal is normalized. The amplitude information is converted into the angle between the out-of-phase signal and the original signal through the out-of-phase angle converter. The out-of-phase angle conversion is implemented in the FPGA using a lookup table method. The lookup table establishes the relationship as the out-of-phase angle Where A is the maximum normalized amplitude. When obtaining the out-of-phase angle through the lookup table, a delay will occur, and the out-of-phase register is required to ensure the out-of-phase angle θ n and The delay is consistent. n and At the same time, the phases of the two out-of-phase signals are obtained through the adder and subtractor and

[0046] Linear digital interpolation phase modulation, which is used for the input signal Perform linear digital interpolation and phase modulation, and output 32 parallel interpolation modulation signals. The linear digital interpolation relationship satisfies equations (1), (2), and (3):

[0047]

[0048] Δσ n =σ n -σ n-1 (2)

[0049]

[0050] where f c is the carrier frequency, F s is the sampling frequency.

[0051] The phase modulated output signal satisfies equation (4):

[0052] S n,k = cos(σ n,k ),k=0,...,31 (4)

[0053] When k takes a value from 0 to 31, it corresponds to 32 parallel output signals.

[0054] The out-of-phase signals output by digital interpolation phase modulation are converted into single-bit signals through 32 single-bit quantizers. The single-bit quantizer is implemented in FPGA by setting the sign bit of the multi-bit out-of-phase signal as the decision threshold.

[0055] The high-speed serial-to-parallel converter converts the above 32 parallel single-bit signals into a single single-bit signal, and realizes the conversion of the out-of-phase signal from the digital domain to the analog domain. Among them, the bit rate of the high-speed serial-to-parallel converter is set to 32*Fs in the FPGA implementation, and the sampling rate is increased by 32 times.

[0056] Similarly, for another input signal The principles of linear digital interpolation phase modulation, quantization, and serial-to-parallel conversion are consistent with the above process and will not be repeated here.

[0057] like Figure 3 As shown, the out-of-phase class E power amplification part includes an out-of-phase class E power amplifier 20, specifically including two broadband input matching circuits 201, 202, two class E amplifiers 203, 204, an out-of-phase power superposition network 205 and an impedance transformation circuit 206, the two broadband input matching circuits are respectively connected to the two class E amplifiers, the two class E amplifiers are respectively connected to one end of the out-of-phase power superposition network, and the other end of the out-of-phase power superposition network is connected to the impedance transformation circuit.

[0058] The out-of-phase power superposition network is a three-port network, which is a lossless three-port network obtained by arbitrarily cascading two two-port networks to achieve out-of-phase power superposition, wherein two ports are connected to two Class E power amplifiers, and the third port is connected to the load, and the ABCD matrix of the three-port network is the same as the ABCD matrix of any cascade of two T-type networks and a Π-type network.

[0059] The present invention adopts an out-of-phase power superposition network to superimpose the power of two out-of-phase signals and simultaneously compensates the phases of the two channels to achieve a high-power fallback effect and improve the amplification efficiency of high peak-to-average ratio signals.

[0060] The microstrip distribution parameters of the combination of the T-type network and the Π-type network are calculated based on the optimal load impedance of the power amplifier peak power and the optimal load impedance of the back-off.

[0061] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A broadband out-of-phase power amplifier transmission system based on FPGA, characterized in that: It includes FPGA out-of-phase signal generation part and out-of-phase Class E power amplifier part; The FPGA out-of-phase signal generation part includes an out-of-phase decomposition module, a linear digital interpolation phase modulation module, a single-bit quantizer and a high-speed parallel-to-serial converter connected in sequence; The out-of-phase class E power amplification part includes an out-of-phase class E power amplifier, a baseband signal is input into an out-of-phase decomposition module, an output signal of the high-speed parallel-to-serial converter is connected to an input end of the out-of-phase class E power amplifier, and the out-of-phase class E power amplifier outputs a radio frequency transmission signal; The out-of-phase decomposition module includes an amplitude-to-phase separator, an out-of-phase angle converter, a register, an adder and a subtractor. The output end of the amplitude-to-phase separator is respectively connected to the input end of the out-of-phase angle converter and the input end of the register. The output end of the out-of-phase angle converter and the output end of the register are connected to the input end of the adder. The output end of the register and the output end of the out-of-phase angle converter are connected to the input end of the subtractor. The output end of the adder and the output end of the subtractor are respectively connected to the linear digital interpolation phase modulation module: An amplitude-phase separator, used for calculating the normalized baseband signal to obtain an amplitude signal and a phase angle signal; An out-of-phase angle converter, used to convert the amplitude signal into a corresponding out-of-phase angle after normalization processing; A register, used for storing a phase angle signal generated by the amplitude-phase separator; An adder for adding the phase angle and the out-of-phase angle; A subtractor, used for subtracting the phase angle from the out-of-phase angle; The out-of-phase class E power amplifier includes two broadband input matching circuits, two class E amplifiers, an out-of-phase power superposition network and an impedance conversion circuit. The two broadband input matching circuits are respectively connected to the two class E amplifiers, the two class E amplifiers are respectively connected to one end of the out-of-phase power superposition network, and the other end of the out-of-phase power superposition network is connected to the impedance conversion circuit.

2. The broadband out-of-phase power amplifier transmission system according to claim 1, characterized in that: The out-of-phase power superposition network is a three-port network.

3. The broadband out-of-phase power amplifier transmission system according to claim 2, characterized in that: The three-port network is obtained by arbitrarily cascading two two-port networks.

4. The broadband out-of-phase power amplifier transmission system according to claim 3, characterized in that: The two-port network is implemented by a T-type network or a Π-type network.

5. The broadband out-of-phase power amplifier transmission system according to claim 4, characterized in that: The microstrip distribution parameters in the T-type network and the Π-type network are calculated based on the optimal load impedance for peak power of the power amplifier and the optimal load impedance for back-off.

6. The broadband out-of-phase power amplifier transmission system according to claim 1, characterized in that: The linear digital interpolation phase modulation module specifically calculates the phase angles of two out-of-phase signals after digital frequency conversion, performs linear digital interpolation on the phase angle of each modulated out-of-phase signal, linearly inserts N-1 phase points between two phase sampling points, and performs parallel amplitude calculation on the N phase points.

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