A method and system for high-speed serial bus data synchronization

Abstract

The present invention provides a method for data synchronization of a high-speed serial bus, comprising: building a RapidIO high-speed communication protocol bus based on an FPGA chip; sending data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascade devices through a switch; the multiple cascade devices execute the synchronization control instructions to achieve clock synchronization; the multi-level device synchronization in the system adopts a parameter-controlled delay method to achieve synchronization of all terminals inside the device, with a smaller synchronization error, achieving system synchronization of high-speed serial bus communication, and the synchronization control instructions have a higher priority and can be inserted into a data frame in real time, thereby improving the real-time performance of the synchronization signal. By changing the external hardware synchronization to the internal software data bus protocol type synchronization, the external synchronization interface of each terminal inside each device in the system is reduced, and the device volume and hardware cost are reduced.

Description

Technical Field

[0001] The invention belongs to the field of digital communication and relates to a method and system for high-speed serial bus data synchronization. Background Art

[0002] The power control and protection system plays an important role in the power system, which is related to the safety and monitoring of the entire system. The control and protection system includes multiple terminal devices, each of which performs its own tasks in each control and protection cycle. Data collection and algorithm execution require strict synchronization control. In power electronic equipment, synchronization stability is also a hard requirement of the system, so a reliable and real-time synchronization mechanism is particularly important. The control and protection system tends to shorten the control cycle and the control strategy is becoming more and more refined, so the control and protection platform is also constantly improving the communication rate. The existing optical fiber synchronization mechanism will not only occupy the physical channel of the system, but also easily cause the optical fiber to break and cause the synchronization signal to be lost. In the future, there will no longer be enough physical space inside the local control and protection miniaturization platform to realize the network of external synchronization signals of each terminal. Summary of the invention

[0003] In view of the fact that the existing optical fiber synchronization mechanism not only occupies the physical channels of the system, but also easily causes the optical fiber to break and cause the synchronization signal to be lost, and the future local control and protection miniaturized platform no longer has enough physical space inside to realize the external synchronization signal network of each terminal, the present invention provides a method for high-speed serial bus data synchronization, and the specific steps are as follows:

[0004] Build RapidIO high-speed communication protocol bus based on FPGA chip;

[0005] Send the data packets and synchronous control instructions of the RapidIO high-speed communication protocol bus to multiple cascaded devices through the switch;

[0006] The multiple cascade devices execute synchronization control instructions to achieve clock synchronization.

[0007] Preferably, the plurality of cascaded devices execute synchronization control instructions to achieve clock synchronization, including:

[0008] After receiving the synchronization control instruction, each level of equipment first sends the synchronization control instruction to the lower level equipment, and then performs synchronization within the equipment at this level.

[0009] Preferably, the synchronization within the device at this level includes:

[0010] According to the specific number of devices, after receiving the synchronization control instruction, each level of equipment will delay it in different levels and then broadcast it to each terminal inside the device to ensure the internal data of each device in the entire system is synchronized.

[0011] Preferably, the delay is determined by the transmission time of the synchronization control instruction and the internal processing time of the switch.

[0012] Preferably, the method of sending the data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascade devices through a switch includes:

[0013] Send the data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascaded devices through the switch in order of priority;

[0014] The priorities from high to low are:

[0015] Data sent during idle time of the RapidIO high-speed communication protocol bus data packet channel or inserted into data being sent in the channel;

[0016] The data packet of the RapidIO high-speed communication protocol bus;

[0017] Non-timed data that is not controlled by the synchronization control instructions.

[0018] Preferably, the data transmission of the RapidIO high-speed communication protocol bus includes: a logical transmission layer, a serial protocol layer, a PCS layer, a PMA layer and an electrical layer;

[0019] The logical transport layer transmits the character stream in the data packet to the serial protocol layer between the RapidIO high-speed communication protocol bus, the switch and the cascade device;

[0020] The serial protocol layer realizes the real-time transmission of the synchronization control instruction based on the character stream in the data packet transmitted by the logical transport layer;

[0021] The PCS layer segments the RapidIO high-speed communication protocol bus data packet channel, generates idle time and executes the character stream in the data packet;

[0022] The PMA layer correctly aligns each of the channels and connects with the electrical layer;

[0023] The electrical layer establishes electrical connections for the plurality of cascaded devices.

[0024] Preferably, the synchronization control instructions include: synchronization control instructions in data packets of a RapidIO high-speed communication protocol bus and synchronization control instructions converted from synchronization signals transmitted by an external device.

[0025] Preferably, the synchronization control instructions include: long-format synchronization control instructions and short-format synchronization control instructions;

[0026] The long-format synchronization control instruction transmits the state information in the process of transmitting the synchronization control instruction, the delimiter of the transmission data packet and the synchronization control instruction requested by the multi-stage device receiving port, and provides extended functions and enhances the error detection capability of burst errors;

[0027] The short-format synchronization control instruction transmits the state information in the process of transmitting the synchronization control instruction, the delimiter of the transmission data packet and the synchronization control instruction requested by the multi-stage device receiving port;

[0028] When the serial link for transmitting data is higher than 5.5 Gbps, the long format synchronization control instruction is used; when the serial link for transmitting data is lower than 5.5 Gbps, the short format synchronization control instruction is used;

[0029] The synchronous control instruction without the delimiter is allowed to be embedded in the data packet of the RapidIO high-speed communication protocol bus.

[0030] Preferably, when the serial link is the RapidIO high-speed communication protocol bus, the data transmission rate of the RapidIO high-speed communication protocol bus is lower than 5.5 Gbps using the short format synchronization control instruction.

[0031] Based on the same concept, the present invention provides a high-speed serial bus data synchronization system, comprising: an FPGA, a switch and a plurality of cascade devices;

[0032] The FPGA is used to build a RapidIO high-speed communication protocol bus;

[0033] The switch is used to send data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascade devices through the switch;

[0034] The multiple cascade devices are used to execute synchronization control instructions to achieve clock synchronization.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. The present invention provides a method for synchronizing high-speed serial bus data, comprising: building a RapidIO high-speed communication protocol bus based on an FPGA chip; sending data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascade devices through a switch; the multiple cascade devices execute the synchronization control instructions to achieve clock synchronization; using multi-level device synchronization to achieve synchronization of all terminals inside the device, with smaller synchronization error;

[0037] 2. The present invention provides a high-speed serial bus data synchronization system, which uses a parameter-controlled delay method to achieve system synchronization of high-speed serial bus communication;

[0038] 3. The present invention provides a method and system for high-speed serial bus data synchronization. The synchronization control instruction has a higher priority and can be inserted into the data frame in real time, thereby improving the real-time performance of the synchronization signal. The external hardware synchronization is changed to the internal software data bus protocol type synchronization, thereby reducing the external synchronization interface of each terminal in each device in the system, and reducing the device size and hardware cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a flow chart of the method of the present invention;

[0040] Figure 2 A RapidIO endpoint structure diagram provided for an embodiment of the present invention;

[0041] Figure 3 A system synchronization block diagram provided by an embodiment of the present invention;

[0042] Figure 4 Provide more data transmission sequence diagrams on 1x serial links for embodiments of the present invention;

[0043] Figure 5 is a system structure diagram of the present invention;

[0044] Figure 6 Format diagram of short form Control symbol;

[0045] Figure 7 Format diagram of the multicast event Control symbol. DETAILED DESCRIPTION

[0046] The embodiments of the present invention are further described below in conjunction with the accompanying drawings.

[0047] Embodiment 1:

[0048] The invention is a method based on a high-speed serial bus communication platform, in which a switch is used to synchronize all terminals in the system. Figure 1 The method flow chart is introduced, and the specific steps are as follows:

[0049] Step 1: Build RapidIO high-speed communication protocol bus based on FPGA chip;

[0050] Step 2: Send the data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascade devices through the switch;

[0051] Step 3: The multiple cascaded devices execute synchronization control instructions to achieve clock synchronization;

[0052] Among them, step 1: build RapidIO high-speed communication protocol bus based on FPGA chip:

[0053] This method needs to be applied on the basis of a high-speed serial bus communication platform built by FPGA using the RapidIO protocol. The switch inserts synchronization control instructions into the data packet or communication idle time on the data communication bus in real time to achieve clock synchronization of each unit within the system.

[0054] Step 2: Send the data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascaded devices through the switch:

[0055] The synchronous control instruction is implemented through the Control symbol (synchronous control instruction) multicast event in the RapidIO protocol. The data communication packet adopts the NWRTE format, in which data communication is only implemented in the logic and transport layers in the RapidIO endpoint structure. The specific transmission rate and number of communication ports can be configured by the development engineer according to the project requirements.

[0056] The high-speed communication bus also includes data frames executed in the synchronization cycle. They are sent and received according to the synchronization control instructions in each cycle. This type of data frame belongs to the second priority data. Under normal circumstances, the data frame is transmitted after each synchronization control instruction is received. The third type of data is non-real-time data. This data packet is not controlled by the synchronization control instruction. It may require external commands or fixed cycle control to send and receive. The size of the data packet may also be very large. This type of data has the lowest priority. The use of synchronization control instructions is to prevent this type of data from occupying the bus channel and being unable to synchronize the system in real time. Therefore, the use of synchronization control instructions can interrupt the transmission of non-real-time data at any time to synchronize the system clock.

[0057] Serial RapidIO packets are delimited by Control symbols when they are sent. Since the packet length is variable, both the start and end of the packet delimiters are required. The Control symbol that marks the end of the packet follows the end of the packet or is embedded behind the Control symbol. For data packets, Control symbol instructions belong to the lower-level instructions used to indicate the status of the data packet. Synchronous control instructions are sent by embedding synchronization information into data packets or channel idle time through Control symbols. The specific implementation method is explained by taking the data stream on a 1x Serial RapidIO link as an example.

[0058] The 1x Serial RapidIO port encodes the demarcation control symbols (instructions in the serial protocol layer, indicating the communication status, which can carry other information and can also be inserted into data packets, equivalent to interrupt instructions in communication, so using it to carry synchronization signals can transmit synchronization signals in real time) and the character stream of the data packet through the 8B / 10B encoder. When there are no synchronization control instructions and data packets, the idle sequence will be sent to the 8B / 10B encoder for encoding and sending to ensure that the entire transceiver link is in a synchronous state. Appendix Figure 4 An example of transmitting synchronous control commands, packets, and idle sequences on a 1x serial link is shown, where / SC / indicates the start of a control symbol, / PD / indicates a packet delimiter control symbol, and / I / indicates an idle sequence.

[0059] 1) The first byte sent indicates the start of the Control symbol / SC / , followed by three data bytes containing 24-bit Control symbol information. The function of the Control symbol is not displayed, but it may be information such as link status.

[0060] 2) The Control symbol is followed by four bytes of idle characters.

[0061] 3) The idle character is followed by a / PD / byte that delimits the packet. The Control symbol information contained in the following three bytes represents the packet delimiter symbol information. The Control symbol indicates that a RapidIO data packet follows the Control symbol and the packet length is 16 bytes.

[0062] 4) When the data is sent to the fourth byte, a synchronization control instruction is received, and after the fourth byte is sent, the synchronization control instruction is inserted into the data packet.

[0063] 5) After the synchronous control instruction is sent, continue to send the data packet that was not sent until 16 bytes are sent.

[0064] 6) After the data is sent, there is a / PD / byte that delimits the packet, and the following three bytes contain the Control symbol information to indicate the end of the packet.

[0065] 1)Followed by four bytes of idle characters.

[0066] 2) After the idle character is sent, a synchronous control instruction is inserted.

[0067] Step 3: The multiple cascaded devices execute synchronization control instructions to achieve clock synchronization:

[0068] Data communication between all terminals inside the module must pass through the switch, and the synchronous control instruction initiator is also initiated by the switch. The functions of each terminal include data collection and aggregation, control strategy algorithm implementation, control instruction sending, data recording, etc. The functions of the switch include receiving external synchronization signals, issuing synchronous control instructions, switch parameter configuration, and building data interaction channels for each terminal.

[0069] The key function that the switch needs to achieve is to build a multicast module to implement the sending of synchronization control instructions inside the module. The synchronization control instruction has the highest priority in the high-speed serial bus inside the module, and the synchronization control instruction can be inserted into the data packet during the data transmission process. After the synchronization control instruction is sent, the data packet continues to be sent. The synchronization control instruction inserted into the data packet needs to wait for the current data being sent to be completed. The synchronization control instruction sent inside the switch is the data length after 8B / 10B encoding, and the maximum delay is 10bit of data transmission time. The specific delay time is related to the transmission rate of the high-speed serial bus. In 1x mode, the minimum SRIO transmission rate is 1.25G, so the maximum delay is 8ns. The delay time must be within the synchronization error range allowed by the system. The delay time can be shortened by using 2x or 4x mode, which can also increase the transmission rate.

[0070] See Appendix for system framework Figure 3 As shown, there can be multiple chassis or modules (cascaded devices) in the system, among which there is a master module connected to the external synchronization signal of the system, the slave modules are hierarchically connected to the synchronization expansion interface of the master module, the first-level slave modules are connected to the synchronization expansion interface of the master module, the second-level slave modules are connected to the first-level slave module synchronization expansion interface, and so on. The specific number of modules depends on the specific project requirements.

[0071] Since the module synchronization is performed in a module cascade mode, each module at each level must first send the synchronization control instruction to the lower module after receiving the external synchronization control instruction, and then perform internal synchronization of the module. The reception time of the synchronization control instruction of each module is inconsistent. The higher the level of the module, the later the synchronization signal is received. Therefore, according to the specific number of modules, each module at each level will delay the synchronization control instruction after receiving it, and then multicast it to each terminal inside the module to ensure the internal data synchronization of each module in the entire system. The hierarchical delay is configured according to the number of modules through the parameter configuration port. The delay time of each level is the transmission time of the synchronization control instruction and the internal processing time of the switch. The specific time depends on the communication rate of the high-speed serial communication interface and the FPGA system clock inside the switch.

[0072] Embodiment 2:

[0073] The synchronization method is based on the Control symbol instruction in the RapidIO protocol, combined with Figure 2 The RapidIO endpoint structure diagram is introduced to achieve real-time insertion of synchronization signals during data transmission, and the command is sent to all lower-level terminal devices (various cascade devices connected to the switch, namely functional modules) through the switch. Functional modules include control or acquisition processing or communication modules.

[0074] This synchronization method is called synchronization control instruction in this paper. The switch receives the external synchronization signal through the external interface, and sends the synchronization control instruction to each terminal in the system through the multicast mode. All the control and data acquisition processing modules in the system start to execute through the synchronization control instruction.

[0075] The synchronous control command sending and receiving functions of the switch and each terminal are implemented through FPGA. The high-speed serial communication platform is based on the RapidIO protocol. The RapidIO protocol endpoint structure includes five layers of links, from top to bottom: 1. Logical and transport layer; 2. Serial protocol layer; 3. PCS layer; 4. PMA layer; 5. Electrical layer. The specific functions of each layer are shown in the block diagram in Appendix 1.

[0076] Development engineers implement the RapidIO high-speed serial bus platform by calling the FPGA's high-speed communication IP core. RapidIO transaction operations consist of request transactions and response transactions. Data packets are used as the basic transmission carrier between switches and terminals, and are interconnected through the switching structure (internal software function module for transaction requests and transaction responses generated during data transmission between switches and modules (cascaded devices). Each module communicates data with the switch through this function module). RapidIO data packets encapsulate bit fields and Control symbol information and transaction information to ensure that transactions are reliably transmitted to the target endpoint. The switching structure uses Control symbols to confirm the receipt or transmission of data packets.

[0077] Control symbol is a message unit used by the serial link port. It is used to manage various functions of serial link operation, including link maintenance, packet delimitation, packet response, error reporting and error recovery. Control symbol in SRIO includes two formats: long and short. The difference is that the short format is used when the serial link rate is lower than 5.5Gbps, and the long format is used when the serial link rate is higher than 5.5Gbps. The long format also provides some additional functions to enhance the error detection capability of burst errors and some other extended functions. This method uses the short format of Control symbol to realize the transmission of synchronous control instructions. All short format Control symbols are 24 bits long, and the format is as follows: Figure 6 shown.

[0078] The short Control symbol carries two functions, one of which is determined by the stype0 field and the other by the stype1 field. The parameter0 field and the parameter1 field are used by the function represented by the stype0 field, while the cmd field is used by the function represented by the stype1 field. The function represented by the stype0 field mainly includes the status information of the port transmitting the Control symbol, while the function represented by the stype1 field mainly transmits the delimiter of the RapidIO packet and some requests for receiving ports. Any Control symbol that does not contain a packet delimiter can be embedded in the packet, but it should be noted that the way and degree of embedding the Control symbol in the link will affect the performance of the link and the system.

[0079] In this method, the synchronous control instruction is sent using the multicast event control symbol. This event is different from other control symbol events in that the information it carries is independent of the link transmission control symbol. The multicast event control symbol allows the sending of user-defined events to be broadcast to the entire system. Its format is Figure 7 shown.

[0080] The PCS layer is responsible for channel segmentation (Striping), generating idle sequences and converting characters into corresponding 8B / 10B encoded K codes and D codes.

[0081] The PMA layer is responsible for connecting with the electrical layer. The PMA layer is also responsible for ensuring that different channels are correctly aligned with each other.

[0082] The electrical layer represents the different devices, receivers, and the electrical connections between them.

[0083] Embodiment 3:

[0084] 1. The method for high-speed serial bus data synchronization is characterized in that it is based on the RapidIO high-speed communication protocol bus platform, and the synchronization control instruction is implemented through the Control symbol instruction of the serial protocol layer in the RapidIO port structure.

[0085] 2. The RapidIO protocol according to claim 1 is implemented through an FPGA chip with a high-speed communication interface, and a high-speed serial communication bus platform is built by calling the FPGA's SRIO IP core.

[0086] 3. The data synchronization according to claim 1 is characterized by ensuring that multiple terminals in multiple modules within the system process the data at the same time or execute the control algorithm at the same time, and can make corresponding control strategies or report the system status information in real time.

[0087] 4. The Control symbol instruction according to claim 1 is characterized in that the serial protocol layer in the RapidIO port structure is lower than the logical transmission layer of the user interface, and is a flag indicating the status of the data packet and the status of the link, so it has a higher priority than data in link transmission. This function is used to carry the synchronization signal to realize the real-time transmission of the synchronous control instruction, which can ensure the real-time and reliability of the synchronization signal.

[0088] According to the method for synchronizing multiple modules as described in claim 3, it is characterized in that multiple modules adopt a cascade mode, the received synchronization control instruction times are inconsistent, and each module needs to perform a hierarchical delay inside. The synchronization of the system is achieved by controlling the synchronization delay of each module through parameters, and the synchronization error is adjustable and controllable.

[0089] 6. The synchronous control instruction according to claim 4 is characterized in that the control symbol instruction is used to carry the synchronization signal, which can be sent when the channel is idle, or the synchronous control instruction can be inserted into the data when the channel is sending data, interrupting the data being sent, sending the synchronous control instruction first, and then continuing to send the data at the time of the previous interruption after the synchronous control instruction is sent.

[0090] 7. According to the insertion of synchronization control instructions as described in claim 5, the synchronization control instructions use the multicast event of Control symbol, and its characteristic is that the multicast event allows user-defined events to be broadcast to the entire system. The switch sends the synchronization control instructions to multiple terminals through the multicast function to achieve synchronization of all terminals or devices in the system.

[0091] 8. The switch according to claim 6 sends synchronous control instructions, characterized in that the switch implements the broadcast of synchronous control instructions by building an internal multicast module through FPGA, and also realizes data interaction between various terminals or devices connected to the switch, and can insert multicast synchronous control instructions into data frames during data transmission.

[0092] Embodiment 4:

[0093] Based on the same concept, the present invention provides a high-speed serial bus data synchronization system, combined with Figure 5 The system structure diagram is introduced, including: FPGA, switch and multiple cascade devices;

[0094] The FPGA is used to build a RapidIO high-speed communication protocol bus;

[0095] The switch is used to send data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascade devices through the switch;

[0096] The multiple cascade devices are used to execute synchronization control instructions to achieve clock synchronization.

[0097] Preferably, the plurality of cascade devices include: a multicast module and an internal synchronization module;

[0098] The multicast module is used for each level of equipment to send the synchronization control instruction to the lower level equipment after receiving the synchronization control instruction;

[0099] The internal synchronization module is used to perform clock synchronization inside the cascade device.

[0100] Preferably, the internal synchronization module comprises: a hierarchical delay submodule and a delay time submodule;

[0101] The hierarchical delay submodule is used to delay each level of equipment after receiving the synchronization control instruction according to the specific number of equipment, and then multicast it to each terminal inside the equipment to ensure the internal data synchronization of each equipment in the whole system;

[0102] The delay time submodule is used to use the transmission time of the synchronization control instruction and the internal processing time of the switch as the delay time of each level.

[0103] Preferably, the switch comprises: a priority module;

[0104] The priority module is used to send the data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascade devices through the switch according to the priority order;

[0105] The priorities are, from high to low, as follows: data sent during the idle time of the RapidIO high-speed communication protocol bus data packet channel or data inserted in the channel being sent;

[0106] The data packet of the RapidIO high-speed communication protocol bus;

[0107] Non-timed data that is not controlled by the synchronization control instructions.

[0108] Preferably, the plurality of cascade devices further include: a master module, a plurality of multi-stage slave modules;

[0109] The master module and multiple slave modules all include a synchronous expansion interface;

[0110] The master module is connected to the next-level multi-level slave modules of the master module through the synchronous expansion interface of the master module;

[0111] Each multi-stage slave module is connected to the next-stage multi-stage slave module of the slave module through the synchronous expansion interface of the multi-stage slave module.

[0112] Preferably, the RapidIO high-speed communication protocol bus comprises: a logical transmission layer, a serial protocol layer, a PCS layer, a PMA layer and an electrical layer connected in sequence;

[0113] The logical transmission layer is used to transmit the character stream in the data packet to the serial protocol layer between the RapidIO high-speed communication protocol bus, the switch and the cascade device;

[0114] The serial protocol layer is used to realize the real-time transmission of the synchronization control instruction based on the character stream in the data packet transmitted by the logical transport layer;

[0115] The PCS layer is used to segment the RapidIO high-speed communication protocol bus data packet channel, generate idle time and execute the character stream in the data packet;

[0116] The PMA layer is connected to the electrical layer to properly align each of the channels;

[0117] The electrical layer is used to establish electrical connections between the multiple cascade devices.

[0118] Preferably, the synchronization control instructions include: long-format synchronization control instructions and short-format synchronization control instructions;

[0119] The long format synchronization control instruction is used to provide extended functions and enhance the error detection capability of burst errors;

[0120] The short-format synchronization control instruction is used to transmit the synchronization control instruction including the status information of the transmission synchronization control instruction process, the delimiter of the transmission data packet and the synchronization control instruction of the multi-stage device receiving port request;

[0121] When the serial link for transmitting data is higher than 5.5 Gbps, the long format synchronization control instruction is used; when the serial link for transmitting data is lower than 5.5 Gbps, the short format synchronization control instruction is used;

[0122] The synchronous control instruction without the delimiter is allowed to be embedded in the data packet of the RapidIO high-speed communication protocol bus.

[0123] Preferably, when the serial link is the RapidIO high-speed communication protocol bus, the data transmission rate of the RapidIO high-speed communication protocol bus is lower than 5.5 Gbps using the short format synchronization control instruction.

[0124] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0125] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0126] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0127] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0128] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are included in the scope of the claims of the present invention to be approved.

Claims

1. A method for high-speed serial bus data synchronization, characterized in that: include: Build RapidIO high-speed communication protocol bus based on FPGA chip; Send the data packets and synchronous control instructions of the RapidIO high-speed communication protocol bus to multiple cascaded devices through the switch; The multiple cascaded devices execute synchronization control instructions to achieve clock synchronization; The synchronization control instructions include: long-format synchronization control instructions and short-format synchronization control instructions; The long-format synchronization control instruction transmits the state information of the transmission synchronization control instruction process, the delimiter of the transmission data packet, and the synchronization control instruction of the receiving port request of multiple cascaded devices, and provides extended functions and enhances the error detection capability of burst errors; The short-format synchronization control instruction transmits the synchronization control instruction including the status information in the process of transmitting the synchronization control instruction, the delimiter of the transmission data packet and the synchronization control instruction of the receiving port request of the plurality of cascaded devices; When the serial link for transmitting data is higher than 5.5 Gbps, the long format synchronization control instruction is used; when the serial link for transmitting data is lower than 5.5 Gbps, the short format synchronization control instruction is used; wherein the synchronization control instruction not containing the delimiter is allowed to be embedded in the data packet of the RapidIO high-speed communication protocol bus; When the serial link is the RapidIO high-speed communication protocol bus, the data transmission rate of the RapidIO high-speed communication protocol bus is lower than 5.5 Gbps using the short format synchronization control instruction.

2. The method according to claim 1, characterized in that The multiple cascaded devices execute synchronization control instructions to achieve clock synchronization, including: After receiving the synchronization control instruction, each level of equipment first sends the synchronization control instruction to the lower level equipment, and then performs synchronization within the equipment at this level.

3. The method according to claim 2, characterized in that The synchronization inside the device at this level includes: According to the specific number of devices, after receiving the synchronization control instruction, each level of equipment will delay it in different levels and then broadcast it to each terminal inside the device to ensure the internal data of each device in the entire system is synchronized.

4. The method according to claim 3, characterized in that The delay is determined by the transmission time of the synchronization control instruction and the internal processing time of the switch.

5. The method according to claim 1, characterized in that The method of sending the data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascade devices through a switch includes: Send the data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascaded devices through the switch in order of priority; The priorities from high to low are: Data sent during idle time of the RapidIO high-speed communication protocol bus data packet channel or inserted into data being sent in the channel; The data packet of the RapidIO high-speed communication protocol bus; Non-timed data that is not controlled by the synchronization control instructions.

6. The method according to claim 5, characterized in that The data transmission of the RapidIO high-speed communication protocol bus includes: a logical transmission layer, a serial protocol layer, a PCS layer, a PMA layer and an electrical layer; The logical transport layer transmits the character stream in the data packet to the serial protocol layer between the RapidIO high-speed communication protocol bus, the switch and the cascade device; The serial protocol layer realizes the real-time transmission of the synchronization control instruction based on the character stream in the data packet transmitted by the logical transport layer; The PCS layer segments the RapidIO high-speed communication protocol bus data packet channel, generates idle time and executes the character stream in the data packet; The PMA layer correctly aligns each of the channels and connects with the electrical layer; The electrical layer establishes electrical connections for the plurality of cascaded devices.

7. The method according to claim 5, characterized in that The synchronization control instructions include: synchronization control instructions in data packets of the RapidIO high-speed communication protocol bus and synchronization control instructions converted from synchronization signals transmitted by external devices.

8. A system for high-speed serial bus data synchronization, characterized in that: include: FPGA, switches, and multiple cascaded devices; The FPGA is used to build a RapidIO high-speed communication protocol bus; The switch is used to send data packets and synchronization control instructions of the RapidIO high-speed communication protocol bus to multiple cascade devices through the switch; The multiple cascade devices are used to execute synchronization control instructions to achieve clock synchronization; The synchronization control instructions in the plurality of cascaded devices include: long-format synchronization control instructions and short-format synchronization control instructions; The long-format synchronization control instruction transmits the state information of the transmission synchronization control instruction process, the delimiter of the transmission data packet, and the synchronization control instruction of the receiving port request of multiple cascaded devices, and provides extended functions and enhances the error detection capability of burst errors; The short-format synchronization control instruction transmits the synchronization control instruction including the status information in the process of transmitting the synchronization control instruction, the delimiter of the transmission data packet and the synchronization control instruction of the receiving port request of the plurality of cascaded devices; When the serial link for transmitting data is higher than 5.5 Gbps, the long format synchronization control instruction is used; when the serial link for transmitting data is lower than 5.5 Gbps, the short format synchronization control instruction is used; wherein the synchronization control instruction not containing the delimiter is allowed to be embedded in the data packet of the RapidIO high-speed communication protocol bus; When the serial link is the RapidIO high-speed communication protocol bus, the data transmission rate of the RapidIO high-speed communication protocol bus is lower than 5.5 Gbps using the short format synchronization control instruction.

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