Dynamic interrupt rate control in computing systems

Abstract

Disclosed are systems, devices, and methods for intentionally delaying the servicing of interrupts in a computing system. The computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays the servicing of the interrupt based on various conditions. If the interrupt is an interrupt of a first type and the processor is in a first power state, the servicing of the interrupt is delayed for a first time period. If the interrupt corresponds to an interrupt of the first type and the processor is in a second power state, the servicing of the interrupt is delayed for a time period longer than the first time period. If a non-maskable interrupt is received before expiration of the first time period or the second time period, servicing of any previously delayed interrupt is allowed to proceed.

Description

[0001] background

[0002] Related technical description

[0003] Modern processors include a variety of circuits and components to facilitate fast and efficient computing. In addition, circuits and components are included to manage communications between devices (including devices external to the processor). For example, an input / output (I / O) controller is generally included to manage communications with external devices (such as display devices, external storage devices, network communications, and various other peripheral devices). In order to communicate with these devices, transactions are passed from and received by the processing elements of the processor (e.g., central processing unit, graphics processing unit, etc.).

[0004] In recent years, greater efforts have been put into reducing the power consumed by computing devices. In the case of battery-operated computing devices, reducing power consumption can mean longer operating time before the battery must be recharged. In other cases, reducing power consumption can be for other purposes, such as reducing the operating temperature of the device or attempting to be more environmentally friendly. Regardless of the reason, one of the disadvantages of reducing power consumption is that the performance of the device is typically reduced as well. If the performance of a device (e.g., a laptop computer, mobile phone, game console, etc.) is significantly degraded due to the mechanisms within the device for reducing power consumption, the user will become frustrated and dissatisfied with the device. Therefore, the user will not purchase the device.

[0005] In order to provide products that meet the performance expectations of users, designers must balance power consumption issues and performance issues. To do this, designers must decide when and to what extent the device can enter a reduced power state. An important component of power consumption management in a computing system is the time that a processing unit (such as a central processing unit, CPU) is in an idle state. Since the CPU consumes a relatively large amount of power when it is not idle, leaving the CPU in an idle state for a longer period of time can reduce power consumption. One activity that interferes with the idle state of the CPU is the processing of interrupts. Interrupts occur in response to activities detected by the system (e.g., I / O). For example, if a user activates an input device, such as a mouse, activity is detected and an interrupt is generated. The interrupt handler then "interrupts" the CPU to let it know that an activity has been detected that must be processed. In response to the interrupt, the CPU takes action to respond to the activity, such as by causing the mouse pointer to move to a certain position on the display device. When processing such an interrupt, the CPU must exit the idle state (if it was originally in the idle state) to enter a higher power performance state (power state). This higher power performance state consumes more power than the idle state. In the case where interrupts are handled as they come, the CPU may be caused to repeatedly enter and exit the idle state, which in turn reduces the effectiveness of the idle state in reducing power consumption.

[0006] Although immediately handling interrupts as described above provides improved performance, it increases power consumption. Although this is the most direct way to ensure that the device maintains high performance, in some cases, immediately handling interrupts may not be necessary to maintain a satisfactory user experience. In view of the above, it is desirable to implement a system and method for more efficient power management. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of one embodiment of a computing system.

[0009] Figure 2 Power performance state transitions and interrupt patterns in a computing system are shown.

[0010] Figure 3 is a table showing system status, interrupt mode, mask timer value, and maskable interrupts.

[0011] Figure 4 An embodiment of a method for managing interrupts in a computing system.

[0012] Figure 5 Embodiments for managing interrupts in a computing system are shown. DETAILED DESCRIPTION

[0013] In the following description, many specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, it will be appreciated by those skilled in the art that various embodiments may be practiced without these specific details. In some cases, well-known structures, components, signals, computer program instructions, and techniques are not shown in detail to avoid obscuring the methods described herein. It should be understood that for simplicity and clarity of illustration, the elements shown in the drawings may not be drawn to scale. For example, the size of some elements may be enlarged relative to other elements.

[0014] Various systems, devices and methods for shielding and unshielding interrupts in a computing system are disclosed herein. Shielded interrupts are intentionally delayed in service and merged during a time period when they are not processed. At a later point in time, the merged interrupts are serviced.

[0015] Figure 1One embodiment of a system 100 is shown that includes an interrupt controller 108 for detecting and handling interrupts in a computing system. In the example shown, a plurality of external devices 120A to 120N (e.g., a mouse, a camera, a storage device, etc.) are coupled to communicate signals that are detected by the interrupt controller 108. In the example shown, the CPU 102 handles the interrupt when notified of the received interrupt by the interrupt controller 108. In various embodiments, the interrupt may be generated by the CPU 102, any of the devices 120, or other components in the system that are not explicitly shown.

[0016] In the illustrated embodiment, the CPU 102 is coupled to communicate with the interrupt controller 108 via a communication architecture 104. The communication architecture 104 represents any bus, crossbar, network, or other mechanism to pass data between the CPU 102 and the link controller 108. In various embodiments, the communication architecture 104 includes separate command and data paths. In other embodiments, a single path is used to pass both commands and data.

[0017] Figure 1 104. A power management controller 106 is also shown in the system 100. In the example shown, the power management controller 106 is coupled to other components in the system 100 via the communication architecture 104. However, as will be appreciated by those skilled in the art, the logic represented by the power management controller 106 may be located elsewhere in the computing system and may communicate with other components in the system via paths other than the communication architecture 104. In general, the power management controller 106 monitors and / or controls various power performance states of components within the system 100. In response to detecting various events, the power management controller 106 causes other components within the system 100 to increase or decrease their current power performance states. Changing the power performance state includes changing the current operating frequency of a component (e.g., CPU 102, architecture 104, etc.) and / or changing the current voltage level of a particular component.

[0018] In addition to the above, Figure 1An interrupt masking unit 110 is included, having an interface for coupling to an interrupt controller 108 and an interface for receiving an indication of a current power state 130 of the system. In various embodiments, the interrupt masking unit 110 provides an indication to the interrupt controller 108 indicating which received interrupts can be serviced in an intentionally delayed manner (i.e., which interrupts can be "masked"). In various embodiments, the determination as to which interrupts can be serviced in a delayed manner is based at least in part on the type of interrupt received and the current power performance state 130 of one or more components within the system 100. Although shown as a separate unit, the masking unit 110 circuitry may be included as part of the interrupt controller 108. In various embodiments, the circuitry of the masking unit 110 is designed to perform the functions described herein. In other embodiments, the masking unit 110 includes circuitry that executes instructions to perform the functions described. In various embodiments, circuitry associated with the interrupt controller 108 and the masking unit 110 remains powered even when other portions of the system are in an idle or reduced power state. Figure 1 In various embodiments, the timer 112 and masking logic 114 are included in the interrupt masking unit 110. In various embodiments, the timer 112 is used to determine how long various types of interrupts will be intentionally delayed. In various embodiments, the masking logic 114 includes circuits for determining the type of interrupt received, setting the timer 112 to various values ​​based on the type of interrupt received and the current power state 130, and determining whether the timer 112 has expired or whether a non-maskable interrupt (i.e., an interrupt whose service cannot be intentionally delayed) has been received.

[0019] Figure 2 A diagram 200 showing the operating states of components in a computing system and the corresponding interrupt modes (interrupt mode 0, interrupt mode 1, and interrupt mode 2) that can be implemented is shown. In the example shown, the power performance state of the component is shown to transition between various states. In general, a given power performance state has a corresponding power level (e.g., as reflected by a specific voltage supplied to the component). The power performance level also includes a given performance associated with a given operating frequency. For discussion purposes, a processor (such as a CPU) is the component. However, other components are possible and are contemplated.

[0020] As shown, three different power performance levels are shown: active, idle S1 and idle S2. Although only three power performance levels are shown, other embodiments may include more or less than three power performance levels. Generally speaking, the "active" level corresponds to the full power level and all components are turned on (all turned on). In other words, the components are not operated in a reduced power state. "Idle S1" represents that the components are idle and have been idle for less than a threshold amount of time and operate in a reduced power state. In this example, the display remains open, the processor core is in a low power state, and the I / O subsystem is in a low power state. "Idle S2" state represents that the components are idle and have been in an idle state for more than a threshold amount of time. When in the idle S2 state, the components operate in a lower power state than when in the idle S1 state. In this example, the display is turned off (display is turned off) and the I / O subsystem is placed in an even lower power state.

[0021] Figure 2 Transitions (210, 212, 214, 216) between these power states are shown. For example, when a component transitions 210 from an active state to an idle S1 state, the component and / or one or more other components may transition to a lower power performance state than its current state. Similarly, transitioning 212 from the idle S1 state to the idle S2 state results in an even lower power operating state. It should be noted that although this example shows transitions between adjacent states (e.g., transitioning from idle S1 to idle S2), embodiments are envisioned in which transitioning from one state to another may "skip" one or more states to directly enter a non-adjacent state. For example, a transition may be made directly from the idle S2 state to the active state.

[0022] Associated with each of the power performance states is a different interrupt handling mode. Figure 2 As shown, there are interruption mode 0 (interruption mode 0), interruption mode 1 (interruption mode 1) and interruption mode 2 (interruption mode 2). In various embodiments, the interruption mode is determined at least in part based on the current power performance state. For example, when the system transitions from the active state to the idle S1 state, the interruption mode transitions from interruption mode 0 to interruption mode 1.

[0023] Figure 3 A table 300 is provided showing one embodiment of an interrupt mode associated with a system state. Table 300 includes four columns. The first column (system state 302) identifies the current power performance state of the system as discussed above. The second column (interrupt mode 304) shows the interrupt mode associated with the corresponding system state. The third column (mask timer 306) indicates whether interrupt masking is on and identifies the masking duration T. In various embodiments, the mask timer is located within the interrupt mask unit 110, such as Figure 1308. However, in other embodiments, the timer is located elsewhere. The fourth column (maskable interrupts 308) identifies which interrupts (if any) can be masked for a given mode. Generally speaking, a "maskable" interrupt is an interrupt whose service can be intentionally delayed under certain conditions. Whether an interrupt is maskable can be determined programmatically or otherwise as needed.

[0024] exist Figure 3 , the first row 310 corresponds to the active state of the system. When in the active state, the components (e.g., CPU) in the system operate in a manner that processes received interrupts without intentional delay. This is referred to as interrupt mode 0. In this mode, interrupts are not masked (interrupts are off), and there are no maskable interrupts (none). Serving an interrupt without intentional delay does not mean that there is no delay in servicing the interrupt. In various embodiments, there is an inherent delay in servicing the interrupt. As used herein, intentional delay refers to intentionally increasing the time added before the service of the interrupt will begin. The second row 312 corresponds to the idle S1 state. In various embodiments, the idle S1 state corresponds to a state in which one or more components have been idle for a certain period of time but not exceeding a threshold amount of time. For example, if the CPU is currently idle and has been idle for N cycles (or some other time measurement) and N is less than a certain threshold amount of time, the CPU is considered to be in the idle S1 state. When in the idle state, the CPU consumes less power than when in the active state. In order to serve the interrupt, the CPU must exit the idle state and enter the active state. Therefore, power consumption increases when the CPU transitions from the idle state to the active state in order to serve the interrupt.

[0025] As shown in Table 300, when in the idle S1 state, enable interrupt masking (mask open) and set duration T equal to a certain value N. N can be the number of cycles or any other desired time measurement. When enabling masking, identify interrupts that can be masked (delayed intentionally). In the example shown, the interrupts of type A and type B are maskable, where A and B are the designations of two types or categories of interrupts that can occur in the system. This means that if an interrupt of type A or type B is generally to occur, the service of these interrupts can be delayed (or "merged"). In various embodiments, merging interrupts includes storing data indicating interrupts (e.g., interrupt type, device ID, etc.) in a queue or other storage structure. When merging interrupts in this way, the CPU will not be aware of the interrupt. Therefore, the CPU remains in its current idle state, rather than transitioning to an active state.

[0026] When enabling shielding as in row 312, duration T effectively sets limits on how long interrupts can be intentionally delayed / merged. For example, in one embodiment, when in interrupt mode 1, shield duration T is set to a certain value N representing a given amount of time. Assuming that only maskable interrupts are received during such program time, the received interrupts will be merged until the time period T expires. When time period T expires, any interrupts that have been merged are serviced. Serving interrupts will cause the CPU to exit the idle state and enter the active state. In the absence of other conditions that keep the CPU in the active state, the CPU can re-enter the idle state after servicing the interrupts. If non-maskable interrupts occur when enabling shielding, then the non-maskable interrupts received will be serviced when they are not combined and without considering the shield duration T. In various embodiments, when servicing non-maskable interrupts, any other interrupts that are merged are also serviced at the same time. Non-maskable interrupts may include interrupts associated with user presence detection devices (e.g., cameras), USB I / O devices (e.g., mice, pens, touch pads, etc.) or other devices.

[0027] Returning to table 300, row 314 corresponds to the idle S2 state. When in the idle S2 state, interrupt mode 2 is effective. When in interrupt mode 2, masking is enabled and mask duration T is set. In this case, duration T is set to a certain value M, where M>N. In fact, when the power performance state is low (compared to idle S1, as in the case of idle S2), masking can be used more actively. In addition to having a longer mask duration, more and / or different types of interrupts can be maskable. In this example, the other two types of interrupts have been identified as maskable, so that the interrupts of type A, type B, type C and type D are all maskable, wherein A, B, C and D are references to different types or categories of interrupts that can occur in the system. Similar to what is discussed above, the interrupts identified as maskable will be merged until the maskable duration expires. After this time period expires, any merged interrupts will be serviced. In addition, as described above, if a non-maskable interrupt is received, the non-maskable interrupt will be serviced without merging and any merged interrupts can also be serviced.

[0028] Row 316 corresponds to an even lower power performance state (idle S3). In this state, interrupt mode 3 is effective and performs masking of maskable interrupts without establishing a specific duration. In this case, the interrupt will be masked until a non-maskable interrupt is received.

[0029] Now go to Figure 4, shows one embodiment of a method 400 for intentionally delaying servicing of an interrupt. In the example shown, an interrupt is received 402 and the current power state of the system is determined (blocks 404, 406, 408, and 410). Depending on the current power state, various actions are taken. In general, Figure 4 The determination of a given power state in can be used to determine a given interrupt mode. For example, a register or indication can be used to determine the current power state of the system. However, in other embodiments, such as with respect to Figure 3 As discussed above, different power states are associated with different interrupt modes. Figure 4 While the illustrated method determines the current power state of the system to determine the interrupt mode, other embodiments may directly determine the current interrupt mode by accessing register values ​​or other means.

[0030] like Figure 4 As shown, after receiving an interrupt, if the current power state of the system is active (404), the interrupt is serviced without introducing any intentional delay (420). As previously discussed, the active state generally corresponds to a full power state. It should be noted that in some embodiments, the active state does not necessarily mean that all system components are turned on or in a full power state. On the contrary, in some embodiments, the active state corresponds to a state in which all components related to servicing a particular interrupt are turned on and are in a power state capable of servicing the interrupt (even if the power state is not the highest power state of the system or device). In addition to the above, it should be noted that servicing an interrupt without introducing an intentional delay does not mean that there is no delay in servicing the interrupt. On the contrary, trying to service an interrupt can cause various unavoidable delays. As used herein, an intentional delay is a delay that has been introduced that can be avoided if necessary. In other words, in the case where the service of the interrupt can occur within N cycles (or some other time measurement), the interrupt is not serviced for at least a period of N+M, where M is an additional amount of time intentionally introduced for the purpose of delaying the service of the interrupt.

[0031] If the current power state is not the active state (404) but is power state S1 (406), a determination is made as to whether the received interrupt corresponds to an interrupt of a particular type (416). In various embodiments, power state S1 represents a power state that is lower than the active state but higher than other power states of the system. In the illustrated embodiment, the particular type of interrupt (416) is one of type A or B, where A and B are references to two types or categories of interrupts that may occur in the system. If the interrupt does not correspond to the specified type (A or B) (416), the received mask is not currently maskable and the received interrupt is serviced without introducing any intentional delay (420). However, if the received interrupt corresponds to one of the specified types (416), the servicing of the interrupt is intentionally delayed according to a given delay mode (mode 1). With regard to Figure 5 Discusses additional details of handling interrupts for various latency modes.

[0032] If the current power state is not S1 (406) but is state S2 (408), it is determined (412) whether the interrupt corresponds to at least one of a plurality of types, including types A, B, C, or D. In various embodiments, power state S2 represents a power state that is lower than state S1 but higher than one or more other power states of the system. When in power state S2, more and / or different interrupt types may be considered maskable. Thus, in the example shown, the categories have been expanded from types A and B (as shown in box 416) to also include types C and D (as shown in box 412). It should be noted that although the discussion describes two types A and B in the first case and four types A, B, C, and D in the second case, this is not intended to be merely exemplary. In various embodiments, any number of desired interrupts or interrupts of any type may be included in each of the various groupings. For purposes of discussion, simply selecting Figure 4 The specified type of interrupt in Figure 3 Those shown in .

[0033] If, in block 412, the received interrupt does not correspond to one of types A, B, C, or D, then the received interrupt is serviced without introducing any intentional delay 424. However, if the received interrupt corresponds to one of the specified types 412, then the servicing of the interrupt is intentionally delayed according to a given delay mode (mode 2).

[0034] Finally, if the current power state is not S2 (block 408) but is state S3 (a lower power state than S2) (410), a determination is made as to whether the received interrupt corresponds to one of a plurality of types 414. In the example shown, the types shown in block 414 are the same as those in block 412. However, this is not necessarily the case. In other embodiments, the types in block 414 may include additional and / or other types. If the received interrupt does not correspond to one of the specified types, the interrupt is serviced without introducing an intentional delay 424. However, if the received interrupt corresponds to one of the specified types, the interrupt is serviced according to the delayed service mode (mode 3). Figure 4 In the example of , S3 is shown as the lowest power state and generally corresponds to sleep or other lower power states. However, other embodiments may include more and / or different power states than those shown. Such embodiments are possible and contemplated. If the current power state does not correspond to S3 (410), then the interrupt is serviced without intentional delay (424).

[0035] Figure 5 Shows Figure 4 1 and 2. Delayed service mode 1 (500), mode 2 (520), and mode 3 (540) are shown. Generally speaking, mode 1 represents the highest power state of the three modes, and mode 3 represents the lowest power state of the three modes. Figure 4As discussed in , an interrupt has been received and a delayed service mode is determined. In delayed service mode 1 (500), it is determined whether a delay timer (T) has been set (502). For example, an interrupt that caused the timer to be set may have been recently received and the timer has not expired (i.e., the timer is active and is still in the process of recording the passage of time, such as via decrement or other means). If the timer is currently inactive, the timer is set to a value N (504). In various embodiments, N may be an integer representing a duration. For example, N may represent a number of clock cycles, microseconds, or some other time measurement. In addition to setting the timer, masking of the interrupt is also started and the service of the received interrupt is intentionally delayed. As time passes, a check is performed on the timer value to determine whether the timer has expired (506). If it has not expired, the masking of the interrupt continues (510). On the other hand, when the timer expires, the intentional delay in the service of the interrupt stops and normal service of the interrupt is allowed to proceed (508). Optionally, even if the timer has not expired (506), if a non-maskable (NM) interrupt is received, then masking of the interrupt is stopped and normal servicing of the interrupt is allowed to proceed (508). In other words, if a type A interrupt is received and the interrupt is currently intentionally delayed (the interrupt is masked), then if a non-maskable interrupt is received, its intentional delay is terminated. In this case, both the non-maskable interrupt and the delayed interrupt will be serviced. In the current example, based on Figure 4 and Figure 5 , interrupts of type A and B are considered maskable. Therefore, if an interrupt of type C or D is received while in service mode 1 (500), the received and currently delayed interrupt will be serviced (508). In other words, receiving a non-maskable interrupt overrides the intentional delay of a maskable interrupt.

[0036] If in block 502, it is determined that the timer is currently active when a maskable interrupt is received, the method abandons setting the duration (i.e., skipping block 504) and proceeds to block 506, where the wait timer expires or a non-maskable interrupt is received, as described above. In this case, the intentional delay of the most recently received maskable interrupt will not be the full duration of N (assuming some time has passed since the timer was set).

[0037] Service mode 2 (520) functions similarly to service mode 1 (500), except for which interrupts are considered maskable and the duration of the intentional delay. As with service mode 1 (500), it is determined whether the timer has been set and active (522). If not, the timer is set to a value M, where M is greater than N (524). In other words, the intentional delay of maskable interrupts under service mode 2 is longer than under service mode 1. The method then proceeds to box 526, where the wait timer expires or a non-maskable interrupt is received. When such an event occurs, service of the interrupt is allowed (528). If such an event has not yet occurred (526), ​​masking of the interrupt continues (530).

[0038] When in service mode 3 (540), the interrupt is masked and its service is intentionally delayed until the system exits the current power state or a non-maskable interrupt is received (542). In this example, the current power state is a sleep state in which the processor is inoperable (i.e., not currently powered to perform work). In this example, there is no timer to stop the intentional delay of the maskable interrupt. Therefore, assuming that the system is not awakened and a non-maskable interrupt is not received, the service of the maskable interrupt can be delayed for a significantly longer period of time than service mode 1 (500) or service mode 2 (520). Assuming that the system is not awakened and a non-maskable interrupt is not received, the masking of the interrupt continues (544). Otherwise, the interrupt will be allowed to be serviced (546).

[0039] although Figure 5 , but in some embodiments, the change of the power state of the system will change the current behavior of the shielding of the interrupt as shown in the figure. For example, if the current mode is delayed service mode 2 (520) and the timer has not expired (526), ​​then the shielding of the interrupt will usually be restored when the timer expires or a non-maskable interrupt is received (whichever occurs first). However, if the system is transformed to a lower power state (e.g., S3) corresponding to service mode 3 (540), the condition for restoring the service of the maskable interrupt changes from the condition of frame 526 to the condition of frame 542. In other words, if the system is transformed to power state S3 and then the timer expires, the service of the maskable interrupt is not restored. On the contrary, the service of the interrupt is restored after the system is awakened or receives a non-maskable interrupt. Similarly, if the system is transformed to power state S1 (corresponding to service mode 1) from power state S2 (corresponding to service mode 2), then any interrupt (e.g., interrupt of type C) that is intentionally delayed but cannot be masked under service mode 1 will cause the system to exit intentional delay and serve the interrupt (508). These and other embodiments are possible and contemplated.

[0040] In various embodiments, the method and / or mechanism described herein are implemented using the program instructions of the software application. For example, it is envisioned that the program instructions can be executed by a general or special processor. In various embodiments, such program instructions can be represented by a high-level programming language. In other embodiments, the program instructions can be compiled from the high-level programming language into a binary, intermediate or other form. Alternatively, program instructions describing the behavior or design of hardware can be written. Such program instructions can be represented by a high-level programming language (such as C). Alternatively, a hardware design language (HDL) such as Verilog can be used. In various embodiments, program instructions are stored on any of a variety of non-temporary computer-readable storage media. The storage medium can be accessed by a computing system during use to provide program instructions to the computing system for program execution. Generally speaking, such a computing system includes at least one or more memories and one or more processors that execute program instructions.

[0041] Although the above embodiments have been described in considerable detail, numerous changes and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the appended claims be interpreted to encompass all such changes and modifications.

Claims

1. A system for merging interrupts, the system comprising: a processor configured to service the interrupt; as well as An interrupt controller, the interrupt controller being configured to: determining that the processor has transitioned from a full power state without maskable interrupts to a first reduced power state of a plurality of reduced power states, each of the plurality of reduced power states having one or more maskable interrupts and one or more non-maskable interrupts; detecting a received interrupt; and Delaying servicing of the interruption in response to determining that: The interrupt corresponds to a first type of interrupt among a plurality of types of interrupts, wherein the first type of interrupt is one of the one or more maskable interrupts of the first reduced power state; and The processor is in the first reduced power state.

2. The system of claim 1, wherein at least two of the plurality of reduced power states have different numbers of maskable interrupts.

3. The system of claim 1 , wherein in response to determining that the processor is in the first reduced power state, the interrupt controller is further configured to set a mask duration equal to a first time period during which servicing of a maskable interrupt is delayed.

4. The system of claim 3, wherein the interrupt controller is further configured to service any received interrupts whose servicing has been delayed in response to detecting expiration of the first time period.

5. The system of claim 3, wherein the interrupt controller is further configured to, in response to detecting receipt of a non-maskable interrupt, service any received interrupt whose servicing has been delayed.

6. The system of claim 3, wherein in response to determining that the processor is in a second power state lower than the first reduced power state, the interrupt controller is further configured to set the masking duration equal to a second time period during which servicing of an interrupt is delayed, wherein the second time period is greater than the first time period.

7. The system of claim 6, wherein in response to determining that the processor is in a third power state lower than the second power state and has no associated mask duration, the interrupt controller is further configured to intentionally delay servicing of a maskable interrupt until the system exits the third power state or receives a non-maskable interrupt.

8. The system of claim 3, wherein in response to determining that the reduced power state corresponds to the first reduced power state and a timer is currently active, the interrupt controller is further configured to forgo setting the masking duration.

9. A method for coalescing interrupts in a computing system, the method comprising: generating an interrupt by a processing device to be serviced by a processor; determining, by an interrupt controller, that the processor has transitioned from a full power state without maskable interrupts to a first reduced power state of a plurality of reduced power states, each of the plurality of reduced power states having one or more maskable interrupts and one or more non-maskable interrupts; The interrupt is detected by the interrupt controller; as well as Delaying servicing of the interrupt by the interrupt controller in response to determining: The interrupt corresponds to a first type of interrupt among a plurality of types of interrupts, wherein the first type of interrupt is one of the one or more maskable interrupts of the first reduced power state; and The processor is in the first reduced power state.

10. The method of claim 9, wherein at least two of the plurality of reduced power states have different numbers of maskable interrupts.

11. The method of claim 9, wherein in response to determining that the processor is in the first reduced power state, the method further comprises, by the interrupt controller, setting a mask duration equal to a first time period during which servicing of a maskable interrupt is delayed.

12. The method of claim 11, further comprising, in response to detecting expiration of the first time period, servicing any received interrupts whose servicing has been delayed.

13. The method of claim 11, further comprising, in response to detecting receipt of a non-maskable interrupt, servicing any received interrupt whose servicing has been delayed.

14. The method of claim 11, wherein in response to determining that the processor is in a second power state lower than the first reduced power state, the method further comprises setting the masking duration equal to a second time period during which servicing of an interrupt is delayed, wherein the second time period is greater than the first time period.

15. The method of claim 14, wherein in response to determining that the processor is in a third power state lower than the second power state and has no associated mask duration, the method further comprises intentionally delaying servicing of a maskable interrupt until the system exits the third power state or receives a non-maskable interrupt.

16. The method of claim 11, wherein in response to determining that the reduced power state corresponds to the first reduced power state and a timer is currently active, the method further comprises forgoing setting the muting duration.

17. A device, comprising: a first interface configured to receive an indication of a current power state of a computing system; a timer configured to measure a duration; as well as Logic comprising circuitry configured to: determining that a transition has been made from a full power state without maskable interrupts to a first reduced power state of a plurality of reduced power states, each of the plurality of reduced power states having one or more maskable interrupts and one or more non-maskable interrupts; Detect the type of interrupt received; as well as The timer is set to a duration corresponding to a delay in servicing the interrupt in response to determining: The interrupt corresponds to a first type of interrupt among a plurality of types of interrupts, wherein the first type of interrupt is one of the one or more maskable interrupts of the first reduced power state; and The current power state is the first reduced power state.

18. The apparatus of claim 17, wherein at least two of the plurality of reduced power states have different numbers of maskable interrupts.

19. The device of claim 17, wherein in response to detecting the first reduced power state, the logic is further configured to set a masking duration equal to a first time period during which servicing of maskable interrupts is delayed.

20. The apparatus of claim 19, wherein the logic is further configured to, in response to detecting expiration of the first time period, service any received interrupts whose servicing has been delayed.

Images